Tools Information FAQs Application Note HA0075E Reset Oscillator Circu
|
|
|
Top Searches for this datasheet
HT49RA1/HT49CA1 Remote Type 8-Bit with
Tools Information FAQs Application Note HA0075E Reset Oscillator Circuits Application Note
Operating voltage: 2.0V~3.6V bidirectional lines, input lines, 8-bit prescaler carrier output (1/2 duty) Software LCD, control Watchdog Timer function Power down wake-up functions reduce
segment output, (input/output)/REM
external interrupt inputs shared with line 8-bit programmable Timer/Event Counter with
overflow interrupt function
Single 16-bit programmable timer/event counter
power consumption
instruction cycle with 4MHz system clock 4-level subroutine nesting manipulation instruction Table read instructions powerful instructions instructions executed machine
with overflow interrupt function
oscillator 32768Hz crystal oscillator driver with segments
type only), logical output option SEG12~SEG19 port option SEG0~SEG3 changing LCDC register
program memory data memory Real Time Clock
cycles
voltage reset/detector function 52-pin QFP, 64-pin LQFP packages
General Description
HT49RA1/HT49CA1 Remote Type 8-bit 8-bit high performance RISC architecture microcontroller. With internal carrier generator Driver functions device especially suitable multiple remote control product applications. usual Holtek features such power down wake-up functions, oscillator options, etc. combine ensure user applications require minimum external components. benefits power consumption, high performance, flexibility low-cost, provide these devices with versatility suit wide range application possibilities such industrial control, consumer products particularly suitable products such infrared remote controllers various, subsystem controllers, etc.
Rev. 1.00
2008
HT49RA1/HT49CA1
Device Types
Devices which have letter within their part number, indicate that they devices offering advantages easy effective program updates, using Holtek range development programming tools. These devices provide designer with means fast low-cost product development cycles. Devices which have letter within their part number indicate that they mask version devices. These devices offer complementary device applications that mature state their design process have high volume cost demands. Fully functionally compatible with their sister devices, mask version devices provide ideal substitute products which have gone beyond their development cycle facing cost-down demands. this datasheet, convenience, when describing device functions, only types mentioned name, however same described functions also apply Mask type devices.
Block Diagram
illa
illa
Note:
This block diagram represents devices, mask devices there Device Programming Circuitry.
Rev. 1.00
2008
HT49RA1/HT49CA1
Assignment
Rev. 1.00
2008
HT49RA1/HT49CA1
Description
Name Configuration Option Description Bidirectional NMOS 8-bit input/output port. Each chosen NMOS output Schmitt trigger input using software instructions. Pull-high resistors permanently connected these pins. 8-bit Schmitt trigger input lines with pull-high resistors. Each configured wake-up input configuration options. Pins PB0, PB1, pin-shared with INT0, INT1, TMR0 TMR1 respectively
PA0~PA7 PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7 PC0/REM
Wake-up
Carrier Output Bidirectional port. configured CMOS output carPull-high rier output using configuration option. Bidirectional NMOS 4-bit input/output port. Each chosen NMOS output Schmitt trigger input using software instructions. Each this port configured either segment normal using LCDC register. When used pins pull-high resistors permanently connected these pins. resistor connected between OSC1 ground implement internal system clock. Real time clock oscillator. OSC3 OSC4 connected 32768Hz crystal oscillator timing purpose. used system clock. selected then OSC3, OSC4 should left floating. power supply. VLCD should larger than connect operation i.e. VLCD voltage pump COM0~COM2 panel common connections. COM3/SEG32 setup panel segment common output driver configuration options. panel segments driver outputs.
PD0/SEG0~ PD3/SEG3
OSC1 OSC3 OSC4 VLCD COM0~COM2 COM3/SEG32 SEG4~SEG11 SEG12~SEG19 SEG20~SEG31 Note:
1/2, Duty
SEG12~SEG19 panel segments driver outputs SEG12~SEG19 setup CMOS Output segment outputs CMOS output configuration option. panel segments driver outputs. Schmitt Trigger reset input. Active low. Positive power supply Negative power supply, ground
Each programmed through configuration option have wake-up function.
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Total .150mA Total Power Dissipation .500mW Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C Total.-100mA
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
Rev. 1.00
2008
HT49RA1/HT49CA1
D.C. Characteristics
Test Conditions Symbol ISTB1 ISTB2 ISTB3 VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 IOL2 IOH2 VLVR Parameter Operating Voltage Operating Current OSC) Standby Current (*fS=T1) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=WDT OSC) Input Voltage Ports, TMR0/TMR1 INT0/INT1 Input High Voltage Ports, TMR0/TMR1 INT0/INT1 Input Voltage (RES) Input High Voltage (RES) Port Sink Current Port Source Current Common Segment Current Common Segment Current Pull-high Resistance Ports Voltage Reset Voltage Conditions load, fSYS=4MHz load, system HALT, HALT load, system HALT, HALT, type load, system HALT HALT, type VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD 2.1V option 3.15V optio voltage 2.2V option voltage 3.3V option VPOR RPOR Note: Start Voltage Ensure Power-on Reset Rise Rate Ensure Power-on Reset tSYS=1/fSYS please refer clock option 0.7VDD 0.9VDD 1.98 2.98 2.08 3.12 0.035 -160 2.10 3.15 2.20 3.30 0.3VDD 0.4VDD 2.22 3.32 2.32 3.50 V/ms Min. Typ. Max. Unit Ta=25°C
VLVD
Voltage Detector Voltage
Rev. 1.00
2008
HT49RA1/HT49CA1
A.C. Characteristics
Test Conditions Symbol Parameter Conditions 0.25 4000 4000 32768 1024 4000 *tSYS 2.0V~ 4MHz 3.6V Temp.= 50°C 3.0V 4MHz Temp.= 25°C fRTCOSC fTIMER Frequency Timer Frequency (TMR0/TMR1) Wake-up from HALT Min. Typ. Max. Unit Ta=25°C
fSYS
System Clock
tWDTOSC Watchdog Oscillator Period tRES tLVR tSST tINT External Reset Pulse Width Voltage Width Reset System Start-up Timer Period Interrupt Pulse Width
Note: *tSYS=1/fSYS
Rev. 1.00
2008
HT49RA1/HT49CA1
System Architecture
factor high-performance features Holtek range microcontrollers attributed internal system architecture. range devices take advantage usual features found within RISC microcontrollers providing increased speed operation enhanced performance. pipelining scheme implemented such that instruction fetching instruction execution overlapped, hence instructions effectively executed cycle, with exception branch call instructions. 8-bit wide used practically operations instruction set. carries arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. internal data path simplified moving data through Accumulator ALU. Certain internal registers implemented Data Memory directly indirectly addressed. simple addressing methods these registers along with additional architectural features ensure that minimum external components required provide functional with maximum reliability flexibility. This makes these devices suitable low-cost, high-volume production controller applications requiring words Program Memory bytes Data Memory storage. Clocking Pipelining main system clock, derived from oscillator subdivided into four internally generated non-overlapping clocks, T1~T4. Program Counter incremented beginning clock during which time instruction fetched. remaining T2~T4 clocks carry decoding execution functions. this way, T1~T4 clock cycle forms instruction cycle. Although fetching execution instructions takes place consecutive instruction cycles, pipelining structure microcontroller ensures that instructions effectively executed instruction cycle. exception this instructions where contents Program Counter changed, such subroutine calls jumps, which case instruction will take more instruction cycle execute. instructions involving branches, such jump call instructions, machine cycles required complete instruction execution. extra cycle required program takes cycle first obtain actual jump call address then another cycle actually execute branch. requirement this extra cycle should taken into account programmers timing sensitive applications.
illa
System Clocking Pipelining
Instruction Fetching
Rev. 1.00
2008
HT49RA1/HT49CA1
Program Counter During program execution, Program Counter used keep track address next instruction executed. automatically incremented each time instruction executed except instructions, such that demand jump non-consecutive Program Memory address. Remote Type series microcontrollers with LCD, note that Program Counter width varies with Program Memory capacity depending upon which device selected. However, must noted that only lower bits, known Program Counter Register, directly addressable user. When executing instructions requiring jumps non-consecutive addresses such jump instruction, subroutine call, interrupt reset, etc., microcontroller manages program control loading required address into Program Counter. conditional skip instructions, once condition been met, next instruction, which already been fetched during present instruction execution, discarded dummy cycle takes place while correct instruction obtained. lower byte Program Counter, known Program Counter register PCL, available program control readable writable register. transferring data directly into this register, short program jump executed directly, however, only this byte available manipulation, jumps limited present page memory, that locations. When such program jumps executed should also noted that dummy cycle will inserted. lower byte Program Counter fully accessible under program control. Manipulating might cause program branching, extra cycle needed pre-fetch. Further information register found Special Function Register section. Stack This special part memory which used save contents Program Counter only. stack have levels neither part data part program space, neither readable writable. activated level indexed Stack Pointer, neither readable writable. subroutine call interrupt acknowledge signal, contents Program Counter pushed onto stack. subroutine interrupt routine, signaled return instruction, RETI, Program Counter restored previous value from stack. After device reset, Stack Pointer will point stack.
Program Counter Bits Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow Time Base Interrupt Interrupt Skip Loading Jump, Call Branch Return from Subroutine PC11 PC10
Program Counter
Program Counter Note: PC11~PC8: Current Program Counter bits @7~@0: bits #11~#0: Instruction code address bits S11~S0: Stack register bits Program Counter bits wide, i.e. from b11~b0.
Rev. 1.00
2008
HT49RA1/HT49CA1
itia
stack full enabled interrupt takes place, interrupt request flag will recorded acknowledge signal will inhibited. When Stack Pointer decremented, RETI, interrupt will serviced. This feature prevents stack overflow allowing programmer structure more easily. However, when stack full, CALL subroutine instruction still executed which will result stack overflow. Precautions should taken avoid such cases which might cause unpredictable program branching. Arithmetic Logic Unit arithmetic-logic unit critical area microcontroller that carries arithmetic logic operations instruction set. Connected main microcontroller data bus, receives related instruction codes performs required arithmetic logical operations after which result will placed specified register. these calculation operations result carry, borrow other status changes, status register will correspondingly updated reflect these changes. supports following functions:
Arithmetic operations: ADD, ADDM, ADC, ADCM,
Program Memory Structure production runs. other type memory mask memory, denoted having within device name. These devices offer most cost effective solutions high volume products. Structure Program Memory capacity bits. Program Memory addressed Program Counter also contains data, table information interrupt entries. Table data, which setup location within Program Memory, addressed separate table pointer registers. Special Vectors Within Program Memory, certain locations reserved special usage such reset interrupts.
Location 000H
SUB, SUBM, SBC, SBCM,
Logic operations: AND, XOR, ANDM, ORM,
XORM, CPL, CPLA
Rotation RRA, RRCA, RRC, RLA, RLCA,
Increment Decrement INCA, INC, DECA, Branch decision, JMP, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
Program Memory location where user code program stored. microcontrollers, types Program Memory usually supplied. first type One-Time Programmable, OTP, memory where users program their application code into device. Devices with memory denoted having within their device name. using appropriate programming tools, devices offer users flexibility freely develop their applications which useful during debug products requiring frequent upgrades program changes. devices also applicable applications that require medium volume
This vector reserved device reset program initialisation. After device reset initiated, program will jump this location begin execution.
Location 004H
This vector used external interrupt. external interrupt INT0 device receives active edge, program will jump this location begin execution external interrupt enabled stack full.
Location 008H
This vector used external interrupt. external interrupt INT1 device receives active edge, program will jump this location begin execution external interrupt enabled stack full.
Rev. 1.00
2008
HT49RA1/HT49CA1
Location 00CH
This internal vector used Timer/Event Counter counter overflow occurs, program will jump this location begin execution timer/event counter interrupt enabled stack full.
Location 010H
following diagram illustrates addressing/data flow look-up table:
This internal vector used Timer/Event Counter counter overflow occurs, program will jump this location begin execution timer/event counter interrupt enabled stack full.
Location 014H
ifie
Table Program Example following example shows table pointer table data defined retrieved from HT49RA1 microcontroller. This example uses table data located last page which stored there using statement. value this statement which refers start address last page within Program Memory HT49RA1 microcontroller. table pointer setup here have initial value This will ensure that first data read from data table will Program Memory address locations after start last page. Note that value table pointer referenced first address present page instruction being used. high byte table data which this case equal zero will transferred TBLH register automatically when instruction executed. Because TBLH register read-only register cannot restored, care should taken ensure protection both main routine Interrupt Service Routine table read instructions. using table read instructions, Interrupt Service Routines change value TBLH subsequently cause errors used again main routine. rule recommended that simultaneous table read instructions should avoided. However, situations where simultaneous cannot avoided, interrupts should disabled prior execution main routine table-read instructions. Note that table related instructions require instruction cycles complete their operation. Table Location Bits
This internal vector used Time Base interrupt. Time Base interrupt occurs, program will jump this location begin execution time base interrupt enabled stack full.
Location 018H
This internal vector used Real Time Clock interrupt. program will jump this location begin execution when Real Time Clock interrupt signal generated interrupt enabled stack full. Look-up Table location within Program Memory defined look-up table where programmers store fixed data. look-up table, table pointer must first setup placing lower order address look data retrieved table pointer register, TBLP. This register defines lower 8-bit address look-up table. After setting table pointer, table data retrieved from current Program Memory page last Program Memory page using instructions, respectively. When these instructions executed, lower order table byte from Program Memory will transferred user defined Data Memory register specified instruction. higher order table data byte from Program Memory will transferred TBLH special register. unused bits this transferred higher order byte will read
Instruction TABRDC TABRDL PC11 PC10
Table Location Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits table address location bits, i.e. from b11~b0.
Rev. 1.00
2008
HT49RA1/HT49CA1
tempreg1 tempreg2 a,06h tblp,a tempreg1 temporary register temporary register
initialise table pointer note that this address referenced last page present page
tabrdl
transfers value table referenced table pointer tempregl data prog. memory address transferred tempreg1 TBLH
tabrdl
tblp tempreg2
reduce value table pointer transfers value table referenced table pointer tempreg2 data prog.memory address transferred tempreg2 TBLH this example data transferred tempreg1 data register tempreg2 value will transferred high byte register TBLH
F00h sets initial address last page (for HT49RA1)
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
Data Memory
Data Memory volatile area 8-bit wide internal memory location where temporary information stored. Divided into three sections, first these area where special function registers located. These registers have fixed locations necessary correct operation device. Many these registers read from written directly under program control, however, some remain
protected from user manipulation. second area Data Memory reserved general purpose use. locations within this area read write accessible under program control. third area reserved Memory. This special area Data Memory mapped directly display data written into this memory area will directly affect displayed data. addresses Memory area overlap those other Memory areas, switching between areas achieved setting Bank Pointer correct value. Structure Special Purpose General Purpose Data Memory located consecutive locations. implemented bits wide length each memory section dictated type microcontroller chosen. start address Data Memory devices address 00H. Registers which common microcontrollers, such ACC, PCL, etc., have same Data Memory address. Data Memory mapped into Bank Data Memory, however, only lower four bits used. higher four bits, read program will return zero value. start Data Memory devices address 40H. However, since Data Memory located Bank access this area Bank Pointer must first value 01H. Note that after power-on contents Data Memory, including
Data Memory Structure Note: Most Data Memory bits directly manipulated using with exception dedicated bits. Data Memory also accessed through memory pointer registers
Rev. 1.00
2008
HT49RA1/HT49CA1
Data Memory, will unknown condition, programmer must therefore ensure that Data Memory properly initialised. General Purpose Data Memory microcontroller programs require area read/write memory where temporary data stored retrieved later. this area memory that known General Purpose Data Memory. This area Data Memory fully accessible user program both read write operations. using instructions individual bits reset under program control giving user large range flexibility manipulation Data Memory. General Purpose Data Memory exists Bank necessary first ensure that Bank Pointer correct value before accessing General Purpose Data Memory. When Bank Pointer value 01H, Memory will accessed. Bank 1must addressed indirectly using Memory Pointer indirect addressing register IAR1. direct addressing indirect addressing using IAR0 will always result data from Bank being accessed. Special Purpose Data Memory This area Data Memory where registers, necessary correct operation microcontroller,
stored. Most registers both readable writable some protected readable only, details which located under relevant Special Function Register section. Note that locations that unused, read instruction these addresses will return value Memory data displayed also stored area fully accessible Data Memory. writing this area RAM, display output directly controlled application program. Memory exists Bank have addresses which into Bank Data Memory, necessary first ensure that Bank Pointer value before accessing Memory. Memory only accessed indirectly using Memory Pointer indirect addressing register IAR1. When Bank Pointer Bank access Data Memory.
Special Function Registers
ensure successful operation microcontroller, certain internal registers implemented Data Memory area. These registers ensure correct operation internal functions such timers, interrupts, etc., well external functions such data control. location these registers within Data Memory begins address unused Data Memory locations between these special function registers point where General Purpose Memory begins reserved future expansion purposes, attempting read data from these locations will return value Indirect Addressing Register IAR0, IAR1 IAR0 IAR1 registers, located Data Memory addresses physically implemented. These special function registers allows what known indirect addressing, which permits data manipulation using Memory Pointers instead usual direct memory addressing method where actual memory address defined. actions IAR0 IAR1 registers will result corresponding read/write operations memory locations specified Memory Pointers MP1. Reading IAR0 IAR1 registers indirectly will return result writing register indirectly will result operation.
Special Purpose Data Memory
Rev. 1.00
2008
HT49RA1/HT49CA1
Memory Pointers MP0, Memory Pointers, known provided. These Memory Pointers physically implemented Data Memory manipulated same normal registers providing convenient with which address track data. When operation relevant Indirect Addressing Registers carried out, actual address that microcontroller directed address specified related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, used access data from Bank0, while IAR1 used access data from Bank0 Bank1. following example shows clear section four locations already defined locations adres1 adres4. data .section adres1 adres2 adres3 adres4 block code .section start: loop: a,04h block,a a,offset adres1 mp0,a IAR0 block loop setup size block Accumulator loaded with first address setup memory pointer with first address clear data address defined increment memory pointer check last memory location been cleared
continue: important point note here that example shown above, reference made specific addresses. Bank Pointer Data Memory area should noted that both Memory other Data Memory share same addresses. Therefore when using instructions access Memory General Purpose Data Memory, necessary ensure that correct area selected. General Purpose located Bank while Memory located Bank Selecting correct Data Memory area achieved using Bank Pointer. data Bank accessed then should cleared zero, while Memory accessed, which located Bank then should loaded with value 01H. must noted that data Bank 1can only accessed indirectly using Memory Pointer IAR1 indirect addressing register. direct addressing indirect addressing using IAR0 will always result data from Bank being accessed. Data Memory Bank Pointer initialised Bank after reset, except time-out reset Power Down Mode, which case, Data Memory Bank Pointer remains unchanged.
should noted that Special Function Data Memory affected bank selection, which means that Special Function Registers accessed from within either Bank Bank Accumulator Accumulator central operation closely related with operations carried ALU. Accumulator place where intermediate results from stored. Without Accumulator would necessary write result each calculation logical operation such addition, subtraction, shift, etc., Data Memory resulting higher programming timing overheads. Data transfer operations usually involve temporary storage function Accumulator; example, when transferring data between user defined register another, necessary this passing data through Accumulator direct transfer between registers permitted.
Bank Pointer Register
Rev. 1.00
2008
HT49RA1/HT49CA1
Program Counter Register provide additional program control functions, byte Program Counter made accessible programmers locating within Special Purpose area Data Memory. manipulating this register, direct jumps other program locations easily implemented. Loading value directly into this register will cause jump specified Program Memory location, however, register only 8-bit wide, only jumps within current Program Memory page permitted. When such operations used, note that dummy cycle will inserted. Look-up Table Registers TBLP, TBLH These special function registers used control operation look-up table which stored Program Memory. TBLP table pointer indicates location where table data located. value must setup before table read commands executed. value changed, example using instructions, allowing easy table data pointing reading. TBLH location where high order byte table data stored after table read data instruction been executed. Note that lower order table data byte transferred user defined location. Status Register STATUS This 8-bit register contains zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). These arithmetic/logical operation system management flags used record status operation microcontroller. With exception flags, bits status register altered instructions like most other registers. data written into status register will change flag. addition, operations related status register give different results different instruction operations. flag affected only system power-up, time-out executing instruction. flag affected only executing
instruction during system power-up. flags generally reflect status latest operations.
operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition, borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logical operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out.
addition, entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status registers important subroutine corrupt status register, precautions must taken correctly save Real Time Clock Control Register RTCC RTCC register controls internal functions which Real Time Clock (RTC) interrupt, whose function provide internal interrupt signal regular fixed intervals. driving clock interrupt comes from internal clock source, known which then further divided give longer time values, which turn generates interrupt signal. value this division ratio determined value programmed into bits 2~0, known RT2~RT0, RTCC register. writing value directly into these
ilia
Status Register
Rev. 1.00
2008
HT49RA1/HT49CA1
8/fS 9/fS 10/fS 11/fS 12/fS 13/fS 14/fS 15/fS
illa
RTCC Register
RTCC register bits, time-out values from 28/fS 215/fS generated. RTCC register also controls quick start function oscillator. This oscillator, which fixed frequency 32768Hz, made start quicker rate setting known QOSC This will value when device powered however, some extra power consumed, QOSC should after about seconds reduce power consumption. Interrupt Control Register INTC0, INTC1 These 8-bit registers, known INTC0 INTC1, control operation both external internal interrupts. setting various bits within these registers using standard manipulation instructions, enable/disable function external interrupts each internal interrupts independently controlled. master interrupt within these registers, bit, acts like global enable/disable used
interrupt enable bits off. This cleared when interrupt routine entered disable further interrupt executing instruction. LCDC Register LCDC LCDC register used control register panel. LCDEN overall on/off control driver used power down driver thus used conserve power when used. four segment lines also pin-shared with four Port lines, bits SEGPT0~SEGPT3 LCDC register used determine which function chosen, either segment line normal line. This register also contains control on/off enable. on/off control however also dependent upon which clock chosen internal clock source. accompanying table shows overall control operation.
LCDEN RTCEN decide On/Off condition normal operation. Clock Source fSYS/4 (WDT enable) (WDT disable) LCD/RTC Control Bits LCDEN, RTCEN=0, off, off, off, off, LCDEN, RTCEN=0, off, off, off, off, LCDEN, RTCEN=1, LCDEN, RTCEN=1,
Rev. 1.00
2008
HT49RA1/HT49CA1
Timer/Event Counter Registers TMR0, TMR0C, TMR1H, TMR1L, TMR1C devices possess single internal 8-bit count-up timer. associated register known TMR0 location where 8-bit value located. This register also preloaded with fixed data allow different time intervals setup. associated control register, known TMR0C, contains setup information this timer, which determines what mode timer used well containing timer on/off control function. devices possess single internal 16-bit count-up timer. associated register known TMR1H, TMR1L location where 16-bit value located. This register also preloaded with fixed data allow different time intervals setup. associated control register, known TMR1C, contains setup information this timer, which determines what mode timer used well containing timer on/off control function. Input/Output Ports Control Registers Within area Special Function Registers, registers their associated control registers play prominent role. ports have designated register correspondingly labeled These labeled registers mapped specific addresses within Data Memory shown Data Memory table, which used transfer appropriate output input data that port. flexible feature these registers ability directly program single bits using instructions. port also control register known PCC, ability change from output input vice versa manipulating register. Port Port input Port known Port These ports mapped Data Memory with specific addresses shown Special Purpose Data Memory table. Port Port ports used both input output operations, however, must noted that unlike Port they have port control registers. Setting port input achieved first setting output high which effectively places NMOS output transistor high impedance state allowing used input. input operation, these ports non-latching, which means inputs must ready rising edge instruction where denotes port address. output operation, data latched remains unchanged until output latch rewritten. Pull-high Resistors Many product applications require pull-high resistors their switch inputs usually requiring external resistor. eliminate need these external resistors, pins Port Port Port have permanently connected pull high resistor. pull high resistor Port chosen configuration option. These pull-high resistors implemented using weak PMOS transistor. Port Wake-up device HALT instruction enabling microcontroller enter Power Down Mode preserve power, feature that important battery other low-power applications. Various methods exist wake-up microcontroller, which change logic condition Port pins from high low. After instruction forces microcontroller into entering HALT condition, processor will remain idle low-power state until logic condition selected wake-up Port changes from high low. This function especially suitable applications that woken external switches. Note that each Port selected individually have this wake-up feature.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility their ports. Although Port remains fixed input only port, pins Port Port Port have ability function either input output. device provides bidirectional input/output lines input lines. Ports known Port
Input/Output Ports
Input Port
Rev. 1.00
2008
HT49RA1/HT49CA1
Input/Output Port Port Control Registers register used control input/output configuration port With this control register, this single CMOS output input with without pull-high resistor structures reconfigured dynamically under software control. Port port directly mapped associated port control register. function input, corresponding control register must written This will then allow logic state input directly read instructions. When corresponding control register written will setup CMOS output. currently setup output, instructions still used read output register. However, should noted that program will fact only read status output data latch actual logic status output pin. Pin-shared Functions flexibility microcontroller range greatly enhanced pins that have more than function. Limited numbers pins force serious design constraints designers supplying pins with multi-functions, many these difficulties overcome. some pins, chosen function multi-function pins configuration options while others function application program control.
External Interrupt Input External Timer Clock Input
external timer TMR0 TMR1 pin-shared with PB3. configure operate timer input, corresponding control bits timer control register must correctly set. applications that require external timer input, used normal pin. Note that used normal timer mode control bits timer control register must select timer mode, which internal clock source, prevent input from interfering with timer operation. Structures following diagrams illustrate internal structures. exact logical construction differ from these drawings, they supplied guide only assist with functional understanding pins. Programming Considerations Within application program, first things consider port initialization. After reset,the port registers will high. important note that NMOS types, when high output NMOS transistor will placed into high impedance condition, allowing used also input. generation high level NMOS outputs therefore reliant upon externally connected circuitry pull-high resistor.
external interrupt INT0 INT1 pin-shared with PB1. applications requiring external interrupt input, pin-shared external interrupt used normal pin, however this, external interrupt enable bits INTC0 register must disabled. Rev. 1.00
Read/Write Timing
2008
HT49RA1/HT49CA1
When using output, logic level setup loading byte wide data into appropriate port register programming individual bits these registers, using instructions. Note that when using these control instructions, read-modify-write operation takes place. microcontroller must first read data entire port, modify required values then rewrite this data back output ports. However, case NMOS type pins, there some special considerations that must noted. case NMOS that high microcontroller, i.e. placed into high impedance condition, driven externally connected circuitry, this would read being condition during read phase [m].i instructions. When ensuing write phase occurs, this pin, having been read being condition during read phase, would then consequently erroneously low. this reason great care must taken when using these control instructions with NMOS output types. Port additional capability providing wake-up functions. When device Power Down Mode, various methods available wake device these high transition Port pins. Single multiple pins Port setup have this function. required, which vary both amplitude time, drive such custom display require many special considerations proper operation occur. This device includes internal signal generating circuitry various configuration options, which will automatically generate these time amplitude varying signals provide means direct driving easy interfacing range custom LCDs. Memory device provides specific area Data Memory data. This data area known Memory. data written here will automatically read internal driver circuits, which will turn automatically generate necessary driving signals. Therefore data written into Memory will immediately reflected into actual display connected microcontroller. start address Memory 40H, address Memory 60H. Data Memory addresses overlap those General Purpose Data Memory, Data Memory stored memory data bank, which different from that General Purpose Data Memory. Data Memory stored Bank Data Memory Bank chosen using Bank Pointer, which special function register Data Memory, with name, When lowest Bank Pointer have binary value only General Purpose Data Memory will accessed, read write actions Memory will take place. access Memory therefore requires first that Bank selected setting lowest Bank Pointer
illa
Liquid Crystal Display (LCD) Driver
large volume applications, which incorporate their design, custom display rather than more expensive character based display reduces costs significantly. However, corresponding signals
Control Register LCDC Rev. 1.00 2008
HT49RA1/HT49CA1
binary value After this, Memory then accessed using indirect addressing through Memory Pointer MP1. With Bank selected, then using read write memory area, 40H~60H, depending upon which device chosen, will result operations Memory. Directly addressing Memory applicable will result data access Bank General Purpose Data Memory. accompanying diagrams show Memory format pixel drive capability. 4-COM format will automatically setup duty configuration option selected while 3-COM format will automatically setup duty configuration option selected. Control Register LCDC device contains single register known LCDC, which used control some internal driver functions. LCDEN overall on/off control driver used power down driver thus used conserve power when used. four segment lines also pin-shared with four Port lines, bits SEGPT0~SEGPT3 LCDC register used determine which function chosen, either segment line normal line. Clock clock driven internal clock source which originate from either oscillator, oscillator fSYS/4, choice which determined configuration option. proper operation, this internal clock source then passes through
Memory
divider, provide clock source frequency near possible 4kHz. Clock Source Oscillator Oscillator fSYS/4
Clock Selection WDT/22 RTC/23
Clock Frequency Selection available division ratios, however, depends clock source that used internal clock source, clock source originates from oscillator, then only fixed division ratio fS/22 available. clock source originates from oscillator, then only division ratio fS/23 available. However, clock source originates from fSYS/4, then range clock frequencies available from fS/22 fS/28, value which selected further available configuration option. These ratios ensure that proper operation, signal frequency near possible 4kHz, selected. clock frequency 4kHz, microcontroller driver circuitry will generate frame frequency between 55Hz 62Hz. This line with general operating frequency range which lies between 25Hz 250Hz. Note that selected clock frequency high, this will result higher than required frame frequency give rise higher power consumption while selecting frequency result flicker. therefore important that fSYS/4 used clock source correct configuration option should chosen obtain clock frequency close 4kHz possible.
Rev. 1.00
2008
HT49RA1/HT49CA1
Driver Output number outputs supplied driver, well biasing duty options, dependent upon configuration options selected. accompanying table lists various options each devices. Duty Driver Number Bias Bias Type type type type voltage minus voltage applied pin. This differential voltage must greater than saturation voltage pixel less than threshold voltage pixel off. requirement limit voltage zero control many pixels possible with minimum number connections, requires that both time amplitude signal generated applied application LCD. These time amplitude varying signals automatically generated driver circuits microcontroller. What known duty determines number common lines used, which also known backplanes COMs. duty, which chosen configuration option have value 1/2, which equates number respectively, therefore defines number time divisions within each signal frame. accompanying timing diagrams depict signals generated microcontroller various values duty bias.
Driver Outputs, Duty Bias Options nature Liquid Crystal Displays require that only voltages applied their pixels application voltages pixels will cause permanent damage. this reason relative contrast display controlled actual voltage applied each pixel, which equal value
Driver Output (1/2 Duty, Bias) Note Bias, VA=VLCD function optioned during Power Down Mode configuration option.
Rev. 1.00
2008
HT49RA1/HT49CA1
Driver Output (1/3 Duty, Bias) Note: Bias, VA=VLCD function optioned during Power Down Mode configuration option.
Rev. 1.00
2008
HT49RA1/HT49CA1
itte
Driver Output (1/4 Duty, Bias) Note: bias VB=VLCD function optioned during Power Down Mode configuration option.
Rev. 1.00
2008
HT49RA1/HT49CA1
Driver Output (1/3 Duty, Bias) Note: bias VB=VLCD function optioned during Power Down Mode configuration option.
Rev. 1.00
2008
HT49RA1/HT49CA1
Voltage Source Biasing time amplitude varying signals generated microcontroller require generation several voltage levels their operation. number voltage levels used signal depends upon device chosen bias configuration options. Biasing device configuration option select either bias. bias configuration option, three voltage levels VSS, utilised. generated internally microcontroller will have value equal VLCD/2. bias option, four voltage levels VSS, utilised. external voltage source also provided VLCD generate these voltages. type bias option uses charge pump circuit, higher voltages than what provided externally VLCD generated. This feature useful applications where microcontroller supply voltage less than supply voltage required LCD. driver type bias, charge-pump capacitor between pins filter capacitors pins required generate necessary voltage levels. Programming Considerations Certain precautions must taken when programming LCD. these ensure that memory properly initialized after microcontroller powered Like General Purpose Data Memory, contents memory unknown condition after power-on. contents memory will mapped into actual LCD, important initialize this memory area into known condition soon after applying power obtain proper display pattern. Consideration must also given capacitive load actual used application. load presented microcontroller pixels generally modeled mainly capacitive nature, important that this excessive, point that particularly true case lines which connected many pixels. accompanying diagram depicts equivalent circuit LCD.
Panel Equivalent Circuit Setting correct frequency clock another factor which must taken into account user applications. have LCDs operate their best frame frequency, which normally between 25Hz 250Hz, important select appropriate clock frequency configuration option. correct option should chosen ensure that clock frequency close 4kHz possible achieved. With such frequency chosen, microcontroller internal driver circuits will ensure that appropriate driving signals generated obtain suitable frame frequency. Note that driver will consume certain amount power disabled using LCDEN LCDC register. battery applications where power consumption important consideration prolong battery life, this should used power down circuitry conserve power.
Type Bias Voltage Levels
Rev. 1.00
2008
HT49RA1/HT49CA1
Timer/Event Counters
provision timers form important part microcontroller, giving designer means carrying time related functions. devices contain 8-bit 16-bit count-up timers. each timer three different operating modes, they configured operate general timer, external event counter pulse width measurement device. There types registers related Timer/Event Counters. first register that contains actual value timer into which initial value preloaded. Reading from this register retrieves contents Timer/Event Counter. second type associated register Timer Control Register which defines timer options determines timer used. devices have timer clock configured come from internal clock source. addition, timer clock source also configured come from external timer pin. Configuring Timer/Event Counter Input Clock Source internal clock originate from various sources, depending upon which timer chosen. system clock input timer source used when timer timer mode pulse width measurement mode. external clock source used when timer event counting mode, clock source being provided external timer TMR0 TMR1, depending upon which timer used. Depending upon condition bit, each high low, high transition external timer will increment counter one. Timer Registers TMR0, TMR1H, TMR1L timer registers special function registers located Special Purpose Data Memory place where actual timer value stored. These registers known TMR0, TMR1H TMR1L, depending upon which device used. value timer registers increases each time internal clock pulse received external transition occurs external timer pin. timer will count from initial value loaded preload register full count FFFFH which point timer overflows internal interrupt signal generated. timer value will then reset with initial preload register value continue counting. Note that achieve maximum full range count FFFFH, preload register must first cleared zeros. should noted that after power-on, preload registers will unknown condition. Note that Timer/Event Counters condition data written their preload registers, this data will immediately written into actual counter. However, counter enabled counting, data written into preload data registers during this period will remain preload registers will only written into actual counter next time overflow occurs.
Timer/Event Counter Structure
Timer/Event Counter Structure Rev. 1.00 2008
HT49RA1/HT49CA1
16-bit Timer/Event Counter which both byte high byte timer registers, accessing these registers carried specific way. must noted when using instructions preload data into byte timer register, namely TMR1L, data will only placed byte buffer directly into byte timer register. actual transfer data into byte timer register only carried when write associated high byte timer register, namely TMR1H, executed. other hand, using instructions preload data into high byte timer register will result data being directly written high byte timer register. same time data byte buffer will transferred into associated byte timer register. this reason, byte timer register should written first when preloading data into 16-bit timer registers. must also noted that read contents byte timer register, read high byte timer register must executed first latch contents byte timer register into associated byte buffer. After this been done, byte timer register read normal way. Note that reading byte timer register will result reading previously latched contents byte buffer actual contents byte timer register. Timer Control Registers TMR0C, TMR1C flexible features Holtek microcontroller Timer/Event Counters enable them operate three different modes, options which determined contents their respective control register. Timer Control Register together with corresponding timer registers that control full operation Timer/Event Counters. Before timers used, essential that appropriate Timer Control Register fully programmed with right data ensure correct operation, process that normally carried during program initialisation. choose which three modes timer operate either timer mode, event counting mode pulse width measurement mode, bits Timer Control Register, which known pair T0M1/T0M0 T1M1/T1M0 respectively, depending upon which timer used, must required logic levels. timer-on bit, which Timer Control Register known T0ON T1ON, depending upon which timer used, provides basic on/off control respective timer. Setting high allows counter run, clearing stops counter. timer event count pulse width measurement mode, active transition edge level type selected logic level Timer Control Register which known depending upon which timer used. Configuring Timer Mode this mode, timer utilized measure fixed time intervals, providing internal interrupt signal each time counter overflows. operate this mode, pair, T0M1/T0M0 T1M1/T1M0 depending upon which timer used, must respectively. this mode internal clock used timer clock. timer-on bit, T0ON T1ON, depending upon which timer used, must high enable timer run. Each time internal clock high transition occurs, timer increments one; when timer full overflows, interrupt signal generated timer will preload value already loaded into preload register continue counting. timer overflow condition corresponding internal interrupt wake-up sources, however, internal interrupts disabled ensuring that ET0I ET1I bits INTC0, INTC1 register reset zero. Configuring Event Counter Mode this mode, number externally changing logic events, occurring external timer pin, recorded internal timer. timer operate event counting mode, pair, T0M1/T0M0 T1M1/T1M0 depending upon which timer used, must respectively. timer-on T0ON T1ON depending upon which timer used, must high enable timer count. Depending upon which counter used, low, counter will increment each time external timer receives
Timer Mode Timing Chart
Event Counter Mode Timing Chart Rev. 1.00 2008
HT49RA1/HT49CA1
high transition. high, counter will increment each time external timer receives high transition. case other modes, when counter full, timer will overflow generate internal interrupt signal. counter will then preload value already loaded into preload register. external timer pins pin-shared with other pins, ensure that configured operate event counter input pin, things have happen. first ensure that T0M1/T0M0 T1M1/T1M0 bits place Timer/Event Counter event counting mode, second ensure that port control register configures input. should noted that timer overflow interrupt wake-up sources. Note that timer interrupts disabled ensuring that ET0I ET1I bits INTC0 INTC1 register reset zero.
llin llin llin
Timer/Event Counter Control Register TMR0C
llin llin llin
Timer/Event Counter Control Register TMR1C
Rev. 1.00
2008
HT49RA1/HT49CA1
Configuring Pulse Width Measurement Mode this mode, width external pulses applied external timer measured. Pulse Width Measurement Mode timer clock source supplied internal clock. timer operate this mode, pair, T0M1/T0M0 T1M1/T1M0, depending upon which timer used, must both high. Depending upon which counter used, T1Ebit low, once high transition been received external timer pin, timer will start counting until external timer returns original high level. this point T0ON T1ON bit, depending upon which counter used, will automatically reset zero timer will stop counting. high, timer will begin counting once high transition been received external timer stop counting when external timer returns original level. before, T0ON T1ON, will automatically reset zero timer will stop counting. important note that Pulse Width Measurement Mode, T0ON T1ON automatically reset zero when external control signal external timer returns original level, whereas other modes T0ON T1ON only reset zero under program control. residual value timer, which read program, therefore represents length pulse received external timer pin. T0ON T1ON been reset, further transitions external timer pin, will ignored. until T0ON T1ON again high program timer begin further pulse width measurements. this way, single shot pulse measurements easily made. should noted that this mode counter controlled logical transitions external timer logic level. case other modes, when counter full, timer will overflow generate internal interrupt signal. counter will also reset value already loaded into preload register. external timer pin-shared with other pins, ensure that configured operate pulse width measuring input pin, things have happen. first ensure that T0M1/T0M0 T1M1/T1M0 bits place Timer/Event Counter pulse width measuring mode, second
ensure that port control register configures input. should noted that timer overflow corresponding timer interrupt wake-up sources. Note that timer interrupts disabled ensuring that ET0I ET1I bits INTC0 INTC1 register reset zero. Interfacing Timer/Event Counter, when configured event counter pulse width measurement mode, require external correct operation. this shared must configured correctly ensure setup Timer/Event Counter input normal pin. This implemented ensuring that mode select bits Timer/Event Counter control register, select either event counter pulse width measurement mode. Additionally Port Control Register must high ensure that setup input. pull-high resistor this will remain valid even used Timer/Event Counter input. Programming Considerations When configured timer mode, internal system clock used timer clock source therefore synchronised with overall operation microcontroller. this mode when appropriate timer register full, microcontroller will generate internal interrupt signal directing program flow respective internal interrupt vector. pulse width measurement mode, internal system clock also used timer clock source timer will only when correct logic condition appears external timer input pin. this external event synchronized with internal timer clock, microcontroller will only this external event when next timer clock pulse arrives. result, there small differences measured values requiring programmers take this into account during programming. same applies timer configured event counting mode, which again external event synchronised with internal system timer clock.
llin
Pulse Width Measure Mode Timing Chart Rev. 1.00 2008
HT49RA1/HT49CA1
When Timer/Event Counter read, data written preload register, clock inhibited avoid errors, however this result counting error, this should taken into account programmer. Care must taken ensure that timers properly initialised before using them first time. associated timer enable bits interrupt control register must properly otherwise internal interrupt associated with timer will remain inactive. edge select, timer mode clock source control bits timer control register must also correctly ensure timer properly configured required application. also important ensure that initial value first loaded into timer registers before timer switched this because after power-on initial values timer registers unknown. After timer been initialised timer turned controlling enable timer control register. Note that setting timer enable high turn timer should only executed after timer mode bits have been properly setup. Setting timer enable high together with mode modification, lead improper timer operation executed single timer control register byte write instruction. When Timer/Event counter overflows, corresponding interrupt request flag interrupt control register will set. timer interrupt enabled this will turn generate interrupt signal. However irrespective whether interrupts enabled not, Timer/Event counter overflow will also generate wake-up signal device Power-down condition. This situation occur Timer/Event Counter Event Counting Mode external signal continues change state. such case, Timer/Event Counter will continue count these external events overflow occurs device will woken from Power-down condition. prevent such wake-up from occurring, timer interrupt request flag should first high before issuing HALT instruction enter Power Down Mode. Timer Program Example This program example shows Timer/Event Counter registers setup, along with interrupts enabled managed. Note Timer/Event Counter turned setting Timer Control Register. Timer/Event Counter turned similar clearing same bit. This example program sets Timer/Event Counter timer mode, which uses internal system clock clock source.
external interrupt vector reti Timer/Event Counter interrupt vector tmrint jump here when Timer overflows main program ;internal Timer/Event Counter interrupt routine tmrint: Timer/Event Counter main program placed here reti begin: ;setup Timer registers a,09bh setup Timer preload value tmr0,a; a,080h setup Timer control register tmr0c,a timer mode setup interrupt register a,009h enable master interrupt timer interrupt int0c,a tmr0c.4 start Timer/Event Counter note mode bits must previously setup
Rev. 1.00
2008
HT49RA1/HT49CA1
Carrier Generator
Some remote control transmitter applications require carrier frequency generator transmit remote control signal appropriate frequency receiving device. These devices include internal carrier frequency generator this purpose, frequency which specified selecting correct configuration options. This carrier signal supplied pin, which also pin-shared with PC0. selection required function, whether remote output CMOS output, implemented selecting required configuration option. remote output selected configuration option, output will activated data register high. This output data used on/off control output. Note that output will output data zero. However, line configured output will switch high level remain until application program resets zero. therefore important note that, devices, configured output pin, transistor connected this output drive infrared LED, will turned during this power-on reset period. general purpose remote controller applications, therefore recommended that configuration option selected together with external transistor drive infrared LED. clock source Carrier Generator supplied system clock divided selecting values using configuration options association with following equation required carrier frequency generated. Carrier Frequency Clock Source mx2n
value either while value range from both values chosen selecting required configuration options. equal duty cycle output waveform will always equal 1/2. equal with exception being equal duty cycle either 1/3, actual value which determined configuration options. Duty Cycle
following table shows examples different carrier frequencies: fSYS 455kHz 56.9kHz only fCARRIER 37.92kHz Duty only
Carrier Signal Generation
Rev. 1.00
2008
HT49RA1/HT49CA1
Interrupts
Interrupts important part microcontroller system. When external event internal function such Timer/Event Counter, Time Base Interrupt requires microcontroller attention, their corresponding interrupt will enforce temporary suspension main program allowing microcontroller direct attention their respective needs. device contains external interrupts four internal interrupt functions. external interrupt controlled action external INT0, INT1 pin, while internal interrupts controlled Timer/Event Counter overflows, Time Base interrupt interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling request flag setting, controlled INTC0 INTC1 registers, which located Data Memory. controlling appropriate enable bits these register each individual interrupt enabled disabled. Also when interrupt occurs, corresponding request flag will microcontroller. global enable flag cleared zero will disable interrupts. Interrupt Operation Timer/Event Counter overflow, Time Base overflow external interrupt line being triggered will generate interrupt request setting their corresponding request flag, their appropriate interrupt enable set. When this happens, Program Counter, which stores address next instruction executed, will transferred onto stack. Program Counter will then loaded with address which will value corresponding interrupt vector. microcontroller will then fetch next instruction from this interrupt vector. instruction this vector will usually statement which will jump another section program which known interrupt service routine. Here located code control appropriate interrupt. interrupt service routine must terminated with RETI statement, which retrieves original Program Counter address from stack allows microcontroller continue with normal execution point where interrupt occurred. various interrupt enable bits, together with their associated request flags, shown accompanying diagram with their order priority. Once interrupt subroutine serviced, other interrupts will blocked, will cleared automatically. This will prevent further interrupt nesting from occurring. However, other interrupt requests occur during this interval, although interrupt will immediately serviced, request flag will still recorded. interrupt requires immediate servicing while program already another interrupt service routine, should after entering routine, allow interrupt nesting. stack full, interrupt request will acknowledged, even related interrupt enabled, until Stack Pointer decremented. immediate service desired, stack must prevented from becoming full. Interrupt Priority Interrupts, occurring interval between rising edges consecutive pulses, will serviced latter pulses, corresponding interrupts enabled. case simultaneous requests, following table shows priority that applied. These masked resetting bit. Interrupt Source External Interrupt Timer/Event Counter Overflow Time Base Interrupt Real Time Clock Interrupt External Interrupt external interrupt occur, global interrupt enable bit, EMI, external interrupt enable bit, EEI0, EEI1, must first set. Additionally correct interrupt edge must selected enable external interrupt function choose trigger edge type. actual external interrupt will take place when external interrupt request flag, EIF0 EIF1, set, situation that will occur when transition, whose type chosen configuration option appears INT0 and, INT1 pins. external interrupt pins pin-shared with pins only configured external interrupt corresponding external interrupt enable INTC0 register have been set. pins must also setup inputs. When interrupt enabled, stack full correct transition type appears external interrupt pin, subroutine call relevant external interrupt vectors locations 08H, will take place. When interrupt serviced, external interrupt request flag, EIF0, EIF1, will automatically reset will automatically cleared disable other interrupts. Priority
Rev. 1.00
2008
HT49RA1/HT49CA1
itte
Interrupt Control Register INTC0
Interrupt Control Register INTC1
Rev. 1.00
2008
HT49RA1/HT49CA1
Timer/Event Counter Interrupt Timer/Event Counter interrupt occur, global interrupt enable bit, EMI, corresponding timer interrupt enable bit, ET0I, ET1I must first set. actual Timer/Event Counter interrupt will take place when relevant Timer/Event Counter request flag, T0F, set, situation that will occur when relevant Timer/Event Counter overflows. When interrupt enabled, stack full Timer/Event Counter overflow occurs, subroutine call timer interrupt vector location 0CH, 10H, will take place. When interrupt serviced, timer interrupt request flag, T0F, will automatically reset will automatically cleared disable other interrupts. Time Base Interrupt Time Base interrupt occur global interrupt enable bit, EMI, corresponding internal interrupt enable bit, which INTC1 register, known ETBI, must first set. actual Time Base interrupt will generated when Time Base interrupt request flag which INTC1 register known TBF. This will occur when when time-out signal generated from Time Base. When master interrupt global enable set, stack full corresponding Time Base interrupt enable set, internal Time Base interrupt will generated when time-out signal generated from Time Base. This will create subroutine call location 014H. When Time Base interrupt occurs, will cleared disable other interrupts. purpose Time Base interrupt provide interrupt signal fixed time periods. Time Base interrupt clock source originates from internal clock source This input clock first passes through divider, division ratio which selected configuration options provide longer Time Base interrupt periods. Time Base interrupt time-out period ranges from 212/fS~215/fS. clock source that generates which turn controls Time Base interrupt period, originate from three different sources, oscillator, Watchdog Timer oscillator System oscillator/4, choice which determine clock source configuration option. Real Time Clock Interrupt Real Time Clock interrupt occur global interrupt enable bit, EMI, corresponding internal interrupt enable bit, which INTC1 register, known ERTI, must first set. actual Real Time Clock interrupt will generated when Real Time Clock interrupt request flag which INTC1 register known RTF. When master interrupt global enable set, stack full corresponding Real Time Clock interrupt enable set, internal Real Time Clock interrupt will generated when time-out signal occurs, subroutine call location 018H will created. When Real Time interrupt occurs, will cleared disable other interrupts. Similar operation Time Base interrupt, purpose interrupt also provide interrupt signal fixed time periods. interrupt clock source originates from internal clock source This input clock first passes through divider, division ratio which selected programming appropriate bits RTCC register obtain longer interrupt periods whose value ranges from 28/fS~215/fS. clock source that generates which turn controls interrupt period, originate from three different sources, oscillator, Watchdog Timer oscillator System oscillator/4, choice which determine clock source configuration option. Note that oscillator selected system clock, then correspondingly interrupt, will also have oscillator clock source.
illa illa
12/fS 15/fS
Time Base Interrupt
illa illa
8/fS 15/fS
Interrupt Rev. 1.00 2008
HT49RA1/HT49CA1
llin
Interrupt Structure
Note that interrupt period controlled both configuration options internal register RTCC. configuration option selects source clock internal clock RTCC register bits RT2, select division ratio. Note that actual division ratio programmed from 215. details actual interrupt periods, consult RTCC register section. Note after wake-up system requires 1024 clock cycles resume normal operation. Programming Considerations disabling interrupt enable bits, requested interrupt prevented from being serviced, however, once interrupt request flag set, will remain this condition INTC0, INTC1 registers until corresponding interrupt serviced until request flag cleared software instruction.
recommended that programs instruction within interrupt subroutine. Interrupts often occur unpredictable manner need serviced immediately some applications. only stack left interrupt well controlled, original control sequence will damaged once executed interrupt subroutine. these interrupts have capability waking processor when Power Down Mode. Only Program Counter pushed onto stack. contents register status register altered interrupt service program, which corrupt desired control sequence, then contents should saved advance.
Rev. 1.00
2008
HT49RA1/HT49CA1
Reset Initialisation
reset function fundamental part microcontroller ensuring that device some predetermined condition irrespective outside parameters. most important reset condition after power first applied microcontroller. this case, internal circuitry will ensure that microcontroller, after short delay, will well defined state ready execute first program instruction. After this power-on reset, certain important internal registers will defined states before program commences. these registers Program Counter, which will reset zero forcing microcontroller begin program execution from lowest Program Memory address. addition power-on reset, situations arise where necessary forcefully apply reset condition when microcontroller running. example this where after power been applied microcontroller already running, line forcefully pulled low. such case, known normal operation reset, some microcontroller registers remain unchanged allowing microcontroller proceed with normal operation after reset line allowed return high. Another type reset when Watchdog Timer overflows resets microcontroller. types reset operations result different register conditions being setup. Another reset exists form Voltage Reset, LVR, where full reset, similar reset implemented situations where power supply voltage falls below certain threshold. Reset Functions There five ways which microcontroller reset occur, through events occurring both internally externally:
Power-on Reset
pin, whose additional time delay will ensure that remains extended period allow power supply stabilise. During this time delay, normal operation microcontroller will inhibited. After line reaches certain voltage value, reset delay time tRSTD invoked provide extra delay time after which microcontroller will begin normal operation. abbreviation figures stands System Start-up Timer.
Power-On Reset Timing Chart most applications resistor connected between capacitor connected between will provide suitable external reset circuit. wiring connected should kept short possible minimise stray noise interference.
Basic Reset Circuit applications that operate within environment where more noise present Enhanced Reset Circuit shown recommended.
most fundamental unavoidable reset that occurs after power first applied microcontroller. well ensuring that Program Memory begins execution from first memory address, power-on reset also ensures that certain other registers preset known conditions. port port control registers will power high condition ensuring that pins will first inputs. Although microcontroller internal reset function, power supply rise time fast enough does stabilise quickly power-on, internal reset function incapable providing proper reset operation. this reason recommended that external network connected
Enhanced Reset Circuit More information regarding external reset circuits located Application Note HA0075E Holtek website.
Rev. 1.00
2008
HT49RA1/HT49CA1
Reset Watchdog Time-out Reset during Power Down
This type reset occurs when microcontroller already running forcefully pulled external hardware such external switch. this case case other reset, Program Counter will reset zero program execution initiated from this point.
Watchdog time-out Reset during Power Down little different from other kinds reset. Most conditions remain unchanged except that Program Counter Stack Pointer will cleared flag will Refer A.C. Characteristics tSST details.
Time-out Reset during Power Down Timing Chart Reset Timing Chart Reset Initial Conditions
Voltage Reset
microcontroller contains voltage reset circuit order monitor supply voltage device, which selected configuration option. supply voltage device drops within range 0.9V~VLVR such might occur when changing battery, will automatically reset device internally. includes following specifications: valid signal, voltage, i.e., voltage range between 0.9V~VLVR must exist greater than value tLVR specified A.C. characteristics. voltage state does exceed 1ms, will ignore will perform reset function.
different types reset described affect reset flags different ways. These flags, known located status register controlled various microcontroller operations, such Power Down function Watchdog Timer. reset flags shown table: RESET Conditions reset during power-on reset during normal operation time-out reset during normal operation time-out reset during Power Down
Note: stands unchanged following table indicates which various components microcontroller affected after power-on reset occurs. Item Condition After RESET Reset zero interrupts will disabled Clear after reset, begins counting Timer Counter will turned Timer Counter Prescaler will cleared
Voltage Reset Timing Chart
Watchdog Time-out Reset during Normal Operation
Program Counter Interrupts Timer/Event Counter Prescaler
Watchdog time-out Reset during normal operation same hardware reset except that Watchdog time-out flag will
Time-out Reset during Normal Operation Timing Chart
Input/Output Ports ports will setup inputs Stack Pointer Stack Pointer will point stack
Rev. 1.00
2008
HT49RA1/HT49CA1
different kinds resets affect internal registers microcontroller different ways. ensure reliable continuation normal program execution after reset occurs, important know what condition microcontroller after particular reset occurs. following table describes each type reset affects each microcontroller internal registers. Note that where more than package type exists table will reflect situation larger package type. Register TBLP TBLH RTCC STATUS INTC0 TMR0 TMR0C TMR1H TMR1L TMR1C INTC1 LCDC Reset (Power-on) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx 0111 xxxx -000 0000 xxxx xxxx 0000 1-xxxx xxxx xxxx xxxx 0000 1-1111 1111 1111 1111 1111 Reset uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu 0111 uuuu -000 0000 xxxx xxxx 0000 1-xxxx xxxx xxxx xxxx 0000 1-1111 1111 1111 1111 1111 Time-out (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu 0111 uuuu -000 0000 xxxx xxxx 0000 1-xxxx xxxx xxxx xxxx 0000 1-1111 1111 1111 1111 1111 Time-out (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu u-uuuu uuuu uuuu uuuu uuuu u-uuuu uuuu uuuu uuuu uuuu
-000 -000 0000
-000 -000 0000
-000 -000 0000
-uuu -uuu 0000
stands unchanged stands unknown stands unimplemented
Rev. 1.00
2008
HT49RA1/HT49CA1
Oscillator
methods generating system clock are:
External oscillator
More information regarding oscillator located Application Note HA0075E Holtek website. External Oscillator oscillator used, external resistor between OSC1 required whose value should 12kW frequency 4MHz. oscillator provides accuracy, conditions are:
VDD=2.0V~3.6V Temp.= 50°C fSYS=4MHz
OSC4 pins, should connected 32768Hz crystal implement this internal oscillator. However, some crystals, ensure oscillation accurate frequency generation, necessary small value external capacitors, exact values should selected consultation with crystal resonator specification. external parallel feedback resistor, normally required some cases needed assist with oscillation start
Internal Typical Values 25°C
Oscillator Internal Component Values Oscillator Values Crystal Frequency 32768Hz
Oscillator External Oscillator When microcontroller enters Power Down Mode, system clock switched stop microcontroller activity conserve power. However, many microcontroller applications necessary keep internal timers operational even when microcontroller Power Down Mode. this, another clock, independent system clock, must provided. this configuration option exists Real Time Clock oscillator. Here OSC3
Note:
values guidance only. crystal manufacturer specified load capacitor value.
32768 Crystal Recommended Capacitor Values
External Oscillator
Rev. 1.00
2008
HT49RA1/HT49CA1
During power there time delay associated with oscillator waiting start RTCC register, known QOSC bit, provided give quick start-up function used minimise this delay. During power condition, this will cleared which will initiate oscillator quick start-up function. However, there additional power consumption associated with this quick start-up function, reduce power consumption after start takes place, recommended that application program should QOSC high about seconds after power should noted that, matter what condition QOSC oscillator will always function normally, only there more power consumption associated with quick start-up function. Watchdog Timer Oscillator oscillator fully integrated free running oscillator with typical period 90ms requiring external components. selected configuration option. selected, when device enters Power Down Mode, system clock will stop running, however oscillator will continue keep watchdog function active. However, will consume certain amount power when Power Down Mode, power applications, desirable disable oscillator configuration option.
will cleared resume counting
clock source selected come from oscillator. will stop clock source originates from system clock.
ports will maintain their present condition. status register, Power Down flag, PDF, will
Watchdog time-out flag, will cleared. Standby Current Considerations main reason entering Power Down Mode keep current consumption value possible, perhaps only order several micro-amps, there other considerations which must also taken into account circuit designer power consumption minimized. Special attention must made pins device. high-impedance input pins must connected either fixed high level floating input pins could create internal oscillations result increased current consumption. This also applies devices which have different package types, there undonbed pins, which must either setup outputs setup inputs must have pull-high resistors connected. Care must also taken with loads, which connected pins, which setup outputs. These should placed condition which minimum current drawn connected only external circuits that draw current, such other CMOS inputs. Also note that additional standby current will also required configuration options have enabled Watchdog Timer internal oscillator. Wake-up After system enters Power Down Mode, woken from various sources listed follows:
external reset external falling edge Port system interrupt overflow
Power Down Mode Wake-up
Power Down Mode Holtek microcontrollers have ability enter Power Down Mode, also known HALT Mode Sleep Mode. When device enters this mode, normal operating current, will reduced extremely standby current level. This occurs because when device enters Power Down Mode, system oscillator stopped which reduces power consumption extremely levels, however, device maintains present internal condition, woken later stage continue running, without requiring full reset. This feature extremely important application areas where must have power supply constantly maintained keep device known condition where power supply capacity limited such battery applications. Entering Power Down Mode There only device enter Power Down Mode that execute instruction application program. When this instruction executed, following will occur:
system oscillator will stop running appli-
cation program will stop instruction.
Data Memory contents registers will maintain
system woken external reset, device will experience full system reset, however, device woken overflow, Watchdog Timer reset will initiated. Although both these wake-up methods will initiate reset operation, actual source wake-up determined examining flags. flag cleared system power-up executing clear Watchdog Timer instructions when executing instruction. flag time-out occurs, causes wake-up that only resets Program Counter Stack Pointer, other flags remain their original status.
their present condition.
Rev. 1.00
2008
HT49RA1/HT49CA1
Each Port setup individual configuration option permit negative transition wake-up system. When Port wake-up occurs, program will resume execution instruction following instruction. system woken interrupt, then possible situations occur. first where related interrupt disabled interrupt enabled stack full, which case program will resume execution instruction following instruction. this situation, interrupt which woke-up device will immediately serviced, will rather serviced later when related interrupt finally enabled when stack level becomes free. other situation where related interrupt enabled stack full, which case regular interrupt response takes place. interrupt request flag before entering Power Down Mode, wake-up function related interrupt will disabled. matter what source wake-up event once wake-up situation occurs, time period equal 1024 system clock periods will required before normal system operation resumes. However, wake-up originated interrupt, actual interrupt subroutine execution will delayed additional more cycles. wake-up results execution next instruction following instruction, this will executed immediately after 1024 system clock period delay ended. Remote Type with series microcontrollers, Watchdog Timer options, such enable/disable, clock source clear instruction type selected through configuration options. There internal registers associated with Remote Type with series. clock sources internal oscillator which approximate period 90ms supply voltage However, should noted that this specified internal clock period vary with VDD, temperature process variations. other clock source option fSYS/4 clock. Whether clock source internal oscillator, from fSYS/4, further divided internal 15-bit counter clearable single counter give longer Watchdog time-outs. this ratio fixed gives overall Watchdog Timer time-out value 215/fS 216/fS. clear instruction only resets last stage divider chain, this reason actual division ratio corresponding Watchdog Timer time-out vary factor two. exact division ratio depends upon residual value Watchdog Timer counter before clear instruction executed. important realise that there independent internal registers configuration options associated with length Watchdog Timer time-out, completely dependent upon frequency fSYS/4, internal oscillator oscillator. fSYS/4 clock used clock source, should noted that when system enters Power Down Mode, then instruction clock stopped will lose protecting purposes. systems that operate noisy environments, using internal oscillator strongly recommended. Under normal program operation, time-out will initialise device reset status However, system Power Down Mode, when time-out occurs, status register will only Program Counter Stack Pointer will reset. Three methods adopted clear contents WDT. first external hardware reset, which means level pin, second using watchdog software instructions third instruction.
Watchdog Timer
Watchdog Timer provided prevent program malfunctions sequences from jumping unknown locations, certain uncontrollable external events such electrical noise. operates providing device reset when counter overflows. clock supplied three sources selected configuration option: self contained dedicated internal oscillator, oscillator fSYS/4. Note that configuration option been disabled, then instruction relating operation will result operation.
illa illa
Watchdog Timer
Rev. 1.00
2008
HT49RA1/HT49CA1
There methods using software instructions clear Watchdog Timer, which must chosen configuration option. first option single instruction while second commands first option, simple execution will clear while second option, both must both executed successfully clear WDT. Note that this second option, used clear WDT, successive executions this instruction will have effect, only execution instruction will clear WDT. Similarly after instruction been executed, only successive instruction clear Watchdog Timer.
Configuration Options
Configuration options refer certain options within that programmed into device during programming process. During development process, these options selected using HT-IDE software development tools. these options programmed into device using hardware programming tools, once they selected they cannot changed later application software control over configuration options. options must defined proper system function, details which shown table. Item Options PB0~PB7: wake-up enable disable (bit option) PC0: CMOS output carrier output (bit option) PC0: Pull-high enable disable (bit option) Options
Options clock: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28 duty: 1/2, 1/3, bias: 1/2, segment 12~15 output CMOS output(Nibble Option) segment 16~19 output CMOS output(Nibble Option)
Interrupt Options INT0 function: enable disable Triggering edge: rising, falling both INT1 function: enable disable Triggering edge: rising, falling both
Oscillator Options internal clock source: oscillator, oscillator fSYS/4
Timer Options Timer/Event Counter clock source: fSYS fSYS/4 Time Base division ratio: fS/212, fS/213, fS/214, fS/215
Time Base Options
Watchdog Options enable disable CLRWDT instructions: instructions
Rev. 1.00
2008
HT49RA1/HT49CA1
Item LVD/LVR Options function: enable disable function: enable disable LVR/LVD voltage: 2.1V/2.2V 3.15V/3.3V Options
Carrier Options Carrier duty: duty duty Carrier frequency: fSYS/8, fSYS/16, fSYS/32, fSYS/64 duty cycle Carrier frequency: fSYS/12, duty cycle Carrier frequency: fSYS/24, fSYS/48, fSYS/96 duty duty cycle
Application Circuits
illa
Rev. 1.00
2008
HT49RA1/HT49CA1
Instruction
Introduction Central successful operation microcontroller instruction set, which program instruction codes that directs microcontroller perform certain operations. case Holtek microcontrollers, comprehensive flexible over instructions provided enable programmers implement their application with minimum programming overheads. easier understanding various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions implemented within instruction cycle. exceptions this branch, call, table read instructions where instruction cycles required. instruction cycle equal system clock cycles, therefore case 8MHz system oscillator, most instructions would implemented within 0.5ms branch call instructions would implemented within 1ms. Although instructions which require more cycle implement generally limited JMP, CALL, RET, RETI table read instructions, important realize that other instructions which involve manipulation Program Counter register will also take more cycle implement. instructions which change contents will imply direct jump that address, more cycle will required. Examples such instructions would PCL, case skip instructions, must noted that result comparison involves skip operation then this will also take more cycle, skip involved then only cycle required. Moving Transferring Data transfer data within microcontroller program most frequently used operations. Making three kinds instructions, data transferred from registers Accumulator vice-versa well being able move specific immediate data directly into Accumulator. most important data transfer applications receive data from input ports transfer data output ports. Arithmetic Operations ability perform certain arithmetic operations data manipulation necessary feature most microcontroller applications. Within Holtek microcontroller instruction range subtract instruction mnemonics enable necessary arithmetic carried out. Care must taken ensure correct handling carry borrow data when results exceed addition less than subtraction. increment decrement instructions INC, INCA, DECA provide simple means increasing decreasing value values destination specified. Logical Rotate Operations standard logical operations such AND, have their instruction within Holtek microcontroller instruction set. with case most instructions involving data manipulation, data must pass through Accumulator which involve additional programming steps. logical data operations, zero flag result operation zero. Another form logical data manipulation comes from rotate instructions such which provide simple means rotating right left. Different rotate instructions exist depending program requirements. Rotate instructions useful serial port programming applications where data rotated from internal register into Carry from where examined necessary serial high low. Another application where rotate data operations used implement multiplication division calculations. Branches Control Transfer Program branching takes form either jumps specified locations using instruction subroutine using CALL instruction. They differ sense that case subroutine call, program must return instruction immediately when subroutine been carried out. This done placing return instruction subroutine which will cause program jump back address right after CALL instruction. case instruction, program simply jumps desired location. There requirement jump back original jumping point case CALL instruction. special extremely useful branch instructions conditional branches. Here decision first made regarding condition certain data memory individual bits. Depending upon conditions, program will continue with next instruction skip over jump following instruction. These instructions decision making branching within program perhaps determined condition certain input switches condition internal data bits.
Rev. 1.00
2008
HT49RA1/HT49CA1
Operations ability provide single operations Data Memory extremely flexible feature Holtek microcontrollers. This feature especially useful output port programming where individual bits port pins directly high using either instructions respectively. feature removes need programmers first read 8-bit output port, manipulate input data ensure that other bits changed then output port with correct data. This read-modify-write process taken care automatically when these operation instructions used. Table Read Operations Data storage normally implemented using registers. However, when working with large amounts fixed data, volume involved often makes inconvenient store fixed data Data Memory. overcome this problem, Holtek microcontrollers allow area Program Memory setup table where data directly stored. easy instructions provides means which this fixed data referenced retrieved from Program Memory. Other Operations addition above functional instructions, range other instructions also exist such instruction Power-down operations instructions control operation Watchdog Timer reliable program operations under extreme electric electromagnetic environments. their relevant operations, refer functional related sections. Instruction Summary following table depicts summary instruction categorised according function consulted basic instruction reference using following listed conventions. Table conventions: Bits immediate data Data Memory address Accumulator number bits addr: Program memory address
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m]
Description
Cycles
Flag Affected
Data Memory Data Memory immediate data Data Memory with Carry Data memory with Carry Subtract immediate data from Subtract Data Memory from Subtract Data Memory from with result Data Memory Subtract Data Memory from with Carry Subtract Data Memory from with Carry, result Data Memory Decimal adjust Addition with result Data Memory
1Note 1Note 1Note 1Note 1Note
Logic Operation A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical immediate Data Logical immediate Data Logical immediate Data Complement Data Memory Complement Data Memory with result 1Note 1Note 1Note 1Note
Increment Decrement INCA DECA Increment Data Memory with result Increment Data Memory Decrement Data Memory with result Decrement Data Memory 1Note 1Note
Rev. 1.00
2008
HT49RA1/HT49CA1
Mnemonic Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT Note: operation Clear Data Memory Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles Data Memory Swap nibbles Data Memory with result Enter power down mode 1Note 1Note 1Note None None None None None Read table (current page) TBLH Data Memory Read table (last page) TBLH Data Memory 2Note 2Note None None Jump unconditionally Skip Data Memory zero Skip Data Memory zero with data movement Skip Data Memory zero Skip Data Memory zero Skip increment Data Memory zero Skip decrement Data Memory zero Skip increment Data Memory zero with result Skip decrement Data Memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note None None None None None None None None None None None None None Clear Data Memory Data Memory 1Note 1Note None None Move Data Memory Move Data Memory Move immediate data 1Note None None None Rotate Data Memory right with result Rotate Data Memory right Rotate Data Memory right through Carry with result Rotate Data Memory right through Carry Rotate Data Memory left with result Rotate Data Memory left Rotate Data Memory left through Carry with result Rotate Data Memory left through Carry 1Note 1Note 1Note 1Note None None None None Description Cycles Flag Affected
skip instructions, result comparison involves skip then cycles required, skip takes place only cycle required. instruction which changes contents will also require cycles execution. instructions flags affected execution status. flags cleared after both instructions consecutively executed. Otherwise flags remain unchanged.
Rev. 1.00
2008
HT49RA1/HT49CA1
Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored Accumulator. Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored specified Data Memory. Data Memory contents specified Data Memory Accumulator added. result stored Accumulator. immediate data contents Accumulator specified immediate data added. result stored Accumulator. Data Memory contents specified Data Memory Accumulator added. result stored specified Data Memory. Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. 2008
HT49RA1/HT49CA1
CALL addr Description Subroutine call Unconditionally calls subroutine specified address. Program Counter then increments obtain address next instruction which then pushed onto stack. specified address then loaded program continues execution from this address. this instruction requires additional operation, cycle instruction. Stack Program Counter Program Counter addr None Clear Data Memory Each specified Data Memory cleared None Clear Data Memory specified Data Memory cleared [m].i None Clear Watchdog Timer flags cleared. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT2 must executed alternately with WDT2 have effect. Repetitively executing this instruction without alternately executing WDT2 will have effect. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT1 must executed alternately with WDT1 have effect. Repetitively executing this instruction without alternately executing WDT1 will have effect. cleared
Operation
Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description Operation
Affected flag(s) WDT1 Description
Operation
Affected flag(s) WDT2 Description
Operation
Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
Description Operation Affected flag(s) CPLA Description Complement Data Memory Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. Complement Data Memory with result Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. complemented result stored Accumulator contents Data Memory remain unchanged. Decimal-Adjust addition with result Data Memory Convert contents Accumulator value Binary Coded Decimal) value resulting from previous addition variables. nibble greater than flag set, then value will added nibble. Otherwise nibble remains unchanged. high nibble greater than flag set, then value will added high nibble. Essentially, decimal conversion performed adding 00H, 06H, depending Accumulator flag conditions. Only flag affected this instruction which indicates that original greater than 100, allows multiple precision decimal addition. Decrement Data Memory Data specified Data Memory decremented Decrement Data Memory with result Data specified Data Memory decremented result stored Accumulator. contents Data Memory remain unchanged. Enter power down mode This instruction stops program execution turns system clock. contents Data Memory registers retained. prescaler cleared. power down flag time-out flag cleared.
Operation Affected flag(s) Description
Operation
Affected flag(s) Description Operation Affected flag(s) DECA Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Increment Data Memory Data specified Data Memory incremented Increment Data Memory with result Data specified Data Memory incremented result stored Accumulator. contents Data Memory remain unchanged. Jump unconditionally contents Program Counter replaced with specified address. Program execution then continues from this address. this requires insertion dummy instruction while address loaded, cycle instruction. Program Counter addr None Move Data Memory contents specified Data Memory copied Accumulator. None Move immediate data immediate data specified loaded into Accumulator. None Move Data Memory contents Accumulator copied specified Data Memory. None operation operation performed. Execution continues with next instruction. operation None Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator.
Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Description Operation Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Return from subroutine Program Counter restored from stack. Program execution continues restored address. Program Counter Stack None Return from subroutine load immediate data Program Counter restored from stack Accumulator loaded with specified immediate data. Program execution continues restored address. Program Counter Stack None Return from interrupt Program Counter restored from stack interrupts re-enabled setting bit. master interrupt global enable bit. interrupt pending when RETI instruction executed, pending Interrupt routine will processed before returning main program. Program Counter Stack None Rotate Data Memory left contents specified Data Memory rotated left with rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 None Rotate Data Memory left with result contents specified Data Memory rotated left with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) Description Operation
Affected flag(s) Description
Operation
Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
Description Operation Rotate Data Memory left through Carry contents specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 Rotate Data Memory left through Carry with result Data specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 Rotate Data Memory right contents specified Data Memory rotated right with rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 None Rotate Data Memory right with result Data specified Data Memory carry flag rotated right with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry contents specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 Rotate Data Memory right through Carry with result Data specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0
Affected flag(s) RLCA Description
Operation
Affected flag(s) Description Operation
Affected flag(s) Description
Operation
Affected flag(s) Description Operation
Affected flag(s) RRCA Description
Operation
Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
A,[m] Description Subtract Data Memory from with Carry contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with Carry result Data Memory contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Skip decrement Data Memory contents specified Data Memory first decremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip decrement Data Memory zero with result contents specified Data Memory first decremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Data Memory Each specified Data Memory None Data Memory specified Data Memory [m].i None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s) SDZA Description
Operation
Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
Description Skip increment Data Memory contents specified Data Memory first incremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip increment Data Memory zero with result contents specified Data Memory first incremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Subtract Data Memory from specified Data Memory subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with result Data Memory specified Data Memory subtracted from contents Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract immediate data from immediate data specified code subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will
Operation Affected flag(s) SIZA Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
SWAP Description Operation Affected flag(s) SWAPA Description Operation Swap nibbles Data Memory low-order high-order nibbles specified Data Memory interchanged. [m].3~[m].0 [m].7 [m].4 None Swap nibbles Data Memory with result low-order high-order nibbles specified Data Memory interchanged. result stored Accumulator. contents Data Memory remain unchanged. ACC.3 ACC.0 [m].7 [m].4 ACC.7 ACC.4 [m].3 [m].0 None Skip Data Memory contents specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory with data movement contents specified Data Memory copied Accumulator. value zero, following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Read table (current page) TBLH Data Memory byte program code (current page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None Read table (last page) TBLH Data Memory byte program code (last page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None
Affected flag(s) Description
Operation Affected flag(s) Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) TABRDC Description Operation
Affected flag(s) TABRDL Description Operation
Affected flag(s)
Rev. 1.00
2008
HT49RA1/HT49CA1
A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator.
Rev. 1.00
2008
HT49RA1/HT49CA1
Package Information
52-pin Outline Dimensions
Symbol
Dimensions Min. 17.3 13.9 17.3 13.9 0.73 Nom. Max. 17.5 14.1 17.5 14.1 1.03
Rev. 1.00
2008
HT49RA1/HT49CA1
64-pin LQFP Outline Dimensions
Symbol
Dimensions Min. 0.13 1.35 0.05 0.45 0.09 Nom. Max. 0.23 1.45 0.15 0.7
Other recent searches
uPD16702 - uPD16702 uPD16702 Datasheet
KST50 - KST50 KST50 Datasheet
KST51 - KST51 KST51 Datasheet
KST52 - KST52 KST52 Datasheet
BST50 - BST50 BST50 Datasheet
BST51 - BST51 BST51 Datasheet
BST52 - BST52 BST52 Datasheet
ELT25 - ELT25 ELT25 Datasheet
ECG012 - ECG012 ECG012 Datasheet
DS04-21339-2E - DS04-21339-2E DS04-21339-2E Datasheet
CSD01060A - CSD01060A CSD01060A Datasheet
CSD01060E - CSD01060E CSD01060E Datasheet
AN2082 - AN2082 AN2082 Datasheet
ACTQ964 - ACTQ964 ACTQ964 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
