Tools Information FAQs Application Note HA0075E Reset Oscillator Circu

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Tools Information FAQs Application Note HA0075E Reset Oscillator Circu

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HT49RA0/HT49CA0 Remote Type 8-Bit with
Tools Information FAQs Application Note HA0075E Reset Oscillator Circuits Application Note
Operating voltage: 2.0V~3.6V bidirectional lines input lines external interrupt input 8-bit programmable timer/event counter driver with segments program memory data memory Real Time Clock (RTC) 8-bit prescaler carrier output (1/2 duty) Software LCD, control On-chip 32768Hz crystal oscillator Watchdog Timer HALT function wake-up feature reduce power
consumption
4-level subroutine nesting manipulation instruction 14-bit table read instruction instruction cycle with 4MHz system clock powerful instructions instructions machine cycles voltage reset/detector function 52-pin package
General Description
HT49RA0/HT49CA0 8-bit high performance, RISC architecture microcontroller devices specifically designed multiple control product applications. mask version HT49CA0 fully functionally compatible with version HT49RA0 device. advantages power consumption, flexibility, timer functions, oscillator options, watchdog timer, HALT wake-up functions, well cost, enhance versatility this device suit wide range application possibilities such industrial control, consumer products, particularly suitable products such infrared remote controllers various subsystem controllers.
Rev. 1.40
December 2008
HT49RA0/HT49CA0
Block Diagram
ifte
Assignment
Rev. 1.40
December 2008
HT49RA0/HT49CA0
Description
Name PA0~PA7 PB0/INT0 PB1/INT1 PB2/TMR PB3~PB7 PC0/REM VLCD COM0~COM2 COM3/SEG20 SEG0~SEG11 SEG12~SEG19 OSC1 OSC3 OSC4 1/2, Duty Options Description Bidirectional 8-bit input/output port with pull-high resistors. Each determined NMOS output Schmitt trigger input software instructions. 8-bit Schmitt trigger input port with pull-high resistors. Eash configured wake-up input code option. Pins PB0, pin-shared with INT0, INT1 respectively.
Wake-up
Level Carrier Level carrier output Pull-high CMOS output carrier output code option. Voltage pump power supply VLCD should larger than correct operation i.e. VLCD VDD. COM3/SEG20 segment common output driver panel options. COM0~COM2 output panel plate. driver outputs panel segments.
SEG12~SEG19 driver outputs panel segments. CMOS output SEG12~SEG19 optioned logical outputs. OSC1 connect resistor internal system clock. Real time clock oscillator. OSC3 OSC4 connected 32768Hz crystal oscillator timing purpose. used system clock. capacitor built-in. selected OSC3,OSC4 should left floating. Schmitt trigger reset input, active low. Negative power supply, ground Positive power supply
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Total .150mA Total Power Dissipation .500mW Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C Total.-100mA
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
D.C. Characteristics
Test Conditions Symbol ISTB1 ISTB2 Parameter Operating Voltage Operating Current OSC) Standby Current (*fS=T1) Standby Current (*fS=32.768kHz OSC) Conditions load, fSYS=4MHz load, system HALT, HALT load, system HALT, HALT, type Min. Typ. Max.
Ta=25°C Unit
Rev. 1.40
December 2008
HT49RA0/HT49CA0
Test Conditions Symbol ISTB3 VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 IOL2 IOH2 VLVR VLVD VPOR RPOR Note: Parameter Standby Current (*fS=WDT OSC) Input Voltage Ports, TMR, INT0 INT1 Input High Voltage Ports, TMR, INT0 INT1 Input Voltage (RES) Input High Voltage (RES) Port Sink Current Port Source Current Common Segment Current Common Segment Current Pull-high Resistance Ports Voltage Reset Voltage Voltage Detector Voltage Start Voltage Ensure Power-on Reset Rise Rate Ensure Power-on Reset Conditions load, system HALT HALT, type VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD 0.7VDD 0.9VDD 0.035 -160 0.3VDD 0.4VDD V/ms Min. Typ. Max. Unit
value refer driver section. tSYS=1/fSYS please refer clock option
A.C. Characteristics
Test Conditions Symbol Parameter fSYS fRTCOSC fTIMER System Clock Frequency Timer Frequency (TMR) Conditions 2.0V~3.6V, 4MHz Temp.= 50°C Wake-up from HALT 0.25 4000 32768 1024 4000 Min. Typ. Max.
Ta=25°C Unit
*tSYS
tWDTOSC Watchdog Oscillator Period tRES tLVR tSST tINT Note: External Reset Pulse Width Voltage Width Reset System Start-up Timer Period Interrupt Pulse Width *tSYS=1/fSYS
Rev. 1.40
December 2008
HT49RA0/HT49CA0
Functional Description
Execution Flow system clock derived from oscillator. internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. pipelining scheme causes each instruction effectively execute cycle. instruction changes value program counter, cycles required complete instruction. Program Counter program counter (PC) bits wide controls sequence which instructions stored program executed. contents specify maximum 2048 addresses. After accessing program memory word fetch instruction code, value incremented one. then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call, initial reset, internal interrupt, external interrupt, returning from subroutine, manipulates program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction; otherwise proceed with next instruction. lower byte (PCL) readable writeable register (06H). Moving data into performs short jump. destination within locations.
Execution Flow Program Counter Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter overflow Time Base Interrupt Interrupt Skip Loading Jump, Call Branch Return From Subroutine
Program Counter
Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: bits
Rev. 1.40
December 2008
HT49RA0/HT49CA0
When control transfer takes place, additional dummy cycle required. Program Memory program memory (ROM) used store program instructions which executed. also contains data, table, interrupt entries, organized into 2048 bits which addressed program counter table pointer. Certain locations reserved special usage:
Location 000H Location 014H
Location 014H reserved real time clock interrupt service program. real time clock interrupt occurs, interrupt enabled, stack full, program begins execution location 014H.
Table location
Location 000H reserved program initialization. After chip reset, program always begins execution this location.
Location 004H
Location 004H reserved external interrupt service program. INT0 input activated, interrupt enabled, stack full, program begins execution location 004H.
Location 008H
location used look-up table. instructions (the current page, page=256 words) (the last page) transfer contents lower-order byte specified data memory, contents higher-order byte TBLH (Table Higher-order byte register) (08H). Only destination lower-order byte table well-defined; other bits table word transferred lower portion TBLH, remaining read TBLH read only, table pointer (TBLP) read/write register (07H), indicating table location. Before accessing table, location should placed TBLP. table related instructions require cycles complete operation. These areas function normal depending upon requirements.
itia
Location 008H reserved external interrupt service program also. INT1 input activated, interrupt enabled, stack full, program begins execution location 008H.
Location 00CH
Location 00CH reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Location 010H
Location 010H reserved Time Base interrupt service program. Time Base interrupt occurs, interrupt enabled, stack full, program begins execution location 010H.
Program Memory
Table Location Instruction(s) TABRDC TABRDL
Table Location Note: *10~*0: Table location bits @7~@0: Table pointer bits P10~P8: Current program Counter bits
Rev. 1.40
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HT49RA0/HT49CA0
Stack Register STACK stack register special part memory used save contents program counter. stack organized into levels neither part data part program, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. commencement subroutine call interrupt acknowledgment, contents program counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), contents program counter restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag recorded acknowledgment still inhibited. Once decremented RETI), interrupt serviced. This feature prevents stack overflow, allowing programmer structure easily. Likewise, stack full, subsequently executed, stack overflow occurs first entry lost (only most recent return addresses stored). Data Memory data memory divided into functional group special function registers general purpose data memory Most them read/write, some read only. unused space before reserved future expanded usage reading these locations will return result 00H. general purpose data memory, addressed from 7FH, used data control information under instruction command. areas directly handle arithmetic, logic, increment, decrement, rotate operations. Except some dedicated bits, each reset They also indirectly accessible through Memory pointer register (MP0;01H) Memory pointer register (MP1;03H). Indirect Addressing Register Location indirect addressing registers that physically implemented. read/write operation [00H] [02H] accesses pointed (01H) MP1(03H) respectively. Reading location indirectly returns result 00H. While, writing indirectly leads operation. function data movement between indirect addressing registers supported. memory pointer registers, MP1, both 7-bit registers used access combining corresponding indirect addressing registers. only applied data memory, while applied data memory display memory.
Mapping Accumulator accumulator (ACC) related operations. also mapped location capable operating with immediate data. data movement between data memory locations must pass through ACC. Arithmetic Logic Unit This circuit performs 8-bit arithmetic logic operations provides following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, etc.)
only saves results data operation also changes status register. December 2008
Rev. 1.40
HT49RA0/HT49CA0
Status Register STATUS status register (0AH) bits wide contains, carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). also records status information controls operation sequence. Except flags, bits status register altered instructions similar other registers. Data written into status register does alter flags. Operations related status register, however, yield different results from those intended. flags only changed Watchdog Timer overflow, chip power-up, clearing Watchdog Timer executing instruction. flags reflect status latest operations. entering interrupt sequence executing subroutine call, status register will automatically pushed onto stack. contents status important, subroutine likely corrupt status register, programmer should take precautions save properly. Interrupts devices provides external interrupts, internal timer/event counter interrupts, internal time base interrupt, internal real time clock interrupt. interrupt control register (INTC0;0BH) interrupt control register (INTC1;1EH) both contain interrupt control bits that used enable/disable status interrupt request flags. Once interrupt subroutine serviced, other interrupts blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests take place during this interval, only interrupt request flag will recorded. certain interrupt requires servicing within service routine, corresponding INTC0 INTC1 order allow interrupt nesting. Once stack full, interrupt request will acknowledged, even related interrupt enabled, until Stack Pointer decremented. immediate service desired, stack should prevented from becoming full. these interrupts support wake-up function. interrupt serviced, control transfer occurs pushing contents program counter onto stack followed branch subroutine specified location ROM. Only contents program counter pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. External interrupts triggered high high both transition INT0 INT1, related interrupt request flag (EIF0;bit INTC0, EIF1;bit INTC0) well. After interrupt enabled, stack full, external interrupt active, subroutine call location occurs. interrupt request flag (EIF0 EIF1) bits cleared disable other interrupts.
Label
Function operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logic operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared either system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Status (0AH) Register
Rev. 1.40
December 2008
HT49RA0/HT49CA0
internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (TF;bit INTC0), which normally caused timer overflow. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (TF) reset, cleared disable further interrupts. time base interrupt initialized setting time base interrupt request flag (TBF;bit INTC1), that caused regular time base signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (TBF) reset cleared disable further interrupts. real time clock interrupt initialized setting real time clock interrupt request flag (RTF; INTC1), that caused regular real time clock signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (RTF) reset cleared disable further interrupts. During execution interrupt subroutine, other interrupt acknowledgments held until instruction executed related interrupt control both stack full). return from interrupt subroutine, invoked. RETI sets enables interrupt service, does not. Interrupts occurring interval between rising edges consecutive pulses serviced latter pulses corresponding interrupts enabled. case simultaneous requests, priorities following table apply. These masked resetting bit. Interrupt Source External interrupt External interrupt Timer/Event Counter overflow Time base interrupt Real time clock interrupt Priority Vector
EMI, EEI0, EEI1, ETI, ETBI ERTI used control enable/disable status interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (RTF, TBF, EIF1, EIF0) set, they remain INTC1 INTC0 respectively until interrupts serviced cleared software instruction.
Label EEI0 EEI1 EIF0 EIF1
Function Controls master (global) interrupt (1=enabled; 0=disabled) Controls external interrupt (1=enabled; 0=disabled) Controls external interrupt (1=enabled; 0=disabled) Controls Timer/Event Counter interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter request flag (1=active; 0=inactive) Unused bit, read INTC0 (0BH) Register
Label ETBI ERTI
Function Controls time base interrupt (1=enabled; 0:disabled) Controls real time clock interrupt (1=enabled; 0:disabled) Unused bit, read Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read INTC1 (1EH) Register
Rev. 1.40
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HT49RA0/HT49CA0
recommended that program within interrupt subroutine. because interrupts often occur unpredictable manner require serviced immediately some applications. this time, only stack left, enabling interrupt well controlled, operation interrupt subroutine damage original control sequence. Oscillator Configuration external resistor between OSC1 needed resistance about 12kW. oscillator provides accuracy, conditions are:
VDD=2.0V~3.6V Temp.= 50°C fSYS=4MHz
illa
System Oscillator
LCD/RTC Control Register (1FH) controlling OSC. Label RTCEN LCDEN Function Controls enable (1=enabled; 0=disabled) Controls enable (1=enabled; 0=disabled) Unused bit, read LCDC (1FH) Register LCDEN RTCEN decide On/Off condition normal operation. Clock Source fSYS/4 (WDT enable) (WDT disable) LCD/WDT Control Bits LCDEN, RTCEN=0, off, off, off, off, LCDEN, RTCEN=0, off, off, off, off, LCDEN, RTCEN=1, LCDEN, RTCEN=1,
Rev. 1.40
December 2008
HT49RA0/HT49CA0
Watchdog Timer clock source implemented dedicated oscillator (WDT oscillator) instruction clock (system clock/4) real time clock oscillator (RTC oscillator). timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. disabled option. disabled, executions related lead operation. time-out period fS/216~fS/215. clock source chooses internal oscillator, time-out period vary with temperature, VDD, process variations. other hand, clock source selects instruction clock instruction executed, stop counting lose protecting purpose, logic only restarted external logic. When device operates noisy environment, using on-chip oscillator (WDT OSC) strongly recommended, since HALT stop system clock. overflow under normal operation initializes sets status HALT mode, overflow initializes only program counter stack pointer reset zero. clear contents WDT, there three methods adopted, i.e., external reset level RES), software instruction, instruction. There types software instructions; other these types instruction, only type instruction active time depending options times selection option. selected (i.e., times equal one), execution instruction clears WDT. case that chosen (i.e., times equal two), these instructions have executed clear WDT; otherwise, reset chip time-out. Time Base time base offers periodic time-out period generate regular internal interrupt. time-out period ranges from fS/212 fS/215 selected options. time base time-out occurs, related interrupt request flag
(TBF; INTC1) set. interrupt enabled, stack full, subroutine call location occurs.
Time Base Real Time Clock real time clock (RTC) operated same manner time base that used supply regular internal interrupt. time-out period ranges from fS/28 fS/215 software programming Writing data RT2, (bit2, RTCC;09H) yields various time-out periods. time-out occurs, related interrupt request flag (RTF; INTC1) set. interrupt enabled, stack full, subroutine call location occurs. real time clock time-out signal also applied clock source Timer/Event Counter getting longer time-out period. Clock Divided Factor 210* 211*
Note: recommended used
Real Time Clock
Watchdog Timer Rev. 1.40 December 2008
HT49RA0/HT49CA0
Power Down Operation HALT HALT mode initialized instruction results following.
system oscillator turns
Reset There three ways which reset occur.
reset during normal operation reset during HALT time-out reset during normal operation
keeps running oscillator real time clock selected).
contents on-chip registers
remain unchanged.
cleared start recounting
clock source from oscillator real time clock oscillator).
ports maintain their original status. flag flag cleared.
system quits HALT mode external reset, interrupt, external falling edge signal port overflow. external reset causes device initialization, overflow performs After examining flags, reason chip reset determined. flag cleared system power-up executing instruction, executing instruction. other hand, flag time-out occurs, causes wake-up that only resets program counter Stack Pointer, leaves others their original state. port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake-up device option. Awakening from port stimulus, program resumes execution next instruction. other hand, awakening from interrupt, sequences occur. related interrupt disabled interrupt enabled stack full, program resumes execution next instruction. interrupt enabled, stack full, regular interrupt response takes place. When interrupt request flag before entering status, system cannot awaken using that interrupt. wake-up events occur, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period inserted after wake-up. wake-up results from interrupt acknowledgment, actual interrupt subroutine execution delayed more than cycle. However, Wake-up results next instruction execution, execution will performed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT status. When HALT state fS=fSYS/4, will turned matter value (LCDEN, RTCEN).
time-out during HALT differs from other chip reset conditions, perform that resets only program counter stack pointer leaves other circuits their original state. Some registers remain unaffected during other reset conditions. Most registers reset once reset conditions met. Examining flags, program distinguish between different Note: Make length wiring, which connected short possible, avoid noise interference. RESET Conditions reset during power-up reset during normal operation Wake-up HALT time-out during normal operation Wake-up HALT
Note:
means unchanged
guarantee that system oscillator started stabilized, (System Start-up Timer) provides extra-delay 1024 system clock pulses when system awakes from HALT state. Awaking from HALT state, delay added. extra delay added during power-up period wakeup from HALT enable only delay. functional unit chip reset status shown below. Program Counter Interrupt Prescaler, Divider WDT, RTC, Time base 000H Disabled Cleared Cleared. After master reset, starts counting
Timer/Event Counter Input/output ports Stack Pointer Input mode Points stack
Rev. 1.40
December 2008
HT49RA0/HT49CA0
Reset Timing Chart
Reset Circuit Note: Most applications Basic Reset Circuit shown, however applications with extensive noise, recommended Hi-noise Reset Circuit.
Reset Configuration
states registers summarized below: Register Program Counter TBLP TBLH RTCC STATUS INTC0 TMRC INTC1 LCDC Note: Reset (Power-on) -xxx xxxx -xxx xxxx 0000 0000 xxxx xxxx 000H xxxx xxxx xxxx 0111 xxxx -000 0000 xxxx xxxx 0000 1-1111 1111 1111 1111 refers warm reset means unchanged means unknown means unimplemented Time-out Reset (Normal Operation) (Normal Operation) -uuu uuuu -uuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu uuuu 0111 uuuu -000 0000 xxxx xxxx 0000 1-1111 1111 1111 1111 -uuu uuuu -uuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu uuuu 0111 uuuu -000 0000 xxxx xxxx 0000 1-1111 1111 1111 1111 Reset (HALT) -uuu uuuu -uuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu uuuu 0111 uuuu -000 0000 xxxx xxxx 0000 1-1111 1111 1111 1111 Time-out (HALT)* -uuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu u-uuuu uuuu uuuu uuuu
Rev. 1.40
December 2008
HT49RA0/HT49CA0
Timer/Event Counter timer/event counters implemented devices. contains 8-bit programmable count-up counter. timer/event counter clock source come from system clock system clock/4 time-out signal external source. System clock source system clock/4 selected option. Using external clock input allows user count external events, measure time internals pulse widths, generate accurate time base. While using internal clock allows user generate accurate time base. There registers related timer/event counter, i.e., (0DH) TMRC (0EH). There also physical registers mapped location; writing places starting value timer/event counter preload register, while reading yields contents timer/event counter. TMRC timer/event counter control register used define some options. bits define operation mode. event count mode used count external events, which means that clock source from external (TMR) pin. timer mode functions normal timer with clock source coming from internal selected clock source. Finally, pulse width measurement Label Unused bit, read define active edge timer/event counter (0=active high; 1=active high low) enable/disable timer counting (0=disabled; 1=enabled) multiplexer control inputs select timer/event counter clock source (0=RTC outputs; system clock system clock/4) define operating mode (TM1, TM0) 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMRC (0EH) Register
mode used count high level duration external signal (TMR), counting based internal selected clock source. event count timer mode, timer/event counter starts counting current contents timer/event counter ends FFH. Once overflow occurs, counter reloaded from timer/event counter preload register, generates interrupt request flag (TF;bit INTC0). pulse width measurement mode with values equal one, after received transient from high high will start counting until returns original level resets TON. measured result remains timer/event counter even activated transient occurs again. other words, only cycle measurement made until set. cycle measurement will re-function long receives further transient pulse. this operation mode, timer/event counter begins counting according logic level transient edges. case counter overflows, counter reloaded from timer/event counter preload register issues interrupt request, other modes, i.e., event timer modes.
Function
Timer/Event Counter Rev. 1.40 December 2008
HT49RA0/HT49CA0
enable counting operation, Timer (TON: TMRC) should pulse width measurement mode, automatically cleared after measurement cycle completed. other modes, only reset instructions. overflow timer/event counter wake-up sources. matter what operation mode writing disables related interrupt service. case timer/event counter condition, writing data timer/event counter preload register also reloads that data timer/event counter. timer/event counter turn data written timer/event counter kept only timer/event counter preload register. timer/event counter still continues operation until overflow occurs. When timer/event counter (reading TMR) read, clock blocked avoid errors. this results counting error, blocking clock should taken into account programmer. strongly recommended load desired value into register first, then turn related timer/event counter proper operation. Because initial value unknown. timer/event scheme, programmer should special attention instruction enable then disable timer first time, whenever there need timer/event function, avoid unpredicatable result. After this procedure, timer/event function operated normally. Carrier Generator HT49RA0/HT49CA0 provides carrier output which shares with PC0. selected carrier output (REM) level output (PC0) code option. carrier output option selected, setting enable carrier output setting disable level output. clock source carrier implemented instruction clock (system clock divided processed frequency divider yield various carry frequency. Carry Frequency= Clock Source
where n=0~3, both selected code option. m=2, duty cycle carrier output duty. m=3, duty cycle carrier output duty duty also determined code option (with exception n=0). Detailed selection carrier duty shown below: Duty Cycle
following table shows examples carrier frequency selection. fSYS 455kHz 56.9kHz only fCARRIER 37.92kHz Duty only
Carrier/Level Output
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HT49RA0/HT49CA0
Input/Output Ports There 8-bit bidirectional input/output port, 8-bit input port one-bit input/output port HT49RA0/HT49CA0, labeled which mapped [12H], [14H], [16H] respectively. Each selected NMOS output Schmitt trigger with pull-high resistor software instruction. PB0~PB7 only used input operation (Schmitt trigger with pull-high resistors). only one-bit input/output port shares with carrier output. When input operation, these ports non-latched, that inputs should ready rising edge instruction (m=12H 14H). output operation, data latched remain unchanged until output latch rewritten. When used input operation, should noted that before reading data from pads, should written related bits disable NMOS device. That instruction (i=0~7 executed first disable related NMOS device, then stable data. After chip reset, remain high level input line. Each output latches cleared (m=12H 16H) instructions respectively. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. Each line wake-up capability device code option. highest seven bits physically implemented, reading them returned writing results no-operation.
Input/Output Ports
Input Ports
Rev. 1.40
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HT49RA0/HT49CA0
Input/Output Ports
Display Memory devices provides area embedded data memory display. This area located from Bank Bank pointer (BP; located RAM) switch between display memory. When data written into 40H~54H will effect display. When cleared data written into 40H~54H means access general purpose data memory. display memory read written only indirect addressing mode using MP1. When data written into display data area, automatically read driver which then generates corresponding driving signals. turn display off, written corresponding display memory, respectively. figure illustrates mapping between display memory pattern devices.
Driver Output output number driver device option. bias type driver type only. capacitor mounted between pins needed. bias selected, capacitor mounted between ground required. bias selected, capacitors needed pins. capacitance capacitors used bias generator suggested 0.1mF. relationships between bias types, bias levels connection listed table. Bias Level Bias Type C1/C2 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF VLCD VLCD VLCD
There clock source needed driver. clock source comes from general purpose prescaler decided code options. clock frequency should selected near 4kHz either from 32768 fSYS/4 clock source. options clock frequency listed following table. Clock Source Oscillator Clock Selection WDT/22 RTC/23 fSYS/24~fSYS/210
Oscillator fSYS/4
Display Memory
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Driver Output (1/3 Duty, Bias, Type)
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Driver Output (1/4 Duty, Bias, Type)
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Voltage Reset/Detector Functions There voltage detector (LVD) voltage reset circuit (LVR) implemented microcontroller. These functions enabled/disabled options. Once options enabled, user RTCC.3 enable/disable (1/0) circuit read detector status (0/1) from RTCC.5; otherwise, function disabled. RTCC register definitions listed below. Label RT0~RT2 LVDC* QOSC LVDO Function multiplexer control inputs select real clock prescaler output enable/disable (1/0) 32768Hz quick start-up oscillating 0/1: quickly/slowly start detection output (1/0) voltage detected, read only Unused bit, read RTCC (09H) Register Once function enabled reference generator should enabled; otherwise reference generator controlled code option. relationship among options LVDC shown. LVDC read/write, LVDO read only. Enable Enable Enable Enable Disable Disable Enable Enable Disable Disable Enable Disable LVDC VREF Generator Enable Enable Enable Disable Enable Disable Comparator Enable Enable Disable Disable Enable Disable Comparator Enable Disable Enable Disable Disable Disable
Rev. 1.40
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HT49RA0/HT49CA0
microcontroller provides voltage reset circuit order monitor supply voltage device. supply voltage device within range 0.9V~VLVR, such might happen when changing battery, will automatically reset device internally. During HALT state, disabled. includes following specifications:
voltage (0.9V~VLVR) state must exists
relationship between VLVR shown below.
more than 1ms, while other circuits remain their original state. voltage state does exceed 1ms, will ignore perform reset function.
uses function with power-on
signal perform chip reset.
Note: VOPR voltage range proper chip operation 4MHz system clock.
Voltage Reset Note: make sure that system oscillator stabilized, provides extra delay 1024 system clock pulses before entering normal operation. voltage state maintained over 1ms, then after delay device enters reset mode.
Rev. 1.40
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HT49RA0/HT49CA0
Options following shows options devices. these options should defined order ensure proper system functioning. Item Options PB0~PB7: wake-up enable disable (bit option) PC0: CMOS output carrier output (bit option) PC0: Pull-high enable disable (bit option) Options
Options clock: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28 duty: 1/2, 1/3, bias: 1/2, segment 12~15 output CMOS output(Nibble Option) segment 16~19 output CMOS output(Nibble Option)
Interrupt Options INT0 function: enable disable Triggering edge: rising, falling both INT1 function: enable disable Triggering edge: rising, falling both
Oscillator Options internal clock source: oscillator, oscillator fSYS/4
Timer Options Timer/Event Counter clock source: fSYS fSYS/4 Time Base division ratio: fS/212, fS/213, fS/214, fS/215
Time Base Options
Watchdog Options enable disable CLRWDT instructions: instructions
LVD/LVR Options Voltage Detect: enable disable function: enable disable
Carrier Options Carrier duty: duty duty Carrier frequency: fSYS/8, fSYS/16, fSYS/32, fSYS/64 duty cycle Carrier frequency: fSYS/12, duty cycle Carrier frequency: fSYS/24, fSYS/48, fSYS/96 duty duty cycle
Rev. 1.40
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HT49RA0/HT49CA0
Application Circuits
illa
Note:
Reset circuit reset circuit resistance capacitance values should chosen ensure that stable remains within operating voltage range before reaches high level. Ensure that length wiring connected kept short possible, avoid noise interference. applications where noise interfere with reset circuit details oscillator external components, refer Application Note HA0075E more information.
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Example
Rev. 1.40
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HT49RA0/HT49CA0
Instruction
Introduction Central successful operation microcontroller instruction set, which program instruction codes that directs microcontroller perform certain operations. case Holtek microcontrollers, comprehensive flexible over instructions provided enable programmers implement their application with minimum programming overheads. easier understanding various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions implemented within instruction cycle. exceptions this branch, call, table read instructions where instruction cycles required. instruction cycle equal system clock cycles, therefore case 8MHz system oscillator, most instructions would implemented within 0.5ms branch call instructions would implemented within 1ms. Although instructions which require more cycle implement generally limited JMP, CALL, RET, RETI table read instructions, important realize that other instructions which involve manipulation Program Counter register will also take more cycle implement. instructions which change contents will imply direct jump that address, more cycle will required. Examples such instructions would PCL, case skip instructions, must noted that result comparison involves skip operation then this will also take more cycle, skip involved then only cycle required. Moving Transferring Data transfer data within microcontroller program most frequently used operations. Making three kinds instructions, data transferred from registers Accumulator vice-versa well being able move specific immediate data directly into Accumulator. most important data transfer applications receive data from input ports transfer data output ports. Arithmetic Operations ability perform certain arithmetic operations data manipulation necessary feature most microcontroller applications. Within Holtek microcontroller instruction range subtract instruction mnemonics enable necessary arithmetic carried out. Care must taken ensure correct handling carry borrow data when results exceed addition less than subtraction. increment decrement instructions INC, INCA, DECA provide simple means increasing decreasing value values destination specified. Logical Rotate Operations standard logical operations such AND, have their instruction within Holtek microcontroller instruction set. with case most instructions involving data manipulation, data must pass through Accumulator which involve additional programming steps. logical data operations, zero flag result operation zero. Another form logical data manipulation comes from rotate instructions such which provide simple means rotating right left. Different rotate instructions exist depending program requirements. Rotate instructions useful serial port programming applications where data rotated from internal register into Carry from where examined necessary serial high low. Another application where rotate data operations used implement multiplication division calculations. Branches Control Transfer Program branching takes form either jumps specified locations using instruction subroutine using CALL instruction. They differ sense that case subroutine call, program must return instruction immediately when subroutine been carried out. This done placing return instruction subroutine which will cause program jump back address right after CALL instruction. case instruction, program simply jumps desired location. There requirement jump back original jumping point case CALL instruction. special extremely useful branch instructions conditional branches. Here decision first made regarding condition certain data memory individual bits. Depending upon conditions, program will continue with next instruction skip over jump following instruction. These instructions decision making branching within program perhaps determined condition certain input switches condition internal data bits.
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Operations ability provide single operations Data Memory extremely flexible feature Holtek microcontrollers. This feature especially useful output port programming where individual bits port pins directly high using either instructions respectively. feature removes need programmers first read 8-bit output port, manipulate input data ensure that other bits changed then output port with correct data. This read-modify-write process taken care automatically when these operation instructions used. Table Read Operations Data storage normally implemented using registers. However, when working with large amounts fixed data, volume involved often makes inconvenient store fixed data Data Memory. overcome this problem, Holtek microcontrollers allow area Program Memory setup table where data directly stored. easy instructions provides means which this fixed data referenced retrieved from Program Memory. Other Operations addition above functional instructions, range other instructions also exist such instruction Power-down operations instructions control operation Watchdog Timer reliable program operations under extreme electric electromagnetic environments. their relevant operations, refer functional related sections. Instruction Summary following table depicts summary instruction categorised according function consulted basic instruction reference using following listed conventions. Table conventions: Bits immediate data Data Memory address Accumulator number bits addr: Program memory address
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA INCA DECA
Description Data Memory Data Memory immediate data Data Memory with Carry Data memory with Carry Subtract immediate data from Subtract Data Memory from Subtract Data Memory from with result Data Memory Subtract Data Memory from with Carry Subtract Data Memory from with Carry, result Data Memory Decimal adjust Addition with result Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical immediate Data Logical immediate Data Logical immediate Data Complement Data Memory Complement Data Memory with result Increment Data Memory with result Increment Data Memory Decrement Data Memory with result Decrement Data Memory
Cycles 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note
Flag Affected
Logic Operation
Increment Decrement
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Mnemonic Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT Note: operation Clear Data Memory Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles Data Memory Swap nibbles Data Memory with result Enter power down mode 1Note 1Note 1Note None None None None None Read table (current page) TBLH Data Memory Read table (last page) TBLH Data Memory 2Note 2Note None None Jump unconditionally Skip Data Memory zero Skip Data Memory zero with data movement Skip Data Memory zero Skip Data Memory zero Skip increment Data Memory zero Skip decrement Data Memory zero Skip increment Data Memory zero with result Skip decrement Data Memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note None None None None None None None None None None None None None Clear Data Memory Data Memory 1Note 1Note None None Move Data Memory Move Data Memory Move immediate data 1Note None None None Rotate Data Memory right with result Rotate Data Memory right Rotate Data Memory right through Carry with result Rotate Data Memory right through Carry Rotate Data Memory left with result Rotate Data Memory left Rotate Data Memory left through Carry with result Rotate Data Memory left through Carry 1Note 1Note 1Note 1Note None None None None Description Cycles Flag Affected
skip instructions, result comparison involves skip then cycles required, skip takes place only cycle required. instruction which changes contents will also require cycles execution. instructions flags affected execution status. flags cleared after both instructions consecutively executed. Otherwise flags remain unchanged.
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Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.40 Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored Accumulator. Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored specified Data Memory. Data Memory contents specified Data Memory Accumulator added. result stored Accumulator. immediate data contents Accumulator specified immediate data added. result stored Accumulator. Data Memory contents specified Data Memory Accumulator added. result stored specified Data Memory. Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. December 2008
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CALL addr Description Subroutine call Unconditionally calls subroutine specified address. Program Counter then increments obtain address next instruction which then pushed onto stack. specified address then loaded program continues execution from this address. this instruction requires additional operation, cycle instruction. Stack Program Counter Program Counter addr None Clear Data Memory Each specified Data Memory cleared None Clear Data Memory specified Data Memory cleared [m].i None Clear Watchdog Timer flags cleared. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT2 must executed alternately with WDT2 have effect. Repetitively executing this instruction without alternately executing WDT2 will have effect. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT1 must executed alternately with WDT1 have effect. Repetitively executing this instruction without alternately executing WDT1 will have effect. cleared
Operation
Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description Operation
Affected flag(s) WDT1 Description
Operation
Affected flag(s) WDT2 Description
Operation
Affected flag(s)
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Description Operation Affected flag(s) CPLA Description Complement Data Memory Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. Complement Data Memory with result Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. complemented result stored Accumulator contents Data Memory remain unchanged. Decimal-Adjust addition with result Data Memory Convert contents Accumulator value Binary Coded Decimal) value resulting from previous addition variables. nibble greater than flag set, then value will added nibble. Otherwise nibble remains unchanged. high nibble greater than flag set, then value will added high nibble. Essentially, decimal conversion performed adding 00H, 06H, depending Accumulator flag conditions. Only flag affected this instruction which indicates that original greater than 100, allows multiple precision decimal addition. Decrement Data Memory Data specified Data Memory decremented Decrement Data Memory with result Data specified Data Memory decremented result stored Accumulator. contents Data Memory remain unchanged. Enter power down mode This instruction stops program execution turns system clock. contents Data Memory registers retained. prescaler cleared. power down flag time-out flag cleared.
Operation Affected flag(s) Description
Operation
Affected flag(s) Description Operation Affected flag(s) DECA Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Increment Data Memory Data specified Data Memory incremented Increment Data Memory with result Data specified Data Memory incremented result stored Accumulator. contents Data Memory remain unchanged. Jump unconditionally contents Program Counter replaced with specified address. Program execution then continues from this address. this requires insertion dummy instruction while address loaded, cycle instruction. Program Counter addr None Move Data Memory contents specified Data Memory copied Accumulator. None Move immediate data immediate data specified loaded into Accumulator. None Move Data Memory contents Accumulator copied specified Data Memory. None operation operation performed. Execution continues with next instruction. operation None Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator.
Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s)
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Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Description Operation Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Return from subroutine Program Counter restored from stack. Program execution continues restored address. Program Counter Stack None Return from subroutine load immediate data Program Counter restored from stack Accumulator loaded with specified immediate data. Program execution continues restored address. Program Counter Stack None Return from interrupt Program Counter restored from stack interrupts re-enabled setting bit. master interrupt global enable bit. interrupt pending when RETI instruction executed, pending Interrupt routine will processed before returning main program. Program Counter Stack None Rotate Data Memory left contents specified Data Memory rotated left with rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 None Rotate Data Memory left with result contents specified Data Memory rotated left with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) Description Operation
Affected flag(s) Description
Operation
Affected flag(s)
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Description Operation Rotate Data Memory left through Carry contents specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 Rotate Data Memory left through Carry with result Data specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 Rotate Data Memory right contents specified Data Memory rotated right with rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 None Rotate Data Memory right with result Data specified Data Memory carry flag rotated right with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry contents specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 Rotate Data Memory right through Carry with result Data specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0
Affected flag(s) RLCA Description
Operation
Affected flag(s) Description Operation
Affected flag(s) Description
Operation
Affected flag(s) Description Operation
Affected flag(s) RRCA Description
Operation
Affected flag(s)
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A,[m] Description Subtract Data Memory from with Carry contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with Carry result Data Memory contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Skip decrement Data Memory contents specified Data Memory first decremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip decrement Data Memory zero with result contents specified Data Memory first decremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Data Memory Each specified Data Memory None Data Memory specified Data Memory [m].i None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s) SDZA Description
Operation
Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s)
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Description Skip increment Data Memory contents specified Data Memory first incremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip increment Data Memory zero with result contents specified Data Memory first incremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Subtract Data Memory from specified Data Memory subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with result Data Memory specified Data Memory subtracted from contents Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract immediate data from immediate data specified code subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will
Operation Affected flag(s) SIZA Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s)
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SWAP Description Operation Affected flag(s) SWAPA Description Operation Swap nibbles Data Memory low-order high-order nibbles specified Data Memory interchanged. [m].3~[m].0 [m].7 [m].4 None Swap nibbles Data Memory with result low-order high-order nibbles specified Data Memory interchanged. result stored Accumulator. contents Data Memory remain unchanged. ACC.3 ACC.0 [m].7 [m].4 ACC.7 ACC.4 [m].3 [m].0 None Skip Data Memory contents specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory with data movement contents specified Data Memory copied Accumulator. value zero, following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Read table (current page) TBLH Data Memory byte program code (current page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None Read table (last page) TBLH Data Memory byte program code (last page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None
Affected flag(s) Description
Operation Affected flag(s) Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) TABRDC Description Operation
Affected flag(s) TABRDL Description Operation
Affected flag(s)
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A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator.
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Package Information
52-pin Outline Dimensions
Symbol
Dimensions Min. 17.3 13.9 17.3 13.9 0.73 Nom. Max. 17.5 14.1 17.5 14.1 1.03
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Room, Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) Unit Productivity Building, Gaoxin 2nd, Middle Zone High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright 2008 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
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