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Tools Information FAQs Application Note HA0017E Controlling Read/Write


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HT49R50A-1/HT49C50-1/HT49C50L Type 8-Bit
Tools Information FAQs Application Note HA0017E Controlling Read/Write Function HT24 Series EEPROM Using HT49 Series MCUs HA0024E Using HT49 Series HA0025E Using Time Base HT49 Series HA0026E Using Ports HT49 Series HA0027E Using Timer/Event Counter HT49 Series
Operating voltage: On-chip crystal, 32768Hz crystal oscillator HALT function wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V HT49R50A-1/HT49C50-1 fSYS=8MHz: 3.3V~5.5V HT49R50A-1/HT49C50-1 fSYS=500kHz: 1.2V~2.2V HT49C50L
input lines bidirectional lines external interrupt input 8-bit programmable timer/event counter with
consumption
6-level subroutine nesting manipulation instruction 15-bit table read instruction 0.5ms instruction cycle with 8MHz system clock
(programmable frequency divider) function
driver with segments program memory data memory Real Time Clock (RTC) 8-bit prescaler Watchdog Timer Buzzer output
HT49R50A-1/HT49C50-1
instruction cycle with 500kHz system clock
HT49C50L
powerful instructions instructions machine cycles voltage reset/detector function
HT49R50A-1/HT49C50-1
48-pin SSOP, 100-pin package
General Description
HT49R50A-1/HT49C50-1/HT49C50L 8-bit, high performance, RISC architecture microcontroller devices specifically designed wide range applications. mask version HT49C50-1 HT49C50L fully functionally compatible with version HT49R50A-1 device. HT49C50L voltage version, with ability operate minimum power supply 1.2V, making suitable single cell battery applications. advantages power consumption, flexibility, programmable frequency divider, timer functions, oscillator options, HALT wake-up functions buzzer driver addition flexible configurable interface, enhance versatility these devices control wide range LCD-based application possibilities such measuring scales, electronic multimeters, meters, timers, calculators, remote controllers many other LCD-based industrial home appliance applications.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Block Diagram
ifte
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Assignment
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Description
Name PA0/BZ PA1/BZ PA3/PFD PA4~PA7 PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7 PC0~PC3 Options Description PA0~PA7 constitute 8-bit bidirectional input/output port with Schmitt trigger input capability. Each port configured wake-up input options. PA0~PA3 configured CMOS output NMOS input/outWake-up Pull-high None with without pull-high resistor options. PA4~PA7 always CMOS NMOS pull-high NMOS input/output. eight bits, PA0~PA1 pins buzzer outputs options. output also options. PB0~PB7 constitute 8-bit Schmitt trigger input port. Each port with pull-high resistor. eight bits, input pins external interrupt control pins (INT0) (INT1) respectively, software application. input timer/event counter input TMR0 TMR1 also software application.
PC0~PC3 constitute 4-bit bidirectional input/output port with Schmitt trigPull-high None input capability. port, such configured CMOS output CMOS NMOS NMOS input/output with without pull-high resistor options. 1/2, Duty Voltage pump HT49R50A-1/HT49C50-1. power supply HT49C50L. power supply HT49R50A-1/HT49C50-1. Voltage pump HT49C50L. Voltage pump SEG32 segment common output driver panel options. COM0~COM2 outputs panel plate. driver outputs panel segments OSC1 OSC2 connected network crystal options) internal system clock. case operation, OSC2 output terminal system clock. system clock come from oscillator. system clock comes from RTCOSC, these pins floating. Real time clock oscillators. OSC3 OSC4 connected 32768Hz crystal oscillator timing purposes system clock source (depending options). built-in capacitor Schmitt trigger reset input, active low. Negative power supply, ground Positive power supply
VLCD COM0~COM2 COM3/SEG32 SEG0~SEG31
OSC1 OSC2
Crystal
OSC3 OSC4
System Clock
Absolute Maximum Ratings
Supply Voltage.VSS-0.3V VSS+6.0V* Storage Temperature .-50°C 125°C Operating Temperature .-40°C 85°C Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability. HT49R50A-1/HT49C50-1 HT49C50L Supply Voltage .VSS-0.3V VSS+2.5V** Input Voltage.VSS-0.3V VDD+0.3V
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
D.C. Characteristics
VDD=1.5V HT49C50L, VDD=3V VDD=5V HT49R50A-1 HT49C50-1 Test Conditions Symbol Parameter Conditions HT49C50L Operating Voltage disable, fSYS=4MHz (for HT49R50A-1/HT49C50-1) fSYS=8MHz (for HT49R50A-1/HT49C50-1) VLCD Power Supply (Note HT49R50A-1/HT49C50-1, load load, system HALT, HALT load, system HALT, HALT, type load, system HALT HALT, type load, system HALT, HALT, type, bias load, system HALT, HALT, type, bias load, system HALT, HALT, type, bias load, system HALT, HALT, type, bias 0.3VDD Min. Typ. Max. Unit Ta=25°C
1.5V load, fSYS=455kHz IDD1 Operating Current (Crystal OSC) 1.5V load, fSYS=400kHz IDD2 Operating Current OSC) Operating Current (Crystal OSC, OSC) Operating Current (fSYS=RTC OSC) IDD3 1.5V IDD4 1.5V ISTB1 Standby Current (*fS=T1) 1.5V ISTB2 Standby Current (*fS=RTC OSC) 1.5V ISTB3 Standby Current (*fS=WDT OSC) ISTB4 Standby Current (*fS=RTC OSC) Standby Current (*fS=RTC OSC) Standby Current (*fS=WDT OSC) Standby Current (*fS=WDT OSC) Input Voltage Ports, load, fSYS=8MHz load, fSYS=4MHz load, fSYS=4MHz
ISTB5
ISTB6
ISTB7
VIL1
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Test Conditions Symbol Parameter VIH1 VIL2 VIH2 Input High Voltage Ports, Input Voltage (RES) Input High Voltage (RES) 1.5V IOL1 Port Sink Current 1.5V IOH1 Port Source Current IOL2 Common Segment Current Common Segment Current 1.5V Pull-high Resistance VLVR VLVD Note: Voltage Reset Voltage Voltage Detector Voltage VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD Conditions HT49C50L HT49R50A-1/HT49C50-1 0.8VDD 0.7VDD 0.9VDD -0.3 -180 -0.6 -160 -360 0.4VDD Min. Typ. Max. Unit
IOH2
value refer driver section. please refer clock option
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
A.C. Characteristics
VDD=1.5V HT49C50L, VDD=3V VDD=5V HT49R50A-1 HT49C50-1 Test Conditions Symbol Parameter fSYS1 System Clock (Crystal OSC) fSYS2 System Clock OSC) System Clock (32768Hz Crystal OSC) Frequency fSYS3 fRTCOSC fTIMER Timer Frequency 1.5V tWDTOSC Watchdog Oscillator Period tRES tSST tLVR tINT External Reset Pulse Width System Start-up Timer Period Voltage Width Reset Interrupt Pulse Width HT49C50L HT49R50A-1/HT49C50-1 Wake-up from HALT HT49C50L HT49R50A-1/HT49C50-1 Conditions 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 0.25 32768 32768 1024 4000 8000 4000 8000 4000 8000 *tSYS Min. Typ. Max. Unit Ta=25°C
Note:
*tSYS= 1/fSYS1, 1/fSYS2 1/fSYS3
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Functional Description
Execution Flow system clock derived from either crystal oscillator 32768Hz crystal oscillator. internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. pipelining scheme causes each instruction effectively execute cycle. instruction changes value program counter, cycles required complete instruction. Program Counter program counter (PC) bits wide controls sequence which instructions stored program executed. contents specify maximum 4096 addresses.
After accessing program memory word fetch instruction code, value incremented one. then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call, initial reset, internal interrupt, external interrupt, returning from subroutine, manipulates program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction; otherwise proceed with next instruction. lower byte (PCL) readable writeable register (06H). Moving data into performs short jump. destination within locations.
Execution Flow Program Counter Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter overflow Timer/Event Counter overflow Time Base Interrupt Interrupt Skip Loading Jump, Call Branch Return From Subroutine
Program Counter
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: bits April 2006
Rev. 2.10
HT49R50A-1/HT49C50-1/HT49C50L
When control transfer takes place, additional dummy cycle required. Program Memory program memory (ROM) used store program instructions which executed. also contains data, table, interrupt entries, organized into 4096 bits which addressed program counter table pointer. Certain locations reserved special usage:
Location 000H
itia
Location 000H reserved program initialization. After chip reset, program always begins execution this location.
Location 004H
Location 004H reserved external interrupt service program. INT0 input activated, interrupt enabled, stack full, program begins execution location 004H.
Location 008H
Program Memory
Location 008H reserved external interrupt service program also. INT1 input activated, interrupt enabled, stack full, program begins execution location 008H.
Location 00CH
Location 018H
Location 018H reserved real time clock interrupt service program. real time clock interrupt occurs, interrupt enabled, stack full, program begins execution location 018H.
Table location
Location 00CH reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Location 010H
Location 010H reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 010H.
Location 014H
Location 014H reserved Time Base interrupt service program. Time Base interrupt occurs, interrupt enabled, stack full, program begins execution location 014H.
location used look-up table. instructions (the current page, page=256 words) (the last page) transfer contents lower-order byte specified data memory, contents higher-order byte TBLH (Table Higher-order byte register) (08H). Only destination lower-order byte table well-defined; other bits table word transferred lower portion TBLH, remaining read TBLH read only, table pointer (TBLP) read/write register (07H), indicating table location. Before accessing table, location should placed TBLP. table related instructions require cycles complete operation. These areas function normal depending upon requirements.
Table Location Instruction(s) TABRDC TABRDL
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program Counter bits
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Stack Register STACK stack register special part memory used save contents program counter. stack organized into levels neither part data part program, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. commencement subroutine call interrupt acknowledgment, contents program counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), contents program counter restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag recorded acknowledgment still inhibited. Once decremented RETI), interrupt serviced. This feature prevents stack overflow, allowing programmer structure easily. Likewise, stack full, subsequently executed, stack overflow occurs first entry lost (only most recent return addresses stored). Data Memory data memory (RAM) designed with bits, divided into functional groups, namely special function registers general purpose data memory, most which readable/writeable, although some read only. types functional groups, special function registers consist Indirect addressing register (00H), Memory pointer register (MP0;01H), Indirect addressing register (02H), Memory pointer register (MP1;03H), Bank pointer (BP;04H), Accumulator (ACC;05H), Program counter lower-order byte register (PCL;06H), Table pointer (TBLP;07H), Table higher-order byte register (TBLH;08H), Real time clock control register (RTCC;09H), Status register (STATUS;0AH), Interrupt control register (INTC0;0BH), Timer/Event Counter (TMR0;0DH), Timer/Event Counter control register (TMR0C;0EH), Timer/Event Counter (TMR1;10H), Timer/Event Counter control register (TMR1C;11H), registers (PA;12H, PB;14H, PC;16H), Interrupt control register (INTC1;1EH). other hand, general purpose data memory, addressed from FFH, used data control information under instruction commands. areas directly handle arithmetic, logic, increment, decrement, rotate operations. Except some dedicated bits, Each reset They also indirectly accessible through Memory pointer register (MP0;01H) Memory pointer register (MP1;03H). Rev. 2.10
Mapping Indirect Addressing Register Location indirect addressing registers that physically implemented. read/write operation [00H] [02H] accesses pointed (01H) MP1(03H) respectively. Reading location indirectly returns result 00H. While, writing indirectly leads operation. function data movement between indirect addressing registers supported. memory pointer registers, MP1, both 8-bit registers used access combining corresponding indirect addressing registers. only applied data memory, while applied data memory display memory.
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Accumulator accumulator (ACC) related operations. also mapped location capable operating with immediate data. data movement between data memory locations must pass through ACC. Arithmetic Logic Unit This circuit performs 8-bit arithmetic logic operations provides following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, etc.)
entering interrupt sequence executing subroutine call, status register will automatically pushed onto stack. contents status important, subroutine likely corrupt status register, programmer should take precautions save properly. Interrupts devices provides external interrupts, internal timer/event counter interrupts, internal time base interrupt, internal real time clock interrupt. interrupt control register (INTC0;0BH) interrupt control register (INTC1;1EH) both contain interrupt control bits that used enable/disable status interrupt request flags. Once interrupt subroutine serviced, other interrupts blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests take place during this interval, only interrupt request flag will recorded. certain interrupt requires servicing within service routine, corresponding INTC0 INTC1 order allow interrupt nesting. Once stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack should prevented from becoming full. these interrupts support wake-up function. interrupt serviced, control transfer occurs pushing contents program counter onto stack followed branch subroutine specified location ROM. Only contents program counter pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. Function
only saves results data operation also changes status register. Status Register STATUS status register (0AH) bits wide contains, carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). also records status information controls operation sequence. Except flags, bits status register altered instructions similar other registers. Data written into status register does alter flags. Operations related status register, however, yield different results from those intended. flags only changed Watchdog Timer overflow, chip power-up, clearing Watchdog Timer executing instruction. flags reflect status latest operations.
Label
operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logic operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared either system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Status (0AH) Register
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
External interrupts triggered high transition INT0 INT1, related interrupt request flag (EIF0;bit INTC0, EIF1;bit INTC0) well. After interrupt enabled, stack full, external interrupt active, subroutine call location occurs. interrupt request flag (EIF0 EIF1) bits cleared disable other interrupts. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T0F;bit INTC0), which normally caused timer overflow. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (T0F) reset, cleared disable further interrupts. Timer/Event Counter operated same manner related interrupt request flag (bit INTC1) subroutine call location 10H. time base interrupt initialized setting time base interrupt request flag (TBF;bit INTC1), that caused regular time base signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (TBF) reset cleared disable further interrupts. real time clock interrupt initialized setting real time clock interrupt request flag (RTF; INTC1), that caused regular real time clock signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (RTF) reset cleared disable further interrupts. During execution interrupt subroutine, other interrupt acknowledgments held until instruction executed related interrupt control both stack full). return from interrupt subroutine, invoked. RETI sets enables interrupt service, does not. Interrupts occurring interval between rising edges consecutive pulses serviced latter pulses corresponding interrupts enabled. case simultaneous requests, priorities following table apply. These masked resetting bit. Interrupt Source External interrupt External interrupt Timer/Event Counter overflow Timer/Event Counter overflow Time base interrupt Real time clock interrupt Function Controls master (global) interrupt (1=enabled; 0=disabled) Controls external interrupt (1=enabled; 0=disabled) Controls external interrupt (1=enabled; 0=disabled) Controls Timer/Event Counter interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter request flag (1=active; 0=inactive) Unused bit, read INTC0 (0BH) Register Label ET1I ETBI ERTI Function Controls Timer/Event Counter interrupt (1=enabled; 0=disabled) Controls time base interrupt (1=enabled; 0:disabled) Controls real time clock interrupt (1=enabled; 0:disabled) Unused bit, read Internal Timer/Event Counter request flag (1=active; 0=inactive) Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read INTC1 (1EH) Register Rev. 2.10 April 2006 Priority Vector
Label EEI0 EEI1 ET0I EIF0 EIF1
HT49R50A-1/HT49C50-1/HT49C50L
Timer/Event Counter interrupt request flag (T0F), external interrupt request flag (EIF1), external interrupt request flag (EIF0), enable Timer/Event Counter interrupt (ET0I), enable external interrupt (EEI1), enable external interrupt (EEI0), enable master interrupt (EMI) make Interrupt Control register (INTC0) which located RAM. real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter interrupt request flag (T1F), enable real time clock interrupt (ERTI), enable time base interrupt (ETBI), enable Timer/Event Counter interrupt (ET1I) other hand, constitute Interrupt Control register (INTC1) which located RAM. EMI, EEI0, EEI1, ET0I, ET1I, ETBI, ERTI used control enable/disable status interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) set, they remain INTC1 INTC0 respectively until interrupts serviced cleared software instruction. recommended that program within interrupt subroutine. because interrupts often occur unpredictable manner require serviced immediately some applications. this time, only stack left, enabling interrupt well controlled, operation interrupt subroutine damage original control sequence. Oscillator Configuration These devices provide three oscillator circuits system clocks, i.e., oscillator crystal oscillator, determined option. matter what type oscillator selected, signal used system clock. HALT mode stops system oscillator ignores external signal conserve power. three oscillators, oscillator used, external resistor between OSC1 required, range resistance should from 24kW HT49R50A-1/HT49C50-1 from 560kW HT49C50L. system clock, divided available OSC2 with pull-high resistor, which used synchronize external logic. oscillator provides most cost effective solution. However, frequency oscillation vary with VDD, temperature, chip itself process variations. therefore, suitable timing sensitive operations where accurate oscillator frequency desired. other hand, crystal oscillator selected, crystal across OSC1 OSC2 needed provide feedback phase shift required oscillator, other external components required. resonator connected between OSC1 OSC2 replace crystal frequency reference, external capacitors OSC1 OSC2 required. Rev. 2.10
illa
illa
System Oscillator
32768Hz Crystal/RTC Oscillator There another oscillator circuit designed real time clock. this case, only 32.768kHz crystal oscillator applied. crystal should connected between OSC3 OSC4, external capacitors along with external resistor required oscillator circuit order stable frequency. oscillator circuit controlled oscillate quickly setting (bit RTCC). recommended turn quick oscillating function upon power turn after seconds. oscillator free running on-chip oscillator, external components required. Although system enters power down mode, system clock stops, oscillator still works with period approximately 65ms oscillator disabled option conserve power. Watchdog Timer clock source implemented dedicated oscillator (WDT oscillator) instruction clock (system clock/4) real time clock oscillator (RTC oscillator). timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. disabled option. disabled, executions related lead operation. time-out period fS/216~fS/215. clock source chooses internal oscillator, time-out period vary with temperature, VDD, process variations. other hand, clock source selects instruction clock instruction executed, stop counting lose protecting purpose, logic only restarted external logic.
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Watchdog Timer When device operates noisy environment, using on-chip oscillator (WDT OSC) strongly recommended, since HALT stop system clock. overflow under normal operation initializes sets status HALT mode, overflow initializes only program counter reset zero. clear contents WDT, there three methods adopted, i.e., external reset level RES), software instruction, instruction. There types software instructions; other these types instruction, only type instruction active time depending options times selection option. selected (i.e., times equal one), execution instruction clears WDT. case that chosen (i.e., times equal two), these instructions have executed clear WDT; otherwise, reset chip time-out. Multi-function Timer These devices provide multi-function timer WDT, time base with different time-out periods. multi-function timer consists 7-stage divider 8-bit prescaler, with clock source coming from instruction clock (i.e., system clock divided multi-function timer also provides selectable frequency signal (ranges from fS/22 fS/28) driver circuits, selectable frequency signal (ranges from fS/22 fS/29) buzzer output option. recommended select near 4kHz signal driver circuits proper display. Time Base time base offers periodic time-out period generate regular internal interrupt. time-out period ranges from fS/212 fS/215 selected options. time base time-out occurs, related interrupt request flag (TBF; INTC1) set. interrupt enabled, stack full, subroutine call location occurs. time base time-out signal also applied clock source Timer/Event Counter getting longer timer-out period. Note: recommended used
Time Base Real Time Clock real time clock (RTC) operated same manner time base that used supply regular internal interrupt. time-out period ranges from fS/28 fS/215 software programming Writing data RT2, (bit2, RTCC;09H) yields various time-out periods. time-out occurs, related interrupt request flag (RTF; INTC1) set. interrupt enabled, stack full, subroutine call location occurs. real time clock time-out signal also applied clock source Timer/Event Counter getting longer time-out period. Clock Divided Factor 210* 211*
Real Time Clock
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Power Down Operation HALT HALT mode initialized instruction results following.
system oscillator turns oscillator
Reset There three ways which reset occur.
reset during normal operation reset during HALT time-out reset during normal operation
keeps running oscillator real time clock selected).
contents on-chip registers
remain unchanged.
cleared start recounting
clock source from oscillator real time clock oscillator).
ports maintain their original status. flag flag cleared. driver still running
selected). system quits HALT mode external reset, interrupt, external falling edge signal port overflow. external reset causes device initialization, overflow performs After examining flags, reason chip reset determined. flag cleared system power-up executing instruction, executing instruction. other hand, flag time-out occurs, causes wake-up that only resets program counter leaves others their original state. port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake-up device option. Awakening from port stimulus, program resumes execution next instruction. other hand, awakening from interrupt, sequences occur. related interrupt disabled interrupt enabled stack full, program resumes execution next instruction. interrupt enabled, stack full, regular interrupt response takes place. When interrupt request flag before entering status, system cannot awaken using that interrupt. wake-up events occur, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period inserted after wake-up. wake-up results from interrupt acknowledgment, actual interrupt subroutine execution delayed more than cycle. However, Wake-up results next instruction execution, execution will performed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT status.
time-out during HALT differs from other chip reset conditions, perform that resets only program counter leaves other circuits their original state. Some registers remain unaffected during other reset conditions. Most registers reset once reset conditions met. Examining flags, program distinguish between different Note: Make length wiring, which connected short possible, avoid noise interference. RESET Conditions reset during power-up reset during normal operation Wake-up HALT time-out during normal operation Wake-up HALT
Note:
means unchanged
guarantee that system oscillator started stabilized, (System Start-up Timer) provides extra-delay 1024 system clock pulses when system awakes from HALT state. Awaking from HALT state, delay added. extra delay added during power-up period wakeup from HALT enable only delay. functional unit chip reset status shown below. Program Counter Interrupt Prescaler, Divider WDT, RTC, Time base 000H Disabled Cleared Cleared. After master reset, starts counting
Timer/Event Counter Input/output ports Stack Pointer Input mode Points stack
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
states registers summarized below: Register TMR0 TMR0C TMR1 TMR1C Program Counter TBLP TBLH STATUS INTC0 INTC1 RTCC Note: Reset (Power xxxx xxxx 0000 1-xxxx xxxx 0000 1-000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx -000 0000 -000 -000 0111 1111 1111 xxxx xxxx 1111 refers warm reset means unchanged means unknown Time-out Reset (Normal Operation) (Normal Operation) xxxx xxxx 0000 1-xxxx xxxx 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 -000 -000 0111 1111 1111 xxxx xxxx 1111 xxxx xxxx 0000 1-xxxx xxxx 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 -000 -000 0111 1111 1111 xxxx xxxx 1111 Reset (HALT) xxxx xxxx 0000 1-xxxx xxxx 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 -000 -000 0111 1111 1111 xxxx xxxx 1111 Time-out (HALT)* uuuu uuuu uuuu u-uuuu uuuu uuuu u-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -uuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu
Reset Timing Chart
Reset Circuit
Reset Configuration
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Timer/Event Counter timer/event counters implemented devices. Both them contain 8-bit programmable count-up counter. timer/event counter clock source come from system clock system clock/4 time-out signal external source. System clock source system clock/4 selected option. timer/event counter clock source come from TMR0 overflow system clock time base time-out signal system clock/4 external source, three former clock source selected option. Using external clock input allows user count external events, measure time internals pulse widths, generate accurate time base. While using internal clock allows user generate accurate time base. timer/event counters operated almost same manner, except clock source related registers.
There registers related Timer/Event Counter i.e., TMR0 ([0DH]) TMR0C ([0EH]), registers related Timer/Event Counter i.e., TMR1 ([10H], TMR1C ([11H]). There also physical registers mapped TMR0 (TMR1) location; writing TMR0 (TMR1) places starting value timer/event counter preload register, while reading yields contents timer/event counter. TMR0C TMR1C timer/event counter control registers used define some options. T0M0 T0M1 (T1M0 T1M1) bits define operation mode. event count mode used count external events, which means that clock source from external (TMR0, TMR1) pin. timer mode functions normal timer with clock source coming from internal selected clock source. Finally, pulse width measurement mode used count high level duration external signal (TMR0, TMR1), counting based internal selected clock source.
Timer/Event Counter
Timer/Event Counter
Source Option
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Label Unused bit, read Defines TMR0 active edge timer/event counter: Event Counter Mode (T0M1,T0M0)=(0,1): 1:count falling edge; 0:count rising edge Pulse Width measurement mode (T0M1,T0M0)=(1,1): start counting rising edge, stop falling edge; start counting falling edge, stop rising edge enable/disable timer counting (0=disabled; 1=enabled) multiplexer control inputs select timer/event counter clock source (0=RTC outputs; system clock system clock/4) define operating mode (T0M1, T0M0) 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMR0C (0EH) Register Label Unused bit, read Defines TMR1 active edge timer/event counter: Event Counter Mode (T1M1,T1M0)=(0,1): 1:count falling edge; 0:count rising edge Pulse Width measurement mode (T1M1,T1M0)=(1,1): start counting rising edge, stop falling edge; start counting falling edge, stop rising edge enable/disable timer counting disabled; enabled) multiplexer control inputs select timer/event counter clock source options clock source; system clock/4) define operating mode (T1M1, T1M0) Event count mode (External clock) Timer mode (Internal clock) Pulse Width measurement mode (External clock) Unused TMR1C (11H) Register event count timer mode, timer/event counter starts counting current contents timer/event counter ends FFH. Once overflow occurs, counter reloaded from timer/event counter preload register, generates interrupt request flag (T0F;bit INTC0, T1F;bit INTC1). pulse width measurement mode with values T0ON/T1ON T0E/T1E bits equal one, after TMR0 (TMR1) received transient from high high T0E/T1E will start counting until TMR0 (TMR1) returns original level resets T0ON/T1ON. measured result remains timer/event counter even activated transient occurs again. other words, only cycle measurement made until T0ON/T1ON set. cycle measurement will re-function long receives further transient pulse. this operation mode, timer/event counter begins counting according logic level transient edges. case counter overflows, counter reloaded from timer/event counter preload register issues interrupt request, other modes, i.e., event timer modes. enable counting operation, Timer (T0ON: TMR0C; T1ON: TMR1C) should pulse width measurement mode, T0ON/T1ON automatically cleared after measurement cycle completed. other modes, T0ON/T1ON only reset instructions. Function Function
T0ON
T0M0 T0M1
T1ON
T1M0 T1M1
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
overflow Timer/Event Counter wake-up sources also applied (Programmable Frequency Divider) output option. Only (PFD0 PFD1) applied options. output, there types selections; PFD0 output, other PFD1 output. PFD0, PFD1 timer overflow signals Timer/Event Counter Timer/Event Counter respectively. matter what operation mode writing ET0I ET1I disables related interrupt service. When function selected, executing instruction enable output executing instruction disable output. case timer/event counter condition, writing data timer/event counter preload register also reloads that data timer/event counter. timer/event counter turn data written timer/event counter kept only timer/event counter preload register. timer/event counter still continues operation until overflow occurs. When timer/event counter (reading TMR0/TMR1) read, clock blocked avoid errors. this results counting error, blocking clock should taken into account programmer. strongly recommended load desired value into TMR0/TMR1 register first, then turn related timer/event counter proper operation. Because initial value TMR0/TMR1 unknown. timer/event scheme, programmer should special attention instruction enable then disable timer first time, whenever there need timer/event function, avoid unpredicatable result. After this procedure, timer/event function operated normally. example given below, using 8-bit width (timer ;timer cascade into 16-bit width. START: ET0I bits intc0, enable timer global interrupt
ET1I enable intc1, timer interrupt operating mode tmr1c, timer mode select mask option clock source 0a0h operating mode timer tmr0c, mode select system clock/4
tmr1c.4 Enable then disable timer tmr1c.4 first time
tmr0, tmr1,
Load desired value into TMR0/TMR1 register Normal operating
tmr0c.4 tmr1c.4
Input/Output Ports There 12-bit bidirectional input/output port, 8-bit input port devices, labeled which mapped [12H], [14H] [16H] RAM, respectively. PA0~PA3 configured CMOS (output) NMOS (input/output) with without pull-high resistor option. PA4~PA7 always pull-high NMOS (input/output). choose NMOS (input), Each port (PA0~PA7) configured wake-up input. only used input operation. contents PC4~PC7 unknown. configured CMOS output NMOS input/output with without pull-high resistor option. port input operation (PA, PC), these ports non-latched, that inputs should ready
Input/Output Ports
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
user wants BZ/BZ function, related port should CMOS output. buzzer output signals controlled data registers defined following table.
Data Register
Data Register
PA0/PA1 State PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0
Input Ports rising edge instruction (m=12H 14H). output operation, data latched remain unchanged until output latch rewritten. When structures open drain NMOS type, should noted that, before reading data from pads, should written related bits disable NMOS device. That executing first instruction (i=0~7 disable related NMOS device, then stable data. After chip reset, these input lines remain high level left floating options). Each these output latches cleared [m], (m=12H 16H) instruction. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. When line used line, related line options should configured NMOS with without pull-high resistor. Once line selected CMOS output, function cannot used. input state line read from related pad. When configured NMOS with without pull-high resistor, should careful when applying read-modify-write instruction Since read-modify-write will read entire port state (pads state) firstly, execute specified instruction then write result port data register. When read operation executed, fault state (caused load effect floating state) read. Errors will then occur. There three function pins that share with port: PA0/BZ, PA1/BZ PA3/PFD. buzzer driving output pair programmable frequency divider output. Timer Note: Timer Preload Value stands undefined stands unknown
Note: stands undefined output signal function controlled data register timer/event counter state. output signal frequency also dependent timer/event counter overflow period. definitions control signal output frequency listed following table. Display Memory devices provides area embedded data memory display. This area located from Bank Bank pointer (BP; located RAM) switch between display memory. When data written into 40H~60H will effect display. When cleared data written into 40H~60H means access general purpose data memory. display memory read written only indirect addressing mode using MP1. When data written into display data area, automatically read driver which then generates corresponding driving signals. turn display off, written corresponding display memory, respectively. figure illustrates mapping between display memory pattern devices.
Display Memory State Frequency
Data Register
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Driver Output output number driver device option (i.e., duty, duty duty). bias type driver type type HT49R50A-1/HT49C50-1 while bias type driver only type HT49C50L. bias type selected, external capacitor required. bias type selected, capacitor mounted between pins needed. driver bias voltage HT49R50A-1/HT49C50-1 bias bias option, while driver bias voltage HT49C50L only bias. bias selected, capacitor mounted between ground required. bias selected, capacitors needed pins. bias power supply selection HT49R50A-1/ HT49C50-1: There types selections: bias bias. bias type selection HT49R50A-1/HT49C50-1: This option determine what kind bias selected, type type. Voltage Reset/Detector Functions There voltage detector (LVD) voltage reset circuit (LVR) implemented microcontroller. These functions enabled/disabled options. Once options enabled, user RTCC.3 enable/disable (1/0) circuit read detector status (0/1) from RTCC.5; otherwise, function disabled. same effect function with external signal which performs chip reset. During HALT state, disabled.
Driver Output (1/3 Duty, Bias, Type) Rev. 2.10 April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Driver Output (1/4 Duty, Bias, Type)
RTCC register definitions listed table next page. Label RT0~RT2 LVDC* QOSC LVDO* Read/Write Reset 111B Function multiplexer control inputs select real clock prescaler output enable/disable (1/0) 32768Hz quick start-up oscillating 0/1: quickly/slowly start detection output (1/0) voltage detected Unused bit, read
Note: HT49R50A-1/HT49C50-1 RTCC (09H) Register
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Options following shows options devices. these options should defined order ensure proper system functioning. Options type selection. This option determine whether Crystal 32768Hz crystal oscillator chosen system clock. Clock source selection. Time Base. There three types selection: system clock/4 OSC. enable/disable selection. enabled disabled options. times selection. This option defines clear instruction. means that clear WDT. means that both have been executed, only then will cleared. Time Base time-out period selection. Time Base time-out period ranges from clock/212 clock/215. means clock source selected options. Buzzer output frequency selection. There eight types frequency signals buzzer output: Clock/22~Clock/29. means clock source selected options. Wake-up selection. This option defines wake-up capability. External pins only) have capability wake-up chip from HALT falling edge. Pull-high selection. This option decide whether pull-high resistance visible PA0~PA3 PA4~PA7 always pull-high) PA0~PA3 CMOS NMOS selection. structure PA0~PA3 each bits selected CMOS NMOS individually. When CMOS selected, related pins only used output operations. When NMOS selected, related pins used input output operations. (PA4~PA7 always NMOS) Clock source selection Timer/Event Counter There types selection: system clock system clock/4. Clock source selection Timer/Event Counter There three types selection: TMR0 overflow, system clock Time Base overflow. pins share with other functions selection. PA0/BZ, PA1/BZ: pins buzzer outputs. PA3/PFD: pins output. common selection. There three types selection: common (1/2 duty) common (1/3 duty) common (1/4 duty). common selected, segment output will common output. bias power supply selection. There types selection: bias bias HT49R50A-1/HT49C50-1. bias type selection. This option decide what kind bias selected, type type HT49R50A-1/HT49C50-1. driver clock selection. There seven types frequency signals driver circuits: fS/22~fS/28. means clock source selection options. ON/OFF HALT selection selection. enable disable options selection. enable disable options selection. output, there types selection; PFD0 output, other PFD1 output. PFD0, PFD1 timer overflow signals Timer/Event Counter Timer/Event Counter respectively.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Application Circuits
HT49R50A-1/HT49C50-1 Application Circuit
illa
illa
illa
following table shows values corresponding different crystal values. (For reference only) Crystal Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 10pF 25pF 25pF 35pF 300pF 300pF 300pF 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
function resistor ensure that oscillator will switch should voltage conditions occur. Such voltage, mentioned here, which less than lowest value operating voltage. Note however that enabled then removed.
Note:
resistance capacitance reset circuit should designed such ensure that stable remains within valid operating voltage range before bringing high. Make length wiring, which connected short possible, avoid noise interference.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
HT49C50L Application Circuit
illa
illa
illa
Note:
resistance capacitance reset circuit should designed such ensure that stable remains within valid operating voltage range before bringing high.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Instruction Summary
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] data memory data memory immediate data data memory with carry data memory with carry Subtract immediate data from Subtract data memory from Subtract data memory from with result data memory Subtract data memory from with carry Subtract data memory from with carry result data memory Decimal adjust addition with result data memory 1(1) 1(1) 1(1) 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Description Instruction Cycle Flag Affected
Logic Operation A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA data memory data memory Exclusive-OR data memory data memory data memory Exclusive-OR data memory immediate data immediate data Exclusive-OR immediate data Complement data memory Complement data memory with result 1(1) 1(1) 1(1) 1(1)
Increment Decrement INCA DECA Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Clear data memory data memory 1(1) 1(1) None None Move data memory Move data memory Move immediate data 1(1) None None None Rotate data memory right with result Rotate data memory right Rotate data memory right through carry with result Rotate data memory right through carry Rotate data memory left with result Rotate data memory left Rotate data memory left through carry with result Rotate data memory left through carry 1(1) 1(1) 1(1) 1(1) None None None None Increment data memory with result Increment data memory Decrement data memory with result Decrement data memory 1(1) 1(1)
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Mnemonic Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT Note: operation Clear data memory data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles data memory Swap nibbles data memory with result Enter power down mode 1(1) 1(1) 1(1) None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read code (current page) data memory TBLH Read code (last page) data memory TBLH 2(1) 2(1) None None Jump unconditionally Skip data memory zero Skip data memory zero with data movement Skip data memory zero Skip data memory zero Skip increment data memory zero Skip decrement data memory zero Skip increment data memory zero with result Skip decrement data memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Immediate data Data memory address Accumulator number bits addr: Program memory address Flag affected Flag affected
loading register occurs, execution cycle instructions will delayed more cycle (four system clocks). skipping next instruction occurs, execution cycle instructions will delayed more cycle (four system clocks). Otherwise original instruction cycle unchanged. flags affected execution status. Watchdog Timer cleared executing WDT1 WDT2 instruction, cleared. Otherwise flags remain unchanged.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) data memory carry accumulator contents specified data memory, accumulator carry flag added simultaneously, leaving result accumulator. ACC+[m]+C
accumulator carry data memory contents specified data memory, accumulator carry flag added simultaneously, leaving result specified data memory. ACC+[m]+C
data memory accumulator contents specified data memory accumulator added. result stored accumulator. ACC+[m]
immediate data accumulator contents accumulator specified data added, leaving result accumulator. ACC+x
accumulator data memory contents specified data memory accumulator added. result stored data memory. ACC+[m]
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) CALL addr Description Logical accumulator with data memory Data accumulator specified data memory perform bitwise logical_AND operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_AND operation. result stored accumulator.
Logical data memory with accumulator Data specified data memory accumulator perform bitwise logical_AND operation. result stored data memory.
Subroutine call instruction unconditionally calls subroutine located indicated address. program counter increments once obtain address next instruction, pushes this onto stack. indicated address then loaded. Program execution continues with instruction this address. Stack Program Counter+1 Program Counter addr
Operation
Affected flag(s)
Description Operation Affected flag(s)
Clear data memory contents specified data memory cleared
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
[m].i Description Operation Affected flag(s) Description Operation Clear data memory specified data memory cleared [m].i
Clear Watchdog Timer cleared (clears WDT). power down (PDF) time-out (TO) cleared.
Affected flag(s)
WDT1 Description
Preclear Watchdog Timer Together with WDT2, clears WDT. also cleared. Only execution this instruction without other preclear instruction just sets indicated flag which implies this instruction been executed flags remain unchanged. 00H*
Operation
Affected flag(s)
WDT2 Description
Preclear Watchdog Timer Together with WDT1, clears WDT. also cleared. Only execution this instruction without other preclear instruction, sets indicated flag which implies this instruction been executed flags remain unchanged. 00H*
Operation
Affected flag(s)
Description Operation Affected flag(s)
Complement data memory Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
CPLA Description Complement data memory place result accumulator Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa. complemented result stored accumulator contents data memory remain unchanged. Description
Operation Affected flag(s)
Decimal-Adjust accumulator addition accumulator value adjusted (Binary Coded Decimal) code. accumulator divided into nibbles. Each nibble adjusted code internal carry (AC1) will done nibble accumulator greater than adjustment done adding original value original value greater than carry set; otherwise original value remains unchanged. result stored data memory only carry flag affected. ACC.3~ACC.0 AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+AC1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s)
Description Operation Affected flag(s)
Decrement data memory Data specified data memory decremented [m]-1
DECA Description Operation Affected flag(s)
Decrement data memory place result accumulator Data specified data memory decremented leaving result accumulator. contents data memory remain unchanged. [m]-1
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
HALT Description Enter power down mode This instruction stops program execution turns system clock. contents registers retained. prescaler cleared. power down (PDF) time-out (TO) cleared. Program Counter Program Counter+1 Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Directly jump program counter replaced with directly-specified address unconditionally, control passed this destination. Program Counter
Operation
Affected flag(s)
Increment data memory Data specified data memory incremented [m]+1
Increment data memory place result accumulator Data specified data memory incremented leaving result accumulator. contents data memory remain unchanged. [m]+1
Move data memory accumulator contents specified data memory copied accumulator.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) operation operation performed. Execution continues with next instruction. Program Counter Program Counter+1 Move immediate data accumulator 8-bit data specified code loaded into accumulator.
Move accumulator data memory contents accumulator copied specified data memory (one data memories).
Logical accumulator with data memory Data accumulator specified data memory (one data memories) perform bitwise logical_OR operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_OR operation. result stored accumulator.
Logical data memory with accumulator Data data memory (one data memories) accumulator perform bitwise logical_OR operation. result stored data memory.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Description Operation Affected flag(s) Description Operation Return from subroutine program counter restored from stack. This 2-cycle instruction. Program Counter Stack
Return place immediate data accumulator program counter restored from stack accumulator loaded with specified 8-bit immediate data. Program Counter Stack
Affected flag(s)
RETI Description Operation
Return from interrupt program counter restored from stack, interrupts enabled setting bit. enable master (global) interrupt bit. Program Counter Stack
Affected flag(s)
Description Operation
Rotate data memory left contents specified data memory rotated left with rotated into [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7
Affected flag(s)
Description Operation
Rotate data memory left place result accumulator Data specified data memory rotated left with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Affected flag(s)
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Description Operation Rotate data memory left through carry contents specified data memory carry flag rotated left. replaces carry bit; original carry flag rotated into position. [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7 RLCA Description
Affected flag(s)
Rotate left through carry place result accumulator Data specified data memory carry flag rotated left. replaces carry original carry flag rotated into position. rotated result stored accumulator contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation
Affected flag(s)
Description Operation
Rotate data memory right contents specified data memory rotated right with rotated [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Affected flag(s)
Description Operation
Rotate right place result accumulator Data specified data memory rotated right with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0
Affected flag(s)
Description Operation
Rotate data memory right through carry contents specified data memory carry flag together rotated right. replaces carry bit; original carry flag rotated into position. [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Affected flag(s)
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
RRCA Description Rotate right through carry place result accumulator Data specified data memory carry flag rotated right. replaces carry original carry flag rotated into position. rotated result stored accumulator. contents data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0 A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) Description
Operation
Affected flag(s)
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result accumulator. ACC+[m]+C
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result data memory. ACC+[m]+C
Skip decrement data memory contents specified data memory decremented result next instruction skipped. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
SDZA Description
Decrement data memory place result ACC, skip contents specified data memory decremented result next instruction skipped. result stored accumulator data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Description Operation Affected flag(s) [m]. Description Operation Affected flag(s) Description data memory Each specified data memory
data memory specified data memory [m].i
Skip increment data memory contents specified data memory incremented result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
SIZA Description
Increment data memory place result ACC, skip contents specified data memory incremented result next instruction skipped result stored accumulator. data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory next instruction skipped. data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip
Operation Affected flag(s)
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) SWAP Description Operation Affected flag(s) SWAPA Description Operation Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result accumulator. ACC+[m]+1
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result data memory. ACC+[m]+1
Subtract immediate data from accumulator immediate data specified code subtracted from contents accumulator, leaving result accumulator. ACC+x+1
Swap nibbles within data memory low-order high-order nibbles specified data memory data memories) interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory place result accumulator low-order high-order nibbles specified data memory interchanged, writing result accumulator. contents data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Affected flag(s)
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Description Skip data memory contents specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
Description
Move data memory ACC, skip contents specified data memory copied accumulator. contents following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m].i=0
Operation Affected flag(s)
TABRDC Description Operation
Move code (current page) TBLH data memory byte code (current page) addressed table pointer (TBLP) moved specified data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Affected flag(s)
TABRDL Description Operation
Move code (last page) TBLH data memory byte code (last page) addressed table pointer (TBLP) moved data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Affected flag(s)
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical accumulator with data memory Data accumulator indicated data memory perform bitwise logical Exclusive_OR operation result stored accumulator.
Logical data memory with accumulator Data indicated data memory accumulator perform bitwise logical Exclusive_OR operation. result stored data memory. flag affected.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical Exclusive_OR operation. result stored accumulator. flag affected.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Package Information
48-pin SSOP (300mil) Outline Dimensions
Symbol
Dimensions Min. Nom. Max.
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
100-pin Outline Dimensions
Symbol
Dimensions Min. 18.50 13.90 24.50 19.90 2.50 0.10 Nom. 0.65 0.30 0.10 Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.40 0.20
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Product Tape Reel Specifications
Reel Dimensions
SSOP Symbol Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Slit Width Space Between Flange Reel Thickness Dimensions 330±1.0 100±0.1 13.0+0.5 -0.2 2.0±0.5 32.2+0.3 -0.2 38.2±0.2
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Carrier Tape Dimensions
SSOP Symbol Description Carrier Tape Width Cavity Pitch Perforation Position Cavity Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions 32.0±0.3 16.0±0.1 1.75±0.1 14.2±0.1 Min. 1.5+0.25 4.0±0.1 2.0±0.1 12.0±0.1 16.20±0.1 2.4±0.1 3.2±0.1 0.35±0.05 25.5
Rev. 2.10
April 2006
HT49R50A-1/HT49C50-1/HT49C50L
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Floor, Building No.889, Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit Productivity Building, Cross Science Road Gaoxin Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright 2006 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
Rev. 2.10
April 2006

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