Tools Information FAQs Application Note HA0003E Communicating bet
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HT48RU80/HT48CU80 Type 8-Bit
Tools Information FAQs Application Note
HA0003E Communicating between HT48 HT46 Series MCUs HT93LC46 EEPROM HA0004E HT48 HT46 UART Software Implementation Method HA0013E HT48 HT46 Interface Design HA0021E Using Ports HT48 Series
Features
Operating voltage: data memory Universal Asynchronous Receiver/Transmitter
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
voltage reset function bidirectional lines (max.) interrupt input programmable timer/event counter
(UART)
HALT function wake-up feature reduce power
consumption
16-level subroutine nesting 0.5ms instruction cycle with 8MHz system clock
overflow interrupts with outputs
programmable timer/event counter On-chip oscillator, external crystal oscil-
VDD=5V
manipulation instruction 16-bit table read instruction powerful instructions instructions machine cycles 48-pin SSOP, 64-pin LQFP package
lator
32768Hz crystal oscillator timing purposes only Watchdog Timer program memory
General Description
HT48RU80/HT48CU80 8-bit high performance, RISC architecture microcontroller devices specifically designed multiple control product applications. mask version HT48CU80 fully functionally compatible with version HT48RU80 device. advantages power consumption, flexibility, timer functions, oscillator options, HALT wake-up functions, watchdog timer, buzzer driver, well cost, enhance versatility these devices suit wide range application possibilities such industrial control, consumer products, subsystem controllers, etc. HT48CU80 under development will available soon.
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Block Diagram
ifte
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Assignment
Description
Name Options Pull-high Wake-up Schmitt Trigger Description Bidirectional 8-bit input/output port. Each configured wake-up input configuration option. Software instructions determine CMOS output input. Configuration options determine pins this port have pull-high resistors inputs Schmitt trigger Schmitt trigger.
PA0~PA7
PB0/BZ PB1/BZ PB2/INT1 PB3/TMR2 PB4~PB7 PC0/TX PC1/RX PC2~PC7 PD0~PD7 PE0~PE7 PF0~PF7 PG0~PG7 INT0 TMR0 TMR1
Pull-high BZ/BZ
Bidirectional 8-bit input/output ports. Software instructions determine CMOS output Schmitt trigger input. configuration option each port determines pins relevant port have pull-high resistors. Pins PB0, PB1, pin-shared with INT1 TMR2, respectively. Pins pin-shared with UART pins
External interrupt Schmitt trigger input. Edge triggered high transition. Schmitt trigger input Timer/Event Counter Schmitt trigger input Timer/Event Counter
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Name Options Description OSC1, OSC2 connected external network external Crystal (determined configuration option) internal system clock. external system clock operation, OSC2 output system clock. These pins also optioned oscillator (32768Hz). this case, system clock comes from internal oscillator whose nominal frequency options, 3.2MHz, 1.6MHz, 800kHz, 400kHz. Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground.
OSC1 OSC2
Crystal Int. RC+RTC
Note: Each PAcan programmed through configuration option have wake-up function. Individual pins cannot selected have pull-high resistors. pull-high configuration chosen particular port, then input pins this port will connected pull-high resistors. Pins PE4~PE7 pins PF4~PF7 only exist 64-pin package. Port only exists 64-pin package.
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Total .150mA Total Power Dissipation .500mW Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability. Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C Total.-100mA
D.C. Characteristics
Symbol Parameter Test Conditions load, system HALT load, system HALT Conditions fSYS=4MHz fSYS=8MHz load, fSYS=4MHz, UART disable load, fSYS=4MHz, UART disable load, fSYS=4MHz, UART load, fSYS=8MHz, UART load, fSYS=8MHz, UART Min. Typ. Max.
Ta=25°C Unit
Operating Voltage Operating Current (Crystal OSC) Operating Current OSC) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Standby Current (WDTOSC Off) Standby Current (WDTOSC Off, Off)
IDD1
IDD2
IDD3 IDD4 IDD5 ISTB1
ISTB2
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Test Conditions load, system HALT Port Sink Current Port Source Current Pull-high Resistance enabled VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD Conditions
Symbol
Parameter Standby Current (WDTOSC Off, Input Voltage Ports Input High Voltage Ports Input Voltage (RES) Input High Voltage (RES) Voltage Reset
Min. 0.7VDD 0.9VDD
Typ.
Max. 0.3VDD 0.4VDD
Unit
ISTB3 VIL1 VIH1 VIL2 VIH2 VLVR
A.C. Characteristics
Symbol Parameter System Clock (Crystal OSC) System Clock OSC) Test Conditions Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3.2MHz fSYS3 System Clock (Internal OSC) 1.6MHz 800kHz 400kHz fTIMER Timer Frequency (TMR) tWDT1 tWDT2 tWDT3 tRES tSST tINT Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) Watchdog Time-out Period (RTC OSC) External Reset Pulse Width System Start-up Timer Period Interrupt Pulse Width 2.2V~5.5V 3.3V~5.5V Without prescaler Without prescaler Without prescaler Wake-up from HALT Min. 1800 Typ. 1024 7.812 1024 Max. 4000 8000 4000 8000 5400 2700 1350 4000 8000
Ta=25°C Unit tSYS tSYS
fSYS1
fSYS2
tWDTOSC Watchdog Oscillator Period
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Functional Description
Execution Flow system clock microcontroller derived from either crystal oscillator. system clock internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. However, pipelining scheme causes each instruction effectively executed cycle. instruction changes program counter, cycles required complete instruction. Program Counter program counter (PC) controls sequence which instructions stored program executed contents specify full range program memory. After accessing program memory word fetch instruction code, contents program counter incremented one. program counter then points memory word containing next instruction code.
When executing jump instruction, conditional skip execution, loading register, subroutine call return from subroutine, initial reset, internal interrupt, external interrupt return from interrupts, manages program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction. Otherwise proceed with next instruction. lower byte program counter (PCL) readable writeable register (06H). Moving data into performs short jump. destination will within current program page. When control transfer takes place, additional dummy cycle required. Program Memory program memory used store program instructions which executed. also contains data, table, interrupt entries, organized into
Execution Flow Mode Initial Reset External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow Timer/Event Counter Overflow External Interrupt UART Interrupt Skip Loading Jump, Call Branch Return (RET, RETI) BP.5 Program Counter
Program Counter+2
Program Counter Note: *13~*0: Program counter bits #13~#0: Instruction code bits Rev. 1.30 S13~S0: Stack register bits @7~@0: bits January 2009
HT48RU80/HT48CU80
banks, addressed Program Counter table pointer. register bit5 used select bank. When bit5=0, bank ranges from 0000H 1FFFH. When bit5=1, bank1 ranges from 2000H 3FFFH. instruction provide only bits address allow branching within program memory bank. When doing instruction, upper address provided BP5. When doing instruction, user must ensure that bank select programmed that desired program memory bank addressed. return from instruction interrupt) executed, entire 14-bit Program Counter popped stack. Certain locations program memory reserved special usage:
itia
Location 000H
This area reserved program initialization. After chip reset, program always begins execution location 000H.
Location 004H
This area reserved external interrupt service program. INT0 interrupt activated, interrupt enabled stack full, program begins execution location 004H.
Location 008H
This area reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 008H.
Location 00CH
This location reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Location 010H
This area reserved external interrupt service program. INT1 interrupt activated, interrupt enabled stack full, program begins execution location 010H.
Location 014H
This area reserved UART interrupt service program. UART interrupt results from UART interrupt enabled stack full, program begins execution location 014H.
Location 018H
This location reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 018H.
Table location
Program Memory
location used look-up table. instructions (page specified TBHP) (the last page) transfer contents lower-order byte specified data memory, contents higher-order byte TBLH (Table Higher-order byte register) (08H). Table Location
Instruction TABRDC TABRDL
*13~*8 TBHP 111111
Table Location Note: *13~*0: Table location bits @7~@0: Table pointer bits Rev. 1.30 January 2009 TBHP: Table pointer higher-order bits
HT48RU80/HT48CU80
Only destination lower-order byte table well-defined; other bits table word transferred lower portion TBLH. TBLH read only, higher-order byte table pointer TBHP (1FH) lower-order byte table pointer TBLP (07H) read/write registers, indicating table location. Before accessing table, location location placed TBHP TBLP. table related instructions require cycles complete operation. These areas function normal depending upon requirements. Stack Register STACK This special part memory which used save contents program counter only. stack organized into levels neither part data part program space, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. subroutine call interrupt acknowledge signal, contents program counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), program counter restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag will recorded acknowledge signal will inhibited. When stack pointer decremented RETI), interrupt will serviced. This feature prevents stack overflow allowing programmer structure more easily. similar case, stack full subsequently executed, stack overflow occurs first entry will lost (only most recent return addresses stored). Data Memory data memory (RAM) designed with bits, divided into functional groups, namely, special function registers general purpose data memory most which readable/ writeable, although some read only. REG] Bit1~Bit0 Bank Bank pointer (BP;04H), Accumulator (ACC;05H), Program counter lower-order byte register (PCL;06H), lower-order byte table pointer (TBLP;07H), Table higher-order byte register (TBLH;08H), Watchdog Timer option setting register (WDTS;09H), Status register (STATUS;0AH), Interrupt control register (INTC0;0BH), Timer/Event Counter higher order byte register (TMR0H;0CH), Timer/Event Counter lower order byte register (TMR0L;0DH), Timer/Event Counter control register (TMR0C;0EH), Timer/Event Counter higher order byte register (TMR1H;0FH), Timer/Event Counter lower order byte register (TMR1L;10H), Timer/Event Counter control register (TMR1C;11H), registers (PA;12H, PB;14H, PC;16H, PD;18H, PE;1AH, PF;1CH, PG;25H) control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H, PEC;1BH, PFC;1DH, PGC;26H), Timer/Event Counter (TMR2;21H), Timer/Event Counter control register (TMR2C;22H), higher-order byte table pointer (TBHP;1FH), Interrupt control register (INTC1;1EH), UART Status register (USR;28H), UART Control register (UCR1;29H), UART Control register (UCR2;2AH), UART TX/RX Buffer register (TXR/RXR;2BH), UART Baud Rate generator prescaler register (BRG;2CH). other hand, general purpose data memory, addressed from (bank0~2), used data control information under instruction commands. data memory areas handle arithmetic, logic, increment, decrement rotate operations directly. Except some dedicated bits, each data memory reset They also indirectly accessible through memory pointer registers (MP0 MP1). Indirect Addressing Register Location indirect addressing registers that physically implemented. read/write operation [00H] ([02H]) will access data memory pointed (MP1). Reading location (02H) itself indirectly will return result 00H. Writing indirectly results operation. memory pointer registers (MP0 MP1) 8-bit registers. Accumulator accumulator closely related operations. also mapped location data memory carry immediate data operations. data movement between data memory locations must pass through accumulator.
special function registers consist Indirect addressing register (IAR0;00H), Memory pointer register (MP0;01H), Indirect addressing register (IAR1;02H), Memory pointer register (MP1;03H),
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Mapping Arithmetic Logic Unit This circuit performs 8-bit arithmetic logic operations. provides following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ)
Status Register STATUS This 8-bit register (0AH) contains zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). also records status information controls operation sequence. With exception flags, bits status register altered instructions like most other registers. data written into status register will change flag. addition, operations related status register
only saves results data operation also changes status register.
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Label Function operation results carry during addition operation borrow does take place during subtraction operation, otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction, otherwise cleared. result arithmetic logic operation zero, otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa, otherwise cleared. cleared system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Status (0AH) Register give different results from those intended. flag affected only system power-up, time-out executing instruction. flag affected only executing instruction during system power-up. flags generally reflect status latest operations. addition, entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status important subroutine corrupt status register, precautions must taken save properly. Interrupt device provides external interrupts, three internal timer/event counter interrupts, UART interrupt. Interrupt Control Register (INTC0; 0BH) Interrupt Control Register (INTC1;1EH) both contain interrupt control bits that used enable/disable status interrupt request flags. Once interrupt subroutine serviced, other interrupts will blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests occur during this interval only interrupt request flag recorded. certain interrupt requires servicing within service routine, corresponding INTC0 INTC1 allow interrupt nesting. stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack must prevented from becoming full. these kinds interrupts have wake-up capability. interrupt serviced, control transfer occurs pushing program counter onto stack, followed branch subroutine specified location proRev. 1.30 gram memory. Only program counter pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. External interrupts triggered high transition INT0 INT1 related interrupt request flag (EIF0; INTC0; EIF1; INTC1) will set. When interrupt enabled, stack full external interrupt active, subroutine call location will occur. interrupt request flag (EIF0 EIF1) bits will cleared disable other interrupts. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T0F; INTC0), caused timer overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T0F) will reset cleared disable further interrupts. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T1F; INTC0), caused overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T1F) will reset cleared disable further interrupts. UART interrupt initialized setting interrupt request flag (URF; INTC1), that caused regular UART receive signal, caused UART transmit signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (URF) reset cleared disable further other interrupts.
January 2009
HT48RU80/HT48CU80
Label EEI0 ET0I ET1I EIF0 Function Controls master (global) interrupt enable; disable) Controls external interrupt enable; disable) Controls Timer/Event Counter interrupt enable; disable) Controls Timer/Event Counter interrupt enable; disable) External interrupt request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Unused bit, read INTC0 (0BH) Register Label EEI1 EURI ET2I EIF1 Function Controls external interrupt enable; disable) Controls UART interrupt enable; disable) Controls Timer/Event Counter overflow interrupt enable; disable) Unused bit, read External interrupt request flag active; inactive) UART interrupt request flag active; inactive) Timer/Event Counter overflow request flag active; inactive) INTC1 (1EH) Register internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T2F; INTC1), caused overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T2F) will reset cleared disable further interrupts. During execution interrupt subroutine, other interrupt acknowledge signals held until instruction executed related interrupt control stack full). return from interrupt subroutine, invoked. RETI will enable interrupt service, will not. Interrupts, occurring interval between rising edges consecutive pulses, will serviced latter pulses, corresponding interrupts enabled. case simultaneous requests following table shows priority that applied. These masked resetting bit. Interrupt Source External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow External Interrupt UART Interrupt Timer/Event Counter Overflow Interrupt Priority Vector 010H 014H 018H
Timer/Event Counter interrupt request flag (T0F/T1F), external interrupt request flag (EIF0), enable Timer/Event Counter interrupt (ET0I/ET1I), enable external interrupt (EEI0) enable master interrupt (EMI) constitute interrupt control register (INTC0) which located data memory. EMI, EEI0, ET0I ET1I used control enabling disabling interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (T0F, T1F, EIF0) set, they will remain INTC0 register until interrupts serviced cleared software instruction.
Rev. 1.30
January 2009
HT48RU80/HT48CU80
External Interrupt request flag (EIF1), UART interrupt request flag (URF), Timer/Event Counter interrupt request flag (T2F), External Interrupt (EEI1), enable UART interrupt (EURI), enable Timer/Event Counter interrupt (ET2I), constitute Interrupt Control register (INTC1) which located data memory. EEI1, EURI ET2I used control enabling disabling interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (EIF1, URF, T2F) set, they will remain INTC1 register until interrupts serviced cleared software instruction. recommended that program does within interrupt subroutine. Interrupts often occur unpredictable manner need serviced immediately some applications. only stack left enabling interrupt well controlled, original control sequence will damaged once operates interrupt subroutine. Oscillator Configuration There three oscillator circuits microcontroller.
cost effective solution. However, frequency oscillation vary with VDD, temperatures chip itself process variations. therefore, suitable timing sensitive operations where accurate oscillator frequency desired. Crystal oscillator used, crystal across OSC1 OSC2 needed provide feedback phase shift required oscillator. other external components required. stead crystal, resonator also connected between OSC1 OSC2 frequency reference, external capacitors OSC1 OSC2 required. internal oscillator used, OSC1 OSC2 selected 32768Hz crystal oscillator (RTC OSC). Also, frequencies internal oscillator 3.2MHz, 1.6MHz, 800kHz 400kHz, depending options. oscillator free running on-chip oscillator, external components required. Even system enters power down mode, system clock stopped, oscillator still works within period approximately 65ms oscillator disabled options conserve power. Watchdog Timer
illa
illa
System Oscillator them designed system clocks, namely, external oscillator, external Crystal oscillator internal oscillator, which determined options. matter what oscillator type selected, signal provides system clock. HALT mode stops system oscillator ignores external signal conserve power. oscillator used, external resistor between OSC1 required resistance must range from 24kW 1MW. system clock, divided available OSC2, which used synchronize external logic. oscillator provides most
clock source implemented dedicated oscillator (WDT oscillator), clock instruction clock (system clock divided determines options. This timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. Watchdog Timer disabled options. Watchdog Timer disabled, executions related result operation. clock enabled only internal RC+RTC mode. Once internal oscillator oscillator with period 65ms normally) selected, first divided (8-stage) nominal time-out period 17ms This time-out period vary with temperatures, process variations. invoking prescaler, longer time-out periods realized. Writing data WS2, WS1, (bits WDTS) give different time-out periods. WS2, WS1, equal division ratio 1:128, maximum time-out period seconds oscillator disabled,
Watchdog Timer
Rev. 1.30
January 2009
HT48RU80/HT48CU80
clock still come from instruction clock operates same manner except that HALT state stop counting lose protecting purpose. this situation logic only restarted external logic. high nibbles WDTS reserved users defined flags, which used indicate some specified status. device operates noisy environment, using on-chip oscillator (WDT OSC) 32kHz crystal oscillator (RTC OSC) strongly recommended, since HALT will stop system clock. WDTS Register overflow under normal operation will initialize status HALT mode, overflow will initialize only Program Counter reset zero. clear contents (including prescaler), three methods adopted; external reset level RES), software instruction instruction. software instruction include other these types instruction, only active depending option times selection selected (i.e. CLRWDT times equal one), execution instruction will clear WDT. case that chosen (i.e. CLRWDT times equal two), these instructions must executed clear WDT, otherwise, reset chip result time-out. Power Down Operation HALT HALT mode initialized instruction results following:
system oscillator will turned ports maintain their original status. flag flag cleared.
Division Ratio 1:16 1:32 1:64 1:128
system leave HALT mode means external reset, interrupt, external falling edge signal port overflow. external reset causes device initialization overflow performs After flags examined, cause chip reset determined. flag cleared system power-up executing instruction when executing instruction. flag time-out occurs, causes wake-up that only resets Program Counter others remain their original status. port wake-up interrupt methods considered continuation normal execution. Each Port independently selected wake-up device options. Awakening from port stimulus, program will resume execution next instruction. awakens from interrupt, sequence occur. related interrupt disabled interrupt enabled stack full, program will resume execution next instruction. interrupt enabled stack full, regular interrupt response takes place. interrupt request flag before entering HALT mode, wake-up function related interrupt will disabled. Once wake-up event occurs, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period will inserted after wake-up. wake-up results from interrupt acknowledge signal, actual interrupt subroutine execution will delayed more cycles. wake-up results next instruction execution, this will executed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT status. oscillator still runs HALT mode oscillator enabled). Reset There three ways which reset occur:
reset during normal operation reset during HALT time-out reset during normal operation
oscillator remains running oscillator selected). contents chip registers remain unchanged.
prescaler will cleared
counted again clock from oscillator).
time-out during HALT different from other chip reset conditions, since perform that resets only Program Counter leaving other circuits their original state. Some registers remain unchanged during other reset conditions. Most registers reset when reset conditions met. examining flags, program distinguish between different
Rev. 1.30
January 2009
HT48RU80/HT48CU80
RESET Conditions reset during power-up reset during normal operation wake-up HALT time-out during normal operation wake-up HALT
Note: stands guarantee that system oscillator started stabilized, (System Start-up Timer) provides extra delay 1024 system clock pulses when system resets (power-up, time-out reset) system awakes from HALT state. When system reset occurs, delay added during reset period. wake-up from HALT will enable delay. extra option load time delay added during system reset (power-up, time-out normal mode reset). functional unit chip reset status shown below. Program Counter Interrupt Prescaler Timer/Event Counter Input/Output Ports Stack Pointer 000H Disable Clear Clear. After master reset, begins counting Input mode Points stack
Reset Circuit Note: Make length wiring, which connected short possible, avoid noise interference.
Reset Timing Chart
Reset Configuration
Rev. 1.30
January 2009
HT48RU80/HT48CU80
states registers summarized following table. Register TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C TMR2 TMR2C Program Counter TBLP TBLH TBHP STATUS INTC0 INTC1 WDTS UCR1 UCR2 TXR/RXR Reset (Power xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx 00-0 1000 000H xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx Time-out Reset (Normal Operation) (Normal Operation) xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx Reset (HALT) xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx xxxx xxxx 00-0 1-xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx Time-out (HALT)* uuuu uuuu uuuu uuuu uu-u u-uuuu uuuu uuuu uuuu uu-u u-uuuu uuuu uu-u uuuu 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note: stands stands stands
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Timer/Event Counter Three timer/event counters (TMR0, TMR1, TMR2) implemented this microcontroller. Timer/Event Counter contains 16-bit programmable count-up counter clock come from external source from system clock divided RTC. Timer/Event Counter contains 16-bit programmable count-up counter clock come from external source from system clock divided RTC. Timer/Event Counter contains 8-bit programmable count-up counter clock come from external source from system clock RTC. Using internal clock sources, there reference time-bases Timer/Event Counter internal clock source selected coming from fSYS/4 (can always optioned) (enabled only system oscillator Int. RC+RTC mode) options. Using internal clock sources, there reference time-bases Timer/Event Counter internal clock source selected coming from fSYS/4 (can always optioned) (enabled only system oscillator Int. RC+RTC mode) options. Using external clock input allows user count external events, measure time internals pulse widths, generate accurate time base. While using internal clock allows user generate accurate time base. There three registers related Timer/Event Counter namely, TMR0H ([0CH]), TMR0L ([0DH]), TMR0C ([0EH]). Writing TMR0L will only written data internal lower-order byte buffer bits) writing TMR0H will transfer specified data contents lower-order byte buffer TMR0H TMR0L preload registers, respectively. Timer/Event Counter preload register changed each writing operations theTMR0H. Reading from TMR0H will latch contents TMR0H TMR0L counters destination lower-order byte buffer, respectively. Reading TMR0L will read contents lower-order byte buffer. TMR0C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. There three registers related Timer/Event Counter TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR1L will only written data internal lower-order byte buffer bits) writing TMR1H will transfer specified data contents lower-order byte buffer TMR1H TMR1L preload registers, respectively. Timer/Event Counter preload register changed each writing operaRev. 1.30 tions TMR1H. Reading from TMR1H will latch contents TMR1H TMR1L counters destination lower-order byte buffer, respectively. Reading TMR1L will read contents lower-order byte buffer. TMR1C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. There registers related timer/event counter, namely, TMR2 (21H) TMR2C (22H). timer/event counter counting mode (T2ON=1), writing TMR2 will only written data preload register bits). timer/event counter preload register changed each writing operations TMR2. Reading from TMR2 will also latch TMR2 destination. TMR2C timer/event counter control register, which defines operating mode, counting enable disable active edge. T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C), T2M0, T2M1 (TMR2C) bits define operating mode. event count mode used count external events, which means clock source comes from external (TMR0/TMR1/TMR2). timer mode functions normal timer with clock source coming from instruction clock clock (Timer0/Timer1/Timer2). pulse width measurement mode used count high level duration external signal (TMR0/TMR1/TMR2). counting based instruction clock clock (Timer0/Timer1/Timer2). event count timer mode, once Timer/Event Counter starts counting, will count from current contents Timer/Event Counter FFFFH. Once overflow occurs, counter reloaded from Timer/Event Counter preload register same time generates interrupt request flag (T0F/T1F; INTC0). event count timer mode, once Timer/Event Counter starts counting, will count from current contents timer/event counter FFH. Once overflow occurs, counter reloaded from Timer/Event Counter preload register same time generates corresponding interrupt request flag (T2F; INTC1). pulse width measurement mode with T0ON/ T1ON/T2ON T0E/T1E/T2E bits equal one, once TMR0/TMR1/TMR2 received transient from high high T0E/T1E/T2E bits will start counting until TMR0/TMR1/ TMR2 returns original level resets T0ON/T1ON/ T2ON. measured result will remain Timer/Event Counter 0/1/2 even activated transient occurs again. other words, only cycle measurement done. Until setting T0ON/T1ON/ T2ON, cycle measurement will function again long receives further transient pulse. Note that, this operating mode, Timer/Event Counter 0/1/2 starts counting according logic level
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HT48RU80/HT48CU80
0~2, Label T0ON Unused bit, read Defines TMR0 active edge Timer/Event Counter (0=active high; 1=active high low) Enables disables Timer counting (0=disable; 1=enable) Defines operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register Function
T0M0 T0M1
0~2,
Label T1ON Unused bit, read
Function
Defines TMR1 active edge Timer/Event Counter (0=active high; 1=active high low) Enables disables Timer counting (0=disable; 1=enable) Defines operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register
T1M0 T1M1
Label Defines prescaler stages 000: fINT=fS/2 001: fINT=fS/4 010: fINT=fS/8 T2PSC0~ 011: fINT=fS/16 T2PSC2 100: fINT=fS/32 101: fINT=fS/64 110: fINT=fS/128 111: fINT=fS/256 T2ON
Function
Defines active edge TMR2 input signal (0=active high; 1=active high low) Enables disables timer counting (0=disable; 1=enable) Unused bit, read Defines operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR2C (22H) Register
T2M0 T2M1
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cording transient edges. case counter overflows, Counter 0/1/2 reloaded from Timer/Event Counter 0/1/2 preload register issues interrupt request just like other modes. enable counting operation, timer (T0ON: TMR0C; T1ON: TMR1C; T2ON: TMR2C) should pulse width measurement mode, T0ON/ T1ON/T2ON will cleared automatically after measurement cycle completed. other modes T0ON/T1ON/T2ON only reset instructions. overflow Timer/Event Counter 0/1/ wake-up sources. matter what operation mode writing ET0I/ET1I/ET2I disfS
able corresponding interrupt services. case Timer/Event Counter 0/1/2 condition, writing data Timer/Event Counter 0/1/2 preload register will also reload that data Timer/Event Counter 0/1/2. Timer/Event Counter 0/1/2 turned data written will only kept Timer/Event Counter 0/1/2 preload register. Timer/Event Counter 0/1/2 will still operate until overflow occurs Timer/Event Counter 0/1/2 reloading will occur same time). When Timer/Event Counter 0/1/2 (reading TMR0/TMR1/TMR2) read, clock will blocked avoid errors. clock blocking results counting error, this must taken into consideration programmer.
Timer/Event Counter
Timer/Event Counter
Timer/Event Counter
Rev. 1.30
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HT48RU80/HT48CU80
Input/Output Ports There bidirectional input/output lines microcontroller, labeled from which mapped data memory [12H], [14H], [16H], [18H], [1AH], [1CH] [25H] respectively. these ports used input output operations. input operation, these ports non-latching, that inputs must ready rising edge instruction (m=12H, 14H, 16H, 18H, 1AH, 25H). output operation, data latched remains unchanged until output latch rewritten. Each line control register (PAC, PBC, PCC, PDC, PEC, PFC, PGC) control input/output configuration. With this control register, CMOS output Schmitt trigger input with without pull-high resistor structures reconfigured dynamically under software control. function input, corresponding latch control register must write input source also depends control register. control register input will read state. control register contents latches will move internal bus. latter possible instruction. output function, CMOS only configuration. These control registers mapped locations 13H, 15H, 17H, 19H, 1BH, 26H. After chip reset, these input/output lines remain high levels floating state (depending pull-high options). Each these input/output latches cleared (m=12H, 14H, 16H, 18H, 1AH, 25H) instructions. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. Each line Port capability waking-up device. There pull-high option available lines (port option). Once pull-high option line selected, line pull-high resistor. Otherwise, pull-high resistor absent. should noted that non-pull-high line operating input mode will cause floating state.
PC2~PC7, Input/Output Ports
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PC0/TX Input/Output Ports
PC1/RX Input/Output Ports
Voltage Reset microcontroller provides voltage reset circuit order monitor supply voltage device. supply voltage device within range 0.9V~VLVR, such changing battery, will automatically reset device internally. includes following specifications:
voltage (0.9V~VLVR) remain origi-
relationship between VLVR shown below.
state longer than 1ms. voltage state does exceed 1ms, will ignore will perform reset function.
uses function with external
signal perform chip reset.
Note: VOPR voltage range proper chip operation 4MHz system clock.
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HT48RU80/HT48CU80
Voltage Reset Note: make sure that system oscillator stabilized, provides extra delay 1024 system clock pulses before entering normal operation. Since voltage maintain original state longer than 1ms, therefore delay enters reset mode. UART Serial Interface HT48RU80/HT48CU80 devices contain integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain serial interface. UART function many features transmit receive data serially transferring frame data with eight nine data bits transmission well being able detect errors when data overwritten incorrectly framed. UART function possesses internal interrupt which used indicate when reception occurs when transmission terminates.
UART features UART external interfacing
integrated UART function contains following features:
Full-duplex, asynchronous communication bits character length Even, parity options stop bits Baud rate generator with 8-bit prescaler Parity, framing, noise overrun error detection Support interrupt address detect (last character bit=1) Separately enabled transmitter receiver 2-byte Deep Fifo Receive Data Buffer Transmit receive interrupts Interrupts initialized following conditions:
communicate with external serial interface, internal UART external pins known UART transmitter pin, which used general purpose configured UART transmitter, which occurs when TXEN UCR2 control register equal zero. Similarly, UART receiver pin, which also used general purpose pin, configured receiver, which occurs RXEN UCR2 register equal zero. Along with UARTEN bit, TXEN RXEN bits, set, will automatically setup these pins their respective output input conditions disable pull-high resistor option which exist pin.
UART data transfer scheme
Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect
block diagram shows overall data transfer structure arrangement UART. actual data transmitted from first transferred register application program. data will then transferred Transmit Shift Register from where will shifted out, first, onto rate controlled Baud Rate Generator. Only register mapped onto Data Memory, Transmit Shift Register mapped therefore inaccessible application program. Data received UART accepted external pin, from where shifted first, Receiver Shift Register rate controlled Baud Rate Generator. When shift register full, data will then transferred from shift register internal register, where buffered manipulated application program. January 2009
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UART Data Transfer Scheme
Only register mapped onto Data Memory, Receiver Shift Register mapped therefore inaccessible application program. should noted that actual register data transmission reception, although referred text, application programs, separate registers, only exists single shared register Data Memory. This shared register known TXR/RXR register used both data transmission data reception.
UART status control registers
with TIDLE then writing register. flag generated when data character, break queued ready sent.
RXIF RXIF flag receive register status flag. When this read only flag indicates that read data register empty. When flag indicates that read data register contains data. When contents shift register transferred register, interrupt generated RIE=1 UCR2 register. more errors detected received word, appropriate receive-related flags FERR, and/or PERR within same clock cycle. RXIF flag cleared when register read with RXIF set, followed read from register, register data available.
There five control registers associated with UART function. USR, UCR1 UCR2 registers control overall function UART, while register controls Baud rate. actual data transmitted received serial interface managed through TXR/RXR data registers.
register
RIDLE RIDLE flag receiver status flag. When this read only flag indicates that receiver between initial detection start completion stop bit. When flag indicates that receiver idle. Between completion stop detection next start bit, RIDLE indicating that UART idle.
register status register UART, which read program determine present status UART. flags within register read only. Further explanation each flags given below:
TXIF TXIF flag transmit data register empty flag. When this read only flag indicates that character transferred transmit shift registers. When flag indicates that transmit shift register received character from data register. TXIF flag cleared reading UART status register (USR) with TXIF then writing data register. Note that when TXEN set, TXIF flag will also since transmit buffer full.
OERR OERR flag overrun error flag, which indicates when receiver buffer overflowed. When this read only flag there overrun error. When flag overrun error occurs which will inhibit further transfers receive data register. flag cleared software sequence, which read status register followed access data register.
FERR FERR flag framing error flag. When this read only flag indicates framing error. When flag indicates that framing error been detected current character. flag also cleared software sequence which will involve read status register followed access data register.
TIDLE TIDLE flag known transmission complete flag. When this read only flag indicates that transmission progress. This flag will when TXIF flag when there transmit data, break character being transmitted. When TIDLE becomes idle. TIDLE flag cleared reading regis-
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HT48RU80/HT48CU80
flag noise flag. When this read only flag indicates noise condition. When flag indicates that UART detected noise receiver input. flag during same cycle RXIF flag will case overrun. flag cleared software sequence which will involve read status register, followed access data register.
UCR1 register
UCR1 register together with UCR2 register UART control registers that used various options UART function, such overall on/off control, parity control, data transfer length etc. Further explanation each bits given below:
This only used 9-bit data transfers used, which case this location will store transmitted data, known TX8. used determine whether data transfers 8-bit 9-bit format.
PERR PERR flag parity error flag. When this read only flag indicates that parity error been detected. When flag indicates that parity received word incorrect. This error flag applicable only Parity mode (odd even) selected. flag also cleared software sequence which involves read status register, followed access data register.
This only used 9-bit data transfers used, which case this location will store received data, known RX8. used determine whether data transfers 8-bit 9-bit format.
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TXBRK TXBRK Transmit Break Character bit. When this there break characters operates normally. When there transmit break characters transmitter will send logic zeros. When equal after buffered data been transmitted, transmitter output held minimum 13-bit length until TXBRK reset.
STOPS This determines stop bits used. When this equal stop bits used, equal then only stop used.
disabled will empty buffer character remaining buffer will discarded. addition, baud rate counter value will reset. When UART disabled, error status flags will reset. TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR, bits will cleared, while TIDLE, TXIF RIDLE bits will set. Other control bits UCR1, UCR2, registers will remain unaffected. UART active UARTEN cleared, pending transmissions receptions will terminated module will reset defined above. When UART re-enabled will restart same configuration.
UCR2 register
This parity type selection bit. When this equal parity will selected, equal then even parity will selected.
PREN This parity enable bit. When this equal parity function will enabled, equal then parity function will disabled.
This used select data length format, which have choice either 8-bits 9-bits. this equal then 9-bit data length will selected, equal then 8-bit data length will selected. 9-bit data length selected then bits will used store received transmitted data respectively.
UCR2 register second UART control registers serves several purposes. main functions control basic enable/disable operation UART Transmitter Receiver well enabling various UART interrupt sources. register also serves control baud rate speed, receiver wake-up enable address detect enable. Further explanation each bits given below: TEIE This enables disables transmitter empty interrupt. this equal when transmitter empty TXIF flag set, transmitter empty condition, UART interrupt request flag will set. this equal UART interrupt request flag will influenced condition TXIF flag.
TIIE This enables disables transmitter idle interrupt. this equal when transmitter idle TIDLE flag set, UART interrupt request flag will set. this equal UART interrupt request flag will influenced condition TIDLE flag.
UARTEN UARTEN UART enable bit. When UART will disabled pins will function General Purpose pins. When UART will enabled pins will function defined TXEN RXEN control bits. When UART
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This enables disables receiver interrupt. this equal when receiver overrun OERR flag receive data available RXIF flag set, UART interrupt request flag will set. this equal UART interrupt will influenced condition OERR RXIF flags.
will controlled UART. Clearing TXEN during transmission will cause transmission aborted will reset transmitter. this occurs, used general purpose pin.
Baud rate generator
WAKE This enables disables receiver wake-up function. this equal Power Down Mode, going edge input will wake-up device. this equal Power Down Mode, edge transitions will wake-up device.
ADDEN ADDEN address detect mode bit. When this address detect mode enabled. When this occurs, bit, which corresponds BNO=0, bit, which corresponds BNO=1, value then received word will identified address, rather than data. corresponding interrupt enabled, interrupt request will generated each time received word address set, which depending value BNO. address interrupt will generated, received data will discarded.
setup speed serial data communication, UART function contains dedicated baud rate generator. baud rate controlled internal free running 8-bit timer, period which determined factors. first these value placed register second value BRGH within UCR2 control register. BRGH decides, baud rate generator used high speed mode speed mode, which turn determines formula that used calculate baud rate. value register determines division factor, which used following baud rate calculation formula. Note that decimal value placed register range between 255. UCR2 BRGH Baud Rate fSYS fSYS
BRGH BRGH selects high speed mode Baud Rate Generator. This bit, together with value placed register, controls Baud Rate UART. this equal high speed mode selected. equal speed mode selected.
programming BRGH which allows selection related formula programming required value register, required baud rate setup. Note that because actual baud rate determined using discrete value, placed register, there will error associated between actual requested value. following example shows register value error value calculated. Calculating register error values clock frequency 8MHz, with BRGH determine register value actual baud rate error value desired baud rate 9600. From above table desired baud rate fSYS fSYS Re-arranging this equation gives (BRx64) 8000000 12.0208 Giving value (9600x obtain closest value, decimal value should placed into register. This gives actual calculated baud rate value 8000000 9615 [64(12 Therefore error equal
RXEN RXEN Receiver Enable Bit. When this equal receiver will disabled with pending data receptions being aborted. addition buffer will reset. this situation used general purpose pin. RXEN equal receiver will enabled UARTEN equal will controlled UART. Clearing RXEN during transmission will cause data reception aborted will reset receiver. this occurs, used general purpose pin.
TXEN TXEN Transmitter Enable Bit. When this equal transmitter will disabled with pending transmissions being aborted. addition buffer will reset. this situation used general purpose pin. TXEN equal transmitter will enabled UARTEN equal
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following tables show actual values baud rate error values values BRGH. Baud Rate K/BPS 19.2 38.4 57.6 115.2 Baud Rates BRGH=0 fSYS=8MHz Kbaud 1.202 2.404 4.807 9.615 17.857 41.667 62.5 Error 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 8.51 fSYS=7.159MHz Kbaud 1.203 2.38 4.863 9.322 18.64 37.29 55.93 111.86 Error 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 -2.9 fSYS=4MHz Kbaud 0.300 1.202 2.404 4.808 8.929 20.83 62.5 Error 0.00 0.16 0.16 0.16 -6.99 8.51 8.51 fSYS=3.579545MHz Kbaud 0.300 1.19 2.432 4.661 9.321 18.643 55.93 Error 0.00 -0.83 1.32 -2.9 -2.9 -2.9 -2.9
Baud Rates Error Values BRGH Baud Rates BRGH=1 fSYS=8MHz Kbaud 2.404 4.808 9.615 19.231 38.462 55.556 Error 0.16 0.16 0.16 0.16 0.16 -3.55 8.51 fSYS=7.159MHz Kbaud 2.405 4.811 9.520 19.454 37.287 55.93 111.86 Error 0.23 0.23 -0.832 1.32 -2.9 -2.9 -2.9 fSYS=4MHz Kbaud 1.202 2.404 4.808 9.615 19.231 35.714 62.5 Error 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 fSYS=3.579545MHz Kbaud 1.203 2.406 4.76 9.727 18.643 37.286 55.930 111.86 Error 0.23 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9
Baud Rate K/BPS 19.2 38.4 57.6 115.2
Baud Rates Error Values BRGH
Setting controlling UART
Introduction data transfer, UART function utilizes non-return-to-zero, more commonly known NRZ, format. This composed start bit, eight nine data bits, stop bits. Parity supported UART hardware, setup even, parity. most common data format, data bits along with parity stop bit, denoted used default setting, which setting power-on. number data bits stop bits, along with parity, setup programming corresponding BNO, PRT, PREN, STOPS bits UCR1 register. baud rate used transmit receive data setup using internal 8-bit baud rate generator, while data transmitted received
first. Although transmitter receiver functionally independent, they both same data format baud rate. cases stop bits will used data transmission.
Enabling/disabling UART basic on/off function internal UART function controlled using UARTEN UCR1 register. UART transmit receive pins, respectively, pin-shared with normal pins, basic functions UARTEN control control UART function these pins. UARTEN, TXEN RXEN bits set, then these pins will setup output input respectively, effect disabling normal function. data being transmitted then will default logic high value.
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Clearing UARTEN will disable pins allow these pins used normal pins. When UART function disabled buffer will reset empty condition, same time discarding remaining residual data. Disabling UART will also reset error status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR being cleared while bits TIDLE, TXIF RIDLE will set. remaining control bits UCR1, UCR2 registers will remain unaffected. UARTEN UCR1 register cleared while UART active, then pending transmissions receptions will immediately suspended UART will reset condition defined above. UART then subsequently re-enabled, will restart again same configuration.
UART transmitter
Data, parity stop selection format data transferred, composed various factors such data length, parity on/off, parity type, address bits number stop bits. These factors determined setup various bits within UCR1 register. controls number data bits which either controls choice even parity, PREN controls parity on/off function STOPS decides whether stop bits used. following table shows various formats data transmission. address identifies frame address character. number stop bits, which either two, independent data length. Start Data Bits Address Bits Parity Bits Stop
Example 8-bit Data Formats
Data word lengths either bits, selected programming UCR1 register. When set, word length will bits. this case bit, which MSB, needs stored UCR1 register. transmitter core lies Transmitter Shift Register, more commonly known TSR, whose data obtained from transmit data register, which known register. data transmitted loaded into this register application program. register written with data until stop from previous transmission been sent out. soon this stop been transmitted, then loaded with data from register, available. should noted that register, unlike many other registers, directly mapped into Data Memory area such available application program direct read/write operations. actual transmission data will normally enabled when TXEN set, data will transmitted until register been loaded with data baud rate generator defined shift clock source. However, transmission also initiated first loading data into register, after which TXEN set. When transmission data begins, normally empty, which case transfer register will result immediate transfer TSR. during transmission TXEN cleared, transmission will immediately cease transmitter will reset. output will then return having normal general purpose function.
Transmitting data When UART transmitting data, data shifted from shift register, with least significant first. transmit mode, register forms buffer between internal transmitter shift register. should noted that 9-bit data format been selected, then will taken from UCR1 register. steps initiate data transfer summarized follows:
Example 9-bit Data Formats
Transmitter Receiver Data Format following diagram shows transmit receive waveforms both 8-bit 9-bit data formats.
Make correct selection BNO, PRT, PREN STOPS bits define required word length, parity type number stop bits. Setup register select desired baud rate.
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TXEN ensure that used UART transmitter pin. Access register write data that transmitted into register. Note that this step will clear TXIF bit. This sequence events repeated send additional data.
should noted that when TXIF=0, data will inhibited from being written register. Clearing TXIF flag always achieved using following software sequence: register access register write execution read-only TXIF flag UART hardware indicates that register empty that other data written into register without overwriting previous data. TEIE then TXIF flag will generate interrupt. During data transmission, write instruction register will place data into register, which will copied shift register present transmission. When there data transmission progress, write instruction register will place data directly into shift register, resulting commencement data transmission, TXIF being immediately set. When frame transmission complete, which happens after stop bits sent after break frame, TIDLE will set. clear TIDLE following software sequence used: register access register write execution Note that both TXIF TIDLE bits cleared same software sequence.
Receive Serial Shift Register, commonly known RSR. data which received external input pin, sent data recovery block. data recovery block operating speed times that baud rate, while main receive serial shifter operates baud rate. After sampled stop bit, received data transferred receive data register, register empty. data which received external input sampled three times majority detect circuit determine logic level that been placed onto pin. should noted that register, unlike many other registers, directly mapped into Data Memory area such available application program direct read/write operations.
Receiving data When UART receiver receiving data, data serially shifted external input pin, first. read mode, register forms buffer between internal receiver shift register. register byte deep FIFO data buffer, where bytes held FIFO while third byte continue received. Note that application program must ensure that data read from before third byte been completely shifted otherwise this third byte will discarded overrun error OERR will subsequently indicated. steps initiate data transfer summarized follows:
Make correct selection BNO, PRT, PREN STOPS bits define word length, parity type number stop bits. Setup register select desired baud rate. RXEN ensure that used UART receiver pin.
Transmit break TXBRK then break characters will sent next transmission. Break character transmission consists start bit, followed bits stop bits, where N=1, etc. break character transmitted then TXBRK must first application program, then cleared generate stop bits. Transmitting break character will generate transmit interrupt. Note that break condition length least bits long. TXBRK continually kept logic high level then transmitter circuitry will transmit continuous break characters. After application program cleared TXBRK bit, transmitter will finish transmitting last break character subsequently send stop bits. automatic logic highs last break character will ensure that start next frame recognized.
this point receiver will enabled which will begin look start bit. When character received following sequence events will occur:
RXIF register will when register data available, least more character read. When contents shift register have been transferred register, then set, interrupt will generated. during reception, frame error, noise error, parity error, overrun error been detected, then error flags set.
RXIF cleared using following software sequence: register access register read execution
UART receiver
Introduction UART capable receiving word lengths either bits. set, word length will bits with being stored UCR1 register. receiver core lies
Receive break break character received UART will managed framing error. receiver will count expect certain number times specified values programmed into
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STOPS bits. break much longer than times, reception will considered complete after number times specified STOPS. RXIF set, FERR set, zeros loaded into receive data register, interrupts generated appropriate RIDLE set. long break signal been detected receiver received start bit, data bits invalid stop bit, which sets FERR flag, receiver must wait valid stop before looking next start bit. receiver will make assumption that break condition line next start bit. break regarded character that contains only zeros with FERR flag set. break character will loaded into buffer further data will received until stop bits received. should noted that RIDLE read only flag will high when stop bits have been received. reception break character UART registers will result following:
OERR flag cleared access register followed read register.
Noise Error Flag Over-sampling used data recovery identify valid incoming data noise. noise detected within frame following will occur:
read only noise flag, register will rising edge RXIF bit. Data will transferred from Shift register register. interrupt will generated. However this rises same time RXIF which itself generates interrupt.
Note that flag reset register read operation followed register read operation.
Framing Error FERR Flag read only framing error flag, FERR, register, zero detected instead stop bits. stop bits selected, both stop bits must high, otherwise FERR flag will set. FERR flag buffered along with received data cleared reset.
framing error flag, FERR, will set. receive data register, RXR, will cleared. OERR, PERR, RIDLE RXIF flags will possibly set.
Idle status When receiver reading data, which means will between detection start reading stop bit, receiver status flag register, otherwise known RIDLE flag, will have zero value. between reception stop detection next start bit, RIDLE flag will have high value, which indicates receiver idle condition.
Parity Error PERR Flag read only parity error flag, PERR, register, parity received word incorrect. This error flag only applicable parity enabled, PREN parity type, even selected. read only PERR flag buffered along with received data bytes. cleared reset. should noted that FERR PERR flags buffered along with corresponding word should read before reading data word.
Receiver interrupt read only receive interrupt flag RXIF register edge generated receiver. interrupt generated RIE=1, when word transferred from Receive Shift Register, RSR, Receive Data Register, RXR. overrun error also generate interrupt RIE=1.
UART interrupt scheme
Managing receiver errors
Several types reception errors occur within UART module, following section describes various types they managed UART.
Overrun Error OERR flag register composed byte deep FIFO data buffer, where bytes held FIFO register, while third byte continue received. Before this third byte been entirely shifted data should read from register. this done, overrun error flag OERR will consequently indicated. event overrun error occurring, following will happen:
OERR flag register will set. contents will lost. shift register will overwritten. interrupt will generated set.
UART internal function possesses internal interrupt independent interrupt vector. Several individual UART conditions generate internal UART interrupt. These conditions are, transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect wake-up. When these conditions created, UART interrupt enabled stack full, program will jump UART interrupt vector where serviced before returning main program. Four these conditions, have corresponding register flag, which will generate UART interrupt associated interrupt enable flag UCR2 register set. transmitter interrupt conditions have their corresponding enable bits, while receiver interrupt conditions have shared enable bit. These enable bits used mask individual UART interrupt sources. address detect condition, which also UART interrupt source, does have associated flag, will generate UART interrupt when address detect condition occurs function enabled setting ADDEN UCR2 register. January 2009
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itte
UART Interrupt Scheme wake-up, which also UART interrupt source, does have associated flag, will generate UART interrupt microcontroller woken going edge pin, WAKE bits UCR2 register set. Note that event wake-up interrupt occurring, there will delay 1024 system clock cycles before system resumes normal operation. Note that register flags read only cannot cleared application program, neither will they cleared when program jumps corresponding interrupt servicing routine, case some other interrupts. flags will cleared automatically when certain actions taken UART, details which given UART register section. overall UART interrupt disabled enabled EURI INTC1 interrupt control register prevent UART interrupt from occurring.
Address detect mode
flag set, irrespective data last status. address detect mode parity enable mutually exclusive functions. Therefore address detect mode enabled, then ensure correct operation, parity function should disabled resetting parity enable zero. ADDEN ADDEN Function
UART operation power down mode
BNO=1, UART Interrupt BNO=0 Generated
Setting Address Detect Mode bit, ADDEN, UCR2 register, enables this special mode. this enabled then additional qualifier will placed generation Receiver Data Available interrupt, which requested RXIF flag. ADDEN enabled, then when data available, interrupt will only generated, highest received high value. Note that EURI interrupt enable bits must also enabled correct interrupt generation. This highest address BNO=1 BNO=0. this high, then received word will defined address rather than data. Data Available interrupt will generated every time last received word set. ADDEN enabled, then Receiver Data Available interrupt will generated each time RXIF Rev. 1.30
When Power Down Mode UART will cease function. When device enters Power Down Mode, clock sources module shutdown. enters Power Down Mode while transmission still progress, then transmission will terminated external transmit will forced logic high level. similar way, enters Power Down Mode while receiving data, then reception data will likewise terminated. When enters Power Down Mode, note that USR, UCR1, UCR2, transmit receive registers, well register will affected. UART function contains receiver wake-up function, which enabled disabled WAKE UCR2 register. this bit, along with UART enable bit, UARTEN, receiver enable bit, RXEN receiver interrupt bit, RIE, before enters Power Down Mode,
January 2009
HT48RU80/HT48CU80
then falling edge will wake-up from Power Down Mode. Note that takes 1024 system clock cycles after wake-up, before normal microcontroller operation resumes, data received during this time will ignored. UART wake-up interrupt occur, addition bits wake-up being set, global interrupt enable bit, EMI, UART interrupt enable bit, EURI must also set. these bits then only wake event will occur interrupt will generated. Note also that takes 1024 system clock cycles after wake-up before normal microcontroller resumes, UART interrupt will generated until after this time elapsed. Buzzer Buzzer function provides means producing variable frequency output, suitable applications such Piezo-buzzer driving other external circuits that require precise frequency generator. pins form complimentary pair, pin-shared with pins, PB1. configuration option used select from three buzzer options. first option both pins used normal I/Os, second option both pins configured buzzer pins, third option selects only used buzzer with retaining normal function. Note that inverse which together generate differential output which supply more power connected interfaces such buzzers. Register PBC0 Register PBC1 clock source BZ/BZ, originate from timer/event counter overflow signal selected configuration options. using BZ/BZ functions, timer/event counter should properly generate buzzer signal. configuration options have selected both pins function complementary pair buzzer outputs, then correct buzzer operation essential that both pins must setup outputs setting bits PBC0 PBC1 port control register zero. data data register must also high enable buzzer outputs, low, both pins will remain low. this single register used on/off control both buzzer outputs. Note that data register control over buzzer PB1. configuration options have selected that only function buzzer pin, then used normal pin. function buzzer pin, must setup output setting PBC0 port control register zero. data data register must also high enable buzzer output, will remain low. this used on/off control buzzer PB0. PBC0 port control register high, then still used input even though configuration option configured buzzer output.
Data Register
Data Register
Output Function PB0=BZ PB1=BZ PB1=input line PB0=BZ PB1=input line PB0=input line PB1=BZ PB0=input line PB1=0 PB0=input line PB1=input line
PB0/PB1 Function Control Note: stand care
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HT48RU80/HT48CU80
Options following table shows kinds options this microcontroller. options must defined ensure having proper functioning system. Options clock source: oscillator fSYS/4 oscillator disable CLRWDT instructions: instructions Timer/Event Counter clock sources: fSYS/4 RTCOSC Timer/Event Counter clock sources: fSYS/4 RTCOSC wake-up enable disable CMOS Schmitt input pull-high enable disable port) System oscillator Ext. Ext. crystal, Int. RC+RTC Buzzer output enable: enabled disabled Buzzer clock selection: TMR0 TMR1 Int. frequency selection: 3.2MHz, 1.6MHz, 800kHz 400kHz enable disable
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Application Circuits
illa
illa
illa
Note: resistance capacitance reset circuit should designed ensure that stable remains valid range operating voltage before bringing high. Make length wiring, which connected short possible, avoid noise interference. following table shows values corresponding different crystal values. (For reference only) Crystal Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 10pF 25pF 25pF 35pF 300pF 300pF 300pF 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
function resistor ensure that oscillator will switch should voltage conditions occur. Such voltage, mentioned here, which less than lowest value operating voltage. Note however that enabled then removed.
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HT48RU80/HT48CU80
Instruction
Introduction Central successful operation microcontroller instruction set, which program instruction codes that directs microcontroller perform certain operations. case Holtek microcontrollers, comprehensive flexible over instructions provided enable programmers implement their application with minimum programming overheads. easier understanding various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions implemented within instruction cycle. exceptions this branch, call, table read instructions where instruction cycles required. instruction cycle equal system clock cycles, therefore case 8MHz system oscillator, most instructions would implemented within 0.5ms branch call instructions would implemented within 1ms. Although instructions which require more cycle implement generally limited JMP, CALL, RET, RETI table read instructions, important realize that other instructions which involve manipulation Program Counter register will also take more cycle implement. instructions which change contents will imply direct jump that address, more cycle will required. Examples such instructions would PCL, case skip instructions, must noted that result comparison involves skip operation then this will also take more cycle, skip involved then only cycle required. Moving Transferring Data transfer data within microcontroller program most frequently used operations. Making three kinds instructions, data transferred from registers Accumulator vice-versa well being able move specific immediate data directly into Accumulator. most important data transfer applications receive data from input ports transfer data output ports. Arithmetic Operations ability perform certain arithmetic operations data manipulation necessary feature most microcontroller applications. Within Holtek microcontroller instruction range subtract instruction mnemonics enable necessary arithmetic carried out. Care must taken ensure correct handling carry borrow data when results exceed addition less than subtraction. increment decrement instructions INC, INCA, DECA provide simple means increasing decreasing value values destination specified. Logical Rotate Operations standard logical operations such AND, have their instruction within Holtek microcontroller instruction set. with case most instructions involving data manipulation, data must pass through Accumulator which involve additional programming steps. logical data operations, zero flag result operation zero. Another form logical data manipulation comes from rotate instructions such which provide simple means rotating right left. Different rotate instructions exist depending program requirements. Rotate instructions useful serial port programming applications where data rotated from internal register into Carry from where examined necessary serial high low. Another application where rotate data operations used implement multiplication division calculations. Branches Control Transfer Program branching takes form either jumps specified locations using instruction subroutine using CALL instruction. They differ sense that case subroutine call, program must return instruction immediately when subroutine been carried out. This done placing return instruction subroutine which will cause program jump back address right after CALL instruction. case instruction, program simply jumps desired location. There requirement jump back original jumping point case CALL instruction. special extremely useful branch instructions conditional branches. Here decision first made regarding condition certain data memory individual bits. Depending upon conditions, program will continue with next instruction skip over jump following instruction. These instructions decision making branching within program perhaps determined condition certain input switches condition internal data bits.
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Operations ability provide single operations Data Memory extremely flexible feature Holtek microcontrollers. This feature especially useful output port programming where individual bits port pins directly high using either instructions respectively. feature removes need programmers first read 8-bit output port, manipulate input data ensure that other bits changed then output port with correct data. This read-modify-write process taken care automatically when these operation instructions used. Table Read Operations Data storage normally implemented using registers. However, when working with large amounts fixed data, volume involved often makes inconvenient store fixed data Data Memory. overcome this problem, Holtek microcontrollers allow area Program Memory setup table where data directly stored. easy instructions provides means which this fixed data referenced retrieved from Program Memory. Other Operations addition above functional instructions, range other instructions also exist such instruction Power-down operations instructions control operation Watchdog Timer reliable program operations under extreme electric electromagnetic environments. their relevant operations, refer functional related sections. Instruction Summary following table depicts summary instruction categorised according function consulted basic instruction reference using following listed conventions. Table conventions: Bits immediate data Data Memory address Accumulator number bits addr: Program memory address
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA INCA DECA
Description
Cycles
Flag Affected
Data Memory Data Memory immediate data Data Memory with Carry Data memory with Carry Subtract immediate data from Subtract Data Memory from Subtract Data Memory from with result Data Memory Subtract Data Memory from with Carry Subtract Data Memory from with Carry, result Data Memory Decimal adjust Addition with result Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical immediate Data Logical immediate Data Logical immediate Data Complement Data Memory Complement Data Memory with result Increment Data Memory with result Increment Data Memory Decrement Data Memory with result Decrement Data Memory
1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note
Logic Operation
Increment Decrement
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Mnemonic Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT operation Clear Data Memory Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles Data Memory Swap nibbles Data Memory with result Enter power down mode 1Note 1Note 1Note None None None None None Read table (current page) TBLH Data Memory Read table (last page) TBLH Data Memory 2Note 2Note None None Jump unconditionally Skip Data Memory zero Skip Data Memory zero with data movement Skip Data Memory zero Skip Data Memory zero Skip increment Data Memory zero Skip decrement Data Memory zero Skip increment Data Memory zero with result Skip decrement Data Memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note None None None None None None None None None None None None None Clear Data Memory Data Memory 1Note 1Note None None Move Data Memory Move Data Memory Move immediate data 1Note None None None Rotate Data Memory right with result Rotate Data Memory right Rotate Data Memory right through Carry with result Rotate Data Memory right through Carry Rotate Data Memory left with result Rotate Data Memory left Rotate Data Memory left through Carry with result Rotate Data Memory left through Carry 1Note 1Note 1Note 1Note None None None None Description Cycles Flag Affected
Note: skip instructions, result comparison involves skip then cycles required, skip takes place only cycle required. instruction which changes contents will also require cycles execution. instructions flags affected execution status. flags cleared after both instructions consecutively executed. Otherwise flags remain unchanged.
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Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored Accumulator. Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored specified Data Memory. Data Memory contents specified Data Memory Accumulator added. result stored Accumulator. immediate data contents Accumulator specified immediate data added. result stored Accumulator. Data Memory contents specified Data Memory Accumulator added. result stored specified Data Memory. Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory.
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CALL addr Description Subroutine call Unconditionally calls subroutine specified address. Program Counter then increments obtain address next instruction which then pushed onto stack. specified address then loaded program continues execution from this address. this instruction requires additional operation, cycle instruction. Stack Program Counter Program Counter addr None Clear Data Memory Each specified Data Memory cleared None Clear Data Memory specified Data Memory cleared [m].i None Clear Watchdog Timer flags cleared. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT2 must executed alternately with WDT2 have effect. Repetitively executing this instruction without alternately executing WDT2 will have effect. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT1 must executed alternately with WDT1 have effect. Repetitively executing this instruction without alternately executing WDT1 will have effect. cleared
Operation Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description Operation
Affected flag(s) WDT1 Description
Operation
Affected flag(s) WDT2 Description
Operation
Affected flag(s)
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Description Operation Affected flag(s) CPLA Description Complement Data Memory Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. Complement Data Memory with result Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. complemented result stored Accumulator contents Data Memory remain unchanged. Decimal-Adjust addition with result Data Memory Convert contents Accumulator value Binary Coded Decimal) value resulting from previous addition variables. nibble greater than flag set, then value will added nibble. Otherwise nibble remains unchanged. high nibble greater than flag set, then value will added high nibble. Essentially, decimal conversion performed adding 00H, 06H, depending Accumulator flag conditions. Only flag affected this instruction which indicates that original greater than 100, allows multiple precision decimal addition. Decrement Data Memory Data specified Data Memory decremented Decrement Data Memory with result Data specified Data Memory decremented result stored Accumulator. contents Data Memory remain unchanged. Enter power down mode This instruction stops program execution turns system clock. contents Data Memory registers retained. prescaler cleared. power down flag time-out flag cleared.
Operation Affected flag(s) Description
Operation
Affected flag(s) Description Operation Affected flag(s) DECA Description Operation Affected flag(s) HALT Description
Operation Affected flag(s)
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HT48RU80/HT48CU80
Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Increment Data Memory Data specified Data Memory incremented Increment Data Memory with result Data specified Data Memory incremented result stored Accumulator. contents Data Memory remain unchanged. Jump unconditionally contents Program Counter replaced with specified address. Program execution then continues from this address. this requires insertion dummy instruction while address loaded, cycle instruction. Program Counter addr None Move Data Memory contents specified Data Memory copied Accumulator. None Move immediate data immediate data specified loaded into Accumulator. None Move Data Memory contents Accumulator copied specified Data Memory. None operation operation performed. Execution continues with next instruction. operation None Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator.
Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s)
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HT48RU80/HT48CU80
Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Description Operation Affected flag(s) RETI Description Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Return from subroutine Program Counter restored from stack. Program execution continues restored address. Program Counter Stack None Return from subroutine load immediate data Program Counter restored from stack Accumulator loaded with specified immediate data. Program execution continues restored address. Program Counter Stack None Return from interrupt Program Counter restored from stack interrupts re-enabled setting bit. master interrupt global enable bit. interrupt pending when RETI instruction executed, pending Interrupt routine will processed before returning main program. Program Counter Stack None Rotate Data Memory left contents specified Data Memory rotated left with rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 None Rotate Data Memory left with result contents specified Data Memory rotated left with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 None
Operation Affected flag(s) Description Operation Affected flag(s) Description
Operation Affected flag(s)
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HT48RU80/HT48CU80
Description Operation Rotate Data Memory left through Carry contents specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 Rotate Data Memory left through Carry with result Data specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 Rotate Data Memory right contents specified Data Memory rotated right with rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 None Rotate Data Memory right with result Data specified Data Memory carry flag rotated right with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry contents specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 Rotate Data Memory right through Carry with result Data specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0
Affected flag(s) RLCA Description
Operation
Affected flag(s) Description Operation Affected flag(s) Description
Operation Affected flag(s) Description Operation
Affected flag(s) RRCA Description
Operation
Affected flag(s)
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HT48RU80/HT48CU80
A,[m] Description Subtract Data Memory from with Carry contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with Carry result Data Memory contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Skip decrement Data Memory contents specified Data Memory first decremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip decrement Data Memory zero with result contents specified Data Memory first decremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Data Memory Each specified Data Memory None Data Memory specified Data Memory [m].i None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s) SDZA Description
Operation Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s)
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HT48RU80/HT48CU80
Description Skip increment Data Memory contents specified Data Memory first incremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip increment Data Memory zero with result contents specified Data Memory first incremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Subtract Data Memory from specified Data Memory subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with result Data Memory specified Data Memory subtracted from contents Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract immediate data from immediate data specified code subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will
Operation Affected flag(s) SIZA Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s)
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HT48RU80/HT48CU80
SWAP Description Operation Affected flag(s) SWAPA Description Operation Affected flag(s) Description Swap nibbles Data Memory low-order high-order nibbles specified Data Memory interchanged. [m].3~[m].0 [m].7 [m].4 None Swap nibbles Data Memory with result low-order high-order nibbles specified Data Memory interchanged. result stored Accumulator. contents Data Memory remain unchanged. ACC.3 ACC.0 [m].7 [m].4 ACC.7 ACC.4 [m].3 [m].0 None Skip Data Memory contents specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory with data movement contents specified Data Memory copied Accumulator. value zero, following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Read table (current page) TBLH Data Memory byte program code (current page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None Read table (last page) TBLH Data Memory byte program code (last page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None
Operation Affected flag(s) Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) TABRDC Description Operation Affected flag(s) TABRDL Description Operation Affected flag(s)
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HT48RU80/HT48CU80
A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator.
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Package Information
48-pin SSOP (300mil) Outline Dimensions
Symbol
Dimensions Min. Nom. Max.
Rev. 1.30
January 2009
HT48RU80/HT48CU80
64-pin LQFP Outline Dimensions
Symbol
Dimensions Min. 0.13 1.35 0.05 0.45 0.09 Nom. Max. 0.23 1.45 0.15 0.75 0.20
Rev. 1.30
January 2009
HT48RU80/HT48CU80
Product Tape Reel Specifications
Reel Dimensions
SSOP Symbol Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Slit Width Space Between Flange Reel Thickness Dimensions 330.0±1.0 100.0±0.1 13.0+0.5/-0.2 2.0±0.5 32.2+0.3/-0.2 38.2±0.2
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HT48RU80/HT48CU80
Carrier Tape Dimensions
llip
SSOP Symbol Description Carrier Tape Width Cavity Pitch Perforation Position Cavity Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions 32.0±0.3 16.0±0.1 1.75±0.10 14.2±0.1 Min. 1.50+0.25/-0.00 4.0±0.1 2.0±0.1 12.0±0.1 16.2±0.1 2.4±0.1 3.2±0.1 0.35±0.05 25.5±0.1
Rev. 1.30
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HT48RU80/HT48CU80
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Room, Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) Unit Productivity Building, Gaoxin 2nd, Middle Zone High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright 2009 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
Rev. 1.30
January 2009
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