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Tools Information FAQs Application Note HA0016E Writing Reading HT24 E


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HT48RA5/HT48CA5 Remote Type 8-Bit
Tools Information FAQs Application Note HA0016E Writing Reading HT24 EEPROM with HT48 Series HA0018E Controlling HT1621 Controller with HT48 Series HA0041E Using HT48CA0 Generate HT6221 Output Signals HA0075E Reset Oscillator Circuits Application Note HA0076E HT48RAx/HT48CAx Software Application Note HA0082E HT48xA0-1 HT48xA0-2 Power-on Reset Timing
Operating voltage: 2.0V~5.5V bidirectional lines (max.) interrupt input shared with line 8-bit programmable timer/event counter with HALT function wake-up feature reduce power
consumption
8-level subroutine nesting instruction cycle with 4MHz system clock
overflow interrupt 8-stage prescaler (TMR0)
16-bit programmable timer/event counter
VDD=3V
manipulation instruction 16-bit table read instruction powerful instructions instructions machine cycles voltage reset function 28-pin SOP/SSOP (209mil) package
overflow interrupts (TMR1)
On-chip crystal oscillator Watchdog Timer program memory banks) data memory supported
General Description
HT48RA5/HT48CA5 8-bit high performance, RISC architecture microcontroller devices specifically designed multiple control product applications. data used store remote control codes. mask version HT48CA5 fully functionally compatible with version HT48RA5 device. advantages power consumption, flexibility, timer functions, oscillator options, watchdog timer, programmable frequency divider, HALT wake-up functions, well cost, enhance versatility these devices suit wide range application possibilities such industrial control, consumer products, subsystem controllers, particularly suitable products such universal remote controller (URC).
Rev. 1.40
2009
HT48RA5/HT48CA5
Block Diagram
ifte
Assignment
Rev. 1.40
2009
HT48RA5/HT48CA5
Description
Name Code Option Wake-up* Pull-high*** Description Bidirectional 8-bit input/output port. Each configured wake-up input option. Software instructions determine CMOS output Schmitt trigger input with/without pull-high resistor. pull-high resistor each input/output line also optional. Bidirectional 8-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with/without pull-high resistor. pull-high resistor each input/output line also optional. output mode used internal signal output used various frequency carrier signal. Bidirectional 6-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with/without pull-high resistor. pull-high resistor each input/output line also optional. shared with TMR0 TMR1 function pins. Bidirectional 1-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with/without pull-high resistor. pull-high resistor this input/output line also optional. shared with function pin. OSC1, OSC2 connected network Crystal (determined option) internal system clock. case operation, OSC2 output terminal system clock. Schmitt trigger reset input, active low. Negative power supply, ground Positive power supply
PA0~PA7
PB0/PFD PB1~PB7
Pull-high**
PC0/TMR0 PC1~PC4 PC5/TMR1
Pull-high*
PF0/INT
Pull-high*
OSC1 OSC2 Note:
option Nibble option Byte option
Crystal
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Total .150mA Total Power Dissipation .500mW Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C Total.-100mA
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
Rev. 1.40
2009
HT48RA5/HT48CA5
D.C. Characteristics
Test Conditions Symbol IDD1 Parameter Operating Voltage Operating Current IDD2 Operating Current (Crystal OSC, OSC) Standby Current (WDT Enabled Standby Current (WDT Disabled) VIL1 VIH1 VIL2 VIH2 VLVR Input Voltage Ports Input High Voltage Ports Input Voltage (RES) Input High Voltage (RES) Voltage Reset Port Sink Current Port Source Current Pull-high Resistance VOH=0.9VDD LVR=2.0V LVR=3.0V VOL=0.1VDD load, system HALT load, system HALT load, fSYS=8MHz Conditions load, fSYS=4MHz 0.7VDD 0.9VDD 0.3VDD 0.4VDD Min. Typ. Max. Unit Ta=25°C
ISTB1
ISTB2
Rev. 1.40
2009
HT48RA5/HT48CA5
A.C. Characteristics
Test Conditions Symbol Parameter fSYS1 System Clock (Crystal OSC) Timer Frequency (TMR0/TMR1) tWDTOSC Watchdog Oscillator Period tWDT1 tWDT2 tRES tSST tLVR tINT Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (fSYS/4) External Reset Pulse Width System Start-up Timer Period Voltage Width Reset Interrupt Pulse Width Without prescaler Without prescaler Power-up reset wake-up from HALT 1024 1024 tSYS tSYS duty Conditions 2.0V~5.5V 3.3V~5.5V 2.0V~5.5V 3.3V~5.5V 4000 8000 4000 8000 4000 8000 Min. Typ. Max. Unit Ta=25°C
fSYS2
System Clock OSC)
fTIMER
Note: tSYS=1/(fSYS)
Power-on Reset Characteristics
Test Conditions Symbol VPOR RRVDD tPOR Parameter Start Voltage Ensure Power-on Reset raising rate Ensure Power-on Reset Minimum Time Stays VPOR Ensure Power-on Reset Conditions 0.05 V/ms Min. Typ. Max. Unit
Rev. 1.40
2009
HT48RA5/HT48CA5
Functional Description
Execution Flow system clock derived from either crystal oscillator. system clock internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. However, pipelining scheme causes each instruction effectively execute cycle. instruction changes program counter, cycles required complete instruction. Program Counter program counter (PC) controls sequence which instructions stored program executed contents specify full range program memory. After accessing program memory word fetch instruction code, contents program counter
incremented one. program counter then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call return from subroutine, initial reset, internal interrupt, external interrupt return from interrupts, manipulates program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction. Otherwise proceed next instruction. lower byte program counter (PCL) readable writeable register (06H). Moving data into performs short jump. destination will within current program page. When control transfer takes place, additional dummy cycle required.
Execution Flow
Program Counter Mode *15~*8 Initial Reset External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow Skip Loading Jump, Call Branch Return (RET, RETI) *15~*8 #15~#8 S15~S8 00000000 00000000 00000000 00000000
*15~*13 (*12~*0+2)=(within-current bank)
Program Counter Note: *15~*0: Program counter bits #15~#0: Instruction code bits bank: words S15~S0: Stack register bits @7~@0: bits
Rev. 1.40
2009
HT48RA5/HT48CA5
Program Memory program memory used store program instructions which executed. also contains data, table, interrupt entries, organized into banks, addressed program counter table pointer. Certain locations program memory reserved special usage:
Location 000H
itia
This area reserved program initialization. After chip reset, program always begins execution location 000H.
Location 004H
This area reserved external interrupt service program. input activated, interrupt enabled stack full, program begins execution location 004H.
Location 008H
This area reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 008H
Location 00CH
Program Memory terrupt(s) supposed disabled prior table read instruction. (They) will enabled until TBLH main routine been backup. table related instructions require cycles complete operation. Stack Register STACK This special part memory which used save contents program counter (PC) only. stack organized into levels neither part data part program space, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. subroutine call interrupt acknowledge signal, contents program counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), program counter restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag will recorded acknowledge signal will inhibited. When stack pointer decremented RETI), interrupt will serviced. This feature prevents stack overflow allowing programmer structure more easily. similar case, stack full subTable Location
This location reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Table location
location program memory used look-up tables. instructions (page specified TBHP) (the last page) transfer contents lower-order byte specified data memory, higher-order byte TBLH (08H). higher-order byte table pointer TBHP (1FH) lower-order byte table pointer TBLP (07H) read/write registers, which indicate table locations. Before accessing table, location placed TBHP TBLP. TBLH read only cannot restored. main routine (interrupt service routine) both employ table read instruction, contents TBLH main routine likely changed table read instruction used ISR. Errors thus brought about. Given this, using table read instruction main routine simultaneously should avoided. However, table read instruction applied both main routine ISR,
Instruction *15~*8 TABRDC TABRDL TBHP 10011111
Table Location Note: *15~*0: Table location bits @7~@0: Table pointer bits
Rev. 1.40
2009
HT48RA5/HT48CA5
sequently executed, stack overflow occurs first entry will lost (only most recent return addresses stored). Data Memory data memory designed with bits. data memory divided into functional groups: special function registers general purpose data memory Most read/write, some read only. special function registers include indirect addressing registers (R0;00H, R1;02H), bank pointer (BP;04H), Timer/Event Counter (TMR0;0DH), Timer/Event Counter control register (TMR0C;0EH), Timer/Event Counter higher order byte register (TMR1H;0FH), Timer/Event Counter lower order byte register (TMR1L;10H), Timer/Event Counter control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H, TBHP;1FH), table higher-order byte register (TBLH;08H), status register (STATUS; 0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), registers (PA;12H, PB;14H, PC;16H, PF;1CH), control registers (PAC;13H, PBC;15H, PCC;17H, PFC;1DH). remaining space before reserved future expanded usage reading these locations will general purpose data memory, addressed from FFH, used data control information under instruction commands. data memory areas handle arithmetic, logic, increment, decrement rotate operations directly. Except some dedicated bits, each data memory reset They also indirectly accessible through memory pointer registers (MP0 MP1). Indirect Addressing Register Location indirect addressing registers that physically implemented. read/write operation [00H] ([02H]) will access data memory pointed (MP1). Reading location (02H) itself indirectly will return result 00H. Writing indirectly results operation. memory pointer registers (MP0 MP1) 8-bit registers. Accumulator accumulator closely related operations. also mapped location data memory carry immediate data operations. data movement between data memory locations must pass through accumulator. Mapping
Arithmetic Logic Unit This circuit performs 8-bit arithmetic logic operations. provides following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, XOR, CPL) Increment decrement (INC, DEC) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ,
only saves results data operation also changes status register.
Rev. 1.40
2009
HT48RA5/HT48CA5
Status Register STATUS This 8-bit register (0AH) contains zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). also records status information controls operation sequence. With exception flags, bits status register altered instructions like most other registers. data written into status register will change flag. addition operations related status register give different results from those intended. flag affected only system power-up, time-out executing instruction. flag affected only executing instruction during system power-up. flags generally reflect status latest operations. addition, entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status important subroutine corrupt status register, precautions must taken save properly. Interrupt device provides external interrupt internal timer/event counter interrupts. Interrupt Control Register (INTC;0BH) contains interrupt control bits enable/disable interrupt request flags. Once interrupt subroutine serviced, other interrupts will blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests occur during this interval only interrupt request flag recorded. certain interBit Label rupt requires servicing within service routine, corresponding INTC allow interrupt nesting. stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack must prevented from becoming full. these kinds interrupts have wake-up capability. interrupt serviced, control transfer occurs pushing program counter onto stack, followed branch subroutine specified location program memory. Only program counter pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. External interrupts triggered high transition related interrupt request flag (EIF; INTC) will set. When interrupt enabled, stack full external interrupt active, subroutine call location will occur. interrupt request flag (EIF) bits will cleared disable other interrupts. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T0F; INTC), caused timer overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T0F) will reset cleared disable further interrupts. internal Timer/Even Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T1F;bit INTC), caused timer overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T1F) will reset cleared disable further interrupts. Function operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logic operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Status (0AH) Register
Rev. 1.40
2009
HT48RA5/HT48CA5
During execution interrupt subroutine, other interrupt acknowledge signals held until instruction executed related interrupt control stack full). return from interrupt subroutine, invoked. RETI will enable interrupt service, will not. Interrupts, occurring interval between rising edges consecutive pulses, will serviced latter pulses, corresponding interrupts enabled. case simultaneous requests following table shows priority that applied. These masked resetting bit. Interrupt Source External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow Priority Vector Oscillator Configuration There oscillator circuits implemented microcontroller.
illa
illa
System Oscillator Both them designed system clocks, namely oscillator crystal oscillator, which determined options. matter what oscillator type selected, signal provides system clock. HALT mode stops system oscillator resists external signal conserve power. oscillator used, external resistor between OSC1 required resistance should range from 100kW 820kW. system clock, divided available OSC2, which used synchronize external logic. internal oscillator provides most cost effective solution. However, frequency oscillation vary with VDD, temperatures chip itself process variations. therefore, suitable timing sensitive operations where accurate oscillator frequency desired. crystal oscillator used, crystal across OSC1 OSC2 needed provide feedback phase shift required oscillator, other external components demanded. Instead crystal, resonator also connected between OSC1 OSC2 frequency reference, external capacitors OSC1 OSC2 required. oscillator free running on-chip oscillator, external components required. Even system enters power down mode, system clock stopped, oscillator still works with period approximately 90ms. oscillator disabled code option conserve power. Function
Timer/Event Counter interrupt request flag (T0F/T1F), external interrupt request flag (EIF), enable Timer/Event Counter interrupt (ET0I/ET1I), enable external interrupt (EEI) enable master interrupt (EMI) constitute interrupt control register (INTC) which located data memory. EMI, EEI, ET0I ET1I used control enabling/disabling interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (T0F, T1F, EIF) set, they will remain INTC register until interrupts serviced cleared software instruction. recommended that program does within interrupt subroutine. Interrupts often occur unpredictable manner need serviced immediately some applications. only stack left enabling interrupt well controlled, original control sequence will damaged once operates interrupt subroutine.
Label ET0I ET1I
Controls master (global) interrupt enabled; disabled) Controls external interrupt enabled; disabled) Controls Timer/Event Counter interrupt enabled; disabled) Controls Timer/Event Counter interrupt enabled; disabled) External interrupt request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Unused bit, read INTC (0BH) Register
Rev. 1.40
2009
HT48RA5/HT48CA5
Watchdog Timer clock source implemented dedicated oscillator (WDT oscillator), instruction clock (system clock divided determines code option. This timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. Watchdog Timer disabled code option. Watchdog Timer disabled, executions related result operation. Once internal oscillator oscillator with period 90ms@3V normally) selected, first divided (8-stage) nominal time-out period 23ms@3V. This time-out period vary with temperatures, process variations. invoking prescaler, longer time-out periods realized. Writing data WS2, WS1, (bit 2,1,0 WDTS) give different time-out periods. WS2, WS1, equal division ratio 1:128, maximum time-out period 2.9s@3V seconds. oscillator disabled, clock still come from instruction clock operates same manner except that HALT state stop counting lose protecting purpose. this situation logic only restarted external logic. high nibble WDTS reserved defined flags, which used indicate some specified status. device operates noisy environment, using on-chip oscillator (WDT OSC) strongly recommended, since HALT will stop system clock. WDTS Register Division Ratio 1:16 1:32 1:64 1:128 overflow under normal operation will initialize status HALT mode, overflow will initialize only program counter reset zero. clear contents (including prescaler), three methods adopted; external reset level RES), software instruction instruction. software instruction include other these types instruction, only active depending code option times selection option. selected (i.e. times equal one), execution instruction will clear WDT. case that chosen (i.e. times equal two), these instructions must executed clear WDT; otherwise, reset chip result time-out. Power Down Operation HALT HALT mode initialized instruction results following.
system oscillator will turned
oscillator remains running oscillator selected).
contents chip registers remain
unchanged.
prescaler will cleared
counted again clock from oscillator).
ports maintain their original status. flag flag cleared.
system leave HALT mode means external reset, interrupt, external falling edge signal port overflow. external reset causes device initialization overflow performs After flags examined, reason chip reset determined. flag cleared system power-up executing instruction when executing instruction. flag time-out occurs, causes wake-up that only resets program counter others remain their original status.
Watchdog Timer
Rev. 1.40
2009
HT48RA5/HT48CA5
port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake device mask option. Awakening from port stimulus, program will resume execution next instruction. awakens from interrupt, sequence occur. related interrupt disabled interrupt enabled stack full, program will resume execution next instruction. interrupt enabled stack full, regular interrupt response takes place. interrupt request flag before entering HALT mode, wake-up function related interrupt will disabled. Once wake-up event occurs, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period will inserted after wake-up. wake-up results from interrupt acknowledge signal, actual interrupt subroutine execution will delayed more cycles. wake-up results next instruction execution, this will executed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT status. Reset There three ways which reset occur:
reset during normal operation reset during HALT time-out reset during normal operation
functional unit chip reset status shown below. Program Counter Interrupt Prescaler Timer/event Counter Input/output Ports Stack Pointer 000H Disable Clear Clear. After master reset, begins counting Input mode Points stack
Reset Timing Chart
time-out during HALT different from other chip reset conditions, since perform that resets only program counter leaving other circuits their original state. Some registers remain unchanged during other reset conditions. Most registers reset when reset conditions met. examining flags, program distinguish between different RESET Conditions reset during power-up reset during normal operation wake-up HALT time-out during normal operation wake-up HALT
Reset Circuit Note: Most applications Basic Reset Circuit shown, however applications with extensive noise, recommended Hi-noise Reset Circuit.
Note: stands unchanged guarantee that system oscillator started stabilized, (System Start-up Timer) provides extra-delay 1024 system clock pulses when system reset (power-up, time-out reset) system awakes from HALT state. When system reset occurs, delay added during reset period. wake-up from HALT will enable delay. Rev. 1.40
Reset Configuration
2009
HT48RA5/HT48CA5
states registers summarized table. Register Program Counter TBLP TBHP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1H TMR1L TMR1C Note: Reset (Power xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx xxxx xxxx 0000 0111 xxxx -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1-1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 stands warm reset stands unchanged stands unknown Time-out (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1-1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 Reset (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1-1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1-1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u-uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Rev. 1.40
2009
HT48RA5/HT48CA5
Timer/Event Counter timer/event counters (TMR0, TMR1) implemented device. Timer/Event Counter contains 8-bit programmable count-up counter clock come from external source system clock. Timer/Event Counter contains 16-bit programmable count-up counter clock come from external source system clock divided timer/event counters, using external clock input allows user count external events, measure time internals pulse widths, generate accurate time base. While using internal clock allows user generate accurate time base. Only Timer/Event Counter generate signal using external internal clock, frequency determine equation There registers related Timer/Event Counter TMR0(0DH), TMR0C(0EH). Timer/Event Counter counting mode (T0ON=1), writing TMR0 will only written data preload register bits). Timer/Event Counter preload register changed each writing TMR0 operations. Reading TMR0 will also latch TMR0 destination. TMR0C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. T0M0, T0M1 bits define operating mode. event count mode used count external events, which means clock source comes from external (TMR0) pin. timer mode functions normal timer with clock source coming from fINT clock. pulse width measurement mode used count high level duration external signal (TMR0). counting based fINT clock. event count timer mode, once Timer/Event Counter starts counting, will count from current contents Timer/Event Counter FFH. Once overflow occurs, counter reloaded from Timer/Event Counter preload register generates corresponding interrupt request flag (T0F; INTC) same time. pulse width measurement mode with T0ON bits equal one, once TMR0 received transition from high high will start counting until TMR0 returns original level reset T0ON. measured result will remain Timer/Event Counter even activated transition occurs again. other words, only cycle measurement done. Until setting T0ON, cycle measurement will function again long receives further transition pulse. Note that, this operating mode, Timer/Event Counter starts counting according logic level according transition edges. case counter overflows, counter reloaded from Timer/Event Counter Rev. 1.40 preload register issues interrupt request just like other modes. enable counting operation, timer (T0ON; TMR0C) should pulse width measurement mode, T0ON will cleared automatically after measurement cycle complete. other modes T0ON only reset instructions. overflow Timer/Event Counter wake-up sources. matter what operation mode writing ET0I disabled corresponding interrupt service. case Timer/Event Counter condition, writing data Timer/Event Counter preload register will also load data Timer/Event Counter Timer/Event Counter turned data written Timer/Event Counter will only kept Timer/Event Counter preload register. Timer/Event Counter will still operate until overflow occurs Timer/Event Counter reloading will occur same time). When Timer/Event Counter (reading TMR0) read, clock will blocked avoid errors. this results counting error, this must taken into consideration programmer. TMR0C used define pre-scaling stages internal clock sources Timer/Event Counter definitions shown. Label Function
define prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS/2 001: fINT=fSYS/4 T0PSC0 010: fINT=fSYS/8 T0PSC1 011: fINT=fSYS/16 T0PSC2 100: fINT=fSYS/32 101: fINT=fSYS/64 110: fINT=fSYS/128 111: fINT=fSYS/256 define TMR0 active edge Timer/Event Counter (0=active high; 1=active high low) enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read define operating mode (T0M1, T0M0) 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register
T0ON
T0M0 T0M1
2009
HT48RA5/HT48CA5
There registers related Timer/Event Counter TMR1H(0FH), TMR1L(10H), TMR1C(11H). Writing TMR1L will only written data internal lower-order byte buffer bits) writing TMR1H will transfer specified data contents lower-order byte buffer TMR1H TMR1L preload registers, respectively. Timer/Event Counter preload register changed each writing TMR1H operations. Reading TMR1H will latch contents TMR1H TMR1L counters destination lower-order byte buffer, respectively. Reading TMR1L will read contents lower-order byte buffer. TMR1C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. T1M0, T1M1 bits define operating mode. event count mode used count external events, which means clock source comes from external (TMR1) pin. timer mode functions normal timer with clock source coming from instruction clock. pulse width measurement mode used count high level duration external signal (TMR1). counting based instruction clock. event count timer mode, once Timer/Event Counter starts counting, will count from current contents Timer/Event Counter FFFFH. Once overflow occurs, counter reloaded from Timer/Event Counter preload register generates corresponding interrupt request flag (T1F; INTC) same time.
pulse width measurement mode with T1ON bits equal one, once TMR1 received transition from high high will start counting until TMR1 returns original level reset T1ON. measured result will remain Timer/Event Counter even activated transition occurs again. other words, only cycle measurement done. Until setting T1ON, cycle measurement will function again long receives further transition pulse. Note that, this operating mode, Timer/Event Counter starts counting according logic level according transition edges. case counter overflows, counter reloaded from Timer/Event Counter preload register issues interrupt request just like other modes. enable counting operation, timer (T1ON; TMR1C) should pulse width measurement mode, T1ON will cleared automatically after measurement cycle complete. other modes T1ON only reset instructions. overflow Timer/Event Counter wake-up sources. matter what operation mode writing ET1I disabled corresponding interrupt service. case Timer/Event Counter condition, writing data Timer/Event Counter preload register will also load data Timer/Event Counter Timer/Event Counter turned data written Timer/Event Counter will only kept
Timer/Event Counter
Timer/Event Counter
Rev. 1.40
2009
HT48RA5/HT48CA5
Timer/Event Counter preload register. Timer/Event Counter will still operate until overflow occurs Timer/Event Counter reloading will occur same time). When Timer/Event Counter (reading TMR1H) read, clock will blocked avoid errors. this results counting error, this must taken into consideration programmer. definitions TMR1C shown. Label Function Unused bit, read define active edge TMR1 input signal (0/1: active high/high low) enable/disable timer counting (0/1: disabled/enabled) Unused bit, read define operating mode (T1M1, T1M0) 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Input/Output Ports There bi-directional input/output lines micro-controller, labeled from which mapped data memory [12H], [14H], [16H] [1CH], respectively. these ports used input output operations. input operation, these ports non-latching, that inputs must ready rising edge instruction 12H, 14H, 1CH). output operation, data latched remains unchanged until output latch rewritten. Each line control register (PAC, PBC, PCC, PFC) control input/output configuration. With this control register, CMOS output Schmitt trigger input with without (depends options) pull-high resistor structures reconfigured dynamically (i.e., on-the fly) under software control. function input, corresponding latch control register pull-high resistor pull-high resistor enabled) will exhibited automatically. input sources also depends control register. control register input will read state read-modify-write instructions"). control register contents latches will move internal data read-modify-write instructions). input paths (pad state latches) read-modify-write instructions dependent control register bits. output function, CMOS only configuration. These control registers mapped locations 13H, 15H, 1DH.
T1ON
T1M0 T1M1
Input/Output Ports
Rev. 1.40
2009
HT48RA5/HT48CA5
After chip reset, these input/output lines stay high levels (pull-high options) floating state (non-pull-high options). Each these input/output latches cleared (m=12H, 14H, 1CH) instructions. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. Each line port capability waking-up device. highest bits port bits port physically implemented; reading them returned whereas writing then results no-operation. Pull-high resistors each port decided option bit. pin-shared with signal, respectively. option selected, output signal output mode will signal. input mode always remain original functions. pin-shared with TMR0. signal directly connected PF0. output signal output mode) controlled data register only. truth table PB0/PFD listed below. truth table PB0/PFD shown. (15H) Bit0 PB0/PFD Option (14H) Bit0 Status Note: When calling subroutine interrupt event occurring, contents program counter save into stack registers. returning from subroutine occurs, contents program counter will restore from stack registers. BP.7 BP.6 BP.5 Bank0 Bank1 Bank2 Bank3 Bank4 Bank Pointer Voltage Reset microcontroller provides voltage reset circuit order monitor supply voltage device. supply voltage device within range 0.9V~VLVR, such changing battery, will automatically reset device internally. includes following specifications:
voltage (0.9V~VLVR) remain their
Address 0000H~1FFFH 2000H~3FFFH 4000H~5FFFH 6000H~7FFFH 8000H~9FFFH
original state exceed 1ms. voltage state does exceed 1ms, will ignore perform reset function.
uses function with external
signal perform chip reset. relationship between VLVR shown below.
Input; Output; Data
Bank Pointer There bank pointer used control program flow banks. bank contains address space. contents bank pointer load into program counter when CALL instruction executed. program counter 16-bit register whose contents used specify executed instruction addresses.
Rev. 1.40
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HT48RA5/HT48CA5
Voltage Reset Note: make sure that system oscillator stabilized, provides extra delay 1024 system clock pulses before entering normal operation. Since voltage maintained original state exceed 1ms, therefore delay enters reset mode.
Options following table shows kinds code option MCU. mask options must defined ensure proper system functioning. Function PA0~PA7 wake-up enable disable options pull-high enable disable pull-high enable disable: Byte option pull-high enable disable pull-high (PB0~PB3, PB4~PB7) enable disable: Nibble option instructions System oscillators: crystal enable disable clock source: WDTOSC system clock/4 function: enable disable voltage: 2.0V 3.0V
Rev. 1.40
2009
HT48RA5/HT48CA5
Application Circuits
illa
illa
Note:
Crystal/resonator system oscillators crystal oscillators, only required some crystal frequencies ensure oscillation. resonator applications normally required oscillation occur. most applications necessary However function disabled, required stop oscillator when falls below operating range, recommended that added. values should selected consultation with crystal/resonator manufacturer specifications. Reset circuit reset circuit resistance capacitance values should chosen ensure that stable remains within operating voltage range before reaches high level. Ensure that length wiring connected kept short possible, avoid noise interference. applications where noise interfere with reset circuit details oscillator external components, refer Application Note HA0075E more information.
Rev. 1.40
2009
HT48RA5/HT48CA5
Example
Rev. 1.40
2009
HT48RA5/HT48CA5
Instruction
Introduction oper microcontroller instruction set, which program instruction codes that directs microcontroller perform certain operations. case Holtek microcontrollers, comprehensive flexible over instructions provided enable programmers implement their application with minimum programming overheads. easier understanding various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions implemented within instruction cycle. exceptions this branch, call, table read instructions where instruction cycles required. instruction cycle equal system clock cycles, therefore case 8MHz system oscillator, most instructions would implemented within 0.5ms branch call instructions would implemented within 1ms. Although instructions which require more cycle implement generally limited JMP, CALL, RET, RETI table read instructions, important realize that other instructions which involve manipulation Program Counter register will also take more cycle implement. instructions which change contents will imply direct jump that address, more cycle will required. Examples such instructions would PCL, case skip instructions, must noted that result comparison involves skip operation then this will also take more cycle, skip involved then only cycle required. Moving Transferring Data transfer data within microcontroller program most frequently used operations. Making three kinds instructions, data transferred from registers Accumulator vice-versa well being able move specific immediate data directly into Accumulator. most important data transfer applications receive data from input ports transfer data output ports. Arithmetic Operations ability perform certain arithmetic operations data manipulation necessary feature most microcontroller applications. Within Holtek microcontroller instruction range subtract instruction mnemonics enable necessary arithmetic carried out. Care must taken ensure correct handling carry borrow data when results exceed addition less than subtraction. increment decrement instructions INC, INCA, DECA provide simple means increasing decreasing value values destination specified. Logical Rotate Operations standard logical operations such AND, have their instruction within Holtek microcontroller instruction set. with case most instructions involving data manipulation, data must pass through Accumulator which involve additional programming steps. logical data operations, zero flag result operation zero. Another form logical data manipulation comes from rotate instructions such which provide simple means rotating right left. Different rotate instructions exist depending program requirements. Rotate instructions useful serial port programming applications where data rotated from internal register into Carry from where examined necessary serial high low. Another application where rotate data operations used implement multiplication division calculations. Branches Control Transfer Program branching takes form either jumps specified locations using instruction subroutine using CALL instruction. They differ sense that case subroutine call, program must return instruction immediately when subroutine been carried out. This done placing return instruction subroutine which will cause program jump back address right after CALL instruction. case instruction, program simply jumps desired location. There requirement jump back original jumping point case CALL instruction. special extremely useful branch instructions conditional branches. Here decision first made regarding condition certain data memory individual bits. Depending upon conditions, program will continue with next instruction skip over jump following instruction. These instructions decision making branching within program perhaps determined condition certain input switches condition internal data bits.
Rev. 1.40
2009
HT48RA5/HT48CA5
Operations ability provide single operations Data Memory extremely flexible feature Holtek microcontrollers. This feature especially useful output port programming where individual bits port pins directly high using either instructions respectively. feature removes need programmers first read 8-bit output port, manipulate input data ensure that other bits changed then output port with correct data. This read-modify-write process taken care automatically when these operation instructions used. Table Read Operations Data storage normally implemented using registers. However, when working with large amounts fixed data, volume involved often makes inconvenient store fixed data Data Memory. overcome this problem, Holtek microcontrollers allow area Program Memory setup table where data directly stored. easy instructions provides means which this fixed data referenced retrieved from Program Memory. Other Operations addition above functional instructions, range other instructions also exist such instruction Power-down operations instructions control operation Watchdog Timer reliable program operations under extreme electric electromagnetic environments. their relevant operations, refer functional related sections. Instruction Summary following table depicts summary instruction categorised according function consulted basic instruction reference using following listed conventions. Table conventions: Bits immediate data Data Memory address Accumulator number bits addr: Program memory address
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA INCA DECA
Description Data Memory Data Memory immediate data Data Memory with Carry Data memory with Carry Subtract immediate data from Subtract Data Memory from Subtract Data Memory from with result Data Memory Subtract Data Memory from with Carry Subtract Data Memory from with Carry, result Data Memory Decimal adjust Addition with result Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical immediate Data Logical immediate Data Logical immediate Data Complement Data Memory Complement Data Memory with result Increment Data Memory with result Increment Data Memory Decrement Data Memory with result Decrement Data Memory
Cycles 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note
Flag Affected
Logic Operation
Increment Decrement
Rev. 1.40
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HT48RA5/HT48CA5
Mnemonic Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT Note: operation Clear Data Memory Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles Data Memory Swap nibbles Data Memory with result Enter power down mode 1Note 1Note 1Note None None None None None Read table (current page) TBLH Data Memory Read table (last page) TBLH Data Memory 2Note 2Note None None Jump unconditionally Skip Data Memory zero Skip Data Memory zero with data movement Skip Data Memory zero Skip Data Memory zero Skip increment Data Memory zero Skip decrement Data Memory zero Skip increment Data Memory zero with result Skip decrement Data Memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note None None None None None None None None None None None None None Clear Data Memory Data Memory 1Note 1Note None None Move Data Memory Move Data Memory Move immediate data 1Note None None None Rotate Data Memory right with result Rotate Data Memory right Rotate Data Memory right through Carry with result Rotate Data Memory right through Carry Rotate Data Memory left with result Rotate Data Memory left Rotate Data Memory left through Carry with result Rotate Data Memory left through Carry 1Note 1Note 1Note 1Note None None None None Description Cycles Flag Affected
skip instructions, result comparison involves skip then cycles required, skip takes place only cycle required. instruction which changes contents will also require cycles execution. instructions flags affected execution status. flags cleared after both instructions consecutively executed. Otherwise flags remain unchanged.
Rev. 1.40
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HT48RA5/HT48CA5
Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.40 Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored Accumulator. Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored specified Data Memory. Data Memory contents specified Data Memory Accumulator added. result stored Accumulator. immediate data contents Accumulator specified immediate data added. result stored Accumulator. Data Memory contents specified Data Memory Accumulator added. result stored specified Data Memory. Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. 2009
HT48RA5/HT48CA5
CALL addr Description Subroutine call Unconditionally calls subroutine specified address. Program Counter then increments obtain address next instruction which then pushed onto stack. specified address then loaded program continues execution from this address. this instruction requires additional operation, cycle instruction. Stack Program Counter Program Counter addr None Clear Data Memory Each specified Data Memory cleared None Clear Data Memory specified Data Memory cleared [m].i None Clear Watchdog Timer flags cleared. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT2 must executed alternately with WDT2 have effect. Repetitively executing this instruction without alternately executing WDT2 will have effect. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT1 must executed alternately with WDT1 have effect. Repetitively executing this instruction without alternately executing WDT1 will have effect. cleared
Operation
Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description Operation
Affected flag(s) WDT1 Description
Operation
Affected flag(s) WDT2 Description
Operation
Affected flag(s)
Rev. 1.40
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HT48RA5/HT48CA5
Description Operation Affected flag(s) CPLA Description Complement Data Memory Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. Complement Data Memory with result Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. complemented result stored Accumulator contents Data Memory remain unchanged. Decimal-Adjust addition with result Data Memory Convert contents Accumulator value Binary Coded Decimal) value resulting from previous addition variables. nibble greater than flag set, then value will added nibble. Otherwise nibble remains unchanged. high nibble greater than flag set, then value will added high nibble. Essentially, decimal conversion performed adding 00H, 06H, depending Accumulator flag conditions. Only flag affected this instruction which indicates that original greater than 100, allows multiple precision decimal addition. Decrement Data Memory Data specified Data Memory decremented Decrement Data Memory with result Data specified Data Memory decremented result stored Accumulator. contents Data Memory remain unchanged. Enter power down mode This instruction stops program execution turns system clock. contents Data Memory registers retained. prescaler cleared. power down flag time-out flag cleared.
Operation Affected flag(s) Description
Operation
Affected flag(s) Description Operation Affected flag(s) DECA Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
Rev. 1.40
2009
HT48RA5/HT48CA5
Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Increment Data Memory Data specified Data Memory incremented Increment Data Memory with result Data specified Data Memory incremented result stored Accumulator. contents Data Memory remain unchanged. Jump unconditionally contents Program Counter replaced with specified address. Program execution then continues from this address. this requires insertion dummy instruction while address loaded, cycle instruction. Program Counter addr None Move Data Memory contents specified Data Memory copied Accumulator. None Move immediate data immediate data specified loaded into Accumulator. None Move Data Memory contents Accumulator copied specified Data Memory. None operation operation performed. Execution continues with next instruction. operation None Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator.
Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s)
Rev. 1.40
2009
HT48RA5/HT48CA5
Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Description Operation Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Return from subroutine Program Counter restored from stack. Program execution continues restored address. Program Counter Stack None Return from subroutine load immediate data Program Counter restored from stack Accumulator loaded with specified immediate data. Program execution continues restored address. Program Counter Stack None Return from interrupt Program Counter restored from stack interrupts re-enabled setting bit. master interrupt global enable bit. interrupt pending when RETI instruction executed, pending Interrupt routine will processed before returning main program. Program Counter Stack None Rotate Data Memory left contents specified Data Memory rotated left with rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 None Rotate Data Memory left with result contents specified Data Memory rotated left with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) Description Operation
Affected flag(s) Description
Operation
Affected flag(s)
Rev. 1.40
2009
HT48RA5/HT48CA5
Description Operation Rotate Data Memory left through Carry contents specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 Rotate Data Memory left through Carry with result Data specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 Rotate Data Memory right contents specified Data Memory rotated right with rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 None Rotate Data Memory right with result Data specified Data Memory carry flag rotated right with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry contents specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 Rotate Data Memory right through Carry with result Data specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0
Affected flag(s) RLCA Description
Operation
Affected flag(s) Description Operation
Affected flag(s) Description
Operation
Affected flag(s) Description Operation
Affected flag(s) RRCA Description
Operation
Affected flag(s)
Rev. 1.40
2009
HT48RA5/HT48CA5
A,[m] Description Subtract Data Memory from with Carry contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with Carry result Data Memory contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Skip decrement Data Memory contents specified Data Memory first decremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip decrement Data Memory zero with result contents specified Data Memory first decremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Data Memory Each specified Data Memory None Data Memory specified Data Memory [m].i None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s) SDZA Description
Operation
Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s)
Rev. 1.40
2009
HT48RA5/HT48CA5
Description Skip increment Data Memory contents specified Data Memory first incremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip increment Data Memory zero with result contents specified Data Memory first incremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Subtract Data Memory from specified Data Memory subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with result Data Memory specified Data Memory subtracted from contents Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract immediate data from immediate data specified code subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will
Operation Affected flag(s) SIZA Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s)
Rev. 1.40
2009
HT48RA5/HT48CA5
SWAP Description Operation Affected flag(s) SWAPA Description Operation Swap nibbles Data Memory low-order high-order nibbles specified Data Memory interchanged. [m].3~[m].0 [m].7 [m].4 None Swap nibbles Data Memory with result low-order high-order nibbles specified Data Memory interchanged. result stored Accumulator. contents Data Memory remain unchanged. ACC.3 ACC.0 [m].7 [m].4 ACC.7 ACC.4 [m].3 [m].0 None Skip Data Memory contents specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory with data movement contents specified Data Memory copied Accumulator. value zero, following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Read table (current page) TBLH Data Memory byte program code (current page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None Read table (last page) TBLH Data Memory byte program code (last page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None
Affected flag(s) Description
Operation Affected flag(s) Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) TABRDC Description Operation
Affected flag(s) TABRDL Description Operation
Affected flag(s)
Rev. 1.40
2009
HT48RA5/HT48CA5
A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator.
Rev. 1.40
2009
HT48RA5/HT48CA5
Package Information
28-pin (300mil) Outline Dimensions
MS-013
Symbol
Dimensions Min. Nom. Max.
Rev. 1.40
2009
HT48RA5/HT48CA5
28-pin SSOP (209mil) Outline Dimensions
MO-150
Symbol
Dimensions Min. 7.40 5.00 0.22 9.90 0.05 0.55 0.09 0.65 Nom. Max. 8.20 5.60 0.33 10.50 2.00 0.95 0.21
Rev. 1.40
2009
HT48RA5/HT48CA5
Product Tape Reel Specifications
Reel Dimensions
(300mil) Symbol Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Slit Width Space Between Flange Reel Thickness Dimensions 330.0±1.0 100.0±1.5 13.0
+0.5/-0.2
2.0±0.5 24.8
+0.3/-0.2
30.2±0.2
SSOP (209mil) Symbol Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Slit Width Space Between Flange Reel Thickness Dimensions 330.0±1.0 100.0±1.5 13.0
+0.5/-0.2
2.0±0.5 28.4
+0.3/-0.2
31.1 (max.)
Rev. 1.40
2009
HT48RA5/HT48CA5
Carrier Tape Dimensions
(300mil) Symbol Description Carrier Tape Width Cavity Pitch Perforation Position Cavity Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions 24.0±0.3 12.0±0.1 1.75±0.10 11.5±0.1 1.50
+0.1/-0.0 +0.25/-0.00
4.0±0.1 2.0±0.1 10.85±0.10 18.34±0.10 2.97±0.10 0.35±0.01 21.3±0.1
SSOP (209mil) Symbol Cavity Pitch Perforation Position Cavity Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions 24.0±0.3 12.0±0.1 1.75±0.10 11.5±0.1 1.50
+0.1/-0.0 +0.25/-0.00
4.0±0.2 2.0±0.1 8.4±0.1 10.65±0.10 2.4±0.1 0.30±0.05 21.3±0.1 2009
Rev. 1.40
HT48RA5/HT48CA5
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Room, Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) Unit Productivity Building, No.5 Gaoxin Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright 2009 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
Rev. 1.40
2009

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