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HT49R30A-1, HT49R50A-1, HT49R70A-1, HT49RU80 Type Handbook
Copyright 2006 HOLTEK SEMICONDUCTOR INC. rights reserved. Printed Taiwan. part this publication reproduced, stored retrieval system, transmitted form means, electronic, mechanical photocopying, recording, otherwise without prior written permission HOLTEK SEMICONDUCTOR INC.
Contents
Part Microcontroller Profile
Chapter Hardware Structure Introduction Features Technology Features Kernel Features Peripheral Features Selection Table Block Diagram Assignment Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics System Architecture Clocking Pipelining Program Counter Stack Arithmetic Logic Unit Program Memory Organization Special Vectors Managing Multiple Banks Look-up Table Table Program Example Data Memory Organization General Purpose Data Memory Special Purpose Data Memory Memory
Type
Special Function Registers Indirect Addressing Registers IAR0, IAR1 Memory Pointers MP0, Bank Pointer Accumulator Program Counter Register Look-up Table Registers TBLP, TBHP, TBLH Real Time Clock Control Register RTCC Status Register STATUS Interrupt Control Registers INTC0, INTC1, MFIC Timer/Event Counter Registers Input/Output Port Registers UART Registers USR, UCR1, UCR2, TXR/RXR, Input/Output Ports Pull-high Resistors Port Wake-up Pin-shared Functions Programming Considerations Liquid Crystal Display (LCD) Driver Memory Clock Driver Output Voltage Source Biasing Programming Considerations Timer/Event Counters Configuring Timer/Event Counter Input Clock Source Timer Registers TMR, TMR0, TMR1, TMR1L/TMR1H, TMR2L/TMR2H Timer Control Registers TMRC, TMR0C, TMR1C, TMR2C Configuring Timer Mode Configuring Event Counter Mode Configuring Pulse Width Measurement Mode Programmable Frequency Divider Interfacing Programming Considerations Interrupts Interrupt Registers Interrupt Priority External Interrupt Timer/Event Counter Interrupt Time Base Interrupt Real Time Clock Interrupt UART Interrupt Multi-Function Interrupt Programming Considerations Reset Initialization Reset
Universal Asynchronous Receiver/Transmitter UART UART Features UART External Interfacing UART Data Transfer Scheme UART Status Control Registers Baud Rate Generator Setting Controlling UART UART Transmitter UART Receiver.96 Managing Receiver Errors UART Interrupt Scheme Address Detect Mode .100 UART Operation Power Down Mode .100 UART Sample Program .101 Oscillator .101 System Clock Configurations .101 System Crystal/Ceramic Oscillator .102 System Oscillator .102 Oscillator .103 Watchdog Timer Oscillator .104 Internal Clock Source .104 Power Down Mode Wake-up .105 Power Down Mode .105 Entering Power Down Mode .105 Standby Current Considerations .105 Wake-up .106 Voltage Detector .107 Watchdog Timer .107 Buzzer .109 Configuration Options .110 Application Circuits .112
Part Programming Language .117
Chapter Instruction Introduction .119 Instruction .119 Instruction Timing .119 Moving Transferring Data .119 Arithmetic Operations .120 Logical Rotate Operations .120 Branches Control Transfer .120 Operations .120 Table Read Operations .121 Other Operations .121 Instruction Summary .121 Convention .121
Type
Chapter Instruction Definition .125 Chapter Assembly Language Cross Assembler .137 Notational Conventions .137 Statement Syntax .138 Name .138 Operation .138 Operand .138 Comment .139 Assembly Directives .139 Conditional Assembly Directives .139 File Control Directives .140 Program Directives .141 Data Definition Directives .144 Macro Directives .146 Assembly Instructions .148 Name .148 Mnemonic .148 Operand, Operator Expression .148 Miscellaneous .150 Forward References .150 Local Labels .150 Reserved Assembly Language Words .151 Cross Assembler Options .152 Assembly Listing File Format .152 Source Program Listing .152 Summary Assembly .153 Miscellaneous .153
Part Development Tools .155
Chapter Programming Tools .157 HT-IDE Development Environment .157 Holtek In-Circuit Emulator HT-ICE .158 HT-ICE Interface Card .158 Programmer .159 Adapter Card .159 System Configuration .159 HT-ICE Interface Card Settings .160 Installation .161 System Requirement .161 Hardware Installation .161 Software Installation .161
Chapter Quick Start .167 Step Create Project .167 Step Source Program Files Project .167 Step Build Project .167 Step Programming Device .167 Step Transmit Code Holtek .168 Chapter Simulator .169 Introduction .169 Panel Configuration File .169 Relationship Between Panel File Current Project .170 Selecting HT-LCDS .170 Panel Picture File .171 Setup Panel Configuration File .171 Setup Panel Configurations .171 Select Patterns Their Positions .172 Pattern .172 Delete Pattern .173 Change Pattern .173 Change Pattern Position .173 User-define Matrix .174 Define Pattern Using Panel Editor .174 Pattern Items Using Batch File .175 Selecting Color Panel .175 Simulating .176 Stop Simulation .176
Appendix .177
Appendix Device Characteristic Graphics .179 Appendix Package Information .187
Type
Preface
Preface
Since founding company, Holtek Semiconductor Inc. concentrated much design efforts area microcontroller development. Although supplying wide range semiconductor devices, microcontroller category always been product category within Holtek range, which will continue expand their devices increase functionality maturity. capitalizing substantial accumulated skills within dedicated microcontroller development department, Holtek been able release comprehensive range high quality low-cost microcontroller devices wide range application areas. some devices full-duplex asynchronous serial communications UART function integrated, giving these devices ability easily communicate with external serial interfaces. high quality embedded microcontroller solutions provide means customers greatly enhance functional contents their LCD-based products, which when combined with comprehensive range development tools provide designers with means reduce their design market times greatly increasing their added value. This handbook divided into three parts user convenience. Most details regarding general datasheet information device specification located within Part Information related microcontroller programming such device instruction set, instruction definition, assembly language directives found within Part Part relates Holtek range Development Tools where information found their installation use. compiling relevant data together handbook hope users Holtek range Type microcontroller devices will have their fingertips useful, complete simple means efficiently implement their microcontroller applications. efforts combine information device specifications, programming development tools into publication have produced handbook which with careful user should result trouble free designs maximum benefit being gained from many features Holtek microcontroller devices. recommend that users regularly check website latest updates handbook also welcome feedback comments from customers regarding further improvements.
Type
viii
Part Microcontroller Profile Part
Microcontroller Profile
Type
Chapter Hardware Structure Chapter
Hardware Structure
This section main datasheet section Type microcontroller handbook contains parameters information related hardware. information contained provides designers with details main hardware features Type series which together with programming section contains information enable swift successful implementation user microcontroller applications. proper consultation relevant parts this section, users ensure that they make most efficient flexible multi-function features within Type microcontroller series.
Introduction
HT49R30A-1/HT49C30-1/HT49C30L, HT49R50A-1/HT49C50-1/HT49C50L HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80 form series 8-bit high-performance, RISC architecture microcontroller devices specifically designed wide range control product applications. Device flexibility enhanced with their internal special features such HALT wake-up functions, oscillator options, buzzer driver, UART, etc. These features combine ensure applications require minimum external components therefore reduce overall product costs. Having advantages low-power consumption, high-performance, flexibility well low-cost, these devices have versatility suit wide range LCD-based application possibilities such scales, electronic multimeters, meters, timers, calculators, remote controllers well many other LCD-based industrial home appliance applications. Many features common devices, however, they differ areas, such segment count, count, capacity, timer number package types, etc. additional feature that incorporated within HT49RU80/HT49CU80 devices full-duplex asynchronous serial communications UART function. HT49R30A-1, HT49R50A-1, HT49R70A-1 HT49RU80 devices offering advantages easy effective program updates, using Holtek range development programming tools. These devices provide designer with means fast low-cost product development cycles. However, applications that mature state their design process, HT49C30-1, HT49C50-1, HT49C70-1, HT49CU80, HT49C30L, HT49C50L HT49C70L mask version devices offer complementary device products with high volume low-cost demands. Fully functionally compatible with their sister devices, such mask version devices provide ideal substitute products which have gone beyond their development cycle facing cost down demands.
Type
HT49C30L, HT49C50L HT49C70L voltage versions Type MCUseries. With ability operate minimum voltage power supply only 1.2V these devices extremely suitable single cell battery applications. Although they only available mask versions, their sister devices, HT49R30A-1, HT49R50A-1 HT49R70A-1 fully compatible available during product development.
Features
Technology Features
High-performance RISC Architecture Low-power Fully Static CMOS Design Operating Voltage: HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1, HT49RU80/HT49CU80 fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V HT49C30L, HT49C50L, HT49C70L fSYS=500kHz: 1.2V~2.2V Power Consumption: Typical 8MHz Cycle Time: 0.5ms Instruction Cycle with 8MHz System Clock (HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1, HT49RU80/HT49CU80) Instruction Cycle with 500kHz System Clock (HT49C30L, HT49C50L, HT49C70L) Temperature Range: Operating Temperature -40°C 85°C (Industrial Grade) Storage Temperature -50°C 125°C
Kernel Features
Program Memory: OTP/Mask (HT49R30A-1/HT49C30-1/HT49C30L) OTP/Mask (HT49R50A-1/HT49C50-1/HT49C50L) OTP/Mask (HT49R70A-1/HT49C70-1/HT49C70L) OTP/Mask (HT49RU80/HT49CU80) Data Memory: (HT49R30A-1/HT49C30-1/HT49C30L) (HT49R50A-1/HT49C50-1/HT49C50L) (HT49R70A-1/HT49C70-1/HT49C70L) (HT49RU80/HT49CU80) Driver: Segments (HT49R30A-1/HT49C30-1/HT49C30L) Segments (HT49R50A-1/HT49C50-1/HT49C50L) Segments (HT49R70A-1/HT49C70-1/HT49C70L) Segments (HT49RU80/HT49CU80)
Chapter Hardware Structure
Table Read Function Multi-level Hardware Stack: 4-level (HT49R30A-1/HT49C30-1/HT49C30L) 6-level (HT49R50A-1/HT49C50-1/HT49C50L) 16-level (HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80) Manipulation Instructions Powerful Instructions Most Instructions Implemented Machine Cycle
Peripheral Features
From Input Pins with Pull-high Resistors From Bidirectional with Pull-high Options Output Pins (HT49RU80/HT49CU80) Internal Driver Internal Dedicated Memory Port Wake-up Options One, Three Event Counter Inputs with Internal Interrupt Universal Asynchronous Receiver/Transmitter, UART (HT49RU80/HT49CU80) External Interrupt Inputs Full Timer Functions with Internal Interrupt Watchdog Timer (WDT) HALT Wake-up Feature Power Saving Operation Output Buzzer Driver Outputs On-chip Crystal, 32768Hz Crystal Oscillator 32768Hz Real Time Clock (RTC) Function Voltage Reset/Detector (LVR/LVD) Feature Brown-out Protection (Except HT49C30L/HT49C50L/HT49C70L) Mask Version Devices Available High Volume Production Programming Interface with Code Protection Voltage Devices Available Single Cell Battery Operation (Only HT49C30L/HT49C50L/HT49C70L) Full Suite Supported Hardware Software Tools Available
Type Selection Table
series Type microcontrollers include comprehensive range features, some which standard some which device dependent. Most features common devices, main features distinguishing them Program Memory, Data Memory capacity, segment count timer functions, etc. assist users their selection most appropriate device their application, following table, which summarizes main features each device, provided.
Part Program Data Memory Memory Timer Int. UART Stack Package Types 48SSOP
HT49R30A-1 2.2V~5.5V HT49C30-1 HT49C30L 1.2V~2.2V HT49R50A-1 2.2V~5.5V HT49C50-1 HT49C50L 1.2V~2.2V HT49R70A-1 2.2V~5.5V HT49C70-1 HT49C70L HT49RU80 HT49CU80 1.2V~2.2V
48SSOP, 100QFP
100QFP
2.2V~5.5V
100QFP
Note
Part numbers including mask version devices, devices. Part numbers including voltage mask version devices. HT49R50A-1/HT49C50-1/HT49C50L devices, above table shows values 100-pin package. 48-pin SSOP package, there input pins, driver pins.
Block Diagram
following block diagram illustrates main functional blocks Type microcontroller series devices.
illa
illa
ifte
Chapter Hardware Structure
Note This block diagram represents devices, mask device there Device Programming Circuitry. UART only exists HT49RU80/HT49CU80.
Assignment
Type
Note
compatibility features microcontroller packages allow straightforward upgrading devices higher functionality with minimal changes application hardware.
Chapter Hardware Structure Description
HT49R30A-1/HT49C30-1/HT49C30L Name Options Description
PA0/BZ PA1/BZ PA3/PFD PA4~PA7
Bidirectional 8-bit input/output port. Each this port configured wake-up input configuration option. Configuration options determine whether pins PA0~PA3 configured CMOS outputs NMOS input/output pins. PA0~PA3 conWake-up CMOS NMOS figured NMOS input/output pins, then pull-high options available apply pins, indiI/O Pull-high PA0/PA1 BZ/BZ vidual pins. Pins PA4~PA7 always configured NMOS input/output pins with pull-high resistors conPA3 nected. inputs Schmitt Trigger types. Pins PA0, pin-shared with respectively, function which chosen configuration options. 6-bit Schmitt Trigger input port. Each input connected internal pull-high resistor. PB0, pin-shared with INT0, INT1 respectively. power supply HT49R30A-1/HT49C30-1. voltage pump HT49C30L. voltage pump HT49R30A-1/HT49C30-1. power supply HT49C30L. voltage pump duty cycle configuration option will determine whether COM3/SEG18 configured SEG18 segment driver common COM3 output driver panel. COM0~COM2 common outputs. driver outputs panel segments OSC1 OSC2 connected external network external crystal (determined configuration option) internal system clock. external system clock operation, OSC2 output system clock. oscillator pins OSC3 OSC4 used system clock, then OSC1 OSC2 pins should left floating. OSC3 OSC4 connected 32768Hz crystal form Real Time Clock timing purposes form system clock.
PB0/INT0 PB1/INT1 PB2/TMR PB3~PB5 VLCD
COM0~COM2 COM3/SEG18
1/2, Duty
SEG0~SEG17
OSC1 OSC2
Crystal
OSC3 OSC4
System Clock
Type
Name Options Description Schmitt Trigger reset input, active low. Positive power supply Negative power supply, ground
Note
Each programmed through configuration option have wake-up function. Only pins PA0~PA3 have pull-high configuration option. This pull-high option only selected these four pins configured NMOS types. pull-high option selected then will apply PA0~PA3 pins, individual pins cannot selected have pull-high resistors. setup CMOS outputs pull-high configuration option disabled.
HT49R50A-1/HT49C50-1/HT49C50L Name Options Description
PA0/BZ PA1/BZ PA3/PFD PA4~PA7
Bidirectional 8-bit input/output port. Each this port configured wake-up input configuration option. Configuration options determine whether pins PA0~PA3 configured CMOS outWake-up puts NMOS input/output pins. PA0~PA3 conCMOS NMOS figured NMOS input/output pins, then pull-high Pull-high options available apply pins, indiPA0/PA1 BZ/BZ vidual pins. Pins PA4~PA7 always configured NMOS input/output pins with pull-high resistors conPA3 nected. inputs Schmitt Trigger types. Pins PA0, pin-shared with respectively, function which chosen configuration options. 8-bit input Schmitt Trigger port. Each input connected internal pull-high resistor. Pins pin-shared with INT0 INT1 respectively. Pins pin-shared with TMR0 TMR1 respectively. Bidirectional 4-bit input/output port. configuration option determines whether four pins PC0~PC3 configured CMOS outputs NMOS input/output pins. Individual pins cannot selected configured CMOS output NMOS input/output pin. PC0~PC3 configured NMOS input/output pins, then pull-high option available applies pins, individual pins. inputs Schmitt Trigger types. power supply HT49R50A-1/HT49C50-1. voltage pump HT49C50L.
PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7
PC0~PC3
CMOS NMOS Pull-high
VLCD
Chapter Hardware Structure
Name Options Description voltage pump HT49R50A-1/HT49C50-1. power supply HT49C50L. voltage pump duty cycle configuration option will determine whether COM3/SEG32 configured SEG32 segment driver common COM3 output driver panel. COM0~COM2 common outputs. driver outputs panel segments OSC1 OSC2 connected external network external crystal (determined configuration option) internal system clock. external system clock operation, OSC2 output system clock. oscillator pins OSC3 OSC4 used system clock, then OSC1 OSC2 pins should left floating. OSC3 OSC4 connected 32768Hz crystal form Real Time Clock timing purposes form system clock. Schmitt Trigger reset input, active low. Positive power supply Negative power supply, ground
COM0~COM2 COM3/SEG32
1/2, Duty
SEG0~SEG31
OSC1 OSC2
Crystal
OSC3 OSC4
System Clock
Note
Each programmed through configuration option have wake-up function. Only pins PA0~PA3 PC0~PC3 have pull-high resistor configuration option. These pull-high options only selected these four pins configured NMOS types. pull-high option selected then will apply four pins, individual pins cannot selected have pull-high resistors. setup CMOS outputs pull-high configuration option disabled. packaging limitations 48-pin SSOP package, pins PB7, Port pins segment pins SEG0~SEG9 SEG28~SEG31 present.
Type
HT49R70A-1/HT49C70-1/HT49C70L Name Options Description
PA0/BZ PA1/BZ PA3/PFD PA4~PA7
Bidirectional 8-bit input/output port. Each this port configured wake-up input configuration option. Configuration options determine whether pins PA0~PA3 configured CMOS outWake-up puts NMOS input/output pins. PA0~PA3 conCMOS NMOS figured NMOS input/output pins, then pull-high Pull-high options available apply pins, indiPA0/PA1 BZ/BZ vidual pins. Pins PA4~PA7 always configured NMOS input/output pins with pull-high resistors connected. inputs Schmitt Trigger types. Pins PA0, pin-shared with respectively, function which chosen configuration options. 8-bit Schmitt Trigger input port. Each input connected internal pull-high resistor. Pins pin-shared with INT0 INT1 respectively. Pins pin-shared with TMR0 TMR1 respectively. Bidirectional 8-bit input/output port. configuration options determine whether four pins PC0~PC3 four pins PC4~PC7 configured CMOS outputs NMOS input/output pins. Pins must configured CMOS outputs NMOS input/output pins blocks four pins, individual pins cannot selected. pins PC0~PC3 PC4~PC7 configured NMOS input/output pins, then pull-high option available each block four pins. Individual pins cannot selected have pull-high option. inputs Schmitt Trigger types. power supply HT49R70A-1/HT49C70-1. voltage pump HT49C70L. voltage pump HT49R70A-1/HT49C70-1. power supply HT49C70L. voltage pump duty cycle configuration option will determine whether COM3/SEG40 configured SEG40 segment driver common COM3 output driver panel. COM0~COM2 common outputs. driver outputs panel segments
PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7
PC0~PC7
CMOS NMOS Pull-high
VLCD
COM0~COM2 COM3/SEG40
1/2, Duty
SEG0~SEG39
Chapter Hardware Structure
Name Options Description OSC1 OSC2 connected external network external crystal (determined configuration option) internal system clock. external system clock operation, OSC2 output system clock. oscillator pins OSC3 OSC4 used system clock, then OSC1 OSC2 pins should left floating. OSC3 OSC4 connected 32768Hz crystal form Real Time Clock timing purposes form system clock. Schmitt Trigger reset input, active low. Positive power supply Negative power supply, ground
OSC1 OSC2
Crystal
OSC3 OSC4
System Clock
Note
Each programmed through configuration option have wake-up function. Only pins PA0~PA3, PC0~PC3 PC4~PC7 have pull-high resistor configuration option. These pull-high options only selected these four pins configured NMOS types. pull-high option selected then will apply four pins, individual pins cannot selected have pull-high resistors. setup CMOS outputs pull-high configuration option disabled.
Type
HT49RU80/HT49CU80 Name Options Description
PA0/BZ PA1/BZ PA3/PFD PA4~PA7
Bidirectional 8-bit input/output port. Each this port configured wake-up input configuration option. Configuration options determine whether pins PA0~PA3 configured CMOS outWake-up puts NMOS input/output pins. PA0~PA3 conCMOS NMOS figured NMOS input/output pins, then pull-high Pull-high options available apply pins, indiPA0/PA1 BZ/BZ vidual pins. Pins PA4~PA7 always configured NMOS input/output pins with pull-high resistors connected. inputs Schmitt Trigger types. Pins PA0, pin-shared with respectively, function which chosen configuration options. 8-bit Schmitt Trigger input port. Each input connected internal pull-high resistor. Pins pin-shared with INT0 INT1 respectively. Pins PB2, pin-shared with TMR0, TMR1 TMR2 respectively. Bidirectional 8-bit input/output port. configuration options determine whether four pins PC0~PC3 four pins PC4~PC7 configured CMOS outputs NMOS input/output pins. Pins must configured CMOS outputs NMOS input/output pins blocks four pins, individual pins cannot selected. pins PC0~PC3 PC4~PC7 configured NMOS input/output pins, then pull-high option available each block four pins. Individual pins cannot selected have pull-high option. inputs Schmitt Trigger types. Pins pin-shared with UART pins respectively. 7-bit output port. Each setup either CMOS output output configuration options. power supply. This implemented power only. VLCD levels greater less than levels. maximum voltage, connect VDD, VLCD voltage pump
PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4/TMR2 PB5~PB7
PC0/TX PC1/RX PC2~PC7
CMOS NMOS Pull-high
PD0/SEG40~ PD6/SEG46
CMOS Output Output
VLCD
VMAX
Chapter Hardware Structure
Name Options Description duty cycle configuration option will determine whether COM3/SEG47 configured SEG47 segment driver common COM3 output driver panel. COM0~COM2 common outputs. driver outputs panel segments OSC1 OSC2 connected external network external crystal (determined configuration option) internal system clock. external system clock operation, OSC2 output system clock. oscillator pins OSC3 OSC4 used system clock, then OSC1 OSC2 pins should left floating. OSC3 OSC4 connected 32768Hz crystal form Real Time Clock timing purposes form system clock. Schmitt Trigger reset input, active low. Positive power supply Negative power supply, ground
COM0~COM2 COM3/SEG47
1/2, Duty
SEG0~SEG39
OSC1 OSC2
Crystal
OSC3 OSC4
System Clock
Note
Each programmed through configuration option have wake-up function. Only pins PA0~PA3, PC0~PC3 PC4~PC7 have pull-high resistor configuration option. These pull-high options only selected these four pins configured NMOS types. pull-high option selected then will apply four pins, individual pins cannot selected have pull-high resistors. setup CMOS outputs pull-high configuration option disabled.
Absolute Maximum Ratings
Supply Voltage (Except HT49C30L, HT49C50L, HT49C70L) .VSS-0.3V VSS+6.0V Supply Voltage (For HT49C30L, HT49C50L, HT49C70L) .VSS-0.3V VSS+2.5V Input Voltage .VSS-0.3V VDD+0.3V Storage Temperature .-50°C 125°C Operating Temperature .-40°C 85°C These stress ratings only. Stresses exceeding range specified under Absolute Maximum Ratings cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
Type D.C. Characteristics
Except HT49RU80/HT49CU80 VDD=3V VDD=5V (Except HT49C30L, HT49C50L, HT49C70L) VDD=1.5V (For HT49C30L, HT49C50L, HT49C70L)
Test Conditions Symbol Parameter Conditions fSYS=500kHz (For HT49C30L, HT49C50L, HT49C70L) Operating Voltage fSYS=4MHz, disabled, (Except HT49C30L, HT49C50L, HT49C70L) fSYS=8MHz (Except HT49C30L, HT49C50L, HT49C70L) VLCD Power Supply (Except HT49C30L, HT49C50L, HT49C70L) Min. Typ. Max. Unit
Ta=25°C
1.5V load, SYS=455kHz IDD1 Operating Current (Crystal OSC) 1.5V load, SYS=400kHz IDD2 Operating Current OSC) Operating Current (Crystal OSC, OSC) Operating Current (fSYS=RTC OSC) IDD3 1.5V IDD4 1.5V ISTB1 Standby Current (fS=T1) 1.5V ISTB2 Standby Current (fS=RTC OSC) 1.5V ISTB3 Standby Current (fS=WDT OSC) ISTB4 Standby Current (fS=RTC OSC) Standby Current (fS=RTC OSC) load, system HALT, HALT, type, bias load, system HALT, HALT, type, bias load, system HALT, HALT, type load, system HALT, HALT, type load, system HALT, HALT load load, SYS=8MHz load, SYS=4MHz load, SYS=4MHz
ISTB5
Chapter Hardware Structure
Test Conditions Symbol Parameter ISTB6 Standby Current (fS=WDT OSC) Standby Current (fS=WDT OSC) Input Voltage Ports, Input High Voltage Ports, Input Voltage (RES) Input High Voltage (RES) Conditions load, system HALT, HALT, type, bias load, system HALT, HALT, type, bias (For HT49C30L, HT49C50L, HT49C70L) (Except HT49C30L, HT49C50L, HT49C70L) 0.8VDD 0.7VDD 0.9VDD VOL=0.1VDD -0.3 VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD -180 -0.6 -160 -360 0.3VDD 0.4VDD Min. Typ. Max. Unit
ISTB7
VIL1
VIH1
VIL2 VIH2
1.5V
IOL1
Port Sink Current
1.5V
IOH1
Port Source Current
IOL2
Common Segment Current Common Segment Current
1.5V
IOH2
Pull-high Resistance
VLVR VLVD
Voltage Reset Voltage Voltage Detector Voltage
Type
HT49RU80/HT49CU80
Test Conditions Symbol Parameter VLCD IDD1 Operating Voltage Power Supply Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (fSYS=RTC OSC) Standby Current (fS=T1) Standby Current (fS=RTC OSC) Standby Current (fS=WDT OSC) Standby Current (fS=RTC OSC) Standby Current (fS=RTC OSC) Standby Current (fS=WDT OSC) Standby Current (fS=WDT OSC) Input Voltage Ports, Input High Voltage Ports, Input Voltage (RES) Input High Voltage (RES) Port Sink Current load, UART VOL=0.1VDD load, system HALT, HALT, UART load, system HALT, HALT, type, UART load, system HALT, HALT, type, UART load, system HALT, HALT, type, bias, UART load, system HALT, HALT, type, bias, UART load, system HALT, HALT, type, bias, UART load, system HALT, HALT, type, bias, UART Conditions disabled, fSYS=4MHz disabled, fSYS=8MHz load, SYS=4MHz, UART load, SYS=4MHz, UART load, SYS=8MHz, UART load, SYS=8MHz, UART 0.7VDD 0.9VDD 0.3VDD 0.4VDD Min. Typ. Max. Unit
Ta=25°C
IDD2 IDD3 IDD4 IDD5
ISTB1
ISTB2
ISTB3
ISTB4
ISTB5
ISTB6
ISTB7
VIL1 VIH1 VIL2 VIH2 IOL1
Chapter Hardware Structure
Test Conditions Symbol Parameter IOH1 Port Source Current IOL2 Common Segment Current Common Segment Current Pull-high Resistance VLVR VLVD Voltage Reset Voltage Voltage Detector Voltage VOH=0.9VDD VOL=0.1VDD Conditions VOH=0.9VDD -180 -160 -360 Min. Typ. Max. Unit
IOH2
A.C. Characteristics
Except HT49RU80/HT49CU80 VDD=3V VDD=5V (Except HT49C30L, HT49C50L, HT49C70L) VDD=1.5V (For HT49C30L, HT49C50L, HT49C70L)
Test Conditions Symbol Parameter Conditions 1.2V~2.2V (For HT49C30L, HT49C50L, HT49C70L) fSYS1 System Clock (Crystal OSC) 32768 32768 4000 8000 4000 8000 4000 8000 Min. Typ. Max. Unit
Ta=25°C
2.2V~5.5V (Except HT49C30L, HT49C50L, HT49C70L) 3.3V~5.5V (Except HT49C30L, HT49C50L, HT49C70L) 1.2V~2.2V (For HT49C30L, HT49C50L, HT49C70L)
fSYS2
System Clock OSC)
2.2V~5.5V (Except HT49C30L, HT49C50L, HT49C70L) 3.3V~5.5V (Except HT49C30L, HT49C50L, HT49C70L)
fSYS3
System Clock (32768Hz Crystal OSC)
1.2V~2.2V (For HT49C30L, HT49C50L, HT49C70L)
fRTCOSC Frequency
fTIMER
Timer Frequency
2.2V~5.5V (Except HT49C30L, HT49C50L, HT49C70L) 3.3V~5.5V (Except HT49C30L, HT49C50L, HT49C70L)
Type
Symbol Parameter Test Conditions 1.5V tWDTOSC Watchdog Oscillator Period External Reset Pulse Width System Start-up Timer Period Voltage Width Reset (For HT49C30L, HT49C50L, HT49C70L) (Except HT49C30L, HT49C50L, HT49C70L) Wake-up from HALT (For HT49C30L, HT49C50L, HT49C70L) (Except HT49C30L, HT49C50L, HT49C70L) Conditions Min. 0.25 Typ. 1024 Max. Unit *tSYS
tRES
tSST tLVR
tINT
Interrupt Pulse Width
*tSYS= 1/fSYS1, 1/fSYS2 1/fSYS3 HT49RU80/HT49CU80
Symbol Parameter Test Conditions tRES tSST tLVR tINT External Reset Pulse Width System Start-up Timer Period Voltage Width Reset Interrupt Pulse Width 2.2V~5.5V 3.3V~5.5V Wake-up from HALT Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V Min. 0.25 Typ. 32768 32768 1024
Ta=25°C
Max. 4000 8000 4000 8000 4000 8000 Unit *tSYS
fSYS1
System Clock (Crystal OSC)
fSYS2 fSYS3
System Clock OSC) System Clock (32768Hz Crystal OSC)
fRTCOSC Frequency fTIMER Timer Frequency (50% Duty)
tWDTOSC Watchdog Oscillator Period
*tSYS= 1/fSYS1, 1/fSYS2 1/fSYS3
Chapter Hardware Structure System Architecture
factor high-performance features Holtek range Type microcontrollers attributed internal system architecture. range devices take advantage usual features found within RISC microcontrollers providing increased speed operation enhanced performance. pipelining scheme implemented such that instruction fetching instruction execution overlapped, hence instructions effectively executed cycle, with exception branch call instructions. 8-bit wide used practically operations instruction set. carries arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. internal data path simplified moving data through Accumulator ALU. Certain internal registers implemented Data Memory directly indirectly addressed. simple addressing methods these registers along with additional architectural features ensure that minimum external components required provide functional control system with maximum reliability flexibility. This makes these devices suitable low-cost, high-volume production controller applications requiring from words Program Memory from bytes data storage.
Clocking Pipelining
main system clock, derived from either Crystal/Resonator oscillator subdivided into four internally generated non-overlapping clocks, T1~T4. Program Counter incremented beginning clock during which time instruction fetched. remaining T2~T4 clocks carry decoding execution functions. this way, T1~T4 clock cycle forms instruction cycle. Although fetching execution instructions takes place consecutive instruction cycles, pipelining structure microcontroller ensures that instructions effectively executed instruction cycle. exception this instructions where contents Program Counter changed, such subroutine calls jumps, which case instruction will take more instruction cycle execute. Note When oscillator used, OSC2 freed phase clock synchronizing pin. This phase clock frequency fSYS/4 with high/low duty cycle.
illa
System Clocking Pipelining
Type
instructions involving branches, such jump call instructions, machine cycles required complete instruction execution. extra cycle required program takes cycle first obtain actual jump call address then another cycle actually execute branch. requirement this extra cycle should taken into account programmers timing sensitive applications
Program Counter
During program execution, Program Counter used keep track address next instruction executed. automatically incremented each time instruction executed except instructions, such that demand jump non-consecutive Program Memory address. Type series, note that Program Counter width varies with Program Memory capacity depending upon which device selected. However, must noted that only lower bits, known Program Counter Register directly addressable user. When executing instructions requiring jumps non-consecutive addresses, such jump instruction, subroutine call, interrupt reset, etc., microcontroller manages program control loading required address into Program Counter. conditional skip instructions, once condition been met, next instruction, which already been fetched during present instruction execution, discarded dummy cycle takes place while correct instruction obtained. lower byte Program Counter, known Program Counter register PCL, available program control readable writable register. transferring data directly into this register short program jump executed directly, however, only this byte available manipulation, jumps limited present page memory, that locations. When such program jumps executed should also noted that dummy cycle will inserted. HT49RU80/HT49CU80 devices, whose Program Memory stored Banks, note that Bank selection under control Bank Pointer. this Bank Pointer that controls highest address Program Counter shown following diagram:
Chapter Hardware Structure
Note lower byte Program Counter fully accessible under program control. might cause program branching, extra cycle needed pre-fetch. Further information register found Special Function Register section.
Except HT49RU80/HT49CU80
Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow (Except HT49R30A-1/HT49C30-1/ HT49C30L) Time Base Interrupt (For HT49R30A-1/HT49C30-1/ HT49C30L) Time Base Interrupt (Except HT49R30A-1/HT49C30-1/ HT49C30L) Interrupt (For HT49R30A-1/HT49C30-1/ HT49C30L) Interrupt (Except HT49R30A-1/HT49C30-1/ HT49C30L) Skip Loading Jump, Call Branch Program Counter Bits
Program Counter+2 PC12 PC11 PC10
HT49RU80/HT49CU80
Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow UART Interrupt Multi-function Interrupt Skip Loading Jump, Call Branch Return from Subroutine Program Counter Bits
Program Counter+2 (With current bank) PC13 PC12 PC11 PC10 BP.5
Type
Note PC13~PC8: Current Program Counter bits. @7~@0: bits. BP.5: Bank Pointer bit. #12~#0: Instruction code bits. S13~S0: Stack register bits. HT49RU80/HT49CU80, Program Counter bits wide, i.e. from b13~b0. HT49R50A-1/HT49C50-1/HT49C50L, since their Program Counter bits wide, column table applicable. HT49R30A-1/HT49C30-1/HT49C30L, since their Program Counter bits wide, columns table applicable. Timer/Event Counter Overflow available only HT49R50A-1/HT49C50-1/ HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L HT49RU80/HT49CU80. HT49R30A-1/HT49C30-1/HT49C30L Timer/Event Counter represents single timer. UART interrupt Multi-function interrupt available only HT49RU80/ HT49CU80 devices.
Stack
This special part memory which used save contents Program Counter only. stack have between levels depending upon which device selected neither part data part program space, neither readable writable. activated level indexed Stack Pointer (SP) neither readable writable. subroutine call interrupt acknowledge signal, contents Program Counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), Program Counter restored previous value from stack. After chip reset, Stack Pointer will point stack. stack full enabled interrupt takes place, interrupt request flag will recorded acknowledge signal will inhibited. When Stack Pointer decremented RETI), interrupt will serviced. This feature prevents stack overflow allowing programmer structure more easily. However, when stack full, instruction still executed which will result stack overflow. Precautions should taken avoid such cases which might cause unpredictable program branching.
Chapter Hardware Structure
Note HT49R30A-1/HT49C30-1/HT49C30L, N=4, i.e. levels stack available. HT49R50A-1/HT49C50-1/HT49C50L, N=6, i.e. levels stack available. HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80, N=16, i.e. levels stack available.
Arithmetic Logic Unit
arithmetic-logic unit critical area microcontroller that carries arithmetic logic operations instruction set. Connected main microcontroller data receives related instruction codes performs required arithmetic logical operations after which result will placed specified register. these calculation operations result carry, borrow other status changes, status register will correspondingly updated reflect these changes. supports following functions: Arithmetic operations ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, Logic operations AND, XOR, ANDM, ORM, XORM, CPL, CPLA Rotation RRA, RRCA, RRC, RLA, RLCA, Increment Decrement INCA, INC, DECA, Branch decision, JMP, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Program Memory
Program Memory location where user code program stored. microcontrollers, types Program Memory usually supplied. first type OneTime Programmable (OTP) Memory where users program their application code into device. Devices with memory denoted having within their device name. using appropriate programming tools, devices offer users flexibility freely develop their applications which useful during debug products requiring frequent upgrades program changes. devices also applicable applications that require medium volume production runs. other type memory mask memory, denoted having within device name. These devices offer most cost effective solutions high volume products.
Organization
Program Memory capacity bits depending upon which device selected. Program Memory addressed Program Counter also contains data, table information interrupt entries. Table data, which setup location within Program Memory, addressed separate table pointer register. case HT49RU80/HT49CU80 devices, Program Memory divided into Banks, Bank Bank each with capacity Program Memory Bank selected controlling Bank Pointer. Clearing this selects Bank while setting selects Bank Care must exercised when using Bank Pointer also used control Data Memory Bank Pointer.
Type
following diagram shows Program Memory Type microcontroller series:
itia itia itia
itia
lti-
Special Vectors
Within Program Memory, certain locations reserved special usage, such reset interrupts. Location 000H This vector reserved chip reset program initialization. After chip reset initiated, program will jump this location begin execution. Location 004H This vector used INT0 external interrupt. external interrupt INT0 device goes low, program will jump this location begin execution INT0 external interrupt enabled stack full. Location 008H This vector used INT1 external interrupt. external interrupt INT1 device goes low, program will jump this location begin execution INT1 external interrupt enabled stack full.
Chapter Hardware Structure
Location 00CH This internal interrupt vector used Timer/Event Counter. counter overflow occurs, program will jump this location begin execution internal interrupt enabled stack full. HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/ HT49C70L HT49RU80/HT49CU80, Timer/Event Counter known Timer/Event Counter Location 010H With exception HT49R30A-1/HT49C30-1/HT49C30L devices, which have only internal timer/event counter, this internal interrupt vector used Timer/Event Counter counter overflow occurs, program will jump this location begin execution internal interrupt enabled stack full. HT49R30A-1/HT49C30-1/HT49C30L devices, this vector used Time Base interrupt. program will jump this location begin execution when Time Base interrupt signal generated interrupt enabled stack full. Location 014H With exception HT49R30A-1/HT49C30-1/HT49C30L HT49RU80/HT49CU80 devices, this internal interrupt vector used Time Base interrupt. When Time Base interrupt signal generated, program will jump this location begin execution interrupt enabled stack full. HT49R30A-1/HT49C30-1/HT49C30L devices, this vector used Real Time Clock interrupt. program will jump this location begin execution when Real Time Clock interrupt signal generated interrupt enabled stack full. HT49RU80/HT49CU80 devices, this internal vector reserved UART interrupt service routine. When UART interrupt resulting from transmission flag reception completed, program will jump this location begin execution interrupt enabled stack full. Location 018H With exception HT49R30A-1/HT49C30-1/HT49C30L HT49RU80/HT49CU80 devices, this internal interrupt vector used Real Time Clock interrupt. This internal interrupt vector available HT49R30A-1/HT49C30-1/HT49C30L devices whose Real Time Clock interrupt vector located 014H. program will jump this location begin execution when Real Time Clock interrupt signal generated interrupt enabled stack full. HT49RU80/HT49CU80 devices, this internal vector reserved Multi-function interrupt service routine. timer interrupt results from Timer/Event Counter overflow, Real Time Clock time-out Time Base time-out, program will jump this location begin execution interrupt enabled stack full.
Type
Managing Multiple Banks
HT49RU80/HT49CU80 devices, which have multiple Program Memory banks, there some special considerations that have taken into account. First, sections program which located into different banks placed using ROMBANK directive. When using instruction call routines located different bank, when using instructions directly jump location different bank, target bank must first selected correctly setting Bank Pointer prior executing instruction. This course achieved directly controlling Bank Pointer, also done using BANK directive shown example. Then, when instruction executed, Bank Pointer value stored register will automatically loaded into Program Counter. When instruction encountered subroutine called from different bank, program will automatically return original bank, however, value will changed will remain value where subroutine located. this reason must carefully managed when moving between banks. following example HT49RU80/HT49CU80 devices illustrates instructions between different banks: include HT49RU80.inc define rombank rombank codesec0 rombank codesec1 define rombank codesec0 .section 000h locates following program section into Bank re-initializing start start: lab0: BANK routb1 bp,a call routb1
codesec1 .section 000h routb1 proc routb1 endp
routine located Bank load bank number routb1 into call subroutine located Bank program will return this location after Bank will retain Bank value clear locates following program section into Bank
return program Bank will retain Bank value
Chapter Hardware Structure
When managing interrupts, care exercised supervising Bank Pointer. Irrespective what Bank program presently running when interrupt occurs, whether external interrupt internal interrupt, program will immediately jump respective interrupt vector located Bank Note however that, although cases program will jump Bank Bank Pointer will retain original value indicate Bank this reason, after entering interrupt subroutine, addition usual backup accumulator status register, important backup original value immediately also clear Bank Pointer indicate Bank especially other calls jumps encountered within Bank Before instruction interrupt subroutine executed, Bank Pointer, along with accumulator status register, must restored ensure program returns correct Bank point from where subroutine called. following example illustrates interrupts managed: include HT49RU80.inc rombank codesec0 define rombank rombank codesec1 define rombank codesec0 .section 000h locates following program section into Bank clear Bank Pointer after power-on reset 004h jump here from bank when ext0_int. occurs retains original value accbuf0,a a,bp ext0_int 008h accbuf1,a a,bp ext1_int 00Ch ext0_int: bp_ext0,a a,status statusbuf0,a a,statusbuf0 status,a a,bp_ext0 bp,a a,accbuf0 reti backup accumulator backup Bank Pointer clear indicate Bank otherwise original value will remain give rise false call addresses jump external interrupt subroutine jump here from bank when ext1_int. occurs retains original value backup accumulator backup Bank Pointer clear indicate Bank otherwise original value will remain give rise false call addresses jump external interrupt subroutine
jump here from bank when Timer int. occurs retains original value external interrupt subroutine backup Bank Pointer backup status register backup status register
restore status register restore Bank Pointer restore accumulator return main program original calling bank
Type
ext1_int: bp_ext1,a a,status statusbuf1,a a,statusbuf1 status,a a,bp_ext1 bp,a a,accbuf1 reti external interrupt subroutine backup Bank Pointer backup status register
restore status register restore Bank Pointer restore accumulator return main program original calling bank
Look-up Table
location within Program Memory defined look-up table where programmers store fixed data. look-up table, table pointer must first setup placing lower-order address look-up data retrieved Table Pointer Register TBLP. This register defines lower 8-bit address look-up table. After setting table pointer, table data retrieved from current Program Memory page last Program Memory page using instructions respectively. When these instructions executed, lower-order table byte from Program Memory will transferred user-defined Data Memory register specified instruction. higher-order table data byte from Program Memory will transferred TBLH special register. unused bits this transferred higher-order byte will read With exception HT49RU80/HT49CU80, following diagram illustrates addressing/data flow look-up table:
ifie
Table Program Example
following example shows table pointer table data defined retrieved from HT49R30A-1/HT49C30-1/HT49C30L Type microcontroller. This example uses table data located last page which stored there using statement. value this statement which refers start address last page within Program Memory HT49R30A-1/HT49C30-1/HT49C30L microcontroller. table pointer setup here have initial value This will ensure that first data read from data table will Program Memory address locations after start last page. Note that value table pointer referenced first address present page instruction being used. high byte table data which this case equal zero will transferred TBLH register automatically when instruction executed.
Chapter Hardware Structure
tempreg1 tempreg2 tabrdl tempreg1 transfers value table referenced table pointer tempregl data prog. memory address 706H transferred tempreg1 TBLH temporary register temporary register
a,06h tblp,a
initialize table pointer note that this address referenced last page present page
tblp
reduce value table pointer transfers value table referenced table pointer tempreg2 data prog. memory address 705H transferred tempreg2 TBLH this example data transferred tempreg1 data register tempreg2 value will transferred high byte register TBLH
tabrdl tempreg2
700h sets initial address last page (for HT49R30A-1)
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
HT49RU80/HT49CU80 devices, there Table Pointer Registers known TBLP TBHP which lower-order higher-order address look-up data retrieved must respectively first written. Unlike other devices which only address byte defined using TBLP register, additional TBHP register allows complete address look-up table defined consequently allow table data from address page directly accessed. these devices, after setting both high byte table pointers, table data then retrieved from area Program Memory using instruction from last page each Program Memory Bank using instruction. When either these instructions executed, lower-order table byte from Program Memory will transferred user-defined Data Memory register specified instruction. higher-order table data byte from Program Memory will transferred TBLH special register. unused bits this transferred higher order byte will read
Type
following diagram illustrates addressing/data flow look-up table HT49RU80/ HT49CU80 devices:
ifie
following example shows table pointer defined table data retrieved from HT49RU80/HT49CU80 devices. This example uses table data which located stored Program Memory using statement. value this statement however, this only indicates offset value from start address Bank which this case table pointer high byte setup have value while value table pointer byte setup here have initial value This will ensure that data byte read from data table will located Program Memory address locations after first address defined statement. When instruction executed, table data byte, which value will transferred user-defined temp register, while table data high byte, which value will transferred TBLH register. include HT49RU80.inc data .section temp rombank codesec0 rombank codesec1 codesec0 .section start 010h start: a,020h tbhp,a a,005h tblp,a tabrdc temp
Bank definition Bank definition
setup table high byte address setup table byte address table pointer address 2005H read table data from address 2005H will placed temp register will placed TBLH register
Chapter Hardware Structure
codesec1 .section 000h 0000h Bank code located here this defines offset from start address Bank which 2000H
000AAh, 011BBh, 022CCh, 033DDh, 044EEh, 055FFh
Because TBLH register read-only register cannot restored, care should taken ensure protection both main routine interrupt service routine table read instructions. using table read instructions, Interrupt Service Routines change value TBLH subsequently cause errors used again main routine. rule recommended that simultaneous table read instructions should avoided. However, situations where simultaneous cannot avoided, interrupts should disabled prior execution main routine table-read instructions. Note that table related instructions require instruction cycles complete their operation. Except HT49RU80/HT49CU80
Table Location Bits Instruction TABRDC PC12 PC11 PC10 TABRDL
HT49RU80/HT49CU80
Table Location Bits Instruction TABRDC TBHP TBHP TBHP TBHP TBHP TBHP TABRDL
Note
PC12~PC8: Current Program Counter bits. @7~@0: Table Pointer TBLPbits. HT49RU80/HT49CU80, Table address location bits, i.e. from b13~b0. HT49R70A-1/HT49C70-1/HT49C70L, Table address location bits, i.e. from b12~b0. HT49R50A-1/HT49C50-1/HT49C50L, Table address location bits, i.e. from b11~b0. HT49R30A-1/HT49C30-1/HT49C30L, Table address location bits, i.e. from b10~b0.
Type Data Memory
Data Memory volatile area 8-bit wide internal memory location where temporary information stored. Divided into three sections, first these area where special function registers located. These registers have fixed locations necessary correct operation device. Many these registers read from written directly under program control, however, some remain protected from user manipulation. second area Data Memory reserved general purpose use. locations within this area read write accessible under program control. third area reserved Memory. This special area Data Memory mapped directly display data written into this memory area will directly affect displayed data. addresses Memory area overlap those General Purpose Data Memory area, switching between areas achieved setting Bank Pointer correct value.
Organization
Special Purpose General Purpose Data Memory located consecutive locations. implemented bits wide length each memory section dictated type microcontroller chosen. start address Data Memory devices address 00H. Registers which common microcontrollers, such ACC, PCL, etc., have same Data Memory address. Data Memory mapped into Bank Data Memory, however, only lower four bits used. higher four bits, read program will return value. start Data Memory devices address 40H. However, since Data Memory located Bank access this area Bank Pointer must first value Note that after power-on contents Data Memory, including Data Memory, will unknown condition, programmer must therefore ensure that Data Memory properly initialized.
Note
Most Data Memory bits directly manipulated using with exception dedicated bits. Data Memory also accessed through Memory Pointer registers MP1.
Chapter Hardware Structure
General Purpose Data Memory
microcontroller programs require area read/write memory where temporary data stored retrieved later. this area memory that known General Purpose Data Memory. This area Data Memory fully accessible user program both read write operations. using instructions individual bits reset under program control giving user large range flexibility manipulation Data Memory. With exception HT49RU80/HT49CU80, General Purpose Data Memory exists Bank HT49RU80/HT49CU80, General Purpose Data Memory exists three Banks, namely Bank Bank Bank therefore necessary first ensure that Bank Pointer correct value before accessing General Purpose Data Memory. When Bank Pointer value 01H, Memory will accessed. Bank Bank Bank must addressed indirectly using Memory Pointer indirect addressing register IAR1. direct addressing indirect addressing using IAR0 will always result data from Bank being accessed. following diagram shows General Purpose Data Memory Organization Type microcontrollers:
Note
bytes General Purpose Data Memory HT49RU80/HT49CU80 devices stored three individual memory banks, known Bank Bank Bank Before reading writing General Purpose Data Memory essential first ensure that correct Data Memory bank selected setting Bank Pointer. Bank Bank Bank only addressed indirectly using IAR1.
Type
Special Purpose Data Memory
This area Data Memory where registers, necessary correct operation microcontroller, stored. Most registers both readable writable some protected read-only, details which located under relevant Special Function Register section. Note that locations that unused, read instruction these addresses will return value following diagram shows detailed Special Purpose Data Memory Organization Type microcontrollers:
Chapter Hardware Structure
Memory
data displayed also stored area fully accessible Data Memory. writing this area RAM, display output directly controlled application program. Memory exists Bank have addresses which into General Purpose Data Memory, necessary first ensure that Bank Pointer value before accessing Memory. Memory only accessed indirectly using Memory Pointer indirect addressing register IAR1. When Bank Pointer Bank access Data Memory, addresses with value less than read, General Purpose Memory Bank will accessed. Also, Bank Pointer Bank addresses higher than last address Bank read, then value will returned. following diagram shows Memory Type microcontroller:
Special Function Registers
ensure successful operation microcontroller, certain internal registers implemented Data Memory area. These registers ensure correct operation internal functions such timers, interrupts, etc., well external functions such data control. location these registers within Data Memory begins address unused Data Memory locations between these special function registers point where General Purpose Memory begins reserved future expansion purposes, attempting read data from these locations will return value
Indirect Addressing Registers IAR0, IAR1
method indirect addressing allows data manipulation using Memory Pointers instead usual direct memory addressing method where actual memory address defined. action Indirect Addressing Registers will result corresponding read/write operations memory location specified corresponding Memory Pointer. devices range microcontrollers contain indirect addressing registers known IAR0 IAR1 Memory Pointers MP1. Note that these Indirect Addressing Registers physically implemented that reading Indirect Addressing Registers indirectly will return result writing registers indirectly will result operation.
Type
Memory Pointers MP0,
devices range microcontrollers contain Memory Pointers, known MP1. These Memory Pointers physically implemented Data Memory manipulated same normal registers providing convenient with which address track data. When operation relevant Indirect Addressing Registers carried out, actual address that microcontroller directed address specified related Memory Pointer. When Bank Pointer setup access data from Bank both Memory Pointers used access data from Bank which General Purpose Data Memory. However, when Bank Pointer setup access data from Bank which Data Memory, access data from Bank Bank HT49RU80/HT49CU80 devices, important note that still, Memory Pointer will only access data from Bank Only Memory Pointer used access data from Bank Bank Bank
Note
HT49R30A-1/HT49R30C-1/HT49C30L devices, Memory Pointers implemented. However, must noted that when Memory Pointers these devices read, value will read.
following example shows clear section four locations already defined locations adres1 adres4. data .section adres1 adres2 adres3 adres4 block code .section start: loop: a,04h setup size block block,a a,offset adres1 Accumulator loaded with first address mp0,a setup Memory Pointer with first address
IAR0 block loop
clear data address defined increment Memory Pointer check last memory location been cleared
continue: important point note here that example shown above, reference made specific addresses.
Chapter Hardware Structure
Bank Pointer
Data Memory area should noted that both General Purpose Data Memory Memory have same Data Memory addresses. Therefore when using instructions access Memory General Purpose Data Memory, necessary ensure that correct area selected. With exception HT49RU80/HT49CU80 devices, General Purpose Data Memory always located Bank General Purpose sub-divided into three banks, Bank Bank Bank HT49RU80/HT49CU80. devices Memory located Bank Selecting correct Data Memory area achieved using Bank Pointer. data either Bank Bank Bank accessed, lowest bits must binary values respectively, however, must noted that data these three banks only addressed indirectly using Memory Pointer IAR1 indirect addressing register. direct addressing indirect addressing using IAR0 will always result data from Bank being accessed. Data Memory Bank Pointer initialized Bank after reset, except time-out reset Power Down Mode, which case, Data Memory Bank Pointer remains unchanged. should noted that Special Function Data Memory affected bank selection, which means that Special Function Registers accessed from within either Bank Bank Bank Bank HT49RU80/HT49CU80 devices, whose Program Memory divided into banks, known Bank Bank Bank Pointer used control which Program Memory Bank selected. Although only some Bank Pointer register bits actually used Data Memory Program Memory bank indicating purposes, note that bits register actually implemented. unused bits must reset
Accumulator
Accumulator central operation microcontroller closely related with operations carried ALU. Accumulator place where intermediate results from stored. Without Accumulator would necessary write result each calculation logical operation such addition, subtraction, shift, etc., Data Memory resulting higher programming timing overheads. Data transfer operations usually involve temporary storage function Accumulator; example, when transferring data between user defined register another, necessary this passing data through Accumulator direct transfer between registers permitted.
Type
Program Counter Register
provide additional program control functions, byte Program Counter made accessible programmers locating within Special Purpose area Data Memory. manipulating this register, direct jumps other program locations easily implemented. Loading value directly into this register will cause jump specified Program Memory location, however, register only 8-bit wide, only jumps within current Program Memory page permitted. When such operations used, note that dummy cycle will inserted.
Look-up Table Registers TBLP, TBHP, TBLH
These special function registers used control operation look-up table which stored Program Memory. TBLP table byte pointer indicates location where table data located. value must setup before table read commands executed. value changed, example using instructions, allowing easy table data pointing reading. TBHP table high byte pointer only available HT49RU80/HT49CU80 devices. TBLH location where high order byte table data stored after table read data instruction been executed. Note that lower order table data byte transferred user defined location.
Real Time Clock Control Register RTCC
RTCC register controls several internal functions which Real Time Clock (RTC) Interrupt, whose function provide internal interrupt signal regular fixed intervals. driving clock interrupt comes from internal clock source, known which then further divided give longer time values, which turn generates interrupt signal. value this division ratio determined value programmed into bits 2~0, known RT2~RT0, RTCC register. writing value directly into these RTCC register bits, time-out values from 28/fS 215/fS generated. RTCC register also controls quick start-up function oscillator. This oscillator which fixed frequency 32768Hz made start-up quicker rate setting known QOSC This will value when device powered however, some extra power consumed, QOSC should after about seconds reduce power consumption. further internal function under control RTCC register Voltage Detector. This function enabled setting known LVDC bit, When power supply voltage falls below certain VLVD value, specified characteristics, which read only known LVDO, will This will remain value power supply voltage above specified level. Note that bits RTCC register used.
Chapter Hardware Structure
illa
Status Register STATUS
This 8-bit register (0AH) contains zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), Power Down flag (PDF), Watchdog time-out flag (TO). also records status information controls operation sequence. With exception flags, bits status register altered instructions like most other registers. data written into status register will change flag. addition, operations related status register give different results different instruction operations. flag affected only system power-up, time-out executing instruction. flag affected only executing instruction during system power-up. flags generally reflect status latest operations. operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition, borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logical operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared cleared system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out.
Type
addition, entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status registers important subroutine corrupt status register, precautions must taken correctly save
ilia
Interrupt Control Registers INTC0, INTC1, MFIC
These 8-bit registers, known INTC0, INTC1 MFIC, control operation both external internal interrupts. setting various bits within these registers using standard manipulation instructions, enable/disable function external interrupts each internal interrupts independently controlled. master interrupt within these registers, bit, acts like global enable/disable used interrupt enable bits off. This cleared when interrupt routine entered disable further interrupt executing instruction. Note situations where other interrupts require servicing within present interrupt service routines, manually program after present interrupt service routine been entered.
Timer/Event Counter Registers
Depending upon which device selected, devices contain one, three integrated Timer/Event Counters either 8-bit 16-bit size. HT49R30A-1/HT49C30-1/HT49C30L devices, which have single 8-bit Timer/Event Counter, associated register, known location where 8-bit value located. associated control register, known TMRC, contains setup information this timer. HT49R50A-1/HT49C50-1/HT49C50L devices, which contain 8-bit Timer/Event Counters, registers, known TMR0 TMR1, used store 8-bit values. pair associated registers, known TMR0C TMR1C, contain setup information these timers. HT49R70A-1/HT49C70-1/ HT49C70L devices, which contain single 8-bit Timer/Event Counter with associated register known TMR0, single 16-bit Timer/Event Counter with associated register pair known TMR1L/TMR1H, where values located. associated control registers, known TMR0C TMR1C contain setup information these timers. HT49RU80/ HT49CU80 devices contain 8-bit Timer/Event Counter with associated timer register known TMR0, 16-bit Timer/Event Counters with associated timer register pairs known TMR1L/TMR1H TMR2L/TMR2H. Their associated control registers known TMR0C, TMR1C TMR2C. Note that timer registers directly written order preload their contents with fixed data allow different time intervals setup.
Chapter Hardware Structure
Input/Output Port Registers
Within area Special Function Registers, registers play prominent role. input output ports have designated register correspondingly labeled etc. These labeled registers mapped specific addresses within Data Memory shown Data Memory table, which used transfer appropriate output input data that port. Type series, both Port Port ports their corresponding registers transfer both input output data. Port other hand only input port whose corresponding register only reads input data. flexible feature these registers ability directly program single bits using instructions.
UART Registers USR, UCR1, UCR2, TXR/RXR,
HT49RU80/HT49CU80 devices each contain internal UART function which controlled these five registers. status register UART while UCR1 UCR2 control registers. actual data that transmitted that received serial interface stored TXR/RXR register while Baud Rate UART setup register.
Input/Output Ports
Holtek microcontrollers offer significant flexibility their ports. Although Port remains fixed input only port, Port HT49RU80/HT49CU80 devices output only port, pins Port Port have ability function either input output. With further options such CMOS NMOS output types, pull-high wake-up functions, user provided with structure meet needs wide range application possibilities. Depending upon which device package chosen, Type series provides from bidirectional, input output lines. Ports known Port Port input Port known Port output Port Port These ports mapped Data Memory with specific addresses shown Special Purpose Data Memory table. Port Port ports used both input output operations, however, must noted that unlike some other series microcontrollers, Type series this achieved through port control registers. Setting input achieved first setting output high which effectively places NMOS output transistor high impedance state allowing used input. Note that this obviously only done output pins first configured NMOS output pins. this reason, configuration options have already setup output CMOS type, cannot subsequently used input. When used input, ports non-latching, which means that inputs must ready rising edge instruction where denotes port address. output operation data latched remains unchanged until output latch rewritten. Note that CMOS NMOS output type option only available Port pins PA0~PA3 Port pins PC0~PC3 PC4~PC7. CMOS NMOS output option applies blocks four pins, individual pins cannot selected this option. Port input port only output function. pins Port permanently connected internal pull-high resistor. There configuration options associated with Port additional Port HT49RU80/HT49CU80 devices output only lines chosen configuration option function either CMOS outputs segment output.
Type
Pull-high Resistors
Many product applications require pull-high resistors their switch inputs usually requiring external resistor. eliminate need these external resistors, some pins, when configured NMOS type have capability being connected internal pull-high resistor. These pull-high resistors selectable configuration options implemented using weak PMOS transistors. Pull-high options only available some pins. Type series, pull-high options selectable individual pins only selected blocks four time, pins PA0~PA3, PC0~PC3 PC4~PC7, while internal pull-high resistors permanently connected pins PA4~PA7 pins input port.
Port Wake-up
Each device HALT feature enabling microcontroller enter Power Down Mode preserve power, feature that important battery other low-power applications. Various methods exist wake-up microcontroller, which change logic condition Port pins from high low. After instruction forces microcontroller into entering HALT condition, processor will remain idle low-power state until logic condition selected wake-up Port changes from high low. This function especially suitable applications that woken external switches. Note that each Port selected individually have this wake-up feature.
Pin-shared Functions
flexibility microcontroller range greatly enhanced pins that have more than function. Limited numbers pins force serious design constraints designers supplying pins with multi-functions, many these difficulties overcome. some pins, chosen function multi-function pins configuration options while others function application program control. Buzzer Output buzzer pins pin-shared with pins PA1. configured buzzer pins, correct configuration options must selected. Output pin-shared with PA3. configured output correct configuration option must selected. External Interrupt Input external interrupt pins INT0 INT1 pin-shared with input pins respectively. applications requiring external interrupt inputs, these pins used normal pins, however, this, external interrupt enable bits INTC0 register must disabled.
Chapter Hardware Structure
External Timer Clock Input Each device Type MCUseries contains either one, three timers depending upon which chosen. Each timer external input pin, which case devices with single timer, known TMR. case devices with timers, their external timer input pins known TMR0 TMR1. HT49RU80/HT49CU80 devices, which contain three timers, their external timer pins known TMR0, TMR1 TMR2. devices with single timer, external input pin-shared with input PB2. devices with timers, external input pins TMR0 TMR1 pin-shared with input pins respectively. HT49RU80/HT49CU80 devices, their three timer pins pin-shared with pins PB2, PB4. these pin-shared pins function timer inputs, corresponding control bits timer control register must correctly set. These external timer input pins used normal data input pins applications that require external timer inputs. such applications, timer mode control bits timer control register must select timer mode, which internal clock source, prevent input from interfering with timer operation. UART Pins HT49RU80/HT49CU80 devices contain internal Universal Asynchronous Receiver/Transmitter UART function, which requires external pins their serial connection external devices. These pins known pin-shared with pins respectively. COM/SEG Outputs pins used directly drive common segment pins LCD. However, each device also which setup either segment common driver, which depending upon which device chosen, known COM3/SEG18, COM3/SEG32, COM3/ SEG40 COM3/SEG47. chosen common segment function these pins determined duty configuration option. duty configuration option chosen, then will setup COM3 driver. duty configuration option chosen, then corresponding function will selected. HT49RU80/HT49CU80 devices, configuration option exists permit Port used either outputs standard CMOS data outputs.
PA0~PA3 Input/Output Ports
Type
PA4~PA7 Input/Output Ports
Input Port
Input/Output Port
Chapter Hardware Structure
PC0/TX Input/Output Port HT49RU80/HT49CU80
PC1/RX Input/Output Port HT49RU80/HT49CU80
Output Port HT49RU80/HT49CU80
Type
Programming Considerations
Within application program, first things consider port initialization. After reset, both port registers, will high. important note that configuration options select NMOS types, when high output NMOS transistor will placed into high impedance condition, allowing used also input. generation high level NMOS outputs therefore reliant upon externally connected circuitry whether pull-high options have been selected. configuration options select CMOS output types, these cannot placed into high impedance condition therefore cannot used inputs. When using output, logic level setup loading byte wide data into appropriate port register Port Port programming individual bits these registers, using instructions. Note that when using these control instructions, read-modify-write operation takes place. microcontroller must first read data entire port, modify required values then rewrite this data back output ports. However, case NMOS type pins, there some special considerations that must noted. case NMOS that high microcontroller, i.e. placed into high impedance condition, driven externally connected circuitry, this would read being condition during read phase instructions. When ensuing write phase occurs, this pin, having been read being condition during read phase, would then consequently erroneously low. this reason great care must taken when using these control instructions with NMOS output types.
Port additional capability providing wake-up functions. When chip HALT state, various methods available wake device these high transition Port pins. Single multiple pins Port setup have this function.
Chapter Hardware Structure Liquid Crystal Display (LCD) Driver
large volume applications, which incorporate their design, custom display rather than more expensive character based display reduces costs significantly. However, corresponding signals required, which vary both amplitude time, drive such custom display require many special considerations proper operation occur. Holtek Type series, with their internal signal generating circuitry various configuration options, will automatically generate these time amplitude varying signals provide means direct driving easy interfacing range custom LCDs.
Memory
Each device Type series provides specific area Data Memory data. This data area known Memory. data written here will automatically read internal driver circuits, which will turn automatically generate necessary driving signals. Therefore data written into Memory will immediately reflected into actual display connected microcontroller. start address Memory devices Type series. However, memory capacity provided varies, dependent upon which device chosen, address Memory varies between 6FH. Data Memory addresses overlap those General Purpose Data Memory, Data Memory stored memory data bank, which different from that General Purpose Data Memory. With exception HT49RU80/HT49CU80 devices, other devices have their General Purpose Data Memory stored single Bank HT49RU80/HT49CU80 devices, General Purpose Data Memory stored Bank Bank Bank devices, Data Memory stored Bank Data Memory Bank chosen using Bank Pointer, which special function register Data Memory, with name, When lowest bits Bank Pointer have binary value additionally HT49RU80/HT49CU80 devices, only General Purpose Data Memory will accessed, read write actions Memory will take place. access Memory therefore requires first that Bank selected setting lowest bits Bank Pointer binary value After this, Memory then accessed using indirect addressing through Memory Pointer MP1. With Bank selected, then using read write memory area, 40H~52H, 40H~60H, 40H~68H 40H~6FH, depending upon which device chosen, will result operations Memory. Directly addressing Memory applicable will result data access Bank General Purpose Data Memory.
Type
Memory HT49RU80/HT49CU80 above diagrams based HT49RU80/HT49CU80 devices, which have either format pixel drive capability, with Memory address either 6FH. HT49R70A-1/HT49C70-1/HT49C70L devices have either format pixel drive capability, with Memory address either 67H. HT49R50A-1/HT49C50-1/HT49C50L devices have either format pixel drive capability, with Memory address either 5FH. HT49R30A-1/HT49C30-1/HT49C30L devices have either format pixel drive capability, with Memory address either 51H. devices, 4-COM format will automatically setup when duty configuration option selected while 3-COM format will automatically setup duty configuration option selected.
Note
type devices, duty configuration option selected then only three connections will provided, allowing each Memory address free general purpose use. However, duty configuration option selected, which will provide four connections less segment connection, then last address Memory will unused, however, user accessible read, will return value
Clock
clock driven internal clock source which originate from either oscillator, oscillator fSYS/4, choice which determined configuration option. proper operation, this internal clock source then passes through divider, provide clock source frequency near possible 4kHz.
Clock Source Oscillator Oscillator fSYS/4
Clock Selection WDT/22 RTC/23
Clock Frequency Selection
Chapter Hardware Structure
available division ratios, however, depends clock source that used internal clock source, clock source originates from oscillator, then only fixed division ratio fS/22 available. clock source originates from oscillator, then only division ratio fS/23 available. However, clock source originates from fSYS/4, then range clock frequencies available from fS/22 fS/28, value which selected further available configuration option. These ratios ensure that proper operation, signal frequency near possible 4kHz, selected. clock frequency 4kHz, microcontroller driver circuitry will generate frame frequency between 55Hz 62Hz. This line with general operating frequency range which lies between 25Hz 250Hz. Note that selected clock frequency high, this will result higher than required frame frequency give rise higher power consumption while selecting frequency result flicker. therefore important that fSYS/4 used clock source correct configuration option should chosen obtain clock frequency close 4kHz possible.
Driver Output
number outputs supplied driver, well biasing duty options, dependent upon device chosen configuration options selected. accompanying table lists various options each devices Type series.
Part HT49R30A-1 HT49C30-1 Duty HT49R50A-1 HT49C50-1 HT49R70A-1 HT49C70-1 HT49RU80 HT49CU80 Driver Number type type type type Bias Bias Type
Driver Outputs, Duty Bias Options Note Voltage HT49C30L, HT49C50L, HT49C70L devices differ from other devices having fixed bias type bias only, however, they have same duty driver number options their mask level sister devices.
Type
nature Liquid Crystal Displays require that only voltages applied their pixels application voltages pixels will cause permanent damage. this reason relative contrast display controlled actual voltage applied each pixel, which equal value voltage minus voltage applied pin. This differential voltage must greater than saturation voltage pixel less than threshold voltage pixel off. requirement limit voltage zero control many pixels possible with minimum number connections, requires that both time amplitude signal generated applied application LCD. These time amplitude varying signals automatically generated driver circuits microcontroller. What known duty determines number common lines used, which also known backplanes COMs. duty, which chosen configuration option have value 1/2, which equates number respectively, therefore defines number time divisions within each signal frame. following timing diagrams depict signals generated microcontroller various values duty bias.
Driver Output (1/3 Duty, Bias)
Chapter Hardware Structure
Note HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 HT49RU80/HT49CU80 devices, VA=VLCD, both type. HT49C30L, HT49C50L HT49C70L devices, VA=2V2, VB=V2, only type bias applicable.
Driver Output (1/2 Duty, Bias)
Note
HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 HT49RU80/HT49CU80 devices, VA=VLCD, both type. HT49C30L, HT49C50L HT49C70L devices, VA=2V2, VB=V2, only type bias applicable.
Type
itte
Driver Output (1/4 Duty, Bias)
Note
HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 HT49RU80/HT49CU80 devices, VA=VLCD, type while VB=VLCD type. HT49C30L, HT49C50L HT49C70L, bias applicable.
Chapter Hardware Structure
Driver Output (1/3 Duty, Bias)
Note
HT49R30A-1/HT49C30-1, HT49R50A-1/HT49C50-1, HT49R70A-1/HT49C70-1 HT49RU80/HT49CU80 devices, VA=VLCD, type while VB=VLCD type. HT49C30L, HT49C50L HT49C70L, bias applicable.
Type
Voltage Source Biasing
time amplitude varying signals generated Holtek Type microcontrollers require generation several voltage levels their operation. number voltage levels used signal depends upon device chosen bias configuration options. Biasing HT49C30L, HT49C50L HT49C70L devices have fixed bias value whereas other devices have configuration option select either bias. bias configuration option, three voltage levels VSS, utilized. With exception HT49C30L, HT49C50L HT49C70L devices, type biasing equal VLCD, which externally supplied voltage source. This could microcontroller power supply some other voltage source. generated internally microcontroller will have value equal VLCD/2. bias option, four voltage levels VSS, utilized. external voltage source also provided VLCD generate these voltages. actual value voltages depends whether type option selected. Note that because type bias option uses charge pump circuit, higher voltages than what provided externally VLCD generated. This feature useful applications where microcontroller supply voltage less than supply voltage required LCD. type bias option, voltage level, same externally supplied VLCD voltage while voltage levels determined internal resistor divider. type bias option, required. Note that external resistors required. however recommended that external capacitors still connected pins stabilize these internally generated voltage levels. case type bias option, charge-pump capacitor between pins filter capacitors pins required generate necessary voltage levels. case HT49C30L, HT49C50L HT49C70L devices, used voltage source input, therefore capacitor omitted from this pin, however, additional capacitor should connected VLCD. HT49C30L, HT49C50L HT49C70L devices, which always utilize voltage supply, perhaps operating from single cell battery, higher supply voltages required generated internal charge pump voltage-doubler circuit. these devices external voltage supply connected normally this microcontroller power supply could some other voltage source. voltage supplied will doubled value internal charge pump circuit creating value. actual value external voltage supplied depends upon voltage requirements application LCD.
Type Bias Voltage Levels
Chapter Hardware Structure
Type Bias Voltage Levels
Note
type bias configuration options available HT49C30L, HT49C50L HT49C70L devices. VMAX only exists HT49RU80/HT49CU80 devices.
VMAX Connection HT49RU80/HT49CU80 only HT49RU80/HT49CU80 devices there additional VMAX which must connected certain depending upon voltage that applied VLCD pin. following table should consulted ensure correct connection this pin.
Biasing Type Bias Type Bias Otherwise VDD>VLCD Type Bias Otherwise Connect VMAX VLCD Connect VMAX VLCD Connect VMAX VLCD Voltage Otherwise VDD>VLCD VMAX Connection Connect VMAX Connect VMAX Connect VMAX
Type
Programming Considerations
Certain precautions must taken when programming LCD. these ensure that memory properly initialized after microcontroller powered Like General Purpose Data Memory, contents memory unknown condition after power-on. contents memory will mapped into actual LCD, important initialize this memory area into known condition soon after applying power obtain proper display pattern. Consideration must also given capacitive load actual used application. load presented microcontroller pixels generally modeled mainly capacitive nature, important that this excessive, point that particularly true case lines which connected many pixels. accompanying diagram depicts equivalent circuit LCD.
Panel Equivalent Circuit
Setting correct frequency clock another factor which must taken into account user applications. have LCDs operate their best frame frequency, which normally between 25Hz 250Hz, important select appropriate clock frequency configuration option. correct option should chosen ensure that clock frequency close 4kHz possible achieved. With such frequency chosen, microcontroller internal driver circuits will ensure that appropriate driving signals generated obtain suitable frame frequency. additional consideration that must taken into account what happens when microcontroller enters HALT condition. configuration option permits powered when Power Down Mode reduce power consumption. this option selected, after instruction executed, driving signals will cease, producing blank display pattern reducing power consumption associated with LCD. memory remains unaffected execution instruction, when microcontroller wakes-up driving signals resume, original display pattern will restored. configuration option selects display remain when Power Down Mode, driving signals will continue generated, therefore pattern will remain undisturbed, however, should noted that such action will result power being consumed.
Chapter Hardware Structure Timer/Event Counters
provision timers forms important part microcontroller giving designer means carrying time related functions. devices Type series contain either one, three count timers either 16-bit capacity depending upon which device selected. each timer three different operating modes, they configured operate general timer, external event counter pulse width measurement device. There types registers related Timer/Event Counters. first register that contains actual value timer into which initial value preloaded. Reading from this register retrieves contents Timer/Event Counter. second type associated register timer control register which defines timer options determines timer used. timer clock source configured come from internal clock source from external timer pin. accompanying table lists associated timer register names.
HT49R30A-1 HT49C30-1 HT49C30L 8-bit Timers Timer Register Name Timer Control Register 16-bit Timers Timer Register Name Timer Control Register TMRC HT49R50A-1 HT49C50-1 HT49C50L TMR0/TMR1 TMR0C/TMR1C HT49R70A-1 HT49C70-1 HT49C70L TMR0 TMR0C TMR1L/TMR1H TMR1C HT49RU80 HT49CU80 TMR0 TMR0C TMR1L/TMR1H TMR2L/TMR2H TMR1C TMR2C
external clock source used when timer event counting mode, clock source being provided external timer known TMR, TMR0, TMR1 TMR2 depending which device selected. These external pins pin-shared with Port Input pins. Depending upon condition T0E, corresponding timer control register, each high low, high transition external timer input will increment counter one.
Configuring Timer/Event Counter Input Clock Source
internal clock originate from various sources, depending upon which device which timer chosen. internal clock input timer source used when timer timer mode pulse width measurement mode. This internal clock source originate from either system clock, system clock/4, clock, Time Base Timer/Event Counter overflow depending upon timer chosen, which configuration options selected upon counter configured application program. external clock source used when timer event counting mode, clock source being provided external timer pin, TMR, TMR0, TMR1 TMR2 depending upon which device which timer used. Depending upon condition T0E, bit, each high low, high transition external timer will increment counter one.
Type
8-bit Timer/Event Counter Structure HT49R30A-1/HT49C30-1/HT49C30L
8-bit Timer/Event Counter Structure HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L HT49RU80/HT49CU80
8-bit Timer/Event Counter Structure HT49R50A-1/HT49C50-1/HT49C50L
16-bit Timer/Event Counter Structure HT49R70A-1/HT49C70-1/HT49C70L, HT49RU80/HT49CU80
Chapter Hardware Structure
16-bit Timer/Event Counter Structure HT49RU80/HT49CU80
Timer Registers TMR0, TMR1, TMR1L/TMR1H, TMR2L/TMR2H
timer registers special function registers located special purpose Data Memory place where actual timer value stored. 8-bit timer, this register known Timer/Event Counter HT49R30A-1/HT49C30-1/HT49C30L devices, Timer/Event Counter HT49R70A-1/HT49C70-1/HT49C70L HT49RU80/HT49CU80 devices well Timer/Event Counter Timer/Event Counter HT49R50A-1/HT49C50-1/HT49C50L devices. case 16-bit timer, pair 8-bit registers required store 16-bit timer values. These known TMR1L/TMR1H HT49R70A-1/HT49C70-1/HT49C70L devices TMR1L/TMR1H TMR2L/TMR2H HT49RU80/HT49CU80 devices. value timer registers increases each time internal clock pulse received external transition occurs external timer pin. timer will count from initial value loaded preload register full count 8-bit timer FFFFH 16-bit timers, which point timer overflows timer internal interrupt signal generated. timer value will then reset with initial preload register value continue counting. Note that achieve maximum full range count 8-bit timer FFFFH 16-bit timers, preload registers must first cleared zeros. should noted that after power-on, preload registers will unknown condition. Note that Timer/Event Counters condition data written their preload registers, this data will immediately written into actual counter. However, counter enabled counting, data written into preload data register during this period will remain preload register will only written into actual counter next time overflow occurs. Note also that when timer registers read, timer clock will blocked avoid errors, however, this result certain timing errors, programmers must take this into account. devices which have 16-bit Timer/Event Counter, which therefore have contain both byte high byte timer registers, accessing these registers carried specific way. must noted that when using instructions preload data into byte register, namely TMR1L TMR2L, data will only placed byte buffer directly into byte register. actual transfer data into byte register only carried when write associated high byte register, namely TMR1H TMR2H, executed. other hand, using instructions preload data into high byte timer register will result data being directly written high byte register. same time data byte buffer will transferred into associated byte register. this reason, when preloading data into 16-bit timer registers, byte should written first. must also noted that read contents byte register, read high byte register must first executed latch contents byte buffer into
Type
associated byte register. After this been done, byte register read normal way. Note that reading byte timer register will only result reading previously latched contents byte buffer actual contents byte timer register.
Timer Control Registers TMRC, TMR0C, TMR1C, TMR2C
flexible features Holtek microcontroller Timer/Event Counters enable them operate three different modes, options which determined contents their respective control register. devices with only timer, single timer control register known TMRC while devices with timers, there timer control registers known TMR0C TMR1C. devices with three timers, there three timer control registers, known TMR0C, TMR1C TMR2C. timer control register together with corresponding timer registers that control full operation Timer/Event Counters. Before timers used, essential that appropriate timer control register fully programmed with right data ensure correct operation, process that normally carried during program initialization. choose which three modes timer operate either timer mode, event counting mode pulse width measurement mode, bits Timer Control Register, which known pair TM1/TM0, T0M1/T0M0, T1M1/T1M0 T2M1/T2M0 respectively, depending upon which timer used, must required logic levels. timer-on bit, which Timer Control Register known TON, T0ON, T1ON T2ON, depending upon which timer used, provides basic on/off control respective timer. Setting high allows counter run, clearing stops counter. timer event count pulse width measurement mode, active transition edge level type selected logic level Timer Control Register which known T0E, T2E, depending upon which timer used. With exception Timer/Event Counter HT49RU80/HT49CU80 devices, additional clock source bit, known T1S, depending upon which timer used, determines which internal clock source used Timer/Event counter.
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Chapter Hardware Structure
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Type
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Configuring Timer Mode
this mode, timer utilized measure fixed time intervals, providing internal interrupt signal each time counter overflows. operate this mode, pair, TM1/TM0, T0M1/T0M0, T1M1/T1M0 T2M1/T2M0, depending upon which timer used, must respectively. this mode, internal clock sources used timer clock. Depending upon which timer used, clock source configuration option logic state T1S, timer input clock source either fSYS, fSYS/4, fRTC, Time Base interrupt Timer/Event Counter overflow. timer-on bit, TON, T0ON, T1ON T2ON, depending upon which timer used, must high enable timer run. Each time internal clock high transition occurs, timer increments one; when timer full overflows, interrupt signal generated timer will preload value already loaded into preload register continue counting. timer overflow condition corresponding internal interrupt wake-up sources, however, internal interrupts disabled ensuring that ET0I ET1I ET2I bits corresponding interrupt register reset zero.
Timer Mode Timing Chart
Chapter Hardware Structure
Configuring Event Counter Mode
this mode, number externally changing logic events, occurring external timer pin, recorded internal timer. timer operate event counting mode, pair, TM1/TM0, T0M1/T0M0, T1M1/T1M0 T2M1/T2M0, depending upon which timer used, must respectively. timer-on bit, TON, T0ON, T1ON T2ON, depending upon which timer used, must high enable timer count. Depending upon which timer used, T0E, low, counter will increment each time external timer receives high transition. T0E, high, counter will increment each time external timer receives high transition. case other modes, when counter full, timer will overflow generate internal interrupt signal. counter will then preload value already loaded into preload register. Since external timer pins pin-shared with other pins, ensure that these configured operate event counter pins, only necessary ensure that TM1/TM0, T0M1/T0M0, T1M1/T1M0 T2M1/T2M0 bits place Timer/Event Counter event counting mode. should noted that timer overflow interrupt wake-up sources.
Event Counter Mode Timing Chart
Configuring Pulse Width Measurement Mode
this mode, width external pulses applied external timer measured. Pulse Width Measurement Mode, timer clock source supplied internal clock. timer operate this mode, pair, TM1/TM0, T0M1/T0M0, T1M1/T1M0 T2M1/T2M0, depending upon which timer used, must both high. Depending upon which counter used, T0E, low, once high transition been received external timer pin, timer will start counting until external timer returns original high level. this point TON, T0ON, T1ON T2ON bit, depending upon which counter used, will automatically reset zero timer will stop counting. T0E, high, timer will begin counting once high transition been received external timer stop counting when external timer returns original level. before, TON, T0ON, T1ON T2ON will automatically reset zero timer will stop counting. important note that Pulse Width Measurement Mode, TON, T0ON, T1ON T2ON automatically reset zero when external control signal external timer returns original level, whereas other modes TON, T0ON, T1ON T2ON only reset zero under program control. residual value timer, which read program, therefore represents length pulse received external timer pin. TON, T0ON, T1ON T2ON been reset, further transitions external timer pin, will ignored. until TON, T0ON, T1ON T2ON again high program timer begin further pulse width measurements. this way, single shot pulse measurements easily made. should noted that this mode counter controlled logical transitions external timer logic level.
Type
case other modes, when counter full, timer will overflow generate internal interrupt signal. counter will also reset value already loaded into preload register. Since external timer pins pin-shared with other pins, ensure that these configured operate pulse width measurement pins, only necessary ensure that TM1/TM0, T0M1/T0M0, T1M1/T1M0 T2M1/T2M0 bits place Timer/Event Counter Pulse Width Measuring Mode. should noted that timer overflow interrupt wake-up sources.
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Pulse Width Measurement Mode Timing Chart
Programmable Frequency Divider
output pin-shared with PA3. function selected configuration option, however, selected operate normal pin. Timer/Event counter overflow signal clock source circuit. Note that HT49R50A-1/ HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L HT49RU80/HT49CU80 devices, which have more than internal Timer/Event Counter, timer source chosen, configuration option, come from either Timer/Event Counter Timer/Event Counter counter driven internal system clock sources initial value controlled value written into preload registers. counter will begin count-up from this preload register value until full, which point overflow signal generated, causing output change state. counter will then automatically reloaded with preload register value continue counting-up. frequency will therefore half frequency timer overflow signal. Refer relevant Timer/Event Counters section details settings operations. output will only activated cleared This output data used on/off control output. Note that output will output data When configuration options select function output, then pins PA0~PA3 will configured CMOS types.
Output Control Using this method frequency generation, crystal oscillator used system clock, very precise values frequency generated.
Chapter Hardware Structure
Interfacing
Timer/Event Counter when configured event counter Pulse Width Measurement Mode, require external timer pins correct operation. These external timer pins pin-shared with other Port input pins which permanently connected pull-high resistors. timers also setup drive pin-shared PFDpin. When selected selecting correct configuration option, output chosen timer made drive this frequency determined contents timer register source clock frequency.
Programming Considerations
When configured timer mode, internal system clock sources used timer clock source therefore synchronized with overall operation microcontroller. this mode, when appropriate timer register full, microcontroller will generate internal interrupt signal directing program flow respective internal interrupt vector. Pulse Width Measurement Mode, internal system clock sources also used timer clock source timer will only when correct logic condition appears external timer input pin. this external event synchronized with internal timer clock, microcontroller will only this external event when next timer clock pulse arrives. result, there small differences measured values requiring programmers take this into account during programming. same applies timer configured event counting mode, which again external event synchronized with internal system timer clock. HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L HT49RU80/HT49CU80 devices which have three internal timers, there configuration option enable overflow Timer/Event Counter clock source Timer/Event Counter cascading timers this 16-bit timer created HT49R50A-1/ HT49C50-1/HT49C50L devices 24-bit timer created HT49R70A-1/HT49C70-1/ HT49C70L HT49RU80/HT49CU80 devices. However, timers used this cascaded configuration part initialization process, Timer/Event Counter must first enabled then immediately disabled before being used. following program example, based HT49R70A-1/HT49C70-1/HT49C70L devices shows interrupt timer control registers initialized timer enable used control on/off function timers. this example Timer/Event Counter clock source Timer/Event Counter this setup configuration option cascade timers together give 24-bit timer. Note when used this configuration Timer/Event Counter first enabled then immediately disabled ensure correct initialization.
Type
Example: Using Timer/Event Counter clock source Timer/Event Counter configure 24-bit counter START: a,09h intc0,a a,01h intc1,a a,80h tmr1c,a a,0a0h tmr0c,a ET0I bits enable Timer global interrupt ET1I enable Timer interrupt Configure Timer operate Timer clock source depends Configure Timer operate select system clock/4 timer mode configuration option timer mode Timer clock source
tmr1c.4 tmr1c.4 a,00h tmr0,a a,00h tmr1l,a tmr1h,a
Enable then disable Timer Necessary step cascaded timers Load desired value into both TMR0 TMR1 registers
tmr0c.4 tmr1c.4
Turn Timer Turn Timer
Interrupts
type microcontrollers each contains range both external internal interrupt functions. external interrupt controlled action external pins INT0 INT1 which present devices. internal interrupts controlled various sources which include Timer/Event Counters, Time Base Real Time Clock. Additionally, HT49RU80/HT49CU80 devices there UART interrupt Multi-function interrupt.
Interrupt Registers
type microcontroller devices, three interrupt control registers, known INTC0, INTC1 MFIC, provided control interrupt control features. Note that only HT49RU80/HT49CU80 devices contain MFIC register. Once interrupt subroutine serviced, other interrupts will blocked, will cleared automatically. This will prevent further interrupt nesting from occurring. However, other interrupt requests occur during this interval, although interrupt will immediately serviced, request flag will still recorded. interrupt requires immediate servicing while program already another interrupt service routine, should after entering routine, allow interrupt nesting. stack full, interrupt request will acknowledged, even related interrupt enabled, until Stack Pointer decremented. immediate service desired, stack must prevented from becoming full.
Chapter Hardware Structure
interrupts have capability waking processor when Power Down Mode. interrupt serviced, control transfer occurs pushing Program Counter onto stack, followed branch subroutine specified location Program Memory. Only Program Counter pushed onto stack. contents accumulator, status register other registers altered interrupt service routine, which corrupt desired control sequence, then contents should saved advance.
Type
Chapter Hardware Structure
lti- lti-
Type
various interrupt enable bits, together with their associated request flags, shown following diagram with their order priority.
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Interrupt Scheme HT49R30A-1/HT49C30-1/HT49C30L
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Interrupt Scheme HT49R50A-1/HT49C50-1/HT49C50L HT49R70A-1/HT49C70-1/HT49C70L
Chapter Hardware Structure
lti-
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Interrupt Scheme HT49RU80/HT49CU80
Interrupt Priority
Interrupts, occurring interval between rising edges consecutive pulses, will serviced latter pulses, corresponding interrupts enabled. case simultaneous requests, following table shows priority that applied.
Interrupt Source HT49R30A-1 HT49C30-1 HT49C30L Priority HT49R50A-1 HT49C50-1 HT49C50L Priority HT49R70A-1 HT49C70-1 HT49C70L Priority HT49RU80 HT49CU80 Priority
External Interrupt External Interrupt Timer/Event Counter Timer/Event Counter Overflow Timer/Event Counter Overflow Timer/Event Counter Overflow UART Interrupt Time Base Interrupt Real Time Clock Interrupt Multi-function Interrupt
Type
Note HT49R30A-1/HT49C30-1/HT49C30L devices, there only timer. HT49R50A-1/HT49C50-1/HT49C50L HT49R70A-1/HT49C70-1/HT49C70L devices have internal timers, HT49RU80/HT49CU80 devices have three internal timers. Only HT49RU80/HT49CU80 devices have UART interrupt. HT49RU80/HT49CU80 devices, Timer/Event Counter overflow, Time Base interrupt interrupt, contained within single Multi-function interrupt.
cases where both external internal interrupts enabled where external internal interrupt occur simultaneously, external interrupt will always have priority will therefore serviced first. Suitable masking individual interrupts using INTC0, INTC1 MFIC registers prevent simultaneous occurrences. external interrupt pins INT0 INT1 pin-shared with input pins respectively only configured external interrupt pins correct register bits have been programmed. Note that these input pins permanently connected pull-high resistors.
External Interrupt
devices Type series possess external interrupts known External Interrupt External Interrupt with corresponding external pin-shared inputs INT0 INT1. external interrupt occur, corresponding external interrupt enable must first set. External Interrupt this INTC0 register known EEI0. External Interrupt this INTC0 register known EEI1. External Interrupt triggered high transition INT0 line, after which related interrupt request flag, EIF0; which INTC0, will set. External Interrupt triggered high transition INT1 line, after which related interrupt request flag, EIF1; which INTC0, will set. When required interrupt enabled stack full, subroutine call location will occur when high transition occurs INT0 line. other hand, call location will occur when high transition occurs INT1 line. interrupt request flag, either EIF0 EIF1, depending upon what external interrupt occurred, will reset will cleared disable other interrupts.
Timer/Event Counter Interrupt
timer generated internal interrupt occur, corresponding internal interrupt enable must first set. devices with single timer, this INTC0 register known ETI. devices with timers, Timer/Event Counter interrupt enable INTC0 register known ET0I while Timer/Event Counter interrupt enable INTC1 register known ET1I. case HT49RU80/HT49CU80 devices, which have three internal Timer/Event Counters, Timer/Event Counter interrupt enable INTC0 register known ET0I, Timer/Event Counter interrupt enable INTC1 register known ET1I Timer/Event Counter interrupt enable MFIC register known ET2I. actual Timer/Event Counter interrupt will initialized when Timer/Event Counter interrupt request flag set, caused timer overflow. HT49R30A-1/HT49C30-1/HT49C30L devices, which have single timer, this INTC0 register known HT49R50A-1/HT49C50-1/HT49C50L, HT49R70A-1/HT49C70-1/HT49C70L HT49RU80/HT49CU80 devices, Timer/Event Counter request flag INTC0 register known T0F, while Timer/Event Counter request flag INTC1 register
Chapter Hardware Structure
known T1F. case HT49RU80/HT49CU80 devices which have three timers, Timer/Event Counter request flag MFIC register known T2F. Because interrupt vector Timer/Event Counter contained with Multi-function interrupt, interrupt generated Timer/Event Counter Multi-function interrupt must also enabled setting EMFI INTC1 register. When this done, Timer/Event Counter overflow will also cause Multi-function request flag, known MFF, which INTC1 register turn generate interrupt. When master interrupt global enable set, stack full corresponding timer internal interrupt enable set, timer interrupt will generated when corresponding timer overflows. This will create subroutine call location 00CH devices with single timer. devices with timers, subroutine call location 00CH will occur Timer/Event Counter subroutine call location 010H
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