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SC9RS08MZ8
Data Sheet: Technical Data
RS08 Microcontrollers
Find most current versions documents http://www.freescale.com
SC9RS08MZ8 Rev. 9/2008
freescale.com
SC9RS08MZ8 Features
8-Bit RS08 Central Processor Unit (CPU) Development Support
across temperature range -40°C 85°C Subset HC08 instruction with added BGND instruction
Single-wire background debug interface Breakpoint capability allow single breakpoint setting during in-circuit debugging
On-Chip Memory
Peripherals
Flash read/program/erase over full operating voltage temperature Random-access memory (RAM) Security circuitry prevent unauthorized access flash contents
Power-Saving Modes
Stop mode Wakeup from power-saving modes using real-time interrupt (RTI) ACMP
Clock Source Options
Oscillator (XOSC) Loop-control Pierce oscillator; crystal ceramic resonator range 31.25 39.0625 Internal Clock Source (ICS) Internal clock source module containing frequency-locked-loop (FLL) controlled internal external reference; precision trimming internal reference allows 0.2% resolution deviation over temperature voltage; supports frequencies
12-channel, 8-bit resolution; conversion time; automatic compare function; operation stop; fully functional from 2-channel; selectable input capture, output compare, buffered edgeor center-aligned each channel MTIM1 MTIM2 8-bit modulo timers ACMP Analog comparator; full rail-to-rail supply operation; option compare fixed internal bandgap reference voltage; operate stop mode
Input/Output
GPIOs including output only input only Hysteresis configurable pullup device input pins; configurable slew rate drive strength output pins
Package Options
20-pin SOIC
System Protection
Watchdog computer operating properly (COP) reset with option from dedicated internal clock source clock Low-voltage detection with reset interrupt Illegal opcode detection with reset Illegal address detection with reset Flash-block protection
SC9RS08MZ8 Data Sheet
Covers: SC9RS08MZ8
SC9RS08MZ8 Rev. 9/2008
Revision History
provide most up-to-date information, revision documents World Wide will most current. Your printed copy earlier revision. verify have latest information available, refer http://freescale.com following revision history table summarizes changes contained this document.
Revision Number
Revision Date
9/11/2008 Initial publish released.
Description Changes
This product incorporates SuperFlash® technology licensed from SST. Freescale Freescale logo trademarks Freescale Semiconductor, Inc. Freescale Semiconductor, Inc., 2008. rights reserved.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
List Chapters
Chapter Number Title Page Chapter Device Overview Chapter Pins Connections Chapter Modes Operation Chapter Memory Chapter Resets, Interrupts, General System Control Chapter Parallel Input/Output Control Chapter Central Processor Unit (RS08CPUV1) Chapter Analog Comparator (RS08ACMPV1) Chapter 8-Bit Analog-to-Digital Converter (RS08ADC10V1) Chapter Internal Clock Source (RS08ICSOSCV1) Chapter Modulo Timer (RS08MTIMV1) Chapter 16-Bit Timer/PWM (RS08TPMV2) Chapter Development Support
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Contents
Section Number Title Chapter Device Overview
Overview Block Diagram System Clock Distribution
Page
Chapter Pins Connections
Introduction Device Assignment Recommended System Connections Detail 2.4.1 Power Pins 2.4.2 PTA5/TCLK/RESET/VPP 2.4.3 PTA4/ACMPO/BKGD/MS 2.4.4 General-Purpose Peripheral Ports
Chapter Modes Operation
Introduction Features Mode Active Background Mode Stop Mode 3.5.1 Active Enabled Stop Mode 3.5.2 Enabled Stop Mode
Chapter Memory
Memory Unimplemented Memory Indexed/Indirect Addressing Register Addresses Assignments Flash 4.6.1 Features 4.6.2 Flash Programming Procedure 4.6.3 Flash Mass Erase Operation 4.6.4 Security
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Flash Registers Control Bits 4.7.1 Flash Options Register (FOPT NVOPT) 4.7.2 Flash Control Register (FLCR) Page Select Register (PAGESEL)
Chapter Resets, Interrupts, General System Control
Introduction Features Reset Computer Operating Properly (COP) Watchdog Interrupts Low-Voltage Detect (LVD) System 5.6.1 Power-On Reset Operation 5.6.2 Reset Operation 5.6.3 Interrupt Operation Real-Time Interrupt (RTI) Reset, Interrupt, System Control Registers Control Bits 5.8.1 System Reset Status Register (SRS) 5.8.2 System Options Register (SOPT) 5.8.3 System Device Identification Register (SDIDH, SDIDL) 5.8.4 System Real-Time Interrupt Status Control Register (SRTISC) 5.8.5 System Power Management Status Control Register (SPMSC1) 5.8.6 System Interrupt Pending Register (SIP1)
Chapter Parallel Input/Output Control
Behavior Low-Power Modes Parallel Registers 6.2.1 Port Registers 6.2.2 Port Registers 6.2.3 Port Registers Control Registers 6.3.1 Port Control Registers 6.3.2 Port Control Registers 6.3.3 Port Control Registers
Chapter Central Processor Unit (RS08CPUV1)
Introduction Programmer's Model Registers 7.2.1 Accumulator 7.2.2 Program Counter (PC) 7.2.3 Shadow Program Counter (SPC) 7.2.4 Condition Code Register (CCR)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
7.2.5 Indexed Data Register (D[X]) 7.2.6 Index Register 7.2.7 Page Select Register (PAGESEL) Addressing Modes 7.3.1 Inherent Addressing Mode (INH) 7.3.2 Relative Addressing Mode (REL) 7.3.3 Immediate Addressing Mode (IMM) 7.3.4 Tiny Addressing Mode (TNY) 7.3.5 Short Addressing Mode (SRT) 7.3.6 Direct Addressing Mode (DIR) 7.3.7 Extended Addressing Mode (EXT) 7.3.8 Indexed Addressing Mode (IX, Implemented Pseudo Instructions) Special Operations 7.4.1 Reset Sequence 7.4.2 Interrupts 7.4.3 Wait Stop Mode 7.4.4 Active Background Mode Summary Instruction Table
Chapter Analog Comparator (RS08ACMPV1)
Introduction 8.1.1 Features 8.1.2 Modes Operation 8.1.3 Block Diagram External Signal Description Register Definition 8.3.1 ACMP Status Control Register (ACMPSC) Functional Description
Chapter 8-Bit Analog-to-Digital Converter (RS08ADC10V1)
Introduction 9.1.1 Module Configurations 9.1.2 Features 9.1.3 Block Diagram External Signal Description 9.2.1 Analog Power (VDDAD) 9.2.2 Analog Ground (VSSAD) 9.2.3 Voltage Reference High (VREFH) 9.2.4 Voltage Reference (VREFL) 9.2.5 Analog Channel Inputs (ADx) Register Definition 9.3.1 Status Control Register (ADCSC1) 9.3.2 Status Control Register (ADCSC2)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
9.3.3 Data Result High Register (ADCRH) 9.3.4 Data Result Register (ADCRL) 9.3.5 Compare Value High Register (ADCCVH) 9.3.6 Compare Value Register (ADCCVL) 9.3.7 Configuration Register (ADCCFG) 9.3.8 Control Register (APCTL1) 9.3.9 Control Register (APCTL2) 9.3.10 Control Register (APCTL3) Functional Description 9.4.1 Clock Select Divide Control 9.4.2 Input Select Control 9.4.3 Hardware Trigger 9.4.4 Conversion Control 9.4.5 Automatic Compare Function .102 9.4.6 Wait Mode Operation .102 9.4.7 Stop Mode Operation .103 Initialization Information .103 9.5.1 Module Initialization Example .104 Application Information .105 9.6.1 External Pins Routing .106 9.6.2 Sources Error .107
Chapter Internal Clock Source (RS08ICSOSCV1)
10.1 Introduction 10.1.1 Features .113 10.1.2 Modes Operation .113 10.1.3 Block Diagram .114 10.2 External Signal Description .115 10.3 Register Definition .115 10.3.1 Control Register (ICSC1) .115 10.3.2 Control Register (ICSC2) .117 10.3.3 Trim Register (ICSTRM) .118 10.3.4 Status Control (ICSSC) .118 10.4 Functional Description .119 10.4.1 Operational Modes .119 10.4.2 Mode Switching .121 10.4.3 Frequency Divider .121 10.4.4 Power Usage .121 10.4.5 Internal Reference Clock .122 10.4.6 Optional External Reference Clock .122 10.4.7 Fixed Frequency Clock .122
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Modulo Timer (RS08MTIMV1)
11.1 Introduction .123 11.1.1 Features .125 11.1.2 Modes Operation .125 11.1.3 Block Diagram .126 11.2 External Signal Description .126 11.3 Register Definition .126 11.3.1 MTIM Status Control Register (MTIMSC) .127 11.3.2 MTIM Clock Configuration Register (MTIMCLK) .128 11.3.3 MTIM Counter Register (MTIMCNT) .128 11.3.4 MTIM Modulo Register (MTIMMOD) .129 11.4 Functional Description .130 11.4.1 MTIM Operation Example .131
Chapter 16-Bit Timer/PWM (RS08TPMV2)
12.1 Introduction .133 12.1.1 Features .135 12.1.2 Block Diagram .135 12.2 External Signal Description .137 12.2.1 External Clock Sources .137 12.2.2 TPMCHn Channel Pins .137 12.3 Register Definition .137 12.3.1 Timer Status Control Register (TPMSC) .138 12.3.2 Timer Counter Registers (TPMCNTH:TPMCNTL) .139 12.3.3 Timer Counter Modulo Registers (TPMMODH:TPMMODL) .140 12.3.4 Timer Channel Status Control Register (TPMCnSC) .141 12.3.5 Timer Channel Value Registers (TPMCnVH:TPMCnVL) .142 12.4 Functional Description .143 12.4.1 Counter .143 12.4.2 Channel Mode Selection .144 12.4.3 Center-Aligned Mode .146 12.5 Interrupts .147 12.5.1 Clearing Timer Interrupt Flags .147 12.5.2 Timer Overflow Interrupt Description .147 12.5.3 Channel Event Interrupt Description .148 12.5.4 End-of-Duty-Cycle Events .148
Chapter Development Support
13.1 Introduction .149 13.2 Features .149 13.3 RS08 Background Debug Controller (BDC) .150 13.3.1 BKGD Description .151
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
13.3.2 Communication Details .151 13.3.3 SYNC Serial Communication Timeout .154 13.4 Registers Control Bits .155 13.4.1 Status Control Register (BDCSCR) .155 13.4.2 Breakpoint Match Register .156 13.5 RS08 Commands .157
Appendix Electrical Characteristics
A.10 A.11 A.12 A.13 A.14 Introduction .161 Parameter Classification .161 Absolute Maximum Ratings .161 Thermal Characteristics .162 Protection Latch-Up Immunity .163 Characteristics .164 Supply Current Characteristics .167 External Oscillator (XOSC) Characteristics .169 Characteristics .170 A.9.1 Control Timing .170 A.9.2 TPM/MTIM Module Timing .170 Analog Comparator (ACMP) Electrical .171 Internal Clock Source Characteristics .171 Characteristics .172 Flash Specifications .174 Performance .176 A.14.1 Radiated Emissions .177
Appendix Ordering Information
Mechanical Drawings .179
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Device Overview
Overview
SC9RS08MZ8 microcontroller unit (MCU) extremely low-cost, small count, high performance device intended home appliances, medical equipment. general purpose microcontroller, this device composed standard on-chip modules including very small highly efficient RS08 core, bytes RAM, bytes flash, 8-bit modulo timers,12-channel 8-bit ADC, 2-channel 16-bit Timer/PWM, analog comparator. device available 20-pin SOIC package.
Block Diagram
block diagram, Figure 1-1, shows SC9RS08MZ8 structure.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Device Overview
RS08 CORE PTA5/TCLK/RESET/VPP PORT ANALOG COMPARATOR (ACMP) 8-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) PTA4/ACMPO/BKGD/MS PTA3/ADP3 PTA2/ADP2 PTA1/TPMCH1/ADP1/ACMP- PTA0/TPMCH0/ADP0/ACMP+ PTB7/EXTAL PTB6/XTAL PTB5/TPMCH1 PORT PTB4/TPMCH0 PTB3/ADP7 PTB2/ADP6 PTB1/ADP5 PTB0/ADP4 PTC3/ADP11 PORT PTC2/ADP10 PTC1/ADP9 PTC0/ADP8
RS08 SYSTEM CONTROL RESETS INTERRUPTS MODES OPERATION POWER MANAGEMENT WAKEUP USER FLASH 8192 BYTES USER BYTES
16-BIT TIMER/PWM MODULE (TPM) 8-BIT TIMER (MTIM1 MTIM2)
INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 39.0625 (XOSC) VOLTAGE REGULATOR
Figure 1-1. SC9RS08MZ8 Block Diagram
Table provides functional versions on-chip modules.
Table 1-1. Block Versions
Module RS08 Analog Comparator (RS08 ACMP) Modulo Timer (RS08 MTIM) Internal Clock Source (RS08 ICSOSC) Analog-to-Digital Converter (RS08 ADC10) 16-Bit Timer/PWM (RS08 TPM) XOSC Version
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Device Overview
System Clock Distribution
SYSTEM CONTROL LOGIC TCLK RTICLKS
ICSERCLK
MTIM1
MTIM2
ICSFFCLK ICSOUT
FIXED CLOCK (XCLK)
CLOCK
XOSC EXTAL XTAL FLASH
Figure 1-2. System Clock Distribution Diagram
Figure shows simplified clock connection diagram MCU. clock frequency half output frequency used internal modules.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Device Overview
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Pins Connections
Introduction
This chapter describes signals that connect package pins. includes pinout diagram, signal properties table, detailed signal discussion.
Device Assignment
Figure show assignments packages SC9RS08MZ8.
PTA5/TCLK/RESET/VPP PTA4/ACMPO/BKGD/MS PTB7/EXTAL PTB6/XTAL PTB5/TPMCH1 PTB4/TPMCH0 PTC3/ADP11 PTC2/ADP10 PTA0/TPMCH0/ADP0/ACMP+ PTA1/TPMCH1/ADP1/ACMP- PTA2/ADP2 PTA3/ADP3 PTB0/ADP4 PTB1/ADP5 PTB2/ADP6 PTB3/ADP7 PTC0/ADP8 PTC1/ADP9
Figure 2-1. SC9RS08MZ8 20-Pin SOIC Package
Recommended System Connections
Figure shows reference connection background debug flash programming.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Pins Connections
CBUK
SC9RS08MZ8
BACKGROUND HEADER RESET/VPP
NOTE
EXTAL
NOTE
XTAL
NOTE NOTES:
required using internal clock option. These same pins PTB6 PTB7.
Figure 2-2. Reference System Connection Diagram
Detail
This section provides detailed description system connections.
2.4.1
Power Pins
primary power supply pins MCU. This voltage source supplies power buffer circuitry internal voltage regulator. internal voltage regulator provides regulated lower-voltage source other internal circuitry. Typically, application systems have separate capacitors across power pins: bulk electrolytic capacitor such tantalum capacitor, provide bulk charge storage overall system, bypass capacitor such 0.1F ceramic capacitor, located near power pins practical suppress high-frequency noise.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
BKGD/MS
Chapter Pins Connections
2.4.2
PTA5/TCLK/RESET/VPP
After power-on reset (POR) into user mode, PTA5/TCLK/RESET/Vpp defaults general-purpose input port pin, PTA5. Setting RSTPE SOPT configures RESET input pin. After configured RESET, remains RESET until next reset. RESET used reset from external source when driven low. When enabled RESET (RSTPE internal pullup device automatically enabled. External voltage (typically Appendix "Electrical Characteristics") required this when performing flash programming erasing. connection always connected internal flash module regardless function. avoid over stressing flash, external voltage must removed voltage higher than must avoided when flash programming erasing does occur. NOTE This does contain clamp diode must driven above when flash programming erasing does occur.
2.4.3
PTA4/ACMPO/BKGD/MS
background/mode select function shared with output-only PTA4 optional analog comparator output. While reset, functions mode select pin. Immediately after reset rises, functions background used background debug communication. While functioning background mode select pin, this internal pullup device enabled. output-only port, clear BKGDPE SOPT. nothing connected this pin, enters normal operating mode rising edge reset. debug system connected 6-pin standard background debug header, hold BKGD/MS during power-on-reset, which forces active background mode. BKGD used primarily background debug controller (BDC) communications using custom protocol that uses clock cycles target MCU's clock time. target MCU's clock equals clock rate; therefore, significant capacitance must connected BKGD/MS that could interfere with background serial communications. Although BKGD pseudo open-drain pin, background debug communication protocol provides brief, actively driven, high speedup pulses ensure fast rise times. Small capacitances from internal pullup device affect rise fall times BKGD pin.
2.4.4
General-Purpose Peripheral Ports
remaining pins shared among general-purpose on-chip peripheral functions such timers analog comparator. Immediately after reset, these pins configured high-impedance general-purpose inputs with internal pullup/pulldown devices disabled.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Pins Connections
NOTE avoid extra current drain from floating input pins, reset initialization routine application program must enable on-chip pullup/pulldown devices change direction unused pins outputs.
Table 2-1. Availability Package Pin-Count
Number
Lowest Port PTA5 PTA4 ACMPO
Priority
Highest RESET
TCLK BKGD
PTB7 PTB6 PTB5 PTB4 PTC3 PTC2 PTC1 PTC0 PTB3 PTB2 PTB1 PTB0 PTA3 PTA2 PTA1 PTA0 TPMCH12 TPMCH02 TPMCH11 TPMCH01 ADP11 ADP10 ADP9 ADP8 ADP7 ADP6 ADP5 ADP4 ADP3 ADP2 ADP1 ADP0
EXTAL XTAL
ACMP- ACMP+
pins remapped PTA0 PTA1
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
Introduction
This chapter describes SC9RS08MZ8 operating modes. also details entry into each mode, exit from each mode, functionality while each modes.
Features
Active background mode code development Stop mode: System clocks stopped internal circuits remain powered fast recovery
Mode
mode normal operating mode SC9RS08MZ8. This mode selected when BKGD/MS high rising edge reset. this mode, executes code from internal memory beginning address $3FFD. instruction (opcode $BC) with operand located $3FFE-$3FFF must programmed into user application correct reset operation. operand defines location where user program starts. Instead using vector fetching process HC08/S08 families, user program responsible performing instruction relocate program counter correct user program start location.
Active Background Mode
active background mode functions managed through background debug controller (BDC) RS08 core. provides means analyzing operation during software development. Active background mode entered four ways: When BKGD/MS during power-on-reset (POR) immediately after issuing background debug force reset (BDC_RESET) command When BACKGROUND command received through BKGD When BGND instruction executed When breakpoint encountered After active background mode entered, stays suspended state waiting serial background commands rather than executing instructions from user application program. Background commands types:
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
Non-intrusive commands Commands that issued while user program running, issued through BKGD while mode. Non-intrusive commands also executed when active background mode. Non-intrusive commands include: Memory access commands Memory-access-with-status commands BACKGROUND command Active background commands executed only while active background mode, include commands Read write registers Trace user program instruction time Leave active background mode return user application program (GO)
Active background mode used program user application code into flash program memory before operated mode first time. When SC9RS08MZ8 shipped, flash program memory usually erased program executed mode until flash memory initially programmed. active background mode also used erase reprogram flash memory after programmed. additional information about active background mode, refer Chapter "Development Support."
Stop Mode
Stop mode entered upon execution STOP instruction when STOPE system option register set. stop mode, internal clocks modules halted. STOPE when executes STOP instruction, does enter stop mode, illegal opcode reset forced. Table summarizes behavior stop mode.
Table 3-1. Stop Mode Behavior
Mode Stop
Standby
Digital Peripherals Standby
ICS1 Optionally
ACMP2 Optionally
Regulator3 Optionally
Pins States held
Optionally
ADC4 Optionally
requires IREFSTEN LVDE LVDSE must allow operation stop. bandgap reference required, LVDE LVDSE bits SPMSC1 must both before entering stop. When enabled, Regulator else, only when LVDE LVDSE bits both SPMSC1 set, Regulator mode. Requires asynchronous clock, LVDE LVDSE bits both SPMSC1 set, otherwise standby mode.
Upon entering stop mode, clocks halted. turned default when IREFSTEN cleared voltage regulator enters standby. states internal registers logic, well content, maintained. states held.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
Exit from stop done asserting reset, enabled asynchronous interrupt, real-time interrupt. asynchronous interrupts interrupt, interrupt ACMP interrupt. stop exited asserting RESET pin, reset program execution starts location $3FFD. exited asynchronous interrupt real-time interrupt, next instruction after location where STOP instruction executed executed accordingly. user program must probe corresponding interrupt source that woke CPU. separate self-clocked source kHz) real-time interrupt allows wakeup from stop mode with external components. When RTIS 000, real-time interrupt function disabled. When STOP mode, disabled, RTICLKS internal oscillator disabled power consumption lower. external clock source also enabled real-time interrupt allow wakeup from stop mode with external components. Setting ERCLKEN=1 EREFSTEN=1 enables external clock source when STOP mode. enable STOP mode, asynchronous clock must enabled setting LVDE LVDSE, otherwise standby. enable XOSC operate with external reference clock source STOP mode, must enabled setting LVDE LVDSE.
3.5.1
Active Enabled Stop Mode
Entry into active background mode from mode enabled ENBDM BDCSCR set. This register described Chapter "Development Support." ENBDM when executes STOP instruction, system clocks background debug logic remain active when enters stop mode background debug communication still possible. voltage regulator does enter low-power standby state. maintains full internal regulation. Most background commands available stop mode. memory-access-with-status commands allow memory access. They report error indicating that stop wait mode. BACKGROUND command used wake from stop enter active background mode ENBDM set. After active background mode entered, background commands available. Table summarizes behavior stop when entry into active background mode enabled.
Table 3-2. Enabled Stop Mode Behavior
Mode Stop Standby Digital Peripherals Standby ACMP Optionally Regulator Pins States held Optionally Optionally
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
3.5.2
Enabled Stop Mode
system generate interrupt reset when supply voltage drops below voltage. voltage regulator remains active enabled stop (LVDE LVDSE bits SPMSC1 both set) when executes STOP instruction. Table summarizes behavior stop when enabled.
Table 3-3. Enabled Stop Mode Behavior
Mode Stop
Standby
Digital Peripherals Standby
Optionally
ACMP Optionally
Regulator
Pins States held
Optionally
ADC1 Optionally
Requires asynchronous clock enabled.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Memory
memory divided into following groups: Fast access using tiny short instructions ($0000 $000D) Indirect data access D[X] ($000E) Index register D[X] ($000F) Frequently used peripheral registers ($0010 $001E, $0020 $002F) PAGESEL register ($001F) SC9RS08MZ8 ($0030 $00BF, $0100 $015F) Paging window ($00C0 $00FF) Other peripheral registers ($0200 $023F) Nonvolatile memory SC9RS08MZ8 ($2000 $3FFF)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
$0000 $000D $000E $000F $0010 $001E $001F $0020 $002F
FAST ACCESS BYTES D[X] REGISTER FREQUENTLY USED REGISTERS PAGESEL REGISTERS
PAGESEL CONTENT
BYTES $00BF $00C0 PAGING WINDOW $00FF $0100 $015F UNIMPLEMENTED $0200 $023F HIGH PAGE REGISTERS (reset value)
BYTES
UNIMPLEMENTED $1FFF $2000
FLASH KBYTES $3FFB $3FFC $3FFD $3FFF NVOPT FLASH
SC9RS08MZ8
Figure 4-1. SC9RS08MZ8 Memory Maps
Unimplemented Memory
Attempting access data instruction unimplemented memory address causes reset.
Indexed/Indirect Addressing
Register D[X] register combined perform indirect data access. Register D[X] mapped address $000E. Register located address $000F. 8-bit register contains address used when register D[X] accessed. Register cleared zero upon reset. programming register location
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
first page ($0000-$00FF) read/written register D[X]. Figure shows relationship between D[X] register example, HC08/S08 syntax latex comparable D[X] RS08 coding when register been programmed with index value. physical location $000E RAM. Accessing location through D[X] returns $000E content when register contains $0E. physical location $000F register itself. Reading location through D[X] returns register content. Writing location modifies register
$0000
$000E $000F
D[X] Register Register specify location between $0000-$00FF
Address indicated Register
Content this location accessed D[X]
$00FF $0100
Figure 4-2. Indirect Addressing Registers
Register Addresses Assignments
short direct addressing mode instructions read write fast access area. tiny addressing mode instructions, operand encoded with opcode single byte.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Frequently used registers make short addressing mode instructions faster load, store, clear operations. short addressing mode instructions, operand encoded along with opcode single byte.
Table 4-1. Register Summary (Sheet
Address Register Name
$0000 $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 D[X]1 ADCSC1 ADCSC2 ADCRH ADCRL Reserved TPMC0SC TPMC0VH TPMC0VL TPMC1SC TPMC1VH TPMC1VL ACMPSC PTAD PTBD PTCD PAGESEL MTIM1SC MTIM1CLK MTIM1CNT MTIM1MOD MTIM2SC MTIM2CLK MTIM2CNT MTIM2MOD TOIE TRST CLKS COCO ADACT ADR7 CH0F Bit15 Bit7 CH1F Bit15 Bit7 ACME PTBD7 AD13 AIEN ADTRG ADR6 CH0IE CH1IE ACBGS PTBD6 AD12 TOIE ADCO ACFE ADR5 MS0B MS1B PTAD5 PTBD5 AD11 TRST CLKS
Fast Access ACFGT ADR4 MS0A MS1A ACIE PTAD4 PTBD4 AD10 TSTP COUNT TSTP COUNT Paging Window COPE COPT STOPE ILOP ILAD RSTPE ADR3 ELS0B ELS1B PTAD3 PTBD3 PTCD3 ADCH ADR2 ELS0A ELS1A ACOPE PTAD2 PTBD2 PTCD2 ADR9 ADR1 ACMOD PTAD1 PTBD1 PTCD1 PTAD0 PTBD0 PTCD0 ADR8 ADR0 Bit8 Bit0 Bit8 Bit0
$0028 Reserved $002F $0030 $00BF $00C0 $00FF $0100 $015F $0160 Unimplemented $01FF $0200 $0201 SOPT
TPMCH1PS TPMCH0PS BKGDPE
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Table 4-1. Register Summary (Sheet (continued)
Address $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 Register Name SIP1
Unimplemented
REV3 RTIF LVDF ADCV7 ADLPC ADPC7 PTBDD7 PTBPE7 PTBPUD7 PTBSE7 Bit15 Bit7 Bit15 Bit7
REV2 RTIACK LVDACK ADCV6 ADIV ADPC6 PTBDD6 PTBPE6 PTBPUD6 PTBSE6 TOIE
ACMP REV1 RTICLKS LVDIE ADCV5 ADPC5 PTAPE5 PTAPUD5 PTBDD5 PTBPE5 PTBPUD5 PTBSE5 CPWMS
REV0 ID[7:0] RTIE LVDRE ADCV4 ADLSMP ADPC4 PTASE4 PTBDD4 PTBPE4 PTBPUD4 PTBSE4 CLKSB
MTIM2 ID[11:8]
MTIM1
Reserved
Unimplemented
SDIDH SDIDL SRTISC SPMSC1
LVDSE HVEN ADCV3 ADPC3 ADPC11 PTADD3 PTAPE3 PTAPUD3 PTASE3 PTBDD3 PTBPE3 PTBPUD3 PTBSE3 PTCDD3 PTCPE3 PTCPUD3 PTCSE3 CLKSA MODE ADPC2 ADPC10 PTADD2 PTAPE2 PTAPUD2 PTASE2 PTBDD2 PTBPE2 PTBPUD2 PTBSE2 PTCDD2 PTCPE2 PTCPUD2 PTCSE2 LVDE MASS ADCV2
RTIS ADCV9 ADCV1 ADPC1 ADPC9 PTADD1 PTAPE1 PTAPUD1 PTASE1 PTBDD1 PTBPE1 PTBPUD1 PTBSE1 PTCDD1 PTCPE1 PTCPUD1 PTCSE1 BGBE SECD ADCV8 ADCV0 ADPC0 ADPC8 PTADD0 PTAPE0 PTAPUD0 PTASE0 PTBDD0 PTBPE0 PTBPUD0 PTBSE0 PTCDD0 PTCPE0 PTCPUD0 PTCSE0 Bit8 Bit0 Bit8 Bit0
$020A Reserved $020B $020C Unimplemented $020F $0210 $0211 FOPT FLCR
$0212 Reserved $0213 $0214 $0215 $0216 $0217 $0218 ADCCVH ADCCVL ADCCFG APCTL1 APCTL2
ADICLK
$0219 Unimplemented $021F $0220 $0221 $0222 $0223 $0224 $0225 $0226 $0227 $0228 $0229 $022A $022B PTADD PTAPE PTAPUD PTASE PTBDD PTBPE PTBPUD PTBSE PTCDD PTCPE PTCPUD PTCSE
$022C Unimplemented $022F $0230 $0231 $0232 $0233 $0234 $0235 TPMSC TPMCNTH TPMCNTL TPMMODH TPMMODL Reserved
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Table 4-1. Register Summary (Sheet (continued)
Address $0236 $0237 $0238 $0239 Register Name Reserved PTADS PTBDS PTCDS PTBDS7 CLKS BDIV RANGE PTBDS6 PTBDS5 PTADS4 PTBDS4 RDIV TRIM CLKST OSCINIT FTRIM PTADS3 PTBDS3 PTCDS3 PTADS2 PTBDS2 PTCDS2 IREFS EREFS PTADS1 PTBDS1 PTCDS1 IRCLKEN PTADS0 PTBDS0 PTCDS0 IREFSTEN
$023A Unimplemented $023B $023C $023D $023E $023F ICSC1 ICSC2 ICSTRM ICSSC
ERCLKEN EREFSTEN
$3FF8 $3FF9 $3FFA2 $3FFB2 $3FFC
Reserved Reserved Reserved Reserved NVOPT
Reserved
FTRIM
Reserved Room Temperature Trim SECD
Unimplemented Reserved
Physical $000E accessed through D[X] register when content index register $0E. using untrimmed, $3FFA $3FFB used applications.
factory-trimmed value will stored 0x3FFA 0x3FFB (bit factory-trimmed frequency MHz.
device includes three static sections. locations from $0000 $000D directly accessed using more efficient tiny addressing mode instructions short addressing mode instructions. Location $000E accessed through D[X] register when register through paging window location $00CE when PAGESEL register $00. second section starts from $0030 $00BF accessed using direct addressing mode instructions. third section starts from $0100 $015F. retains data when low-power wait stop mode. data unaffected reset supply voltage does drop below minimum value retention.
Flash
flash memory program storage. In-circuit programming allows operating program loaded into flash memory after final assembly application product. program entire array through single-wire background debug interface. Because device does include on-chip charge pump circuitry, external required program erase operations.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
4.6.1
Features
Flash memory features include: 1000 program/erase cycles typical voltage temperature Security feature flash
4.6.2
Flash Programming Procedure
Flash memory programmed basis. consists consecutive bytes starting from addresses $2X00, $2X40, $2X80, $2XC0. program flash memory: Apply external VPP. bit. This configures memory program operation enables latching address data programming. Write data flash location high-page-accessing window $00C0-$00FF, within address range programmed. (Prior data writing operation, PAGESEL register must configured correctly high-page-accessing window corresponding flash row.) Wait time, tnvs. HVEN bit. Wait time, tpgs. Write data flash location programmed. Wait time, tprog. Repeat steps seven eight until bytes within programmed. Clear bit. Wait time, tnvh. Clear HVEN bit. After time, trcv, memory accessed read mode again. Remove external VPP. This program sequence repeated throughout memory until data programmed. NOTE Software code executed from flash locations cannot program erase flash memory. program erase flash, commands must executed from commands. User code must enter wait stop during erase program sequence. These operations must performed order shown, other unrelated operations occur between steps.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
4.6.3
Flash Mass Erase Operation
mass erase entire flash memory: Apply external VPP. MASS flash control register. Write data flash location high page accessing window $00C0-$00FF. (Prior data writing operation, PAGESEL register must configured correctly highpage-accessing window flash locations.) Wait time, tnvs. HVEN bit. Wait time tme. Clear MASS bit. Wait time, tnvh1. Clear HVEN bit. After trcv time, memory accessed read mode again. Remove external VPP. NOTE Software code executed from flash locations cannot program erase flash memory. program erase flash, commands must executed from commands. User code must enter wait stop during erase program sequence. These operations must performed order shown other unrelated operations occur between steps.
4.6.4
Security
SC9RS08MZ8 includes circuitry help prevent unauthorized access flash memory contents. When security engaged, flash secure resource. RAM, direct-page registers, background debug controller unsecured resources. Attempts access secure memory location blocked (reads return they through background debug interface, when BKGDPE set. Security engaged disengaged based state nonvolatile register (SECD) FOPT register. During reset, nonvolatile location NVOPT contents copied from flash into working FOPT register high-page register space. Engage security programming NVOPT location. this while flash memory programmed. erased state (SECD makes unsecure. When SECD NVOPT programmed (SECD next time device reset POR, internal reset, external reset, security engaged. disengage security, mass erase must performed commands followed reset. separate background debug controller still used registers access. commands, flash mass erase possible writing flash control register that follows flash mass erase procedure listed Section 4.6.3, "Flash Mass Erase Operation."
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Security always disengaged through background debug interface when you: Mass erase flash background commands loaded program. Perform reset. device boots with security disengaged. NOTE When device boots normal operating mode, where high during reset, with SECD programmed (SECD flash security engaged. BKGDPE reset communication blocked, background debug allowed.
Flash Registers Control Bits
flash module nonvolatile register NVOPT ($3FFC) flash memory which copied into corresponding control register FOPT ($0210) reset.
4.7.1
Flash Options Register (FOPT NVOPT)
During reset, nonvolatile location NVOPT contents copied from flash into FOPT. Bits through used always read This register read time, writes have meaning effect. change value this register, erase reprogram NVOPT location flash memory then issue reset.
Reset
SECD
This register loaded from nonvolatile location NVOPT during reset. Unimplemented Reserved
Figure 4-3. Flash Options Register (FOPT) Table 4-2. FOPT Field Descriptions
Field SECD Description Security State Code This field determines security state. When secured, flash memory contents cannot accessed instructions from unsecured source including background debug interface; Section 4.6.4, "Security." Security engaged. Security disengaged.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
4.7.2
Flash Control Register (FLCR)
Reset
HVEN MASS
PGM1
Unimplemented Reserved
Figure 4-4. Flash Control Register (FLCR) Table 4-3. FLCR Field Descriptions
Field HVEN Description High Voltage Enable This read/write enables high voltages flash array program erase operations. HVEN only MASS proper sequence program erase followed. High voltage disabled array. High voltage enabled array. Mass Erase Control This read/write configures memory mass erase operation. Mass-erase operation selected. Mass-erase operation selected. Program Control This read/write configures memory program operation. interlocked with MASS bit, both bits cannot equal same time. Program operation selected. Program operation selected.
MASS PGM1
When flash security engaged, writing effect. result, flash programming allowed.
Page Select Register (PAGESEL)
There 64-byte window ($00C0 $00FF) direct-page reserved paging access. Programming page-select register determines corresponding 64-byte block memory direct-page access. example, when PAGESEL register programmed with value $08, high-page registers ($0200 $023F) accessed through paging window ($00C0 $00FF) direct addressing mode instructions.
AD13 Reset AD12 AD11 AD10
Figure 4-5. Page Select Register (PAGESEL) Table 4-4. PAGESEL Field Descriptions
Field AD[13:6] Description Page Selector- These bits define address line which determines 64-byte block boundary memory block accessed direct page window. Figure Table 4-5.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
14-bit memory address Start address memory block selected AD[13:6]
Figure 4-6. Memory Block Boundary Selector
Table shows memory block accessed through paging window ($00C0 $00FF).
Table 4-5. Paging Window $00C0-$00FF
Page Memory Address $0000-$003F $0040-$007F $0080-$00BF $00C0-$00FF $0100-$013F $3F80-$3FBF $3FC0-$3FFF
NOTE Physical location $0000-$000E RAM. Physical location $000F register D[X] register mapped address $000E only. physical $000E accessed through D[X] register when register with PAGESEL $00. When PAGESEL register $00, paging window mapped first page ($00 $3F). Paged location $00C0 $00CE mapped physical location $0000 $000E, that RAM. Paged location $00CF mapped register Therefore, accessing address returns physical content $000E. Accessing address $000E returns D[X] register content.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Introduction
This chapter discusses basic reset, interrupt mechanisms, various reset interrupt sources SC9RS08MZ8. Some interrupt sources from peripheral modules discussed detail other chapters this data sheet. This chapter gathers basic information about reset interrupt sources place easy reference. reset wakeup sources, including computer operating properly (COP) watchdog real-time interrupt (RTI), part on-chip peripheral systems with their chapters part system control logic.
Features
Reset interrupt features include: Multiple sources reset flexible system configuration reliable operation System reset status register (SRS) indicate source most recent reset System interrupt pending register (SIP1) indicate status pending system interrupts Analog comparator interrupt with enable Modulo timer interrupt with enable Real-time interrupt with enable interrupt with enable interrupt with enable
Reset
Resetting provides start processing from known conditions. During reset, most control status registers forced initial values, program counter started from location $3FFD. instruction (opcode $BC) with operand located $3FFE $3FFF must programmed into user application correct reset operation. operand defines location which user program starts. On-chip peripheral modules disabled pins initially configured general-purpose, high-impedance inputs with pullup/pulldown devices disabled. SC9RS08MZ8 seven reset sources: External reset (PIN) Enabled using RSTPE SOPT Power-on reset (POR) Low-voltage detect (LVD) Computer operating properly (COP) timer
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Illegal opcode detect (ILOP) Illegal address detect (ILAD) Background debug forced reset command BDC_RESET
Each source except background debug forced reset associated system reset status register (SRS).
Computer Operating Properly (COP) Watchdog
watchdog used force system reset application software fails execute expected. prevent system reset from timer (when enabled), application software must periodically reset counter. application program gets lost fails reset counter before times out, system reset generated force system back known starting point. After reset, COPE becomes SOPT, which enables watchdog (see Section 5.8.2, "System Options Register (SOPT)."). watchdog used application, disabled clearing COPE. counter reset writing value address SRS. This write does affect data read-only SRS. Instead, writing this address decoded sends reset signal counter. There associated short long time-out controlled COPT SOPT. Table summarizes COPT control functions. watchdog operates from clock source defaults associated long time-out cycles).
Table 5-1. Configuration Options
COPT
Overflow Count1 cycles cycles (256
Values this column based tRTI tRTI "SC9RS08MZ8 Data Sheet," tolerance value.
Even application uses reset default settings COPE COPT, write write-once SOPT registers during reset initialization lock settings they cannot changed accidentally application program gets lost. initial write SOPT resets counter. background debug mode, counter does increment. When enters stop mode, counter re-initialized zero upon entry stop mode. counter begins from zero soon exits stop mode.
Interrupts
SC9RS08MZ8 does include interrupt controller with vector table lookup mechanism used HC08 HCS08 devices. However, interrupt sources from modules such LVD, ADC, ACMP still available wake from wait stop mode. user application's responsibility poll corresponding module determine source wakeup.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Each wakeup source module associated with corresponding interrupt enable bit. disabled, interrupt source gated, that particular source cannot wake from wait stop mode. However, corresponding interrupt flag still indicate that external wakeup event occurred. system interrupt pending register (SIP1) indicates system-pending interrupt status. When read-only SIP1 enabled, shows pending interrupt serviced from indicated module. Writing register effect. pending interrupt flag cleared automatically when corresponding interrupt flags from indicated module cleared.
Low-Voltage Detect (LVD) System
SC9RS08MZ8 includes system protect memory contents control system states against voltage conditions during supply voltage variations. system composed power-on reset (POR) circuit circuit with predefined trip voltage. circuit enabled with LVDE SPMSC1. disabled upon entering stop mode unless LVDSE SPMSC1. LVDSE LVDE both set, current consumption stop with enabled greater.
5.6.1
Power-On Reset Operation
When power initially applied MCU, when supply voltage drops below VPOR level, circuit causes reset condition. supply voltage rises, circuit holds reset until supply rises above VLVD level. after POR.
5.6.2
Reset Operation
configured generate reset upon detecting voltage condition setting LVDRE After reset occurs, system holds reset until supply voltage rises above level VLVD. register after reset POR.
5.6.3
Interrupt Operation
When voltage condition detected circuit configured using SPMSC1 interrupt operation (LVDE set, LVDIE set, LVDRE clear), LVDF SPMSC1 interrupt request occurs.
Real-Time Interrupt (RTI)
real-time interrupt function used generate periodic interrupts. driven from internal clock oscillator external clock souce. RTICLKS SRTISC used select clock source. internal external clock sources used when run, wait, stop mode. When using external oscillator normal wait mode, setting ERCLKEN=1. When using external oscillator stop mode, ERCLKEN=1 EREFSTEN=1. SRTISC register includes read-only status flag, write-only acknowledge bit, 3-bit control value (RTIS) used select seven wakeup periods disable RTI. local interrupt enable RTIE allow masking real-time interrupt. disabled writing each
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
RTIS interrupts generated. Section 5.8.4, "System Real-Time Interrupt Status Control Register (SRTISC)," more information.
Reset, Interrupt, System Control Registers Control Bits
Refer direct-page register summary Chapter "Memory," absolute address assignments registers. This section refers registers control bits only their names. Freescale-provided equate header file used translate these names into appropriate absolute addresses. Some control bits SOPT register related operation modes. Although brief descriptions these bits provided here, related functions further discussed Chapter "Modes Operation."
5.8.1
System Reset Status Register (SRS)
This high page register includes read-only status flags indicate source most recent reset. When debug host forces reset BDC_RESET command, status bits cleared. Writing value this register address clears watchdog timer without affecting this register's contents. reset state these bits depends what caused reset.
POR: LVR: other reset:
ILOP
ILAD
Writing value address clears watchdog timer. Note Note Note Note
these reset sources that active time reset entry causes corresponding bit(s) set; bits corresponding sources active time reset entry cleared.
Figure 5-1. System Reset Status (SRS) Table 5-2. Field Descriptions
Field Description Power-On Reset Reset caused power-on detection logic. Because internal supply voltage ramping time, low-voltage reset (LVR) status also indicate that reset occurred while internal supply below threshold. Reset caused POR. caused reset. External Reset Reset caused active-low level external reset pin. Reset caused external reset pin. External reset caused reset. Computer Operating Properly (COP) Watchdog Reset caused watchdog timer timing out. COPE block reset source. Reset caused timeout. timeout caused reset.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-2. Field Descriptions (continued)
Field ILOP Description Illegal Opcode Reset caused attempt execute unimplemented illegal opcode. STOP instruction considered illegal STOPE SOPT register disables stop mode. BGND instruction considered illegal ENBDM BDCSC register disables stop mode. Reset caused illegal opcode. Illegal opcode caused reset. Illegal Address Reset caused attempt access either data instruction unimplemented memory address. Reset caused illegal address. Illegal address caused reset. Voltage Detect LVDRE supply drops below trip voltage, reset occurs. sets this bit. Reset caused trip POR. Either trip caused reset.
ILAD
5.8.2
System Options Register (SOPT)
This high page register write-once register only first write after reset honored. read time. subsequent attempt write SOPT (intentionally unintentionally) ignored avoid accidental changes these sensitive settings. SOPT must written during user's reset initialization program desired controls even desired settings reset settings same.
COPE Reset: POR: (Note (Note1) COPT STOPE TPMCH1PS TPMCH0PS BKGDPE RSTPE
Unimplemented Reserved
Unaffected
When device power reset, BKGEPE reset When device reset into normal operating mode high during reset), BKGDPE reset flash security disengaged (SECD BKGDPE reset flash security engaged (SECD When device reset into active mode during reset), BKGDPE always reset such that communication allowed.
Figure 5-2. System Options Register (SOPT) Table 5-3. SOPT Register Field Descriptions
Field COPE COPT Description Watchdog Enable This write-once selects whether watchdog enabled. watchdog timer disabled. watchdog timer enabled (force reset timeout). Watchdog Timeout This write-once selects timeout period COP. Short timeout period selected. Long timeout period selected.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-3. SOPT Register Field Descriptions (continued)
Field STOPE Description Stop Mode Enable This write-once used enable stop mode. stop mode disabled user program attempts execute STOP instruction, illegal opcode reset forced. Stop mode disabled. Stop mode enabled.
TPMCH1 Select- This selects location TPMCH1 module. TPMCH1PS TPMCH1 PTA1. TPMCH1 PTB5. TPMCH0 Select- This selects location TPMCH0 module. TPMCH0PS TPMCH0 PTA0. TPMCH0 PTB4. Background Debug Mode Enable -When set, this write-once enables PTA4/ACMPO/BKGD/MS BKGDPE1,2 function BKGD/MS. When clear, functions output only alternative functions. This defaults BKGD/MS function following reset. PTA4/ACMPO/BKGD/MS functions PTA4 ACMPO. PTA4/ACMPO/BKGD/MS functions BKGD/MS. RSTPE RESET Enable When set, this write-once enables PTA5/TCLK/RESET/VPP function RESET. When clear, functions input-only alternative functions. This input-only port function following POR. When RSTPE set, internal pullup device enabled RESET. PTA5/TCLK/RESET/VPP functions PTA5/TCLK/VPP. PTA5/TCLK/RESET/VPP functions RESET/VPP.
When device power reset, BKGEPE reset When device reset into normal operating mode high during reset), BKGDPE reset flash security disengaged (SECD BKGDPE reset flash security engaged (SECD When device reset into active mode during reset), BKGDPE reset that communication allowed. BKGDPE write only once from value Writing from value user software allowed. BKGDPE changed back only reset with proper condition stated Note
5.8.3
System Device Identification Register (SDIDH, SDIDL)
These high-page, read-only registers included host development systems identify RS08 derivative revision number. This allows development software recognize where specific memory blocks, registers, control bits located target MCU.
Reset:
REV3
REV2
REV1
REV0
ID11
ID10
(Note
(Note
(Note
(Note
Unimplemented Reserved
revision number hard coded into these bits reflects current silicon revision level.
Figure 5-3. System Device Identification Register High (SDIDH)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-4. SDIDH Register Field Descriptions
Field REV[3:0] ID[11:8] Description Revision Number high-order bits address SDIDH hard coded reflect current mask revision number Part Identification Number Each derivative RS08 Family unique identification number. SC9RS08MZ8 hard coded value $0803. also bits Figure 5-4.
Reset:
Unimplemented Reserved
Figure 5-4. System Device Identification Register (SDIDL) Table 5-5. SDIDL Register Field Descriptions
Field ID[7:0] Description Part Identification Number Each derivative RS08 Family unique identification number. SC9RS08MZ8 hard coded value $0803. also bits Figure 5-3.
5.8.4
System Real-Time Interrupt Status Control Register (SRTISC)
This high-page register contains status control bits RTI.
Reset:
RTIF
RTICLKS RTIACK RTIE
RTIS
Unimplemented Reserved
Figure 5-5. System Status Control Register (SRTISC) Table 5-6. SRTISC Register Field Descriptions
Field RTIF RTIACK RTICLKS Description Real-Time Interrupt Flag Read-only status indicates periodic wakeup timer timed out. Periodic wakeup timer timed out. Periodic wakeup timer timed out. Real-Time Interrupt Acknowledge Write-only acknowledges real-time interrupt request (write clear RTIF). Writing meaning effect. Reads always return Real-Time Interrupt Clock Select Read/write selects clock source real-time interrupt. Real-time interrupt request clock source internal oscillator. Real-time interrupt request clock source external clock.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-6. SRTISC Register Field Descriptions (continued)
Field RTIE RTIS Description Real-Time Interrupt Enable Read-write enables real-time interrupts. Real-time interrupts disabled. Real-time interrupts enabled. Real-Time Interrupt Delay Selects These read/write bits select period RTI. Table 5-7.
Table 5-7. Real-Time Interrupt Period
RTIS
Using Oscillator Source1 Disable clear Counter 1.024
Using External Clock Input Disable clear Counter 1/fextclk 1/fextclk 1024 1/fextclk 2048 1/fextclk 4096 1/fextclk 8192 1/fextclk 16384 1/fextclk 32768
Values shown this column based fRTI kHz. Consult Appendix "Electrical Characteristics."
5.8.5
System Power Management Status Control Register (SPMSC1)
This high page register contains status control bits support voltage detect function, enable bandgap voltage reference ACMP module.
Reset:
LVDF
LVDIE LVDACK
LVDRE1
LVDSE
LVDE1
BGBE
Unimplemented Reserved
This written only once after reset. Additional writes ignored.
Figure 5-6. System Power Management Status Control Register (SPMSC1)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-8. SPMSC1 Register Field Descriptions
Field LVDF LVDACK LVDIE LVDRE Description Low-Voltage Detect Flag Provided LVDE this read-only status indicates low-voltage detect event. Low-Voltage Detect Acknowledge Write-only used acknowledge voltage detection errors (write clear LVDF). Reads always return Low-Voltage Detect Interrupt Enable Enables hardware interrupt requests LVDF. Hardware interrupt disabled (use polling). Request hardware interrupt when LVDF Low-Voltage Detect Reset Enable Write-once enables low-voltage detect events generate hardware reset (provided LVDE LVDF does generate hardware resets. Force reset when LVDF Low-Voltage Detect Stop Enable Provided LVDE this read/write determines whether low-voltagedetect function operates when stop mode. Low-voltage detect disabled during stop mode. Low-voltage detect enabled during stop mode. Low-Voltage Detect Enable Write-once enables low-voltage detect logic operation other bits this register. logic disabled. logic enabled. Bandgap Buffer Enable Enables internal buffer bandgap-voltage reference ACMP module internal channels. Bandgap buffer disabled. Bandgap buffer enabled.
LVDSE
LVDE
BGBE
5.8.6
System Interrupt Pending Register (SIP1)
This high-page register contains status pending interrupt from modules.
Reset:
ACMP
MTIM2
MTIM1
Unimplemented Reserved
Figure 5-7. System Interrupt Pending Register (SIP1)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-9. SIP1 Register Field Descriptions
Field ACMP Description Analog Comparator Interrupt Pending Read-only indicates pending interrupt from ACMP module. Clearing flag ACMPSC register clears this bit. Reset also clears this bit. pending ACMP interrupt; i.e., flag and/or ACIE cleared. Pending ACMP interrupt; i.e., flag ACIE set. Interrupt Pending Read-only indicates pending interrupt from module. Clearing COCO flag ADCSC1 register clears this bit. Reset also clears this bit. pending interrupt, i.e., COCO flag and/or AIEN cleared. Pending interrupt, i.e., COCO flag AIEN set. Timer/PWM Interrupt Pending Read-only indicates pending interrupts from module. Clearing flag TPMSC register and/or CHnF flags TPMCnSC register clears this bit. Reset also clears this bit. pending Timer/PWM interrupt i.e., either flag and/or TOIE cleared.; CH0F flag and/or CH0IE cleared.; CH1F flag and/or CH1IE cleared. Pending Timer/PWM interrupt, i.e., either flag TOIE set.; CH0F flag CH0IE set.; CH1F flag CH1IE set. Modulo Timer Interrupt Pending Read-only indicates pending interrupt from MTIM2 module. Clearing flag MTIM2SC register clears this bit. Reset also clears this bit. pending MTIM2 interrupt; i.e., flag and/or TOIE cleared. Pending MTIM2 interrupt; i.e., flag TOIE set. Modulo Timer Interrupt Pending Read-only indicates pending interrupt from MTIM1 module. Clearing flag MTIM1SC register clears this bit. Reset also clears this bit. pending MTIM1 interrupt; i.e., flag and/or TOIE cleared. Pending MTIM1 interrupt; i.e., flag TOIE set. Real-Time Interrupt Pending Read-only indicates pending interrupt from RTI. Clearing RTIF flag SRTISC register clears this bit. Reset also clears this bit. pending interrupt; i.e., RTIF flag and/or RTIE cleared. Pending interrupt; i.e., RTIF flag RTIE set.
MTIM2
MTIM1
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
This chapter explains software controls related parallel input/output (I/O) control. Chapter "Pins Connections," more information about assignments external hardware considerations these pins. these pins shared with on-chip peripheral functions (see Table 2-1). peripheral modules have priority over I/Os. When peripheral enabled, functions associated with shared pins disabled. After reset, shared peripheral functions disabled controls pins. I/Os configured inputs (PTADDn with pullup/pulldown devices disabled (PTAPEn except output-only PTA4, which defaults BKGD/MS function. pins' default-low-drive strengths selected (PTxDSn= after reset Reading writing parallel I/Os performed through port data registers. direction, either input output, controlled through port data direction registers. block diagram Figure illustrates parallel port function individual pin.
PTADDn Output Enable
PTADn Output Data
Port Read Data Synchronizer Input Data
BUSCLK
Figure 6-1. Parallel Block Diagram
data direction control (PTADDn) determines whether output buffer associated enabled, also controls source port data register reads. input buffer associated always enabled unless enabled analog function output-only pin. When shared digital function enabled pin, shared function controls output buffer. However, data direction register continues controlling source reads port data register.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
When shared analog function enabled pin, input output buffers disabled. value read port data where input (PTADDn input buffer disabled. general, whenever shared with alternative digital function analog function, analog function priority such that digital analog functions enabled, analog function controls pin. Write port data register before changing direction port become output. This ensures driven temporarily with data value that happened port data register. registers associated with parallel ports located high page register space that operate independently parallel registers. These registers used control pullup/pulldown slew rate pins. Section 6.3, "Pin Control Registers."
Behavior Low-Power Modes
wait stop modes, states maintained because internal logic stays powered Upon recovery, functions revert state they were prior entering stop mode.
Parallel Registers
This section provides information about registers associated with parallel ports. parallel data registers located within $001F memory boundary memory map, that short direct addressing mode instructions used. Refer tables Chapter "Memory," absolute address assignments parallel I/O. This section refers registers control bits only their names. Freescale Semiconductor-provided equate header file normally used translate these names into appropriate absolute addresses.
6.2.1
Port Registers
Port parallel function controlled data data direction registers described this section.
Reset:
PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
Figure 6-2. Port Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions
Field PTAD[5:0] Description Port Data Register Bits port pins that inputs, reads return logic level pin. port pins that configured outputs, reads return last value written this register. Writes latched into bits this register. port pins that configured outputs, logic level driven corresponding pin. Reset forces PTAD these driven corresponding pins because reset also configures port pins high-impedance inputs with pullup/pulldowns disabled.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Reset:
PTADD3 PTADD2 PTADD1 PTADD0
Figure 6-3. Port Data Direction Register (PTADD) Table 6-2. PTADD Register Field Descriptions
Field PTADD[3:0] Description Data Direction Port Bits These read/write bits control port pins direction what read PTAD reads. Input (output driver disabled) reads return value. Output driver enabled port PTAD reads return contents PTADn.
6.2.2
Port Registers
Port parallel function controlled data data direction registers described this section.
PTBD7 Reset: PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
Figure 6-4. Port Data Register (PTBD) Table 6-3. PTBD Register Field Descriptions
Field PTBD[7:0] Description Port Data Register Bits port pins that inputs, reads return logic level pin. port pins that configured outputs, reads return last value written this register. Writes latched into bits this register. port pins configured outputs, logic level driven corresponding pin. Reset forces PTBD these driven corresponding pins because reset also configures port pins high-impedance inputs with pullup/pulldowns disabled.
PTBDD7 Reset: PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
Figure 6-5. Port Data Direction Register (PTBDD)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-4. PTBDD Register Field Descriptions
Field PTBDD[7:0] Description Data Direction Port Bits These read/write bits control port pins direction what read PTBD reads. Input (output driver disabled) reads return value. Output driver enabled port PTBD reads return contents PTBDn.
6.2.3
Port Registers
Port parallel function controlled data data direction registers described this section.
Reset:
PTCD3 PTCD2 PTCD1 PTCD0
Figure 6-6. Port Data Register (PTCD)
Table 6-5. PTCD Register Field Descriptions
Field PTCD[3:0] Description Port Data Register Bits port pins that inputs, reads return logic level pin. port pins configured outputs, reads return last value written this register. Writes latched into bits this register. port pins configured outputs, logic level driven corresponding pin. Reset forces PTCD these driven corresponding pins because reset also configures port pins high-impedance inputs with pullup/pulldowns disabled.
Reset:
PTCDD3 PTCDD2 PTCDD1 PTCDD0
Figure 6-7. Port Data Direction Register (PTCDD) Table 6-6. PTCDD Register Field Descriptions
Field PTCDD[3:0] Description Data Direction Port Bits These read/write bits control direction port pins what read PTCD reads. Input (output driver disabled) reads return value. Output driver enabled port PTCD reads return contents PTCDn.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Control Registers
This section provides information about registers associated with parallel ports that used control functions. Refer tables Chapter "Memory," absolute address assignments control registers. This section refers registers control bits only their names. Freescale Semiconductor-provided equate header file normally used translate these names into appropriate absolute addresses. NOTE output selected have high output drive strength setting corresponding drive strength select register (PTxDSn). When high drive selected, capable sourcing sinking greater current. Even though every selected high drive, exceed total current source sink limits MCU. Drive strength selection affects behavior pins. However, behavior also affected. High drive allows drive greater load with same switching speed drive enabled into smaller load. Because this, emissions affected enabling pins high drive.
6.3.1
Port Control Registers
pins associated with port controlled registers provided this section. These registers control pullup/pulldown slew rate port pins independent parallel registers.
6.3.1.1
Internal Pulling Device Enable
internal pulling device enabled each port setting corresponding pulling device enable register (PTAPEn). pulling device disabled configured output parallel control logic shared peripheral output function regardless state corresponding pulling-device-enable-register bit. pulling device also disabled analog function controls pin.
Reset:
PTAPE5
PTAPE3 PTAPE2 PTAPE1 PTAPE0
Figure 6-8. Internal Pulling Device Enable Port Register (PTAPE)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-7. PTAPE Register Field Descriptions
Field 5,3:0 PTAPE[5,3:0] Description Internal Pulling Device Enable Port Bits Each these control bits determines whether internal pulling device enabled associated pin. port pins configured outputs, these bits have effect internal pullup devices disabled. Internal pulling device disabled port Internal pulling device enabled port
6.3.1.2
Pullup/Pulldown Control
Pullup/pulldown control used select pullup pulldown device enabled corresponding PTAPE bit.
Reset:
PTAPUD5
PTAPUD3 PTAPUD2 PTAPUD1 PTAPUD0
Figure 6-9. Pullup/Pulldown Device Control Port (PTAPUD) Table 6-8. PTAPUD Register Field Descriptions
Field 5,3:0 PTAPUD[5,3:0] Description Pullup/Pulldown Device Control Port Bits Each these control bits determines whether internal pullup pulldown device selected associated pin. actual pullup/pulldown device only enabled enabling associated PTAPE bit. Internal pullup device selected port Internal pulldown device selected port
6.3.1.3
Output Slew Rate Control Enable
Slew rate control enabled each port setting corresponding slew rate control register (PTASEn). When enabled, slew control limits rate which output transited reduce emissions. Slew rate control effect pins configured inputs.
Reset:
PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
Figure 6-10. Slew Rate Enable Port Register (PTASE)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-9. PTASE Register Field Descriptions
Field PTASE[4:0] Description Output Slew Rate Enable Port Bits Each these control bits determines whether output slew rate control enabled associated pin. port pins configured inputs, these bits have effect. Output slew rate control disabled port Output slew rate control enabled port
6.3.1.4
Reset
Port Drive Strength Selection Register (PTADS)
PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
Figure 6-11. Output Drive Strength Selection Port (PTADS) Table 6-10. PTADS Register Field Descriptions
Field Description
Output Drive Strength Selection Port Bits Each these control bits selects between high PTADS[4:0] output drive associated pin. output drive enabled port High output drive enabled port
6.3.2
Port Control Registers
pins associated with port controlled registers provided this section. These registers control pullup/pulldown slew rate port pins independent parallel registers.
6.3.2.1
Internal Pulling Device Enable
internal pulling device enabled each port setting corresponding pulling device enable register (PTBPEn). pulling device disabled configured output parallel control logic shared peripheral output function regardless state corresponding pulling device enable register bit. pulling device also disabled analog function controls pin.
PTBPE7 Reset: PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
Figure 6-12. Internal Pulling Device Enable Port Register (PTBPE)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-11. PTBPE Register Field Descriptions
Field PTBPE[7:0] Description Internal Pulling Device Enable Port Bits Each these control bits determines whether internal pulling device enabled associated pin. port pins that configured outputs, these bits have effect internal pullup devices disabled. Internal pulling device disabled port Internal pulling device enabled port
6.3.2.2
Pullup/Pulldown Control
Pullup/pulldown control used select pullup pulldown device enabled corresponding PTBPE bit.
PTBPUD7 Reset: PTBPUD6 PTBPUD5 PTBPUD4 PTBPUD3 PTBPUD2 PTBPUD1 PTBPUD0
Figure 6-13. Pullup/Pulldown Device Control Port (PTBPUD) Table 6-12. PTBPUD Register Field Descriptions
Field PTBPUD[7:0] Description Pullup/Pulldown Device Control Port Bits Each these control bits determines whether internal pullup pulldown device selected associated pin. actual pullup/pulldown device only enabled enabling associated PTBPE bit. Internal pullup device selected port Internal pulldown device selected port
6.3.2.3
Output Slew Rate Control Enable
Slew rate control enabled each port setting corresponding slew rate control register (PTBSEn). When enabled, slew control limits rate which output transited reduce emissions. Slew rate control effect pins configured inputs.
PTBSE7 Reset: PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
Figure 6-14. Slew Rate Enable Port Register (PTBSE)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-13. PTBSE Register Field Descriptions
Field PTBSE[7:0] Description Output Slew Rate Enable Port Bits Each these control bits determines whether output slew rate control enabled associated pin. port pins that configured inputs, these bits have effect. Output slew rate control disabled port Output slew rate control enabled port
6.3.2.4
Port Drive Strength Selection Register (PTBDS)
PTBDS7 Reset
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
Figure 6-15. Output Drive Strength Selection Port (PTBDS) Table 6-14. PTBDS Register Field Descriptions
Field Description
Output Drive Strength Selection Port Bits Each these control bits selects between high PTBDS[7:0] output drive associated pin. output drive enabled port High output drive enabled port
6.3.3
Port Control Registers
pins associated with port controlled registers provided this section. These registers control pullup/pulldown slew rate port pins independent parallel registers.
6.3.3.1
Internal Pulling Device Enable
internal pulling device enabled each port setting corresponding pulling device enable register (PTCPEn). pulling device disabled configured output parallel control logic shared peripheral output function regardless state corresponding pulling device enable register bit. pulling device also disabled analog function controls pin.
Reset:
PTCPE3 PTCPE2 PTCPE1 PTCPE0
Figure 6-16. Internal Pulling Device Enable Port Register (PTCPE)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-15. PTCPE Register Field Descriptions
Field PTCPE[3:0] Description Internal Pulling Device Enable Port Bits Each these control bits determines whether internal pulling device enabled associated pin. port pins that configured outputs, these bits have effect internal pullup devices disabled. Internal pulling device disabled port Internal pulling device enabled port
6.3.3.2
Pullup/Pulldown Control
Pullup/pulldown control used select pullup pulldown device enabled corresponding PTCPE bit.
Reset:
PTCPUD3 PTCPUD2 PTCPUD1 PTCPUD0
Figure 6-17. Pullup/Pulldown Device Control Port (PTCPUD) Table 6-16. PTCPUD Register Field Descriptions
Field PTCPUD[3:0] Description Pullup/Pulldown Device Control Port Bits Each these control bits determines whether internal pullup pulldown device selected associated pin. actual pullup/pulldown device only enabled enabling associated PTCPE bit. Internal pullup device selected port Internal pulldown device selected port
6.3.3.3
Output Slew Rate Control Enable
Slew rate control enabled each port setting corresponding slew rate control register (PTCSEn). When enabled, slew control limits rate which output transited reduce emissions. Slew rate control effect pins configured inputs.
Reset:
PTCSE3 PTCSE2 PTCSE1 PTCSE0
Figure 6-18. Slew Rate Enable Port Register (PTCSE)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-17. PTCSE Register Field Descriptions
Field PTCSE[3:0] Description Output Slew Rate Enable Port Bits Each these control bits determines whether output slew rate control enabled associated pin. port pins that configured inputs, these bits have effect. Output slew rate control disabled port Output slew rate control enabled port
6.3.3.4
Reset
Port Drive Strength Selection Register (PTCDS)
PTCDS3 PTCDS2 PTCDS1 PTCDS0
Figure 6-19. Output Drive Strength Selection Port (PTCDS) Table 6-18. PTCDS Register Field Descriptions
Field Description
Output Drive Strength Selection Port Bits Each these control bits selected between high PTCDS[3:0] output drive associated pin. output drive enabled port High output drive enabled port
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Introduction
This chapter summary information about registers, addressing modes, instruction RS08 family CPU. more detailed discussion, refer RS08 Core Reference Manual, volume Freescale Semiconductor document order number RS08RMv1. RS08 been developed target extremely low-cost embedded applications using process-independent design methodology, allowing keep pace with rapid developments silicon processing technology. main features RS08 core are: Streamlined programmer's model Subset HCS08 instruction with minor instruction extensions Minimal instruction cost-sensitive embedded applications instructions shadow program counter manipulation, short tiny addressing modes code size optimization bytes accessible memory space Reset will fetch first instruction from $3FFD Low-power modes supported through execution STOP WAIT instructions Debug FLASH programming support using background debug controller module Illegal address opcode detection with reset
Programmer's Model Registers
Figure shows programmer's model RS08 CPU. These registers located memory microcontroller. They built directly inside logic.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
ACCUMULATOR SHADOW PROGRAM COUNTER PROGRAM COUNTER
CONDITION CODE REGISTER
CARRY ZERO
Figure 7-1. Registers
addition registers, there three memory mapped registers that tightly coupled with core address generation during data read write operations. They indexed data register (D[X]), index register (X), page select register (PAGESEL). These registers located $000E, $000F, $001F, respectively.
INDEXED DATA REGISTER INDEX REGISTER PAGE SELECT PAGESEL (location $001F) (location $000F) D[X] (location $000E)
Figure 7-2. Memory Mapped Registers
7.2.1
Accumulator
This general-purpose 8-bit register primary data register RS08 MCUs. Data read from memory into with load accumulator (LDA) instruction. data written into memory with store accumulator (STA) instruction. Various addressing mode variations allow great deal flexibility specifying memory location involved load store instruction. Exchange instructions allow values exchanged between high (SHA) also between (SLA). Arithmetic, shift, logical operations performed value ADD, SUB, RORA, INCA, DECA, AND, ORA, EOR, etc. some these instructions, such INCA LSLA, value only input operand result replaces value other cases, such AND, there operands: value second value from memory. result arithmetic logical operation replaces value Some instructions, such memory-to-memory move instructions (MOV), accumulator. DBNZ also relieves because allows loop counter implemented memory variable rather than accumulator. During reset, accumulator loaded with $00.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
7.2.2
Program Counter (PC)
program counter 14-bit register that contains address next instruction operand fetched. During normal execution, program counter automatically increments next sequential memory location each time instruction operand fetched. Jump, branch, return operations load program counter with address other than that next sequential location. This called change-of-flow. During reset, program counter loaded with $3FFD program will start execution from this specific location.
7.2.3
Shadow Program Counter (SPC)
shadow program counter 14-bit register. During subroutine call using either instruction, return address will saved into SPC. Upon completion subroutine, instruction will restore content program counter from shadow program counter. During reset, shadow program counter loaded with $3FFD.
7.2.4
Condition Code Register (CCR)
2-bit condition code register contains status flags. content RS08 directly readable. bits tested using conditional branch instructions such BEQ. These register bits directly accessible through interface. following paragraphs provide detailed information about bits they used. Figure identifies bits their positions.
CONDITION CODE REGISTER
CARRY ZERO
Figure 7-3. Condition Code Register (CCR)
status bits cleared after reset. status bits indicate results arithmetic other instructions. Conditional branch instructions will either branch program location allow program continue next instruction after branch, depending values status bit. Conditional branch instructions, such BCC, BCS, BNE, cause branch depending state single bit. Often, conditional branch immediately follows instruction that caused bit(s) updated, this sequence:
more: lower: deca lower ;compare accumulator ;branch smaller this higher than same
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Other instructions executed between test conditional branch long only instructions used those which disturb bits that affect conditional branch. instance, test performed subroutine function conditional branch executed until subroutine returned main program. This form parameter passing (that information returned calling program condition code bits). Zero Flag indicate result operation $00. Branch equal (BEQ) branch equal (BNE) simple branches that branch based solely value bit. load, store, move, arithmetic, logical, shift, rotate instructions cause updated. Carry After addition operation, source operands were both greater than equal operands greater than equal result less than $80. This equivalent unsigned overflow. subtract compare performs subtraction memory operand from contents register after subtract operation, unsigned value memory operand greater than unsigned value register. This equivalent unsigned borrow underflow. Branch carry clear (BCC) branch carry (BCS) branches that branch based solely value bit. also used unsigned branches BHS. Add, subtract, shift, rotate instructions cause updated. branch (BRSET) branch clear (BRCLR) instructions copy tested into facilitate efficient serial-to-parallel conversion algorithms. carry (SEC) clear carry (CLC) allow carry cleared directly. This useful combination with shift rotate instructions routines that pass status information back main program, from subroutine, bit. included shift rotate operations those operations easily extended multi-byte operands. shift rotate operations considered 9-bit shifts that include 8-bit operand register carry CCR. After logical shift, holds that shifted 8-bit operand. rotate instruction used next, this shifted into operand rotate, that gets shifted other operand replaces value used subsequent rotate instructions.
7.2.5
Indexed Data Register (D[X])
This 8-bit indexed data register allows user access data direct page address space indexed This register resides memory mapped location $000E. details D[X] register, please refer Section 7.3.8, "Indexed Addressing Mode (IX, Implemented Pseudo Instructions)."
7.2.6
Index Register
This 8-bit index register allows user index address location direct page address space. This register resides memory mapped location $000F. details register, please refer Section 7.3.8, "Indexed Addressing Mode (IX, Implemented Pseudo Instructions)."
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
7.2.7
Page Select Register (PAGESEL)
This 8-bit page select register allows user access memory locations entire 16K-byte address space through page window located from $00C0 $00FF. This register resides memory mapped location $001F. details PAGESEL register, please refer RS08 Core Reference Manual.
Addressing Modes
Whenever reads information from memory writes information into memory, addressing mode used determine exact address where information read from written This section explains several addressing modes each useful different programming situations. Every opcode tells perform certain operation certain way. Many instructions, such load accumulator (LDA), allow several different ways specify memory location operated each addressing mode variation requires separate opcode. these variations same instruction mnemonic, assembler knows which opcode based syntax location operand field. some cases, special characters used indicate specific addressing mode (such [pound] symbol, which indicates immediate addressing mode). other cases, value operand tells assembler which addressing mode use. example, assembler chooses short addressing mode instead direct addressing mode operand address from $0000 $001F. Besides allowing assembler choose addressing mode based operand address, assembler directives also used force direct tiny/short addressing mode using prefix before operand, respectively. Some instructions more than addressing mode. example, move instructions addressing mode access source value from memory second addressing mode access destination memory location. these move instructions, both addressing modes listed documentation. branch instructions relative (REL) addressing mode determine destination branch, BRCLR, BRSET, CBEQ, DBNZ also must access memory operand. These instructions classified addressing mode used memory operand, relative addressing mode branch offset assumed. discussion following paragraphs includes each addressing mode works syntax clues that instruct assembler specific addressing mode.
7.3.1
Inherent Addressing Mode (INH)
This addressing mode used when inherently knows everything needs complete instruction addressing information supplied source code. Usually, operands that needs located CPU's internal registers, LSLA, CLRA, INCA, SLA, RTS, others. inherent instructions, including operation (NOP) background (BGND), have operands.
7.3.2
Relative Addressing Mode (REL)
Relative addressing mode used specify offset address branch instructions relative program counter. Typically, programmer specifies destination with program label
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
expression operand field branch instruction; assembler calculates difference between location counter (which points next address after branch instruction time) address represented label expression operand field. This difference called offset 8-bit two's complement number. assembler stores this offset object code branch instruction. During execution, evaluates condition that controls branch. branch condition true, sign-extends offset 14-bit value, adds offset current uses this address where will fetch next instruction continue execution rather than continuing execution with next instruction after branch. Because offset 8-bit two's complement value, destination must within range -128 +127 locations from address that follows last byte object code branch instruction. common method create simple infinite loop branch instruction that branches itself. This sometimes used short code segments during debug. Typically, this infinite loop, debug host (through background commands) stop program, examine registers memory, start execution from location. This construct used normal application programs except case where program detected error wants force watchdog timer timeout. (The branch infinite loop executes repeatedly until watchdog timer eventually causes reset.)
7.3.3
Immediate Addressing Mode (IMM)
this addressing mode, operand located immediately after opcode instruction stream. This addressing mode used when programmer wants explicit value that known time program written. (pound) symbol used tell assembler operand data value rather than address where desired value will accessed. size immediate operand always bits. assembler automatically will truncate extend operand needed match size needed instruction. Most assemblers generate warning 16-bit operand provided. programmer's responsibility symbol tell assembler when immediate addressing will used. assembler does consider error leave symbol because resulting statement still valid instruction (although mean something different than programmer intended).
7.3.4
Tiny Addressing Mode (TNY)
addressing mode capable addressing only first bytes address map, from $0000 $000F. This addressing mode available INC, DEC, ADD, instructions. system optimized placing most computation-intensive data this area memory. Because 4-bit address embedded opcode, only least significant four bits address must included instruction; this saves program space execution time. During execution, adds high-order 4-bit operand address uses combined 14-bit address ($000x) access intended operand.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
7.3.5
Short Addressing Mode (SRT)
addressing mode capable addressing only first bytes address map, from $0000 $001F. This addressing mode available CLR, LDA, instructions. system optimized placing most computation-intensive data this area memory. Because 5-bit address embedded opcode, only least significant five bits address must included instruction; this saves program space execution time. During execution, adds nine high-order 5-bit operand address uses combined 14-bit address ($000x $001x) access intended operand.
7.3.6
Direct Addressing Mode (DIR)
addressing mode used access operands located direct address space ($0000 through $00FF). During execution, adds high-order byte direct address operand that follows opcode. uses combined 14-bit address ($00xx) access intended operand.
7.3.7
Extended Addressing Mode (EXT)
extended addressing mode, 14-bit address operand included object code low-order bits next bytes after opcode. This addressing mode only used instructions jump destination address RS08 MCUs.
7.3.8
Indexed Addressing Mode (IX, Implemented Pseudo Instructions)
Indexed addressing mode sometimes called indirect addressing mode because index register used reference access intended operand. important feature indexed addressing mode that operand address computed during execution based current contents index register located $000F memory rather than being constant address location that determined during program assembly. This allows writing program that accesses different operand locations depending results earlier program instructions (rather than accessing location that determined when program written). index addressing mode supported RS08 Family uses register located $000F index D[X] register located $000E indexed data register. programming index register location direct page read/written indexed data register D[X]. These pseudo instructions used with instructions supporting direct, short, tiny addressing modes using D[X] operand.
Special Operations
Most what does described instruction set, special operations must considered, such starts beginning application program after power first applied. After program begins running, current instruction normally determines what will next. exceptional events cause temporarily suspend normal program execution:
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Reset events force start over beginning application program, which forces execution start $3FFD. host development system cause active background mode rather than continuing next instruction application program.
7.4.1
Reset Sequence
Processing begins trailing edge reset event. number things that cause reset events vary slightly from RS08 derivative another; however, most common sources are: power-on reset, external RESET pin, low-voltage reset, watchdog timeout, illegal opcode detect, illegal address access. more information about recognizes reset events determines difference between internal external causes, refer Resets Interrupts chapter. Reset events force immediately stop what doing begin responding reset. instruction that process will aborted immediately without completing remaining clock cycles. short sequence activities completed decide whether source reset internal external record cause reset. remainder time, reset source remains active internal clocks stopped save power. trailing edge reset event, clocks resume exits from reset condition. program counter reset $3FFD instruction fetch will started after release reset. device execute code from on-chip memory starting from $3FFD after reset, care must taken force BKDG reset because this will force device into active background mode where will wait command from background communication interface.
7.4.2
Interrupts
interrupt mechanism RS08 used interrupt normal flow instructions; used wake RS08 from wait stop modes. mode, interrupt events must polled CPU. interrupt feature compatible with Freescale's HC05, HC08, HCS08 Families.
7.4.3
Wait Stop Mode
Wait stop modes entered executing WAIT STOP instruction, respectively. these modes, clocks shut down save power activity suspended. remains this low-power state until interrupt reset event wakes Please refer Resets Interrupts chapter effects wait stop other device peripherals.
7.4.4
Active Background Mode
Active background mode refers condition which stopped executing user program instructions waiting serial commands from background debug system. Refer Development Support chapter detailed information active background mode. arithmetic left shift pseudo instruction also available because operation identical logical shift left.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Summary Instruction Table
Instruction Summary Nomenclature nomenclature listed here used instruction descriptions Table through Table 7-2. Operators
Contents register memory location shown inside parentheses loaded with (read: "gets") Exchange with Boolean Boolean Boolean exclusive-OR Concatenate Accumulator Condition code register Program counter Program counter, higher order (most significant) bits Program counter, lower order (least significant) eight bits Shadow program counter Shadow program counter, higher order (most significant) bits Shadow program counter, lower order (least significant) eight bits
registers SPCH SPCL
Memory addressing memory location absolute data, depending addressing mode relative offset, which two's complement number stored last byte machine code corresponding branch instruction Pseudo index register, memory location $000F D[X] Memory location $000E pointing memory location defined pseudo index register (location $000F) Condition code register (CCR) bits Zero indicator Carry/borrow activity notation affected forced forced cleared according results operation Undefined after operation Machine coding notation
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Source form
Low-order eight bits direct address $0000-$00FF (high byte assumed $00) byte immediate data High-order 6-bit 14-bit extended address prefixed with 2-bit Low-order byte 14-bit extended address Relative offset
Everything source forms columns, except expressions italic characters, literal information which must appear assembly source file exactly shown. initial 5-letter mnemonic always literal expression. commas, pound signs (#), parentheses, plus signs literal characters. label expression that evaluates single integer range 0-7. label expression that evaluates single hexadecimal integer range $0-$F. opr8i label expression that evaluates 8-bit immediate value. opr4a label expression that evaluates Tiny address (4-bit value). instruction treats this 4-bit value order four bits address 16-Kbyte address space ($0000-$000F). This 4-bit value embedded order four bits opcode. opr5a label expression that evaluates Short address (5-bit value). instruction treats this 5-bit value order five bits address 16-Kbyte address space ($0000-$001F). This 5-bit value embedded order bits opcode. opr8a label expression that evaluates 8-bit value. instruction treats this 8-bit value order eight bits address 16-Kbyte address space ($0000-$00FF). opr16a label expression that evaluates 14-bit value. RS08 core, upper bits always instruction treats this value address 16-Kbyte address space. label expression that refers address that within -128 +127 locations from next address after last byte object code current instruction. assembler will calculate 8-bit signed offset include object code this instruction. Address modes Inherent operands) Immediate Direct instruction) Immediate Direct Direct instruction) Direct Short Tiny Extended 8-bit relative offset
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Table 7-1. Instruction Summary (Sheet
Source Form
#opr8i opr8a #opr8i opr8a opr4a #opr8i opr8a
Description
Operation
Effect
Operand
Address Mode
Opcode
with Carry
without Carry
Logical
ASLA(1)
Arithmetic Shift Left Branch Carry Clear
(PC) $0002 rel,
BCLR n,opr8a
BCLR n,D[X]
Clear Memory
BCLR
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
BGND
Branch Carry (Same BLO) Branch Equal Background
(PC) $0002 rel, (PC) $0002 rel, Enter Background Debug Mode
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 7-1. Instruction Summary (Sheet
Source Form
Description
Branch Higher Same (Same BCC) Branch Lower (Same BCS) Branch Equal Branch Always Branch Never
Operation
Effect
Operand
Address Mode
Opcode
(PC) $0002 rel, (PC) $0002 rel, (PC) $0002 rel, (PC) $0002 (PC) $0002
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
BRCLR n,opr8a,rel
BRCLR n,D[X],rel
Branch Memory Clear
(PC) $0003 rel, (Mn)
BRCLR n,X,rel
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 7-1. Instruction Summary (Sheet
Source Form Effect Operand Address Mode Opcode Cycles
Description
Operation
BRSET n,opr8a,rel
BRSET n,D[X],rel
Branch Memory
(PC) $0003 rel, (Mn)
BRSET n,X,rel
BSET n,opr8a
BSET n,D[X]
Memory
BSET
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register. SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Table 7-1. Instruction Summary (Sheet
Source Form Effect Operand Address Mode Opcode Cycles
Description
Operation
(PC) Push shadow (PC) (PC) $0003 rel, (PC) $0003 rel, (PC) $0003 rel,
CBEQA #opr8i,rel CBEQ opr8a,rel CBEQ ,X,rel (1),(2) CBEQ X,rel opr8a opr5a CLRA CLRX #opr8i opr8a COMA
Branch Subroutine
Cx/Dx
Compare Branch Equal Clear Carry
Clear
Compare Accumulator with Memory Complement (One's Complement)
DBNZ opr8a,rel DBNZ ,X,rel DBNZA DBNZX
(PC) $0003 (result) DBNZ direct Decrement Branch (PC) $0002 (result) Zero DBNZA (PC) $0003 (result) Decrement
opr8a opr4a DECA #opr8i opr8a opr8a opr4a INCA INCX opr16a opr16a #opr8i opr8a opr5a
Exclusive Memory with Accumulator
Increment Effective Address (PC) Push shadow Effective Address
Jump Jump Subroutine
Load Accumulator from Memory
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Table 7-1. Instruction Summary (Sheet
Source Form
#opr8i opr8a LSLA
Description
Operation
Effect
Operand
Address Mode
Opcode
Load Index Register from Memory
Logical Shift Left
LSRA
Logical Shift Right
IX/DIR DIR/IX IMM/IX
opr8a,opr8a #opr8i,opr8a D[X],opr8a opr8a,D[X] #opr8i,D[X] #opr8i opr8a ROLA
Move
(M)destination (M)source
Operation Inclusive Accumulator Memory
None
Rotate Left through Carry
RORA
Rotate Right through Carry Return from Subroutine
#opr8i opr8a opr8a opr5a opr8a STOP
Pull from shadow
Subtract with Carry
Carry Swap Shadow High with Swap Shadow with Store Accumulator Memory Store Index Register Memory into stop mode
SPCH SPCL
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 7-1. Instruction Summary (Sheet
Source Form Effect Operand Address Mode Opcode Cycles
Description
Operation
#opr8i opr8a opr4a TAX(1) opr8a TSTA TSTX TXA(1) WAIT
Subtract
Transfer
Test Zero
Transfer into WAIT mode
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Table 7-2. Opcode
HIGH DIR/REL IMM/INH DIR/EXT
BRSET0 BSET0
BRCLR0 BCLR0
CBEQ
CBEQA
BRSET1 BSET1
BRCLR1 BCLR1
COMA
BRSET2 BSET2
LSRA
BRCLR2 BCLR2
BRSET3 BSET3
RORA
BRCLR3 BCLR3
BRSET4 BSET4
LSLA
BRCLR4 BCLR4
ROLA
BRSET5 BSET5
DECA
BRCLR5 BCLR5
DBNZ
DBNZA
BRSET6 BSET6
INCA
BRCLR6 BCLR6
BRSET7 BSET7
STOP
BRCLR7 BCLR7
Inherent Immediate Direct Extended Direct-Direct
CLRA
WAIT
BGND
Relative Short Tiny Immediate-Direct
High Byte Opcode Hexadecimal
Gray decoded illegal instruction Byte Opcode Hexadecimal
RS08 Cycles Opcode Mnemonic Number Bytes Addressing Mode
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter Analog Comparator (RS08ACMPV1)
Introduction
analog comparator module (ACMP) provides circuit comparing analog input voltages comparing analog input voltage with internal bandgap reference voltage. comparator circuit operate across full range supply voltage (rail rail operation). Figure shows SC9RS08MZ8 block diagram with ACMP block pins highlighted.
RS08 CORE ANALOG COMPARATOR (ACMP) 8-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) PTA5/TCLK/RESET/VPP PTA4/ACMPO/BKGD/MS PTA3/ADP3 PTA2/ADP2 PTA1/TPMCH1/ADP1/ACMP- PTA0/TPMCH0/ADP0/ACMP+ PTB7/EXTAL PTB6/XTAL PTB5/TPMCH1 16-BIT TIMER/PWM MODULE (TPM) 8-BIT TIMER (MTIM1 MTIM2) USER BYTES PORT PTB4/TPMCH0 PTB3/ADP7 PTB2/ADP6 PTB1/ADP5 PTB0/ADP4 PTC3/ADP11 PORT PTC2/ADP10 PTC1/ADP9 PTC0/ADP8
RS08 SYSTEM CONTROL RESETS INTERRUPTS MODES OPERATION POWER MANAGEMENT WAKEUP USER FLASH 8192 BYTES
INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 39.0625
(XOSC)
VOLTAGE REGULATOR
Figure 8-1. SC9RS08MZ8 Block Diagram Highlighting ACMP Block Pins
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
PORT
Analog Comparator (RS08ACMPV1)
8.1.1
Features
ACMP following features: Full rail-to-rail supply operation Less than input offset Less than hysteresis Selectable interrupt rising edge, falling edge, either rising falling edges comparator output Option compare fixed internal bandgap reference voltage Option allow comparator output visible pin, ACMPO Remains operational stop mode
8.1.2
Modes Operation
This section defines ACMP operation wait, stop, background debug modes.
8.1.2.1
Operation Wait Mode
ACMP continues operate wait mode enabled before executing WAIT instruction. Therefore, ACMP used bring wait mode ACMP interrupt enabled (ACIE lowest possible current consumption, ACMP must disabled software required interrupt source during wait mode.
8.1.2.2
Operation Stop Mode
ACMP continues operate stop mode enabled compare operation remains active. ACOPE enabled, comparator output operates normal operating mode comparator output placed onto external pin. brought stop when compare event occurs ACIE enabled; flag sets accordingly. stop exited with reset, ACMP will into reset state.
8.1.2.3
Operation Active Background Mode
When active background mode, ACMP will continue operate normally.
8.1.3
Block Diagram
block diagram analog comparator module shown Figure 8-2.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Analog Comparator (RS08ACMPV1)
Internal Bandgap Reference Voltage ACBGS ACME ACMOD
Internal ACMP INTERRUPT REQUEST
ACIE Status Control Register ACOPE
ACMP+ Comparator
ACME Interrupt Control
ACMP-
ACMPO
Figure 8-2. Analog Comparator (ACMP) Block Diagram
External Signal Description
ACMP analog input pins, ACMP+ ACMP-, digital output pin, ACMPO. Each input pins accept input voltage that varies across full operating voltage range MCU. shown Figure 8-2, ACMP- connected inverting input comparator, ACMP+ connected non-inverting input comparator ACBGS=0. shown Figure 8-2, ACMPO enabled drive external pin. signal properties ACMP shown Table 8-1.
Table 8-1. Signal Properties
Signal ACMP- ACMP+ ACMPO Function Inverting analog input ACMP (Minus input) Non-inverting analog input ACMP (Positive input) Digital output ACMP
Register Definition
ACMP includes register: 8-bit status control register Refer direct-page register summary memory chapter this data sheet absolute address assignments ACMP registers.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Analog Comparator (RS08ACMPV1)
8.3.1
ACMP Status Control Register (ACMPSC)
ACMPSC contains status flag control bits which used enable configure ACMP.
ACME Reset: Unimplemented ACBGS ACIE
ACOPE ACMOD
Figure 8-3. ACMP Status Control Register (ACMPSC) Table 8-2. ACMPSC Field Descriptions
Field ACME ACBGS Description Analog Comparator Module Enable ACME enables ACMP module. ACMP enabled. ACMP enabled. Analog Comparator Bandgap Select ACBGS used select between internal bandgap reference voltage ACMP+ non-inverting input analog comparator. External ACMP+ selected non-inverting input comparator. Internal bandgap reference voltage selected non-inverting input comparator. Analog Comparator Flag when compare event occurs. Compare events defined ACMOD. cleared writing ACF. Compare event occurred. Compare event occurred. Analog Comparator Interrupt Enable ACIE enables interrupt ACMP. When ACIE set, interrupt will asserted when set. Interrupt disabled. Interrupt enabled. Analog Comparator Output Reading will return current value analog comparator output. reset will read when ACMP disabled (ACME Analog Comparator Output Enable ACOPE used enable comparator output placed onto external pin, ACMPO. ACOPE will only control ACMP active (ACME=1). Analog comparator output available ACMPO. Analog comparator output driven ACMPO. Analog Comparator Mode ACMOD selects type compare event which sets ACF. Encoding Comparator output falling edge. Encoding Comparator output rising edge. Encoding Comparator output falling edge. Encoding Comparator output rising falling edge.
ACIE
ACOPE
ACMOD
Functional Description
analog comparator used compare analog input voltages applied ACMP+ ACMP-; used compare analog input voltage applied ACMP- with internal bandgap reference
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Analog Comparator (RS08ACMPV1)
voltage. ACBGS used select between bandgap reference voltage ACMP+ input non-inverting input analog comparator. comparator output high when non-inverting input greater than inverting input, when non-inverting input less than inverting input. ACMOD used select condition which will cause set. rising edge comparator output, falling edge comparator output, either rising falling edge (toggle). comparator output read directly through ACO. comparator output also driven onto ACMPO using ACOPE. NOTE Comparator inputs high impedance analog pins which sensitive noise. Noisy and/or toggling adjacent analog inputs cause comparator offset/hysteresis performance exceed specified values. Maximum source impedance restricted value specified SC9RS08MZ8 Data Sheet. achieve maximum performance device recommended enter WAIT/STOP mode ACMP measurement adjacent toggling must avoided.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Analog Comparator (RS08ACMPV1)
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter 8-Bit Analog-to-Digital Converter (RS08ADC10V1)
Introduction
8-bit analog-to-digital converter (ADC) successive approximation designed operation within integrated microcontroller system-on-chip. NOTE SC9RS08MZ8 device only provides 8-bit operation. 10-bit 12-bit operations supported. This chapter reserves description 10-bit 12-bit operations compatible with data sheet other Freescale 8-bit MCUs. Figure shows SC9RS08MZ8 with module pins highlighted.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
Chapter 8-Bit Analog-to-Digital Converter (RS08ADC10V1)
RS08 CORE ANALOG COMPARATOR (ACMP) 8-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) PTA5/TCLK/RESET/VPP PTA4/ACMPO/BKGD/MS PTA3/ADP3 PTA2/ADP2 PTA1/TPMCH1/ADP1/ACMP- PTA0/TPMCH0/ADP0/ACMP+ PTB7/EXTAL PTB6/XTAL PTB5/TPMCH1 16-BIT TIMER/PWM MODULE (TPM) 8-BIT TIMER (MTIM1 MTIM2) USER PORT BYTES PORT PTB4/TPMCH0 PTB3/ADP7 PTB2/ADP6 PTB1/ADP5 PTB0/ADP4 PTC3/ADP11 PTC2/ADP10 PTC1/ADP9 PTC0/ADP8
RS08 SYSTEM CONTROL RESETS INTERRUPTS MODES OPERATION POWER MANAGEMENT WAKEUP USER FLASH 8192 BYTES
INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 39.0625
(XOSC)
VOLTAGE REGULATOR
Figure 9-1. SC9RS08MZ8 Block Diagram Highlighting Block Pins
9.1.1
Module Configurations
This section provides device-specific information configuring SC9RS08MZ8 device.
9.1.1.1
Analog Supply Voltage Reference Connections
VDDAD VREFH sources internally connected pin. VSSAD VREFL sources internally connected pin.
9.1.1.2
Alternate Clock
perform conversions using clock, clock divided two, local asynchronous clock (ADACK) within module. alternate clock, ALTCLK, input SC9RS08MZ8 device implemented.
SC9RS08MZ8 Data Sheet, Rev. Freescale Semiconductor
PORT
Chapter 8-Bit Analog-to-Digital Converter (RS08ADC10V1)
9.1.1.3
Hardware Trigger
hardware trigger ADHWT output from real-time interrupt (RTI) counter. ICSERCLK nominal clock source within block clock counter. input clock frequency RTIS bits determine period. counter free-running counter that generates overflow rate determined RTIS bits. When hardware trigger enabled, conversion initiates upon counter overflow. configured cause hardware trigger run, stop. NOTE quick hardware trigger, clock source must high frequency external clock source.
9.1.1.4
Analog Enables
SC9RS08MZ8 device contains only analog enable registers, APCTL1 APCTL2. channel assignments SC9RS08MZ8 device shown table below. Reserved c
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