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MC9S12Q128 Reference Manual Covers MC9S12Q Family
HCS12 Microcontrollers
1.09 MC9S12Q128 12/2007
freescale.com
provide most up-to-date information, revision documents World Wide will most current. Your printed copy earlier revision. verify have latest information available, refer http://freescale.com/ full list family members options included appendices. following revision history table summarizes changes contained this document. This document contains information constituent modules, with exception CPU. information please refer Reference Manual.
Date July, 2005 August, 2005
Revision Level 01.00 01.01 Book Corrected Typos Adjusted assert level Added package option
Description
October, 2005 December, 2005 December, 2005 January, 2006 2006 2006 2007 2007
01.02 01.03 01.04 01.05
Corrected Typos (PW4 references, registers, 25MHz references) Corrected enhanced layout drawings Added note block diagram figure Added rerouting note 80QFP package diagram Updated levels electrical parameter section Fixed incorrect reference TSCR2 Added 0M66G PART number Corrected missing overbars names Added units MSCAN timing table Corrected CRGFLG contents register summary Corrected unintended symbol font Added emulation package info. Corrected channel count section Updated section Corrected typos inconsistent register listing format Added PartID
01.06
01.07
01.08
01.09
Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter
MC9S12Q Device Overview (MC9S12Q128-Family) Port Integration Module (PIM9C32) Module Mapping Control (MMCV4) Multiplexed External Interface (MEBIV3) Interrupt (INTV1) Background Debug Module (BDMV4) Debug Module (DBGV1) Analog-to-Digital Converter (ATD10B8C) Clocks Reset Generator (CRGV4) Scalable Controller Area Network (S12MSCANV2) Oscillator (OSCV2) Pulse-Width Modulator (PWM8B4CV1). Serial Communications Interface (S12SCIV2) Serial Peripheral Interface (SPIV3) Timer Module (TIM16B6C) Dual Output Voltage Regulator (VREG3V3V2) Kbyte Flash Module (S12FTS32KV1) Kbyte Flash Module (S12FTS64KV4) Kbyte Flash Module (S12FTS96KV1) Kbyte Flash Module (S12FTS128K1V1)
Appendix Electrical Characteristics. Appendix Emulation Information Appendix Package Information Appendix Derivative Differences Appendix Ordering Information
Freescale Semiconductor
MC9S12Q128 1.09
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Introduction 1.1.1 Features 1.1.2 Modes Operation 1.1.3 Block Diagram Memory Registers 1.2.1 Device Memory 1.2.2 Detailed Register 1.2.3 Part Assignments Signal Description 1.3.1 Device Pinouts 1.3.2 Signal Properties Summary 1.3.3 Initialization 52-Pin LQFP Bond Versions 1.3.4 Detailed Signal Descriptions 1.3.5 Power Supply Pins System Clock Description Modes Operation 1.5.1 Chip Configuration Summary 1.5.2 Security 1.5.3 Low-Power Modes Resets Interrupts 1.6.1 Vectors 1.6.2 Resets Device Specific Information Module Dependencies 1.7.1 PPAGE 1.7.2 Alternate Clock 1.7.3 Extended Address Range Emulation Implications 1.7.4 VREGEN 1.7.5 VDD1, VDD2, VSS1, VSS2 1.7.6 Clock Reset Generator VREG Interface 1.7.7 Analog-to-Digital Converter 1.7.8 MODRR Register Port Port Mapping 1.7.9 Port Dependency Registers Recommended Printed Circuit Board Layout
Chapter Port Integration Module (PIM9C32) Block Description
Introduction 2.1.1 Features 2.1.2 Block Diagram Signal Description Memory Registers 2.3.1 Module Memory
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MC9S12Q128 1.09
2.3.2 Register Descriptions Functional Description 2.4.1 Registers 2.4.2 Port Descriptions 2.4.3 Port BKGD 2.4.4 External Descriptions 2.4.5 Power Options Initialization Information 2.5.1 Reset Initialization Interrupts 2.6.1 Interrupt Sources 2.6.2 Recovery from STOP Application Information
Chapter Module Mapping Control (MMCV4) Block Description
Introduction 3.1.1 Features 3.1.2 Modes Operation External Signal Description Memory Register Definition 3.3.1 Module Memory 3.3.2 Register Descriptions Functional Description 3.4.1 Control 3.4.2 Address Decoding 3.4.3 Memory Expansion
Chapter Multiplexed External Interface (MEBIV3)
Introduction 4.1.1 Features 4.1.2 Modes Operation External Signal Description Memory Register Definition 4.3.1 Module Memory 4.3.2 Register Descriptions Functional Description 4.4.1 Detecting Access Type from External Signals 4.4.2 Stretched Cycles 4.4.3 Modes Operation 4.4.4 Internal Visibility 4.4.5 Low-Power Options
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Chapter Interrupt (INTV1) Block Description
Introduction 5.1.1 Features 5.1.2 Modes Operation External Signal Description Memory Register Definition 5.3.1 Module Memory 5.3.2 Register Descriptions Functional Description 5.4.1 Low-Power Modes Resets Interrupts 5.6.1 Interrupt Registers 5.6.2 Highest Priority I-Bit Maskable Interrupt 5.6.3 Interrupt Priority Decoder Exception Priority
Chapter Background Debug Module (BDMV4) Block Description
Introduction 6.1.1 Features 6.1.2 Modes Operation External Signal Description 6.2.1 BKGD Background Interface 6.2.2 TAGHI High Byte Instruction Tagging 6.2.3 TAGLO Byte Instruction Tagging Memory Register Definition 6.3.1 Module Memory 6.3.2 Register Descriptions Functional Description 6.4.1 Security 6.4.2 Enabling Activating 6.4.3 Hardware Commands 6.4.4 Standard Firmware Commands 6.4.5 Command Structure 6.4.6 Serial Interface 6.4.7 Serial Interface Hardware Handshake Protocol 6.4.8 Hardware Handshake Abort Procedure 6.4.9 SYNC Request Timed Reference Pulse 6.4.10 Instruction Tracing 6.4.11 Instruction Tagging 6.4.12 Serial Communication Time-Out 6.4.13 Operation Wait Mode
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6.4.14 Operation Stop Mode
Chapter Debug Module (DBGV1) Block Description
Introduction 7.1.1 Features 7.1.2 Modes Operation 7.1.3 Block Diagram External Signal Description Memory Register Definition 7.3.1 Module Memory 7.3.2 Register Descriptions Functional Description 7.4.1 Operating Mode 7.4.2 Operating Mode 7.4.3 Breakpoints Resets Interrupts
Chapter Analog-to-Digital Converter (ATD10B8C) Block Description
Introduction 8.1.1 Features 8.1.2 Modes Operation 8.1.3 Block Diagram Signal Description 8.2.1 ETRIG PAD7 8.2.2 PAD6 8.2.3 PAD5 8.2.4 PAD4 8.2.5 PAD3 8.2.6 PAD2 8.2.7 PAD1 8.2.8 PAD0 8.2.9 VRH, 8.2.10 VDDA, VSSA Memory Registers 8.3.1 Module Memory 8.3.2 Register Descriptions Functional Description 8.4.1 Analog Sub-block 8.4.2 Digital Sub-block Initialization/Application Information
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8.5.1 Setting starting conversion 8.5.2 Aborting conversion Resets Interrupts
Chapter Clocks Reset Generator (CRGV4) Block Description
Introduction 9.1.1 Features 9.1.2 Modes Operation 9.1.3 Block Diagram External Signal Description 9.2.1 VDDPLL, VSSPLL Operating Voltage, Ground 9.2.2 Loop Filter 9.2.3 RESET Reset Memory Register Definition 9.3.1 Module Memory 9.3.2 Register Descriptions Functional Description 9.4.1 Phase Locked Loop (PLL) 9.4.2 System Clocks Generator 9.4.3 Clock Monitor (CM) 9.4.4 Clock Quality Checker 9.4.5 Computer Operating Properly Watchdog (COP) 9.4.6 Real-Time Interrupt (RTI) 9.4.7 Modes Operation 9.4.8 Low-Power Operation Mode 9.4.9 Low-Power Operation Wait Mode 9.4.10 Low-Power Operation Stop Mode Resets 9.5.1 Clock Monitor Reset 9.5.2 Computer Operating Properly Watchdog (COP) Reset 9.5.3 Power-On Reset, Voltage Reset Interrupts 9.6.1 Real-Time Interrupt 9.6.2 Lock Interrupt 9.6.3 Self-Clock Mode Interrupt
Chapter Freescale's Scalable Controller Area Network (S12MSCANV2)
10.1 Introduction 10.1.1 Glossary 10.1.2 Block Diagram 10.1.3 Features
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10.2
10.3
10.4
10.5
10.1.4 Modes Operation External Signal Description 10.2.1 RXCAN Receiver Input 10.2.2 TXCAN Transmitter Output 10.2.3 System Memory Register Definition 10.3.1 Module Memory 10.3.2 Register Descriptions 10.3.3 Programmer's Model Message Storage Functional Description 10.4.1 General 10.4.2 Message Storage 10.4.3 Identifier Acceptance Filter 10.4.4 Modes Operation 10.4.5 Low-Power Options 10.4.6 Reset Initialization 10.4.7 Interrupts Initialization/Application Information 10.5.1 MSCAN initialization
Chapter Oscillator (OSCV2) Block Description
11.1 Introduction 11.1.1 Features 11.1.2 Modes Operation 11.2 External Signal Description 11.2.1 VDDPLL VSSPLL Operating Voltage, Ground 11.2.2 EXTAL XTAL Clock/Crystal Source Pins 11.2.3 XCLKS Colpitts/Pierce Oscillator Selection Signal 11.3 Memory Register Definition 11.4 Functional Description 11.4.1 Amplitude Limitation Control (ALC) 11.4.2 Clock Monitor (CM) 11.5 Interrupts
Chapter Pulse-Width Modulator (PWM8B4C) Block Description
12.1 Introduction 12.1.1 Features 12.1.2 Modes Operation 12.1.3 Block Diagram 12.2 External Signal Description 12.2.1 PWM3 Pulse Width Modulator Channel 12.2.2 PWM2 Pulse Width Modulator Channel
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12.3
12.4
12.5 12.6
12.2.3 PWM1 Pulse Width Modulator Channel 12.2.4 PWM0 Pulse Width Modulator Channel Memory Registers 12.3.1 Module Memory 12.3.2 Register Descriptions Functional Description 12.4.1 Clock Select 12.4.2 Channel Timers Resets Interrupts
Chapter Serial Communications Interface (S12SCIV2) Block Description
13.1 Introduction 13.1.1 Glossary 13.1.2 Features 13.1.3 Modes Operation 13.1.4 Block Diagram 13.2 External Signal Description 13.2.1 TXD-SCI Transmit 13.2.2 RXD-SCI Receive 13.3 Memory Registers 13.3.1 Module Memory 13.3.2 Register Descriptions 13.4 Functional Description 13.4.1 Data Format 13.4.2 Baud Rate Generation 13.4.3 Transmitter 13.4.4 Receiver 13.4.5 Single-Wire Operation 13.4.6 Loop Operation 13.5 Initialization Information 13.5.1 Reset Initialization 13.5.2 Interrupt Operation 13.5.3 Recovery from Wait Mode
Chapter Serial Peripheral Interface (SPIV3) Block Description
14.1 Introduction 14.1.1 Features 14.1.2 Modes Operation 14.1.3 Block Diagram 14.2 External Signal Description
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14.3
14.4
14.5 14.6
14.2.1 MOSI Master Out/Slave 14.2.2 MISO Master In/Slave 14.2.3 Slave Select 14.2.4 Serial Clock Memory Register Definition 14.3.1 Module Memory 14.3.2 Register Descriptions Functional Description 14.4.1 Master Mode 14.4.2 Slave Mode 14.4.3 Transmission Formats 14.4.4 Baud Rate Generation 14.4.5 Special Features 14.4.6 Error Conditions 14.4.7 Operation Mode 14.4.8 Operation Wait Mode 14.4.9 Operation Stop Mode Reset Interrupts 14.6.1 MODF 14.6.2 SPIF 14.6.3 SPTEF
Chapter Timer Module (TIM16B6CV1) Block Description
15.1 Introduction 15.1.1 Features 15.1.2 Modes Operation 15.1.3 Block Diagrams 15.2 External Signal Description 15.2.1 IOC7 Input Capture Output Compare Channel 15.2.2 IOC6 Input Capture Output Compare Channel 15.2.3 IOC5 Input Capture Output Compare Channel 15.2.4 IOC4 Input Capture Output Compare Channel 15.2.5 IOC3 Input Capture Output Compare Channel 15.2.6 IOC2 Input Capture Output Compare Channel 15.3 Memory Registers 15.3.1 Module Memory 15.3.2 Register Descriptions 15.4 Functional Description 15.4.1 Prescaler 15.4.2 Input Capture 15.4.3 Output Compare 15.4.4 Pulse Accumulator 15.4.5 Event Counter Mode
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15.4.6 Gated Time Accumulation Mode 15.5 Resets 15.6 Interrupts 15.6.1 Channel [7:2] Interrupt (C[7:2]F) 15.6.2 Pulse Accumulator Input Interrupt (PAOVI) 15.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) 15.6.4 Timer Overflow Interrupt (TOF)
Chapter Dual Output Voltage Regulator (VREG3V3V2) Block Description
16.1 Introduction 16.1.1 Features 16.1.2 Modes Operation 16.1.3 Block Diagram 16.2 External Signal Description 16.2.1 VDDR Regulator Power Input 16.2.2 VDDA, VSSA Regulator Reference Supply 16.2.3 VDD, Regulator Output1 (Core Logic) 16.2.4 VDDPLL, VSSPLL Regulator Output2 (PLL) 16.2.5 VREGEN Optional Regulator Enable 16.3 Memory Register Definition 16.3.1 Module Memory 16.3.2 Register Descriptions 16.4 Functional Description 16.4.1 Regulator Core 16.4.2 Full-Performance Mode 16.4.3 Reduced-Power Mode 16.4.4 Low-Voltage Detect 16.4.5 Power-On Reset 16.4.6 Low-Voltage Reset 16.4.7 CTRL Regulator Control 16.5 Resets 16.5.1 Power-On Reset 16.5.2 Low-Voltage Reset 16.6 Interrupts 16.6.1 Low-Voltage Interrupt
Chapter Kbyte Flash Module (S12FTS32KV1)
17.1 Introduction 17.1.1 Glossary 17.1.2 Features 17.1.3 Modes Operation
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17.1.4 Block Diagram 17.2 External Signal Description 17.3 Memory Registers 17.3.1 Module Memory 17.3.2 Register Descriptions 17.4 Functional Description 17.4.1 Flash Command Operations 17.4.2 Operating Modes 17.4.3 Flash Module Security 17.4.4 Flash Reset Sequence 17.4.5 Interrupts
Chapter Kbyte Flash Module (S12FTS64KV4)
18.1 Introduction 18.1.1 Glossary 18.1.2 Features 18.1.3 Modes Operation 18.1.4 Block Diagram 18.2 External Signal Description 18.3 Memory Registers 18.3.1 Module Memory 18.3.2 Register Descriptions 18.4 Functional Description 18.4.1 Flash Command Operations 18.4.2 Operating Modes 18.4.3 Flash Module Security 18.4.4 Flash Reset Sequence 18.4.5 Interrupts
Chapter Kbyte Flash Module (S12FTS96KV1)
19.1 Introduction 19.1.1 Glossary 19.1.2 Features 19.1.3 Modes Operation 19.1.4 Block Diagram 19.2 External Signal Description 19.3 Memory Registers 19.3.1 Module Memory 19.3.2 Register Descriptions 19.4 Functional Description 19.4.1 Flash Command Operations 19.4.2 Operating Modes
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19.4.3 Flash Module Security 19.4.4 Flash Reset Sequence 19.4.5 Interrupts
Chapter Kbyte Flash Module (S12FTS128K1V1)
20.1 Introduction 20.1.1 Glossary 20.1.2 Features 20.1.3 Modes Operation 20.1.4 Block Diagram 20.2 External Signal Description 20.3 Memory Registers 20.3.1 Module Memory 20.3.2 Register Descriptions 20.4 Functional Description 20.4.1 Flash Command Operations 20.4.2 Operating Modes 20.4.3 Flash Module Security 20.4.4 Flash Reset Sequence 20.4.5 Interrupts
Appendix Electrical Characteristics
General A.1.1 Parameter Classification A.1.2 Power Supply A.1.3 Pins A.1.4 Current Injection A.1.5 Absolute Maximum Ratings A.1.6 Protection Latch-up Immunity. A.1.7 Operating Conditions A.1.8 Power Dissipation Thermal Characteristics A.1.9 Characteristics A.1.10 Supply Currents Characteristics A.2.1 Operating Characteristics Range A.2.2 Operating Characteristics 3.3V Range A.2.3 Factors Influencing Accuracy A.2.4 Accuracy Range) A.2.5 Accuracy (3.3V Range) MSCAN. Reset, Oscillator A.4.1 Startup
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A.4.2 Oscillator. A.4.3 Phase Locked Loop. NVM, Flash, EEPROM A.5.1 Timing A.5.2 Reliability A.6.1 Master Mode A.6.2 Slave Mode Voltage Regulator A.7.1 Voltage Regulator Operating Conditions A.7.2 Chip Power-up LVI/LVR Graphical Explanation A.7.3 Output Loads.
Appendix Emulation Information
General B.1.1 PK[2:0] XADDR[16:14].
Appendix Package Information
General C.1.1 C.1.2 C.1.3 80-Pin Package 52-Pin LQFP Package. 48-Pin LQFP Package.
Appendix Derivative Differences Appendix Ordering Information
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Introduction
MC9S12Q128-Family 48/52/80 Flash-based family, which delivers power flexibility core whole range cost space sensitive, general purpose Industrial Automotive network applications MC9S12Q128-Familymembers feature standard on-chip peripherals including 16-bit central processing unit (CPU12), 128K bytes Flash EEPROM ROM), bytes RAM, asynchronous serial communications interface (SCI), serial peripheral interface (SPI), 6-channel 16-bit timermodule (TIM), 4-channel 8-bit pulse width modulator (PWM), 8-channel, 10-bit analog-to-digital converter (ADC). MC9S12Q128-Family devices feature full 16-bit data paths throughout. inclusion circuit allows power consumption performance adjusted suit operational requirements. addition ports available each module, dedicated port bits available with wake-up capability from stop wait mode. MC9S12Q128-Family devices available 48-, 52-, 80-pin packages, with 80-pin version compatible HCS12 Family derivatives.
1.1.1
Features
16-bit HCS12 core: HCS12 Upward compatible with M68HC11 instruction Interrupt stacking programmer's model identical M68HC11 Instruction queue Enhanced indexed addressing (memory interface) (interrupt control) (background debug mode) DBG12 (enhanced debug12 module, including breakpoints change-of-flow trace buffer) MEBI (multiplexed expansion interface) available only 80-pin package version Wake-up interrupt inputs: port bits available wake interrupt function with digital filtering
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Memory options: 32Kbyte Flash EEPROM (erasable 512-byte sectors) 64K, 96K, 128Kbyte Flash EEPROM (erasable 1024-byte sectors) Byte Analog-to-digital converters: 8-channel module with 10-bit resolution External conversion trigger capability second, software compatible module Five receive three transmit buffers Flexible identifier filter programmable bit, bit, Four separate interrupt channels error, wake-up Low-pass filter wake-up function Loop-back self test operation Timer module (TIM): 6-Channel timer Each channel configurable either input capture output compare Simple mode Modulo reset timer counter 16-bit pulse accumulator External event counting Gated time accumulation module: Programmable period duty cycle 8-bit 4-channel 16-bit 2-channel Separate control each pulse width duty cycle Center-aligned left-aligned outputs Programmable clock select logic with wide range frequencies Fast emergency shutdown input Serial interfaces: asynchronous serial communications interface (SCI) synchronous serial peripheral interface (SPI) (clock reset generator module) Windowed watchdog Real time interrupt Clock monitor Pierce current Colpitts oscillator Phase-locked loop clock frequency multiplier Limp home mode absence external clock power 0.5MHz 16MHz crystal oscillator reference clock :Operating frequency
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
16MHz equivalent 8MHz Speed single chip 16MHz equivalent 8MHz Speed expanded modes Option equivalent 16MHz Speed Internal 2.5V regulator: Supports input voltage range from 2.97V 5.5V power mode capability Includes voltage reset (LVR) circuitry Includes voltage interrupt (LVI) circuitry 48-pin LQFP, 52-pin LQFP, 80-pin package: lines with input drive capability (80-pin package) dedicated input only lines (IRQ, XIRQ) converter inputs Development support: Single-wire background debugmode (BDM) On-chip hardware breakpoints Enhanced DBG12 debug features
1.1.2
Modes Operation
User modes (expanded modes only available 80-pin package version). Normal emulation operating modes: Normal single-chip mode Normal expanded wide mode Normal expanded narrow mode Emulation expanded wide mode Emulation expanded narrow mode Special operating modes: Special single-chip mode with active background debug mode Special test mode (Freescale only) Special peripheral mode (Freescale only) power modes: Stop mode Pseudo stop mode Wait mode
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
1.1.3
Block Diagram
Figure 1-1. MC9S12Q128-Family Block Diagram
VSSR VDDR VDDX VSSX VDDA VSSA VDDA VSSA PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7
Voltage Regulator
DDRAD DDRT Keypad Interrupt DDRP DDRJ DDRS DDRM
VDD2 VSS2 VDD1 VSS1 BKGD VDDPLL VSSPLL EXTAL XTAL RESET TEST/VPP
32K, 64K, 96K, 128K Byte Flash/ROM Byte
Single-wire Background Debug12 Module
HCS12 Timer Module
Clock Reset Generation Module
Watchdog Clock Monitor Periodic Interrupt
IOC2 IOC3 IOC4 IOC5 IOC6 IOC7
XIRQ System Integration LSTRB/TAGLO Module ECLK (SIM) MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS
DDRE
Module
Module only available 128K Versions
Multiplexed Address/Data DDRA
DDRB MSCAN
RXCAN TXCAN MISO MOSI
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
Multiplexed Wide
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Signals shown Bold available Package Signals shown Bold Italic available Package
Internal Logic 2.5V
VDD1,2 VSS1,2
Driver
VDDX VSSX
2.5V
VDDPLL VSSPLL
Converter
VDDA VSSA
bonded internally VSSA packages
Voltage Regulator
VDDR VSSR
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P
PTAD
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
1.2.1
Memory Registers
Device Memory
Table shows device register after reset. Figure through Figure illustrate full device memory map.
Table 1-1. Device Register Overview
Address 0x0000-0x0017 0x0018 0x0019 0x001A-0x001B 0x001C-0x001F 0x0020-0x002F 0x0030-0x0033 0x0034-0x003F 0x0040-0x006F 0x0070-0x007F 0x0080-0x009F 0x00A0-0x00C7 0x00D0-0x00D7 0x00E0-0x00FF 0x0100-0x010F 0x0110-0x013F 0x0140-0x017F 0x0180-0x023F 0x0240-0x027F Reserved Voltage regulator (VREG) Device register Core (MEMSIZ, IRQ, HPRIO) Core (DBG) Core (PPAGE(1)) Clock reset generator (CRG) Standard timer module (TIM) Reserved Analog-to-digital converter (ATD) Reserved Reserved Pulse width modulator (PWM) Flash control register Reserved Scalable controller area network (MSCAN) Reserved Port integration module (PIM) Module Core (ports modes, inits, test) Size
0x00C8-0x00CF Serial communications interface (SCI) 0x00D8-0x00DF Serial peripheral interface (SPI)
0x0280-0x03FF Reserved External memory paging supported this device (Section 1.7.1, "PPAGE").
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$0000 $0000 $0400 $03FF $0000
Register Space Mappable Boundary Fixed Flash EEPROM/ROM
$3FFF $3000 $3000 $3FFF $4000 $4000 Bytes Mappable Boundary
Fixed Flash EEPROM/ROM
$7FFF $8000 $8000 Page Window Flash EEPROM/ROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM/ROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0000 $0FFF: (only visible $0400 $0FFF) Flash Erase Sector Size 1024 Bytes Figure 1-2. MCxS12Q128 User Configurable Memory
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
$0000 $0000 $0400 $03FF $0000
Register Space Mappable Boundary Fixed Flash EEPROM/ROM
$3FFF $3400 $3400 $3FFF $4000 $4000 Bytes Mappable Boundary
Fixed Flash EEPROM/ROM
$7FFF $8000 $8000 Page Window Flash EEPROM/ROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM/ROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0400 $0FFF: Flash Erase Sector Size 1024 Bytes Figure 1-3. MCxS12Q96 User Configurable Memory
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
$0000 $0000 $0400 $03FF $0000
Register Space Mappable Boundary Fixed Flash EEPROM/ROM
$3FFF $3800 $3800 $3FFF $4000 $4000 Bytes Mappable Boundary
Fixed Flash EEPROM/ROM
$7FFF $8000 $8000 Page Window Flash EEPROM/ROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM/ROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0800 $0FFF: Flash Erase Sector Size Bytes Figure 1-4. MCxS12Q64 User Configurable Memory
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
$0000 $0000 $0400 $03FF
Register Space Mappable Boundary
$3C00
$3C00 $3FFF
Bytes Mappable Boundary
$4000
$8000
$8000 Page Window Flash EEPROM/ROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM/ROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0C00 $0FFF: Flash Erase Sector Size Bytes Figure 1-5. MCxS12Q32 User Configurable Memory
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
1.2.2
Detailed Register
detailed register MC9S12Q128-Family listed address order below. 0x0000-0x000F
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
MEBI (HCS12 Multiplexed External Interface)
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: Write: Read: Write:
PIPOE MODA
NECLK
LSTRE IVIS
RDWE
MODB
PUPBE RDPB
PUPAE RDPA ESTR
PUPEE RDPE
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0010-0x0014
Address 0x0010 0x0011 0x0012 0x0013 0x0014 Name INITRM INITRG INITEE MISC Reserved
(HCS12 Module Mapping Control)
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: RAM15 RAM14 REG14 EE14 RAM13 REG13 EE13 RAM12 REG12 EE12 RAM11 REG11 EE11 EXSTR1 RAMHAL
EE15
EEON ROMON
EXSTR0
ROMHM
0x0015-0x0016
Address 0x0015 0x0016 Name ITCR ITEST
(HCS12 Interrupt)
Read: Write: Read: Write: WRINT INT8 ADR3 INT6 ADR2 INT4 ADR1 INT2 ADR0 INT0
INTE
INTC
INTA
0x0017-0x0017
Address 0x0017 Name Reserved
(HCS12 Module Mapping Control)
Read: Write:
0x0018-0x0018
Address 0x0018 Name Reserved
Miscellaneous Peripherals (Device User Guide)
Read: Write:
0x0019-0x0019
Address $0019 Name VREGCTRL
VREG3V3 (Voltage Regulator)
Read: Write: LVDS LVIE LVIF
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x001A-0x001B
Address Name
Miscellaneous Peripherals (Device User Guide)
0x001A 0x001B
PARTIDH PARTIDL
Read: Write: Read: Write:
ID15
ID14
ID13
ID12
ID11
ID10
0x001C-0x001D
Address 0x001C 0x001D Name MEMSIZ0 MEMSIZ1
(HCS12 Module Mapping Control, Device User Guide)
Read:
reg_sw0
rom_sw0
eep_sw1
eep_sw0
ram_sw2
ram_sw1 pag_sw1
ram_sw0 pag_sw0
Write: Read: rom_sw1 Write:
0x001E-0x001E
Address 0x001E Name INTCR
MEBI (HCS12 Multiplexed External Interface)
Read: Write:
IRQE
IRQEN
0x001F-0x001F
Address 0x001F Name HPRIO
(HCS12 Interrupt)
Read: Write: PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0x0020-0x002F
Address 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 Name DBGC1 DBGSC DBGTBH DBGTBL DBGCNT DBGCCX
(Including BKP) (HCS12 Debug)
TRGSEL BEGIN DBGBRK Read: DBGEN Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: PAGSEL Write:
CAPMOD
EXTCMP
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0020-0x002F
Address 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F Name DBGCCH DBGCCL DBGC2 BKPCT0 DBGC3 BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
(Including BKP) (HCS12 Debug) (continued)
BKCEN RWAEN TAGC RWCEN RWBEN Read: Write: Read: Write: Read: BKABEN FULL TAGAB Write: Read: BKAMBH BKAMBL BKBMBH BKBMBL Write: Read: PAGSEL Write: Read: Write: Read: Write: Read: PAGSEL Write: Read: Write: Read: Write:
EXTCMP EXTCMP
0x0030-0x0031
Address 0x0030 0x0031 Name PPAGE Reserved
(HCS12 Module Mapping Control)
Read: Write: Read: Write: PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
0x0032-0x0033
Address Name
MEBI (HCS12 Multiplexed External Interface)
Address $0032 $0033
Name Reserved Reserved Read: Write: Read: Write:
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0034-0x003F
Address 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP
(Clock Reset Generator)
Read: Write: Read: Write: Read: TOUT7 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: Write: Read: Write: Read: WCOP Write: Read: RTIBYP Write: Read: TCTL7 Write: Read: Write: TOUT6 SYN5 TOUT5 SYN4 TOUT4 SYN3 REFDV3 TOUT3 LOCK SYN2 REFDV2 TOUT2 TRACK SYN1 REFDV1 TOUT1 SYN0 REFDV0 TOUT0
PORF
LVRF
LOCKIF LOCKIE ROAWAI RTR4
SCMIF SCMIE RTIWAI RTR1 TCTL1
PSTP PLLON RTR6 RSBCK COPBYP TCTL6
SYSWAI AUTO RTR5 TCTL5
PLLWAI
CWAI RTR2 TCTL2
COPWAI SCME RTR0 TCTL0
RTR3 TCLT3
PLLBYP TCTL4
0x0040-0x006F
Address
0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046
Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1
Read: IOS7 Write: Read: Write: FOC7 Read: OC7M7 Write: Read: OC7D7 Write: Read: Write: Read: Write: Read: Write:
IOS6
FOC6
IOS5
FOC5
IOS4
FOC4
IOS3
FOC3
IOS2
FOC2
OC7M6 OC7D6
OC7M5 OC7D5
OC7M4 OC7D4
OC7M3 OC7D3
OC7M2 OC7D2
TSWAI
TSFRZ
TFFCA
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0040-0x006F
Address
0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B
Name TTOV TCTL1 TCTL2 TCTL3 TCTL4 TSCR2 TFLG1 TFLG2 Reserved Reserved Reserved Reserved (hi) (lo) (hi) (lo) (hi) (lo) (hi) (lo)
Read: TOV7 Write: Read: Write: Read: Write: Read: EDG7B Write: Read: EDG3B Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
TOV6 EDG7A EDG3A
TOV5 EDG6B EDG2B
TOV4 EDG6A EDG2A
TOV3
TOV2
EDG5B
EDG5A
EDG4B
EDG4A
TCRE
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0040-0x006F
Address
0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F
Name (hi) (lo) (hi) (lo) PACTL PAFLG PACNT (hi) PACNT (lo) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAOVF
PAIF
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0070-0x007F
Address 0x0070- 0x007F Name Reserved
Reserved
Read: Write:
0x0080-0x009F
Address 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x0090 0x0091 0x0092 Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 Reserved ATDSTAT1 Reserved ATDDIEN Reserved PORTAD ATDDR0H ATDDR0L ATDDR1H
(Analog-to-Digital Converter Channel)
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ASCIF
ADPU
AFFC SMP1 DSGN CCF6
AWAI SMP0 SCAN ETORF CCF5
ETRIGLE PRS4 MULT FIFOR CCF4
ETRIGP PRS3 CCF3
ETRIG FIFO PRS2 CCF2
ASCIE FRZ1 PRS1 CCF1
FRZ0 PRS0
SRES8 CCF7
CCF0
Bit7 Bit15 Bit7 Bit15
Bit6
Bit8 Bit8
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0080-0x009F
Address 0x0093 0x0094 0x0095 0x0096 0x0097 0x0098 0x0099 0x009A 0x009B 0x009C 0x009D 0x009E 0x009F Name ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L
(Analog-to-Digital Converter Channel) (continued)
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8
0x00A0-0x00C7
Address Name
Reserved
0x00A0- 0x00C7
Reserved
Read: Write:
0x00C8-0x00CF
Address 0x00C8 0x00C9 0x00CA 0x00CB Name SCIBDH SCIBDL SCICR1 SCICR2
(Asynchronous Serial Interface)
Read: Write: Read: Write: Read: Write: Read: Write: SBR12 SBR4 ILIE SBR11 SBR3 WAKE SBR10 SBR2 SBR9 SBR1 SBR8 SBR0
SBR7 LOOPS
SBR6 SCISWAI TCIE
SBR5 RSRC
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x00C8-0x00CF
Address 0x00CC 0x00CD 0x00CE 0x00CF Name SCISR1 SCISR2 SCIDRH SCIDRL
(Asynchronous Serial Interface) (continued)
Read: Write: Read: Write: Read: Write: Read: Write: TDRE RDRF IDLE
BRK13
TXDIR
0x00D0-0x00D7
Address 0x00D0- 0x00D7 Name Reserved
Reserved
Read: Write:
0x00D8-0x00DF
Address 0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE 0x00DF Name SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved Reserved
(Serial Peripheral Interface)
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: SPIE SPIF SPTIE MSTR CPOL CPHA SSOE SPISWAI SPR1 LSBFE SPC0 SPR0
MODFEN BIDIROE SPPR0 MODF
SPPR2
SPPR1 SPTEF
SPR2
Bit7
Bit0
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MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x00E0-0x00FF
Address
0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x00E7 0x00E8 0x00E9 0x00EA 0x00EB 0x00EC 0x00ED 0x00EE 0x00EF 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4
Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA PWMSCLB PWMSCNTA PWMSCNTB PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 Reserved Reserved PWMPER0 PWMPER1 PWMPER2 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PWME3 PPOL3 PCLK3
PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ
PWME1 PPOL1 PCLK1 PCKA1 CAE1
PWME0 PPOL0 PCLK0 PCKA0 CAE0
PCKB2
PCKB1
PCKB0
CAE3 CON23 CON01 PSWAI
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x00E0-0x00FF
Address
0x00E5 0x00E6 0x00E7 0x00E8 0x00E9 0x00EA 0x00EB 0x00EC 0x00ED
Name PWMPER3 Reserved Reserved PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
0x00EE
PWMIF
PWMIE
PWMRSTR PWMLVL
PWM5IN PWM5INL PWM5ENA
0x00EF
0x0100-0x010F
Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 Name FCLKDIV FSEC FTSTMOD FCNFG FPROT FSTAT FCMD Reserved Factory Test
Flash Control Register
Read: FDIVLD Write: Read: KEYEN1 Write: Read: Write: Read: CBEIE Write: Read: FPOPEN Write: Read: CBEIF Write: Read: Write: Read: Write: PRDIV8 KEYEN0 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 SEC1 FDIV0 SEC0
CCIE CCIF
KEYACC FPHDIS PVIOL CMDB5
WRALL
FPHS1 ACCERR
FPHS0
FPLDIS BLANK CMDB2
FPLS1
FPLS0
CMDB6
CMDB0
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0100-0x010F
Address 0x0108 0x0109 0x010A 0x010B 0x010C 0x010D 0x010E 0x010F Name Reserved Factory Test Reserved Factory Test Reserved Factory Test Reserved Factory Test Reserved Reserved Reserved Reserved
Flash Control Register (continued)
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
0x0110-0x013F
Address 0x0110- 0x003F Name Reserved
Reserved
Read: Write:
0x0140-0x017F
Address 0x0140 0x0141 0x0142 0x0143 0x0144 0x0145 0x0146 0x0147 Name CANCTL0 CANCTL1 CANBTR0 CANBTR1 CANRFLG CANRIER CANTFLG CANTIER
(Scalable Controller Area Network MSCAN)
Read: RXFRM Write: Read: CANE Write: Read: SJW1 Write: Read: SAMP Write: Read: WUPIF Write: Read: WUPIE Write: Read: Write: Read: Write: RXACT CSWAI LOOPB BRP5 TSEG21 RSTAT1 SYNCH TIME WUPE WUPM BRP2 TSEG12 TSTAT0 SLPRQ SLPAK INITRQ INITAK
CLKSRC SJW0 TSEG22 CSCIF CSCIE
LISTEN BRP4 TSEG20 RSTAT0
BRP3 TSEG13 TSTAT1
BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1
BRP0 TSEG10 RXFIE TXE0 TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 TXE2 TXEIE2
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0140-0x017F
Address 0x0148 0x0149 0x014A 0x014B 0x014C 0x014D 0x014E 0x014F 0x0150- 0x0153 0x0154- 0x0157 0x0158- 0x015B 0x015C- 0x015F 0x0160- 0x016F 0x0170- 0x017F Name CANTARQ CANTAAK CANTBSEL CANIDAC Reserved Reserved CANRXERR CANTXERR CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 CANIDAR4 CANIDAR7 CANIDMR4 CANIDMR7 CANRXFG CANTXFG
(Scalable Controller Area Network MSCAN) (continued)
Read: ABTRQ2 ABTRQ1 ABTRQ0 Write: Read: ABTAK2 ABTAK1 ABTAK0 Write: Read: Write: Read: IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 Write: Read: Write: Read: Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: FOREGROUND RECEIVE BUFFER Table Write: Read: FOREGROUND TRANSMIT BUFFER Table Write:
Table 1-2. Detailed MSCAN Foreground Receive Transmit Buffer Layout
Address 0xXXX0 Name Extended Standard CANxRIDR0 Extended Standard CANxRIDR1 Extended Standard CANxRIDR2 Extended Standard CANxRIDR3 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: ID28 ID10 ID20 ID14 ID27 ID19 ID13 ID26 ID18 ID12 ID25 SRR=1 ID11 ID24 IDE=1 IDE=0 ID10 ID23 ID17 ID22 ID16 ID21 ID15
0xXXX1
0xXXX2
0xXXX3
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MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Table 1-2. Detailed MSCAN Foreground Receive Transmit Buffer Layout (continued)
Address Name DLC3 DLC2 DLC1 DLC0
0xXXX4- CANxRDSR0- Read: 0xXXXB CANxRDSR7 Write: Read: 0xXXXC CANRxDLR Write: Read: 0xXXXD Reserved Write: Read: 0xXXXE CANxRTSRH Write: Read: 0xXXXF CANxRTSRL Write: Extended Read: CANxTIDR0 Write: 0xxx10 Read: Standard Write: Extended Read: CANxTIDR1 Write: 0xxx11 Read: Standard Write: Extended Read: CANxTIDR2 Write: 0xxx12 Read: Standard Write: Extended Read: CANxTIDR3 Write: 0xxx13 Read: Standard Write: 0xxx14- CANxTDSR0- Read: 0xxx1B CANxTDSR7 Write: Read: 0xxx1C CANxTDLR Write: Read: 0xxx1D CONxTTBPR Write: Read: 0xxx1E CANxTTSRH Write: Read: 0xxx1F CANxTTSRL Write:
TSR15 TSR7
TSR14 TSR6
TSR13 TSR5
TSR12 TSR4
TSR11 TSR3
TSR10 TSR2
TSR9 TSR1
TSR8 TSR0
ID28 ID10 ID20 ID14
ID27 ID19 ID13
ID26 ID18 ID12
ID25 SRR=1 ID11
ID24 IDE=1 IDE=0 ID10
ID23 ID17
ID22 ID16
ID21 ID15
DLC3
DLC2 PRIO2 TSR10 TSR2
DLC1 PRIO1 TSR9 TSR1
DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
0x0180-0x023F
Address 0x0180- 0x023F Name Reserved
Reserved
Read: Write:
MC9S12Q128 1.09
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0240-0x027F
Address 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 0x0247 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 Name PTIT DDRT RDRT PERT PPST Reserved MODRR PTIS DDRS RDRS PERS PPSS WOMS Reserved PPTIM DDRM RDRM PERM PPSM
(Port Interface Module) (Sheet
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: PTT7 PTIT7 PTT6 PTIT6 PTT5 PTIT5 PTT4 PTIT4 PTT3 PTIT3 PTT2 PTIT2 PTT1 PTIT1 PTT0 PTIT0
DDRT7 RDRT7 PERT7 PPST7
DDRT7 RDRT6 PERT6 PPST6
DDRT5 RDRT5 PERT5 PPST5
DDRT4 RDRT4 PERT4 PPST4
DDRT3 RDRT3 PERT3 PPST3
DDRT2 RDRT2 PERT2 PPST2
DDRT1 RDRT1 PERT1 PPST1
DDRT0 RDRT0 PERT0 PPST0
MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTS3 PTIS3 PTS2 PTIS2 PTS1 PTIS1 PTS0 PTIS0
DDRS3 RDRS3 PERS3 PPSS3 WOMS3
DDRS2 RDRS2 PERS2 PPSS2 WOMS2
DDRS1 RDRS1 PERS1 PPSS1 WOMS1
DDRS0 RDRS0 PERS0 PPSS0 WOMS0
PTM5 PTIM5
PTM4 PTIM4
PTM3 PTIM3
PTM2 PTIM2
PTM1 PTIM1
PTM0 PTIM0
DDRM5 RDRM5 PERM5 PPSM5
DDRM4 RDRM4 PERM4 PPSM4
DDRM3 RDRM3 PERM3 PPSM3
DDRM2 RDRM2 PERM2 PPSM2
DDRM1 RDRM1 PERM1 PPSM1
DDRM0 RDRM0 PERM0 PPSM0
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0240-0x027F
Address 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 0x0266 0x0267 0x0268 0x0269 0x026A 0x026B 0x026C Name WOMM Reserved PTIP DDRP RDRP PERP PPSP PIEP PIFP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PTIJ DDRJ RDRJ PERJ
(Port Interface Module) (Sheet
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
PTP7 PTIP7
PTP6 PTIP6
PTP5 PTIP5
PTP4 PTIP4
PTP3 PTIP3
PTP2 PTIP2
PTP1 PTIP1
PTP0 PTIP0
DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7
DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6
DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5
DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4
DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3
DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2
DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1
DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0
PTJ7 PTIJ7
PTJ6 PTIJ6
DDRJ7 RDRJ7 PERJ7
DDRJ7 RDRJ6 PERJ6
MC9S12Q128 1.09
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
0x0240-0x027F
Address 0x026D 0x026E 0x026F 0x0270 0x0271 0x0272 0x0273 0x0274 0x0275 0x02760x027F Name PPSJ PIEJ PIFJ PTAD PTIAD DDRAD RDRAD PERAD PPSAD Reserved
(Port Interface Module) (Sheet
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: PPSJ7 PIEJ7 PIFJ7 PTAD7 PTIAD7 PPSJ6 PIEJ6 PIFJ6 PTAD6 PTIAD6
PTAD5 PTIAD5
PTAD4 PTIAD4
PTAD3 PTIAD3
PTAD2 PTIAD2
PTAD1 PTIAD1
PTAD0 PTIJ7
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 PERAD7 PPSAD7 PERAD6 PPSAD6 PERAD5 PPSAD5 PERAD4 PPSAD4 PERAD3 PPSAD3 PERAD2 PPSAD2 PERAD1 PPSAD1 PERAD0 PPSAD0
0x0280-0x03FF
Address 0x0280- 0x2FF Name Reserved
Reserved Space
Read: Write: Read: 0x0300 Unimplemented -0x03FF Write:
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
1.2.3
Part Assignments
part located 8-bit registers PARTIDH PARTIDL (addresses 0x001A ox001B after reset). read-only value unique part each revision chip. Table shows assigned part numbers production mask sets.
Table 1-3. Assigned Part Numbers
MC9S12Q32 MC9S12Q32 MC9S12Q64, MC9S12Q96, MC9S12Q128 MC9S12Q64, MC9S12Q96, MC9S12Q128 MC3S12Q32 MC3S12Q32 MC3S12Q64, MC3S12Q96, MC3S12Q128 MC3S12Q64, MC3S12Q96, MC3S12Q128 2L45J 1M34C 2L09S 0M66G 2L45J 1M34C 2L09S 0M66G $3302 $3311 $3102 $3103 $3302 $3311 $3102 $3103
device memory sizes located 8-bit registers MEMSIZ0 MEMSIZ1 (addresses 0x001C 0x001D after reset). Table shows read-only values these registers. Refer Module Mapping Control (MMC) Block Guide further details.
Table 1-4. Memory Size Registers
Device MC9S12Q32 MC9S12Q64 MC9S12Q96 MC9S12Q128 Register Name MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 Value
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
1.3.1
Signal Description
Device Pinouts
Figure 1-6. Assignments 80-Pin
PP4/KWP4 PP5/KWP5 PP7/KWP7 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 PP6/KWP6/ROMCTL PS1/TXD PS0/RXD VSSA PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0 PW0/PT0 PW1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
MC9S12Q128-Family
VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown Bold available Package Signals shown Bold Italic available Package
MODRR register within allows mapping channels Port absence Port pins count packages. 80QFP package option recommended MODRR since this intended support channel availability count packages. Note that when mapping channels Port 80QFP option, associated channels then mapped both Port Port
Freescale Semiconductor
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL VSSPLL EXTAL XTAL TEST/VPP LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
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PM0/RXCAN
PM1/TXCAN
PP4/KWP4
PP5/KWP5
PM2/MISO
PM4/MOSI
PM5/SCK
PM3/SS
VDDX
VSSX
PS0/RXD VSSA
PS1/TXD
PW3/KWP3/PP3 PW0/PT0 PW1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD
VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00
MC9S12Q128-Family
EXTAL
XCLKS/PE7
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
VSSPLL
XTAL
Signals shown Bold italic available Package Figure 1-7. Assignments 52-Pin LQFP
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TEST/VPP IRQ/PE1 XIRQ/PE0
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PM0/RXCAN
PM1/TXCAN
PP5/KWP5
PM4/MOSI
PM2/MISO
PM5/SCK
PW0/PT0 PW1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD
PS0/RXD VSSA
PS1/TXD
PM3/SS
VDDX
VSSX
VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 XIRQ/PE0
MC9S12Q128-Family
XTAL
XCLKS/PE7
ECLK/PE4
RESET
VDDPLL
VSSPLL
EXTAL
Figure 1-8. Assignments 48-Pin LQFP
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VSSR
VDDR
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
1.3.2
Signal Properties Summary
Table 1-5. Signal Properties
Internal Pull Resistor Description CTRL Reset State None External reset loop filter Test only Background debug, mode pin, signal high Port pin, access, clock select Port pipe status Port pipe status Port pin, clock output Port pin, strobe, signal Port pin, expanded modes Port input, external interrupt Port input, non-maskable interrupt Port multiplexed address/data Port multiplexed address/data Port multiplexed address/data Port multiplexed address/data Port multiplexed address/data Port multiplexed address/data Oscillator pins
Name Function EXTAL XTAL RESET TEST BKGD PA[7:3] PA[2:1] PA[0] PB[7:5] PB[4] PB[3:0] PAD[7:0] PP[7] PP[6] PP[5] PP[4:3]
Name Function MODC NOACC IPIPE1 IPIPE0 ECLK LSTRB XIRQ ADDR[15:1/ DATA[15:1] ADDR[10:9/ DATA[10:9] ADDR[8]/ DATA[8] ADDR[7:5]/ DATA[7:5] ADDR[4]/ DATA[4] ADDR[3:0]/ DATA[3:0] AN[7:0] KWP[7] KWP[6] KWP[5] KWP[4:3]
Name Function TAGHI XCLKS MODB MODA TAGLO ROMCTL PW[3]
Power Domain VDDPLL VDDPLL VDDX VDDPLL VSSX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDA VDDX VDDX VDDX VDDX
None PUCR
While RESET low: Down While RESET low: Down PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR Mode Dep(1) Mode Dep1 Mode Dep1 Disabled Disabled Disabled Disabled Disabled Disabled
PERAD/P Port pins inputs Disabled PSAD PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP Disabled Disabled Disabled Disabled Port pins keypad wake-up Port pins, keypad wake-up, ROMON enable. Port pin, keypad wake-up, output Port pin, keypad wake-up, output
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Table 1-5. Signal Properties (continued)
Internal Pull Resistor Description CTRL PP[2:0] PJ[7:6] PS[3:2] PT[7:5] PT[4:0] KWP[2:0] KWJ[7:6] MOSI MISO TXCAN RXCAN IOC[7:5] IOC[4:2] PW[2:0] PW[3:0] VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX PERP/ PPSP PERJ/ PPSJ PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST Reset State Disabled Disabled Disabled Port pins, keypad wake-up, outputs Port pins keypad wake-up Port signal Port MOSI signal Port signal Port MISO signal Port transmit signal Port receive signal Port pins Port transmit signal Port receive signal Port pins shared with timer (TIM)
Name Function
Name Function
Name Function
Power Domain
PERT/ Port pins shared with timer Disabled PPST Port output buffer enable signal control reset determined PEAR register mode dependent. example, special test mode RDWE LSTRE which enables PE[3:2] output buffers disables pull-ups. Refer S12_MEBI user guide PEAR register details.
1.3.3
Initialization 52-Pin LQFP Bond Versions
Bonded Pins: port pins bonded chosen package user should initialize registers inputs with enabled pull resistance avoid excess current consumption. This applies following pins: (48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2] (52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2]
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1.3.4
1.3.4.1
Detailed Signal Descriptions
EXTAL, XTAL Oscillator Pins
EXTAL XTAL crystal driver external clock pins. reset device clocks derived from EXTAL input frequency. XTAL crystal output.
1.3.4.2
RESET External Reset
RESET active bidirectional control signal that acts input initialize known start-up state. also acts open-drain output indicate that internal failure been detected either clock monitor watchdog circuit. External circuitry connected RESET should include large capacitance that would interfere with ability this signal rise valid logic within ECLK cycles after drive released. Upon detection reset, internal circuit drives RESET clocked reset sequence controls when begin normal processing.
1.3.4.3
TEST Test
This reserved test must tied applications.
1.3.4.4
Loop Filter
Dedicated used create loop filter. more detailed information.PLL loop filter. Please your Motorola representative interactive application note compute loop filter elements. current leakage this must avoided.
VDDPLL VDDPLL
Figure 1-9. Loop Filter Connections
1.3.4.5
BKGD TAGHI MODC Background Debug, High, Mode
BKGD TAGHI MODC used pseudo-open-drain background debug communication. expanded modes operation when instruction tagging input this during falling edge E-clock tags high half instruction word being read into instruction queue. also used operating mode select rising edge during reset, when state this latched MODC bit.
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1.3.4.6
PA[7:0] ADDR[15:8] DATA[15:8] Port Pins
PA7-PA0 general purpose input output pins,. expanded modes operation, these pins used multiplexed external address data bus. PA[7:1] pins available 48-pin package version. PA[7:3] available 52-pin package version.
1.3.4.7
PB[7:0] ADDR[7:0] DATA[7:0] Port Pins
PB7-PB0 general purpose input output pins. expanded modes operation, these pins used multiplexed external address data bus. PB[7:5] PB[3:0] pins available 48-pin 52-pin package version.
1.3.4.8
NOACC XCLKS Port
general purpose input output pin. During expanded modes operation, NOACC signal, when enabled, used indicate that current cycle unused "free" cycle. This signal will assert when using bus.The XCLKS input signal which controls whether crystal combination with internal Colpitts (low power) oscillator used whether Pierce oscillator/external clock circuitry used. state this latched rising edge RESET. input logic EXTAL configured external clock drive Pierce oscillator. input logic high Colpitts oscillator circuit configured EXTAL XTAL. Since this input with pull-up device during reset, left floating, default configuration Colpitts oscillator circuit EXTAL XTAL.
EXTAL CDC1 Crystal Ceramic Resonator
XTAL VSSPLL nature translated ground Colpitts oscillator voltage bias applied crystal. Please contact crystal manufacturer crystal
Figure 1-10. Colpitts Oscillator Connections (PE7
EXTAL XTAL VSSPLL zero (shorted) when used with higher frequency crystals, refer manufacturer's data. Crystal Ceramic Resonator
Figure 1-11. Pierce Oscillator Connections (PE7
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EXTAL
CMOS Compatible External Oscillator (VDDPLL Level)
XTAL
Connected
Figure 1-12. External Clock Connections (PE7
1.3.4.9
MODB IPIPE1 Port
general purpose input output pin. used operating mode select during reset. state this latched MODB rising edge RESET. This shared with instruction queue tracking signal IPIPE1. This input with pull-down device which only active when RESET low. PE[6] available 52-pin package versions.
1.3.4.10
MODA IPIPE0 Port
general purpose input output pin. used operating mode select during reset. state this latched MODA rising edge RESET. This shared with instruction queue tracking signal IPIPE0. This input with pull-down device which only active when RESET low. This available 52-pin package versions.
1.3.4.11
ECLK- Port E-Clock Output
ECLK output connection internal clock. used demultiplex address data expanded modes used timing reference. ECLK frequency equal crystal frequency reset. ECLK initially configured ECLK output with stretch expanded modes. clock output function depends upon settings NECLK PEAR register, IVIS MODE register ESTR EBICTL register. clocks, including clock, halted when stop mode. possible configure interface slow external memory. ECLK stretched such accesses. Reference MISC register (EXSTR[1:0] bits) more information. normal expanded narrow mode, clock available external select decode logic constant speed clock external application system. Alternatively used general purpose input output pin.
1.3.4.12
LSTRB Port Low-Byte Strobe (LSTRB)
modes this used general-purpose input with active pull-up reset. strobe function required, should enabled setting LSTRE PEAR register. This signal used write operations. Therefore external byte writes will possible until this function enabled. This also used TAGLO special expanded modes multiplexed with LSTRB function. This available 52-pin package versions.
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1.3.4.13
Port Read/Write
modes this used general-purpose input with active pull-up reset. read/write function required should enabled setting RDWE PEAR register. External writes will possible until enabled. This available 52-pin package versions.
1.3.4.14
Port Input Maskable Interrupt
input provides means applying asynchronous interrupt requests MCU. Either falling edge-sensitive triggering level-sensitive triggering program selectable (INTCR register). always enabled configured level-sensitive triggering reset. disabled clearing IRQEN (INTCR register). When reset function masked condition code register. This always input always read. There active pull-up this while reset immediately reset. pull-up turned clearing PUPEE PUCR register.
1.3.4.15
XIRQ Port input Maskable Interrupt
XIRQ input provides means requesting non-maskable interrupt after reset initialization. During reset, condition code register (CCR) interrupt masked until software enables Because XIRQ input level sensitive, connected multiple-source wired-OR network. This always input always read. There active pull-up this while reset immediately reset. pull-up turned clearing PUPEE PUCR register.
1.3.4.16
PAD[7:0] AN[7:0] Port Pins [7:0]
PAD7-PAD0 general purpose pins also analog inputs analog digital converter. order standard input, corresponding ATDDIEN register must set. These bits cleared reset configure pins operation. When converter active multi-channel mode, port inputs scanned converted irrespective Port configuration. Thus Port pins that configured digital inputs digital outputs also converted conversion sequence.
1.3.4.17
PP[7] KWP[7] Port
general purpose input output pin, shared with keypad interrupt function. When configured input, generate interrupts causing exit stop wait mode. This available 52-pin package versions.
1.3.4.18
PP[6] KWP[6]/ROMCTL Port
general purpose input output pin, shared with keypad interrupt function. When configured input, generate interrupts causing exit stop wait mode. This available 52-pin package versions. During expanded modes operation, this used enable
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Flash EEPROM memory memory (ROMCTL). rising edge RESET, state this latched ROMON bit. emulation modes equates ROMON (ROM space externally mapped) expanded modes equates ROMON (ROM space externally mapped)
1.3.4.19
PP[5:0] KWP[5:0] PW[3:0] Port Pins [5:0]
PP[5:0] general purpose input output pins, shared with keypad interrupt function. When configured inputs, they generate interrupts causing exit stop wait mode. PP[3:0] also shared with output signals, PW[3:0].Pins PP[2:0] only available 80pin package version. Pins PP[4:3] available 48-pin package version.
1.3.4.20
PJ[7:6] KWJ[7:6] Port Pins [7:6]
PJ[7:6] general purpose input output pins, shared with keypad interrupt function. When configured inputs, they generate interrupts causing exit stop wait mode. These pins available 48-pin package version 52-pin package version.
1.3.4.21
Port
general purpose input output also serial clock serial peripheral interface (SPI).
1.3.4.22
MOSI Port
general purpose input output also master output (during master mode) slave input (during slave mode) serial peripheral interface (SPI).
1.3.4.23
Port
general purpose input output also slave select serial peripheral interface (SPI).
1.3.4.24
MISO Port
general purpose input output also master input (during master mode) slave output (during slave mode) serial peripheral interface (SPI).
1.3.4.25
TXCAN Port
general purpose input output transmit pin, TXCAN, module available.
1.3.4.26
RXCAN Port
general purpose input output receive pin, RXCAN, module available.
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1.3.4.27
PS[3:2] Port Pins [3:2]
general purpose input output pins. These pins available 52-pin package versions.
1.3.4.28
Port
general purpose input output transmit pin, TXD, serial communication interface (SCI).
1.3.4.29
Port
general purpose input output receive pin, RXD, serial communication interface (SCI).
1.3.4.30
PT[7:5] IOC[7:5] Port Pins [7:5]
PT7-PT5 general purpose input output pins. They also configured timer system input capture output compare pins IOC7-IOC5.
1.3.4.31
PT[4:0] IOC[4:2] PW[3:0]- Port Pins [4:0]
PT4-PT0 general purpose input output pins. They also configured timer system input capture output compare pins IOC[n] outputs PW[n].
1.3.5
1.3.5.1
Power Supply Pins
VDDX,VSSX Power Ground Pins Drivers
External power ground drivers. Bypass requirements depend heavily pins loaded.
1.3.5.2
VDDR, VSSR Power Ground Pins Drivers Internal Voltage Regulator
External power ground internal voltage regulator. Connecting VDDR ground disables internal voltage regulator.
1.3.5.3
VDD1, VDD2, VSS1, VSS2 Internal Logic Power Pins
Power supplied through VSS. This 2.5V supply derived from internal voltage regulator. There static load those pins allowed. internal voltage regulator turned off, VDDR tied ground.
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1.3.5.4
VDDA, VSSA Power Supply Pins VREG
VDDA, VSSA power supply ground input pins voltage regulator reference analog digital converter.
1.3.5.5
VRH, Reference Voltage Input Pins
reference voltage input pins analog digital converter.
1.3.5.6
VDDPLL, VSSPLL Power Supply Pins
Provides operating voltage ground oscillator phased-locked loop. This allows supply voltage oscillator bypassed independently. This 2.5V voltage generated internal voltage regulator.
Table 1-6. Power Ground Connection Summary
Mnemonic VDD1, VDD2 VSS1, VSS2 VDDR VSSR VDDX VSSX VDDA VSSA VDDPLL VSSPLL Nominal Voltage Operating voltage ground analog-to-digital converters reference internal voltage regulator, allows supply voltage bypassed independently. Reference voltage converter. LQFP packages bonded VSSA. Provides operating voltage ground phased-locked loop. This allows supply voltage bypassed independently. Internal power ground generated internal regulator. External power ground, supply drivers. Description Internal power ground generated internal regulator. These also allow external source supply core VDD/VSS voltages bypass internal voltage regulator. LQFP packages VDD2 VSS2 available. External power ground, supply internal voltage regulator.
NOTE pins must connected together application. Because fast signal transitions place high, short-duration current demands power supply, bypass capacitors with high-frequency characteristics place them close possible. Bypass requirements depend load.
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System Clock Description
clock reset generator provides internal clock signals core peripheral modules. Figure 1-13 shows clock connections from modules. Consult Block User Guide details clock generation.
S12_CORE Core Clock
Flash EXTAL Clock Oscillator Clock XTAL VREG MSCAN 9S12GC
Figure 1-13. Clock Connections
Modes Operation
Eight possible modes determine device operating configuration. Each mode associated default memory external configuration controlled further pin. Three power modes exist device.
1.5.1
Chip Configuration Summary
operating mode reset determined states MODC, MODB, MODA pins during reset. MODC, MODB, MODA bits MODE register show current operating mode provide limited mode switching during operation. states MODC, MODB, MODA pins latched into these bits rising edge reset signal. ROMCTL signal allows setting ROMON MISC register thus controlling whether internal Flash visible memory map. ROMON mean Flash visible memory map. state ROMCTL latched into ROMON MISC register rising edge reset signal.
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Table 1-7. Mode Selection
BKGD MODC MODB MODA ROMCTL ROMON Peripheral; allowed operations would cause conflicts (must used) Normal Expanded Wide, allowed Normal Single Chip, allowed Normal Expanded Narrow, allowed Special Test (Expanded Wide), allowed Emulation Expanded Wide, allowed Mode Description Special Single Chip, allowed ACTIVE. allowed other modes serial command required make active. Emulation Expanded Narrow, allowed
further explanation modes refer S12_MEBI block guide.
Table 1-8. Clock Selection Based
XCLKS Description Colpitts Oscillator selected Pierce Oscillator/external clock selected
1.5.2
Security
device will make available security feature preventing unauthorized read write memory contents. This feature allows: Protection contents FLASH, Operation single-chip mode, Operation from external memory with internal FLASH disabled. user must reminded that part security must with user's code. extreme example would user's code that dumps contents internal program. This code would defeat purpose security. same time user also wish back door user's program. example this user downloads through which allows access programming routine that updates parameters.
1.5.2.1
Securing Microcontroller
Once user programmed FLASH, part secured programming security bits located FLASH module. These non-volatile bits will keep part secured through resetting part through powering down part.
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security byte resides portion Flash array. Check Flash Block User Guide more details security configuration.
1.5.2.2
1.5.2.2.1
Operation Secured Microcontroller
Normal Single Chip Mode
This will most common usage secured part. Everything will appear same part secured with exception operation. operation will blocked. 1.5.2.2.2 Executing from External Memory
user wish execute from external space with secured microcontroller. This accomplished resetting directly into expanded mode. internal FLASH will disabled. operations will blocked.
1.5.2.3
Unsecuring Microcontroller
order unsecure microcontroller, internal FLASH must erased. This done through external program expanded mode sequence commands. Unsecuring also possible Backdoor Access. Refer Flash Block Guide details. Once user erased FLASH, part reset into special single chip mode. This invokes program that verifies erasure internal FLASH. Once this program completes, user erase program FLASH security bits unsecured state. This generally done through BDM, user could also change expanded mode writing mode bits through BDM) jumping external program (again through commands). Note that part goes through reset before security bits reprogrammed unsecure state, part will secured again.
1.5.3
Low-Power Modes
microcontroller features three main power modes. Consult respective Block User Guide information module behavior stop, pseudo stop, wait mode. important source information about clock system Clock Reset Generator User Guide (CRG).
1.5.3.1
Stop
Executing STOP instruction stops clocks oscillator thus putting chip fully static mode. Wake from this mode done reset external interrupts.
1.5.3.2
Pseudo Stop
This mode entered executing STOP instruction. this mode oscillator still running real time interrupt (RTI) watchdog (COP) module stay active. Other peripherals turned off. This mode consumes more current than full stop mode, wake time from this mode significantly shorter.
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1.5.3.3
Wait
This mode entered executing instruction. this mode will execute instructions. internal signals (address data bus) will fully static. peripherals stay active. further power consumption reduction peripherals individually turn their local clocks.
1.5.3.4
Although this low-power mode, unused peripheral modules should enabled order save power.
Resets Interrupts
Consult Exception Processing section CPU12 Reference Manual information.
1.6.1
Vectors
Table 1-9. Interrupt Vector Locations
Table lists interrupt sources vectors default order priority.
Vector Address
Interrupt Source External reset, power reset, voltage reset (see flags register determine reset source) Clock monitor fail reset failure reset Unimplemented instruction trap XIRQ Real time Interrupt
Mask
Local Enable
HPRIO Value Elevate
0xFFFE, 0xFFFF
None
None
0xFFFC, 0xFFFD 0xFFFA, 0xFFFB 0xFFF8, 0xFFF9 0xFFF6, 0xFFF7 0xFFF4, 0xFFF5 0xFFF2, 0xFFF3 0xFFF0, 0xFFF1 $FFEE, $FFEF $FFEC, $FFED 0xFFEA, 0xFFEB 0xFFE8, 0xFFE9 0xFFE6, 0xFFE7 0xFFE4, 0xFFE5 0xFFE2, 0xFFE3 0xFFE0, 0xFFE1 0xFFDE, 0xFFDF 0xFFDC, 0xFFDD
None None None None X-Bit Reserved Reserved
COPCTL (CME, FCME) rate select None None None INTCR (IRQEN) CRGINT (RTIE)
0x00F2 0x00F0
Standard timer channel Standard timer channel Standard timer channel Standard timer channel Standard timer channel Standard timer channel Standard timer overflow Pulse accumulator overflow
(C2I) (C3I) (C4I) (C5I) (C6I) (C7I) TMSK2 (TOI) PACTL (PAOVI)
0x00EA 0x00E8 0x00E6 0x00E4 0x00E2 0x00E0 0x00DE 0x00DC
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Table 1-9. Interrupt Vector Locations (continued)
Vector Address 0xFFDA, 0xFFDB 0xFFD8, 0xFFD9 0xFFD6, 0xFFD7 0xFFD4, 0xFFD5 0xFFD2, 0xFFD3 0xFFD0, 0xFFD1 0xFFCE, 0xFFCF 0xFFCC, 0xFFCD 0xFFCA, 0xFFCB 0xFFC8, 0xFFC9 0xFFC6, 0xFFC7 0xFFC4, 0xFFC5 0xFFBA 0xFFC3 0xFFB8, 0xFFB9 0xFFB6, 0xFFB7 0xFFB4, 0xFFB5 0xFFB2, 0xFFB3 0xFFB0, 0xFFB1 0xFF90 0xFFAF 0xFF8E, 0xFF8F 0xFF8C, 0xFF8D 0xFF8A, 0xFF8B 0xFF80 0xFF89 VREG Port FLASH wake-up errors receive transmit lock self clock mode Port Interrupt Source Pulse accumulator input edge Mask Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CTRL0 (LVIE) 0x008A PIEP (PIEP7-0) 0x008E FCNFG (CCIE, CBEIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) 0x00B8 0x00B6 0x00B4 0x00B2 0x00B0 PLLCR (LOCKIE) PLLCR (SCMIE) 0x00C6 0x00C4 PIEP (PIEP7-6) 0x00CE ATDCTL2 (ASCIE) 0x00D2 Local Enable PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) HPRIO Value Elevate 0x00DA 0x00D8 0x00D6
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1.6.2
Resets
Resets subset interrupts featured Table 1-9. different sources capable generating system reset summarized Table 1-10. When reset occurs, registers control bits changed known start-up states. Refer respective module Block User Guides register reset states.
1.6.2.1
Reset Summary Table
Table 1-10. Reset Summary
Reset Power-on Reset External Reset Voltage Reset Clock Monitor Reset Watchdog Reset Priority Source module RESET VREG module module module Vector 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFC, 0xFFFD 0xFFFA, 0xFFFB
1.6.2.2
Effects Reset
When reset occurs, registers control bits changed known start-up states. Refer respective module Block User Guides register reset states. Refer HCS12 Multiplexed External Interface (MEBI) Block Guide mode dependent configuration port reset. Refer Block User Guide reset configurations peripheral module ports. Refer Figure 1-2. Figure 1-5. footnotes locations memories depending operating mode after reset. array automatically initialized reset. NOTE devices assembled 48-pin 52-pin LQFP packages non-bonded pins should configured outputs after reset order avoid current drawn from floating inputs. Refer Table affected pins.
1.7.1
Device Specific Information Module Dependencies
PPAGE
External paging supported these devices. order access flash blocks address range 0x8000-0xBFFF PPAGE register must loaded with corresponding value this range. Refer Table 1-11 device specific page mapping. devices Flash Page visible 0xC000-0xFFFF range ROMON set. devices (except MC9S12GC16) Page also visible 0x4000-0x7FFF range ROMHM cleared ROMON set. devices apart from MC9S12Q32 Flash Page visible 0x0000-0x3FFF range ROMON set.
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Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Table 1-11. Device Specific Flash PAGE Mapping
Device MC9S12Q32 PAGE MC9S12Q64 MC9S12Q96 MC9S12Q128 PAGE Visible with PPAGE Contents $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F $02,$0A,$12,$1A,$22,$2A,$32,$3A $03,$0B,$13,$1B,$23,$2B,$33,$3B $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F $00,$08,$10,$18,$20,$28,$30,$38 $01,$09,$11,$19,$21,$29,$31,$39 $02,$0A,$12,$1A,$22,$2A,$32,$3A $03,$0B,$13,$1B,$23,$2B,$33,$3B $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F
1.7.2
Alternate Clock
section reference alternate clock equivalent oscillator clock.
1.7.3
Extended Address Range Emulation Implications
order emulate devices, external addressing 128K memory required. This provided LQFP package version which includes necessary extra external address signals PortK[2:0]. This package version emulation only provided general production package. reset state DDRK 0x0000, configuring pins inputs. reset state PUPKE PUCR register enabling internal Port pullups. this reset state pull-ups provide defined state prevent floating input, thereby preventing unnecessary current flow input stage. prevent unnecessary current flow production package options, states DDRK PUPKE should changed software.
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MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
1.7.4
VREGEN
VREGEN input mentioned VREG section device internal, connected internally VDDR.
1.7.5
VDD1, VDD2, VSS1, VSS2
80-pin package versions, both internal 2.5V domain bonded sides device pairs (VDD1, VSS1 VDD2, VSS2). VDD1 VDD2 connected together internally. VSS1 VSS2 connected together internally. extra pair enables systems using 80-pin package employ better supply routing further decoupling.
1.7.6
Clock Reset Generator VREG Interface
voltage reset feature uses voltage reset signal from VREG module input module. When regulator output voltage supply internal chip logic falls below specified threshold signal from VREG module causes module generate reset. NOTE voltage regulator shut down connecting VDDR ground then LVRF flag flags register (CRGFLG) undefined.
1.7.7
Analog-to-Digital Converter
52-pin package versions, bonded internally VSSA pin.
1.7.8
MODRR Register Port Port Mapping
MODRR register within allows mapping channels port absence port pins count packages. 80QFP package option recommended MODRR since this intended support channel availability count packages. Note that when mapping channels port 80QFP option, associated channels then mapped both port port MODRR[4] must for.
1.7.9
Port Dependency Registers
port pins interface module. However, port digital state read from either PORTAD register register from PTAD register register map. order read digital value from PORTAD corresponding ATDDIEN must corresponding DDRDA cleared. corresponding ATDDIEN cleared then configured analog input PORTAD reads back "1". order read digital value from PTAD, corresponding DDRAD must cleared, configure input. Furthermore order port analog input, corresponding DDRAD must cleared configure input
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Recommended Printed Circuit Board Layout
must carefully laid ensure proper operation voltage regulator well itself. following rules must observed: Every supply pair must decoupled ceramic capacitor connected near possible corresponding pins. Central point ground star should VSSR pin. ohmic inductance connections between VSS1, VSS2, VSSR. VSSPLL must directly connected VSSR. Keep traces VSSPLL, EXTAL, XTAL short possible occupied board area C11, small possible. place other signals supplies underneath area occupied connection area MCU. Central power input should VDDA/VSSA pins.
Table 1-12. Recommended Component Values
Component Purpose VDD1 filter capacitor VDDR filter capacitor VDDPLL filter capacitor loop filter capacitor specification chapter loop filter capacitor load capacitor specification chapter load capacitor VDD2 filter capacitor only) VDDA filter capacitor VDDX filter capacitor cutoff capacitor Pierce Mode Select Pullup loop filter resistor loop filter resistor Pierce mode only loop filter resistor Ceramic Ceramic X7R/tantalum 220nF 100nF >=100nF Type Ceramic X7R/tantalum Ceramic Value 220nF, 470nF(1) >=100nF 100nF
Colpitts mode only, recommended quartz manufacturer Pierce Mode Only Specification chapter
Quartz 48LQFP 52LQFP package versions, VDD2 available. Thus 470nF must connected VDD1.
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Figure 1-14. Recommended Layout LQFP) Colpitts Oscillator
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Figure 1-15. Recommended Layout LQFP) Colpitts Oscillator
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Figure 1-16. Recommended Layout QFP) Colpitts Oscillator
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Figure 1-17. Recommended Layout LQFP Pierce Oscillator
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Figure 1-18. Recommended Layout LQFP Pierce Oscillator
MC9S12Q128 1.09
Freescale Semiconductor
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
Figure 1-19. Recommended Layout 80QFP Pierce Oscillator
Freescale Semiconductor
MC9S12Q128 1.09
Chapter MC9S12Q Device Overview (MC9S12Q128-Family)
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
Introduction
Port Integration Module establishes interface between peripheral modules pins ports. This chapter covers: Port related core logic multiplexed interface Port connected module (PWM module routed port well) Port connected module Port associated MSCAN module Port connected module, external interrupt sources available Port pins used external interrupt sources standard I/O's following configurations selected: Available pins: Input/output selection Drive strength reduction Enable select pull resistors Available Port Port pins: Interrupt enable status flags implementation Port Integration Module device dependent.
2.1.1
Features
standard port following minimum features: Input/output selection output drive with selectable drive strength digital analog input Input with selectable pull-up pull-down device Optional features: Open drain wired-OR connections Interrupt inputs with glitch filtering
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MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.1.2
Block Diagram
Figure block diagram PIM.
Port Integration Module
IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Interrupt Logic
Logic
Port
PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7
RXCAN TXCAN MISO MOSI
CORE ADDR8/DATA8 ADDR9/DATA9 ADDR10/DATA10 ADDR11/DATA11 ADDR12/DATA12 ADDR13/DATA13 ADDR14/DATA14 ADDR15/DATA15
Port
Figure 2-1. Block Diagram
Note: MODRR register within allows mapping channels Port absence Port pins count packages. 80QFP package option recommended MODRR since this intended support channel availability count packages. Note that when mapping channels Port 80QFP option, associated channels then mapped both Port Port
MC9S12Q128 1.09
Freescale Semiconductor
Port
ADDR0/DATA0 ADDR1/DATA1 ADDR2/DATA2 ADDR3/DATA3 ADDR4/DATA4 ADDR5/DATA5 ADDR6/DATA6 ADDR7/DATA7
Port
Port
Port
Port
PWM0 PWM1 PWM2 PWM3
Port
BKGD/MODC/TAGHI XIRQ LSTRB/TAGLO ECLK IPIPE0/MODA IPIPE1/MODB NOACC/XCLKS
BKGD
Chapter Port Integration Module (PIM9C32) Block Description
Signal Description
This section lists describes signals that connect off-chip. Table shows pins their functions that controlled module. there more than function associated pin, priority indicated position table from (highest priority) down (lowest priority).
Table 2-1. Functions Priorities
Port Port Name PT[7:0] Function PWM[3:0] IOC[7:2] GPIO Port GPIO GPIO GPIO GPIO Port Port PP[7:0] MOSI MISO TXCAN RXCAN PWM[3:0] GPIO[7:0] PP[6] Port Port PJ[7:6] PAD[7:0] ROMON GPIO ATD[7:0] GPIO[7:0] Port PA[7:0] ADDR[15:8]/ DATA[15:8]/ GPIO ADDR[7:0]/ DATA[7:0]/ GPIO Description outputs (only available enabled MODRR register) Standard timer channels General-purpose General-purpose General purpose Serial communication interface transmit General-purpose Serial communication interface receive General-purpose clock transmit slave select line receive MSCAN transmit MSCAN receive outputs General purpose with interrupt ROMON input signal General purpose with interrupt analog inputs General purpose Refer MEBI Block Guide. Function after Reset GPIO
Port
PB[7:0]
Refer MEBI Block Guide.
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Chapter Port Integration Module (PIM9C32) Block Description
Table 2-1. Functions Priorities (continued)
Port Name Function NOACC/ XCLKS/ GPIO IPIPE1/ MODB/ GPIO IPIPE0/ MODA/ GPIO ECLK/GPIO LSTRB/ TAGLO/ GPIO R/W/ GPIO IRQ/GPI XIRQ/GPI Description Function after Reset
Port
Refer MEBI Block Guide.
Memory Registers
This section provides detailed description registers.
2.3.1
Address
Module Memory
Name PTT7 IOC7 PTIT7 PTT6 IOC6 PTIT6 PTT5 IOC5 PTIT5 PTT4 IOC4 PTIT4 PTT3 IOC3 PWM3 PTIT3 PTT2 IOC2 PWM2 PTIT2 PTT1 PTT0
Figure shows register Port Integration Module.
0x0000 0x0001 0x0002 0x0003 0x0004 0x0005
PTIT DDRT RDRT PERT PPST
PWM1 PTIT1
PWM0 PTIT0
DDRT7 RDRT7 PERT7 PPST7
DDRT6 RDRT6 PERT6 PPST6
DDRT5 RDRT5 PERT5 PPST5
DDRT4 RDRT4 PERT4 PPST4
DDRT3 RDRT3 PERT3 PPST3
DDRT2 RDRT2 PERT2 PPST2
DDRT1 RDRT1 PERT1 PPST1
DDRT0 RDRT0 PERT0 PPST0
Unimplemented Reserved
Figure 2-2. Quick Reference Registers (Sheet
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Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
Address
Name
0x0006 Reserved 0x0007 MODRR 0x0008 0x0009 PTIS 0x000A DDRS 0x000B RDRS 0x000C PERS 0x000D PPSS 0x000E WOMS 0x000F Reserved 0x0010 PMSCAN 0x0011 PTIM 0x0012 DDRM 0x0013 RDRM 0x0014 PERM 0x0015 PPSM 0x0016 WOMM 0x0017 Reserved 0x0018 0x0019 PTIP
MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTS3 PTIS3 PTS2 PTIS2 PTS1 PTIS1 PTS0 PTIS0
DDRS3 RDRS3 PERS3 PPSS3 WOMS3
DDRS2 RDRS2 PERS2 PPSS2 WOMS2
DDRS1 RDRS1 PERS1 PPSS1 WOMS1
DDRS0 RDRS0 PERS0 PPSS0 WOMS0
PTM5 PTIM5
PTM4 MOSI PTIM4
PTM3 PTIM3
PTM2 MISO PTIM2
PTM1 TXCAN PTIM1
PTM0 RXCAN PTIM0
DDRM5 RDRM5 PERM5 PPSM5 WOMM5
DDRM4 RDRM4 PERM4 PPSM4 WOMM4
DDRM3 RDRM3 PERM3 PPSM3 WOMM3
DDRM2 RDRM2 PERM2 PPSM2 WOMM2
DDRM1 RDRM1 PERM1 PPSM1 WOMM1
DDRM0 RDRM0 PERM0 PPSM0 WOMM0
PTP7 PTIP7
PTP6 PTIP6
PTP5 PTIP5
PTP4 PTIP4
PTP3 PWM3 PTIP3
PTP2 PWM2 PTIP2
PTP1 PWM1 PTIP1
PTP0 PWM0 PTIP0
Unimplemented Reserved
Figure 2-2. Quick Reference Registers (Sheet
Freescale Semiconductor
MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
Address 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F
Name DDRP RDRP PERP PPSP PIEP PIFP
DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7
DDRP6 RDRP6 PERP6 PPSP6 PIEP6 PIFP6
DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5
DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4
DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3
DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2
DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1
DDRP0 RDRP0 PERP0 PPSP0 PIEP0 PIFP0
0x0020- Reserved 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ PTAD PTIAD DDRAD RDRAD PERAD PPSAD
PTJ7 PTIJ7
PTJ6 PTIJ6
DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 PTAD7 PTIAD7
DDRJ6 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 PTAD6 PTIAD6
PTAD5 PTIAD5
PTAD4 PTIAD4
PTAD3 PTIAD3
PTAD2 PTIAD2
PTAD1 PTIAD1
PTAD0 PTIAD0
DDRAD7 RDRAD7 PERAD7 PPSAD7
DDRAD6 RDRAD6 PERAD6 PPSAD6
DDRAD5 RDRAD5 PERAD5 PPSAD5
DDRAD4 RDRAD4 PERAD4 PPSAD4
DDRAD3 RDRAD3 PERAD3 PPSAD3
DDRAD2 RDRAD2 PERAD2 PPSAD2
DDRAD1 RDRAD1 PERAD1 PPSAD1
DDRAD0 RDRAD0 PERAD0 PPSAD0
0x0036- Reserved 0x003F
Unimplemented Reserved
Figure 2-2. Quick Reference Registers (Sheet
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2
Register Descriptions
Table summarizes effect various configuration bits data direction (DDR), input/output level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), interrupt enable (IE) ports. configuration used purposes: Configure sensitive interrupt edge (rising falling), interrupt enabled. Select either pull-up pull-down device active.
Table 2-2. Configuration Summary
IE(1) Function Input Input Input Input Input Input Input Output, full drive Output, full drive Output, reduced drive Output, reduced drive Output, full drive Output, full drive Output, reduced drive Output, reduced drive Pull Device Disabled Pull Pull down Disabled Disabled Pull Pull down Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Interrupt Disabled Disabled Disabled Falling edge Rising edge Falling edge rising edge Disabled Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge
Applicable only ports
NOTE bits registers this module completely synchronous internal clocks during register read.
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MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.1
2.3.2.1.1
Port Registers
Port Register (PTT)
Module Base 0x0000
PTT7 Reset IOC7 IOC6 IOC5 IOC4 IOC3 PWM3 IOC2 PWM2 PWM1 PWM0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
Unimplemented Reserved
Figure 2-3. Port Register (PTT)
Read: Anytime. Write: Anytime. data direction bits associated pins read returns value port register, otherwise value pins read. TIM-channel defined output, related port assigned function. addition possible timer functionality port pins channels routed port this Module Routing Register (MODRR) needs configured.
Table 2-3. Port T[4:0] Functionality Configurations(1)
MODRR[x] PWME[x] TIMEN[x]
Port T[x] Output General Purpose Timer General Purpose Timer General Purpose Timer
fields that shaded standard cases. TIMEN[x] means that timer enabled (TSCR1[7]), related channel configured output compare function (TIOS[x] special output timer overflow event configurable TTOV[x]) timer output routed port (TCTL1/TCTL2).
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Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.1.2
Port Input Register (PTIT)
Module Base 0x0001
Reset
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
Unimplemented Reserved
Figure 2-4. Port Input Register (PTIT)
Read: Anytime. Write: Never, writes this register have effect.
Table 2-4. PTIT Field Descriptions
Field PTIT[7:0] Description Port Input Register This register always reads back status associated pins. This also used detect overload short circuit conditions output pins.
2.3.2.1.3
Port Data Direction Register (DDRT)
Module Base 0x0002
DDRT7 Reset DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Figure 2-5. Port Data Direction Register (DDRT)
Read: Anytime. Write: Anytime.
Table 2-5. DDRT Field Descriptions
Field DDRT[7:0] Description Data Direction Port This register configures each port either input output. standard modules forces state output each standard module port associated with enabled output compare. these cases data direction bits will change. DDRT bits revert controlling direction when associated timer output compare disabled. timer input capture always monitors state pin. Associated configured input. Associated configured output. Note: internal synchronization circuits, take cycles until correct value read PTIT registers, when changing DDRT register.
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MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.1.4
Port Reduced Drive Register (RDRT)
Module Base 0x0003
RDRT7 Reset RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Figure 2-6. Port Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime.
Table 2-6. RDRT Field Descriptions
Field RDRT[7:0] Description Reduced Drive Port This register configures drive strength each port output either full reduced. port used input this ignored. Full drive strength output. Associated drives about full drive strength.
2.3.2.1.5
Port Pull Device Enable Register (PERT)
Module Base 0x0004
PERT7 Reset PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Figure 2-7. Port Pull Device Enable Register (PERT)
Read: Anytime. Write: Anytime.
Table 2-7. PERT Field Descriptions
Field PERT[7:0] Description Pull Device Enable This register configures whether pull-up pull-down device activated, port used input. This effect port used output. reset pull device enabled. Pull-up pull-down device disabled. Either pull-up pull-down device enabled.
MC9S12Q128 1.09
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Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.1.6
Port Polarity Select Register (PTTST)
Module Base 0x0005
PPST7 Reset PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Figure 2-8. Port Polarity Select Register (PPST)
Read: Anytime. Write: Anytime.
Table 2-8. PPST Field Descriptions
Field PPST[7:0] Description Pull Select Port This register selects whether pull-down pull-up device connected pin. pull-up device connected associated port pin, enabled associated register PERT port used input. pull-down device connected associated port pin, enabled associated register PERT port used input.
2.3.2.1.7
Port Module Routing Register (MODRR)
Module Base 0x0007
Reset
MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
Unimplemented Reserved
Figure 2-9. Port Module Routing Register (MODRR)
Read: Anytime. Write: Anytime. NOTE MODRR[4] must kept clear devices featuring channel PWM.
Table 2-9. MODRR Field Descriptions
Field Description
Module Routing Register Port This register selects module connected port MODRR[4:0] Associated connected module Associated connected module
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MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.2
2.3.2.2.1
Port Registers
Port Register (PTS)
Module Base 0x0008
Reset
PTS3 PTS2 PTS1 PTS0
Unimplemented Reserved
Figure 2-10. Port Register (PTS)
Read: Anytime. Write: Anytime. data direction bits associated pins read returns value port register, otherwise value pins read. port associated with transmit configured output transmitter enabled associated with receive configured input receiver enabled. Please refer Block User Guide details. 2.3.2.2.2 Port Input Register (PTIS)
Module Base 0x0009
Reset
PTIS3
PTIS2
PTIS1
PTIS0
Unimplemented Reserved
Figure 2-11. Port Input Register (PTIS)
Read: Anytime. Write: Never, writes this register have effect.
Table 2-10. PTIS Field Descriptions
Field PTIS[3:0] Description Port Input Register This register always reads back status associated pins. This also used detect overload short circuit conditions output pins.
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.2.3
Port Data Direction Register (DDRS)
Module Base 0x000A
Reset
DDRS3 DDRS2 DDRS1 DDRS0
Unimplemented Reserved
Figure 2-12. Port Data Direction Register (DDRS)
Read: Anytime. Write: Anytime.
Table 2-11. DDRS Field Descriptions
Field DDRS[3:0] Description Direction Register Port This register configures each port either input output. associated transmit receive channel enabled this register effect pins. forced output transmit channel enabled, forced input receive channel enabled. DDRS bits revert controlling direction when associated channel disabled. Associated configured input. Associated configured output. Note: internal synchronization circuits, take cycles until correct value read PTIS registers, when changing DDRS register.
Freescale Semiconductor
MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.2.4
Port Reduced Drive Register (RDRS)
Module Base 0x000B
Reset
RDRS3 RDRS2 RDRS1 RDRS0
Unimplemented Reserved
Figure 2-13. Port Reduced Drive Register (RDRS)
Read: Anytime. Write: Anytime.
Table 2-12. RDRS Field Descriptions
Field RDRS[3:0] Description Reduced Drive Port This register configures drive strength each port output either full reduced. port used input this ignored. Full drive strength output. Associated drives about full drive strength.
2.3.2.2.5
Port Pull Device Enable Register (PERS)
Module Base 0x000C
Reset
PERS3 PERS2 PERS1 PERS0
Unimplemented Reserved
Figure 2-14. Port Pull Device Enable Register (PERS)
Read: Anytime. Write: Anytime.
Table 2-13. PERS Field Descriptions
Field PERS[3:0] Description Reduced Drive Port This register configures whether pull-up pull-down device activated, port used input output wired-or (open drain) mode. This effect port used push-pull output. reset pull-up device enabled. Pull-up pull-down device disabled. Either pull-up pull-down device enabled.
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.2.6
Port Polarity Select Register (PPSS)
Module Base 0x000D
Reset
PPSS3 PPSS2 PPSS1 PPSS0
Unimplemented Reserved
Figure 2-15. Port Polarity Select Register (PPSS)
Read: Anytime. Write: Anytime.
Table 2-14. PPSS Field Descriptions
Field PPSS[3:0] Description Pull Select Port This register selects whether pull-down pull-up device connected pin. pull-up device connected associated port pin, enabled associated register PERS port used input wired-or output. pull-down device connected associated port pin, enabled associated register PERS port used input.
2.3.2.2.7
Port Wired-OR Mode Register (WOMS)
Module Base 0x000E
Reset
WOMS3 WOMS2 WOMS1 WOMS0
Unimplemented Reserved
Figure 2-16. Port Wired-Or Mode Register (WOMS)
Read: Anytime. Write: Anytime.
Table 2-15. WOMS Field Descriptions
Field Description
Wired-OR Mode Port This register configures output pins wired-or. enabled output driven WOMS[3:0] active only (open-drain). logic level driven. This influence pins used inputs. Output buffers operate push-pull outputs. Output buffers operate open-drain outputs.
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MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.3
2.3.2.3.1
Port Registers
Port Register (PTM)
Module Base 0x0010
MSCAN/ Reset
PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
MOSI
MISO
TXCAN
RXCAN
Unimplemented Reserved
Figure 2-17. Port Register (PTM)
Read: Anytime. Write: Anytime. data direction bits associated pins read returns value port register, otherwise value pins read. configurations (PM[5:2]) determined several status bits module. Please refer Block User Guide details. 2.3.2.3.2 Port Input Register (PTIM)
Module Base 0x0011
Reset
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
Unimplemented Reserved
Figure 2-18. Port Input Register (PTIM)
Read: Anytime. Write: Never, writes this register have effect.
Table 2-16. PTIM Field Descriptions
Field PTIM[5:0] Description Port Input Register This register always reads back status associated pins. This also used detect overload short circuit conditions output pins.
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.3.3
Port Data Direction Register (DDRM)
Module Base 0x0012
Reset
DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
Unimplemented Reserved
Figure 2-19. Port Data Direction Register (DDRM)
Read: Anytime. Write: Anytime.
Table 2-17. DDRM Field Descriptions
Field DDRM[5:0] Description Data Direction Port This register configures each port either input output MSCAN enabled, MSCAN modules determines directions. Please refer MSCAN Block User Guides details. associated MSCAN transmit receive channels enabled, this register effect pins. pins forced outputs MSCAN transmit channels enabled, they forced inputs MSCAN receive channels enabled. DDRS bits revert controlling direction when associated channel disabled. Associated configured input. Associated configured output. Note: internal synchronization circuits, take cycles until correct value read PTIM registers, when changing DDRM register.
Freescale Semiconductor
MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.3.4
Port Reduced Drive Register (RDRM)
Module Base 0x0013
Reset
RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
Unimplemented Reserved
Figure 2-20. Port Reduced Drive Register (RDRM)
Read: Anytime. Write: Anytime.
Table 2-18. RDRM Field Descriptions
Field RDRM[5:0] Description Reduced Drive Port This register configures drive strength each port output either full reduced. port used input this ignored. Full drive strength output. Associated drives about full drive strength.
2.3.2.3.5
Port Pull Device Enable Register (PERM)
Module Base 0x0014
Reset
PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
Unimplemented Reserved
Figure 2-21. Port Pull Device Enable Register (PERM)
Read: Anytime. Write: Anytime.
Table 2-19. PERM Field Descriptions
Field PERM[5:0] Description Pull Device Enable Port This register configures whether pull-up pull-down device activated, port used input output wired-or (open drain) mode. This effect port used push-pull output. reset pull-up device enabled. Pull-up pull-down device disabled. Either pull-up pull-down device enabled.
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.3.6
Port Polarity Select Register (PPSM)
Module Base 0x0015
Reset
PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
Unimplemented Reserved
Figure 2-22. Port Polarity Select Register (PPSM)
Read: Anytime. Write: Anytime.
Table 2-20. PPSM Field Descriptions
Field PPSM[5:0] Description Polarity Select Port This register selects whether pull-down pull-up device connected pin. pull-up device connected associated port pin, enabled associated register PERM port used input wired-or output. pull-down device connected associated port pin, enabled associated register PERM port used input.
2.3.2.3.7
Port Wired-OR Mode Register (WOMM)
Module Base 0x0016
Reset
WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Unimplemented Reserved
Figure 2-23. Port Wired-OR Mode Register (WOMM)
Read: Anytime. Write: Anytime.
Table 2-21. WOMM Field Descriptions
Field Description
Wired-OR Mode Port This register configures output pins wired-or. enabled output driven WOMM[5:0] active only (open-drain). logic level driven. This influence pins used inputs. Output buffers operate push-pull outputs. Output buffers operate open-drain outputs.
Freescale Semiconductor
MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.4
2.3.2.4.1
Port Registers
Port Register (PTP)
Module Base 0x0018
PTP7 Reset PWM3 PWM2 PWM1 PWM0 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
Figure 2-24. Port Register (PTP)
Read: Anytime. Write: Anytime. data direction bits associated pins read returns value port register, otherwise value pins read. 2.3.2.4.2 Port Input Register (PTIP)
Module Base 0x0019
Reset
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
Unimplemented Reserved
Figure 2-25. Port Input Register (PTIP)
Read: Anytime. Write: Never, writes this register have effect. This register always reads back status associated pins. This also used detect overload short circuit conditions output pins.
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.4.3
Port Data Direction Register (DDRP)
Module Base 0x001A
DDRP7 Reset DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Figure 2-26. Port Data Direction Register (DDRP)
Read: Anytime. Write: Anytime.
Table 2-22. DDRP Field Descriptions
Field DDRP[7:0] Description Data Direction Port This register configures each port either input output. Associated configured input. Associated configured output. Note: internal synchronization circuits, take cycles until correct value read PTIP registers, when changing DDRP register.
2.3.2.4.4
Port Reduced Drive Register (RDRP)
Module Base 0x001B
RDRP7 Reset RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Figure 2-27. Port Reduced Drive Register (RDRP)
Read: Anytime. Write: Anytime.
Table 2-23. RDRP Field Descriptions
Field RDRP[7:0] Description Reduced Drive Port This register configures drive strength each port output either full reduced. port used input this ignored. Full drive strength output. Associated drives about full drive strength.
Freescale Semiconductor
MC9S12Q128 1.09
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.4.5
Port Pull Device Enable Register (PERP)
Module Base 0x001C
PERP7 Reset PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
Figure 2-28. Port Pull Device Enable Register (PERP)
Read: Anytime. Write: Anytime.
Table 2-24. PERP Field Descriptions
Field PERP[7:0] Description Pull Device Enable Port This register configures whether pull-up pull-down device activated, port used input. This effect port used output. reset pull device enabled. Pull-up pull-down device disabled. Either pull-up pull-down device enabled.
2.3.2.4.6
Port Polarity Select Register (PPSP)
Module Base 0x001D
PPSP7 Reset PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
Figure 2-29. Port Polarity Select Register (PPSP)
Read: Anytime. Write: Anytime.
Table 2-25. PPSP Field Descriptions
Field PPSP[7:0] Description Pull Select Port This register serves dual purpose selecting polarity active interrupt edge well selecting pull-up pull-down device enabled. Falling edge associated port sets associated flag PIFP register.A pull-up device connected associated port pin, enabled associated register PERP port used input. Rising edge associated port sets associated flag PIFP register.A pull-down device connected associated port pin, enabled associated register PERP port used input.
MC9S12Q128 1.09
Freescale Semiconductor
Chapter Port Integration Module (PIM9C32) Block Description
2.3.2.4.7
Port Interrupt Enable Register (PIEP)
Module Base 0x001E
PIEP7 Reset PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
Figure 2-30. Port Interrupt Enable Register (PIEP)
Read: Anytime. Write: Anytime.
Table 2-26. PIEP Field Descriptions
Field PIEP[7:0] Description Pull Select Port This register disables enables basis edge sensitive external interrupt associated with port Interrupt disabled (interrupt flag masked). Interrupt enabled.
2.3.2.4.8
Port Interrupt Flag Register (PIFP)
Module Base 0x001F
PIFP7 Reset PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
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