MC72000/D Rev. 2.6, 1/2003 MC72000 Integrated BluetoothRadio MC72
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Advance Information Data Sheet
MC72000/D Rev. 2.6, 1/2003 MC72000 Integrated BluetoothRadio
MC72000
Package Information Plastic Package Case 1398-01 (MAPBGA-100)
Freescale Semiconductor, Inc.
Ordering Information
Device MC72000 Operating Temperature Range -40° Package MAPBGA
Contents
MC72000 Features System Overview Electrical Characteristics. Package Pinout System Description Radio Functional Description Hardware Functional Description Bluetooth Baseband Functionality Overview. Features. Applications Information Application Example Evaluation Printed Circuit Boards Mechanical Outline (Package Information) Appendix Radio Register
MC72000 Integrated BluetoothRadio provides complete, low-power Bluetooth radio solution. design based Motorola's third-generation Bluetooth architecture that high standard interoperability, complete functionality, compliance with Bluetooth specification. MC72000 Integrated Bluetooth Radio from Motorola implements baseband host controller interface (HCI) Bluetooth protocol small package. MC72000 ideal solution low-power, short-range Bluetooth applications with small size constraints includes superior performance features like dedicated Bluetooth audio processor module on-chip memory. Debug production test fully supported through joint test action group (JTAG) interface. portion radio provides unique combination high sensitivity, excellent performance, power consumption. These performance parameters extremely important maintaining robust link high interference environments created devices such mobile phones, high density Bluetooth networks, 802.11b networks, microwave ovens. MC72000 uses innovative, highly advanced packaging technique combine die-the baseband functions-into single, cost-effective package. Motorola's optimized two-chip architecture avoids compromises between cost performance that other one-chip solutions must make. With Motorola's integrated solution, customers best both. Each implemented optimal process technology deliver cost, power, small size.
This document contains information product. Specifications information herein subject change without notice. Motorola, Inc., 2003. rights reserved.
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MC72000 Features
MC72000 Features
Radio Transceiver Current Drain
Power Down Modes Power Conservation Receiver with On-Chip Filters Fully Integrated Demodulator with Direct Launch Transmitter Multi-Accumulator, Dual-Port, Fractional-N Synthesizer RSSI with Bluetooth Class Radio (Class supported using external Crystal Independent MHz) Reference Oscillator supplied externally Power Supply Range: Bluetooth Specification Compliant Point-to-multipoint with slaves connection types packet types power saving modes Master/Slave switch Encryption UART transport layer
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Baseband Controller
Outstanding Audio Performance Sample rate synchronization between CODECs Bluetooth clock domains avoid clicking effects Simultaneous channels supported Bluetooth encoding/decoding schemes supported (CVSD, A-Law, µ-Law) Very audio delay avoid need echo cancellation
Support Sample Rate CODECs Bluetooth Link Controller Bluetooth Audio Signal Processor ARM7 Processor Complex Peripherals High-speed UART Mbps) High-speed Mbps) High-speed Mbps)
Embedded Memory SRAM (256
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JTAG Test Interface Controller Operating Voltage: 1.65 1.95
System Overview
32.768 Oscillator Power Operation
System Overview
This section provides brief description system MC72000. system overview shown Figure
Signal Path Antenna Bandpass Filter Rx/Tx Switch MC72000 32.768
XTAL
Interface UART Interface GPIO reset
Freescale Semiconductor, Inc.
12-15
XTAL
SEEPROM Application Software Configuration Data
Figure MC72000 Example Application Block Diagram
main block MC72000, which will described depth Section "System Description." addition MC72000, there three other blocks: signal Path Interfaces Reference clocks
Signal Path
switch bandpass filter, antenna found signal path.
Interfaces
There four bi-directional interfaces reset that only host initiate. interface used audio purposes. UART interface used communication from host (for example, commands). used communication with SEEPROM. GPIO pins used different configurations MC72000.
Clocks/Crystals
MC72000 clocks:
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Electrical Characteristics
ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 reference clock (12-26 MHz) used when MC72000 active. Note that crystal connected on-chip oscillator, frequency range 12-15 shown Figure
power clock (32.768 kHz) also included have high initial tolerance.
Electrical Characteristics
absolute maximum ratings given Table stress ratings only, functional operation maximum guaranteed. Stress beyond these ratings affect device reliability cause permanent damage device.
WARNING:
Freescale Semiconductor, Inc.
This device contains protective circuitry guard against damage high static voltage electrical fields. However, normal precautions advised avoid application voltages higher than maximum rated voltages high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (for example, either GND), except JTAG signals. Refer Section 10.12, "JTAG Interface," details handle JTAG signals.
Electrical Characteristics
following tables provide information electrical characteristics MC72000.
Table Absolute Maximum Ratings
Characteristics Power Supply Voltage, Power Supply Voltage, Power Supply Voltage, Junction Temperature Storage Temperature Range Tstg Symbol Value (GND 0.3) (GND 0.3) (GND 0.3) Unit
Table Protection Characteristics
Characteristics Human Body Model (HBM) pins, except RFIN, PAO+, PAORFIN, PAO+, PAOMachine Model (MM) pins, except RFIN, PAO+, PAORFIN, PAO+, PAOSymbol Unit VHBM VRFHBM VRFMM 2000
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Table Recommended Operating Conditions
Characteristics Power Supply Voltage, Power Supply Voltage, Power Supply Voltage, Input Frequency Ambient Temperature Range Frequency Range (only integral multiples used) Symbol VCCRF VDDBB VDDIO fref 32.768 32.768 1.65 1.95 Unit
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With Crystal
External Source Power Frequency Range With Crystal External Source
Table Digital Electrical Specifications
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Input Current High (VIN VDD) Digital Pins Digital Pins Input Current (VIN GND) Digital Pins Digital Pins Output Current High-Impedance State Output Short-Circuit Current (VOUT VDD/VCC) Digital Pins Digital Pins Digital Pins (VOUT GND) Digital Pins Digital Pins Digital Pins Input Voltage High Digital Pins Digital Pins Input Voltage Digital Pins Digital Pins Symbol VDD_BB VDD_IO -0.3 -0.3 VDD_BB VDD_IO VDD_BB VDD_IO Unit
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Electrical Characteristics
Table Digital Electrical Specifications (Continued)
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Output Voltage High Digital Pins (IOH -3mA) Digital Pins (IOH -3mA) Digital Pins (IOH -100µA) Output Voltage Digital Pins (IOL 3mA) Digital Pins (IOL 3mA) Digital Pins (IOL 100µA) Symbol VDD_BB VDD_IO VCC_RF VDD_BB VDD_IO VDD_RF IIOPUL IIOPUH IBBPUL IBBPUH IBBPDL IBBPDH CBBIN CIOIN VDD_BB VDD_IO VCC_RF Unit
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Internal Pull-up Device Current Digital pins VILMAX Digital pins VIHMIN MODE1, TTS, TMS, VILMAX MODE1, TTS, TMS, VIHMIN Internal Pull-down Device Current RESET_BB, TCK, TRST_B VILMAX RESET_BB, TCK, TRST_B VIHMIN Input Capacitance Digital Pins Digital Pins
Table Electrical Specifications
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure except R11/7 unless otherwise noted. Figure Characteristics Output Voltage EPADAC, Iload PADAC 000000 PADAC 100000 PADAC 111111 Resolution Linearity Average Supply Current (1-slot packet) Symbol Vout Unit
0.02 1.60 3.08
Bits
RESOL INL/DNL ICCDAC
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Freescale Semiconductor, Inc. Electrical Characteristics
Table Power Consumption Characteristics
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Total Power Supply Current link, link, link, link, 1-slot symmetric link, 3-slot symmetric link, 5-slot symmetric Standby Mode activity) Sniff Mode, Sniff Mode, Sniff Mode, Hold Mode Inquiry Scan Mode, 1.28 interval Page Scan Mode, 1.28 interval Inquiry Page Scan Mode, 1.28 interval Power Supply Current Transmit, slot Transmit, slot Transmit, slot Transmit, Transmit, Transmit, Transmit, Continuous Receive, slot Receive, slot Receive, slot Receive, Receive, Receive, Receive, Continuous Standby Mode activity) Sniff Mode, 0.5s Sniff Mode, 1.0s Sniff Mode, 2.0s Hold Mode Inquiry Scan Mode, 1.28s interval Page Scan Mode, 1.28s interval Inquiry Page Scan Mode, 1.28s interval Symbol Typical Average Peak Unit ITOTHV1 ITOTHV2 ITOTHV3 ITOTA1 ITOTA3 ITOTA5 ITOTSTBY ITOTS0.5 ITOTS1.0 ITOTS2.0 ITOTHOLD ITOTIS ITOTPS ITOTIPS ICCRFtx1 ICCRFtx3 ICCRFtx5 ICCRFtxHV1 ICCRFtxHV2 ICCRFtxHV3 ICCRFtxc ICCRFrx1 ICCRFrx3 ICCRFrx5 ICCRFrxHV1 ICCRFrxHV2 ICCRFrxHV3 ICCRFrxc ICCRFstby ICCRFs0.5 ICCRFs1.0 ICCRFs2.0 ICCRFhold ICCRFis ICCRFps ICCRFips
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MOTOROLA
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Electrical Characteristics
Table Power Consumption Characteristics (Continued)
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Power Supply Current Transmit, slot Transmit, slot Transmit, slot Transmit, Transmit, Transmit, Transmit, Continuous Receive, slot Receive, slot Receive, slot Receive, Receive, Receive, Receive, Continuous Standby Mode activity) Sniff Mode, 0.5s Sniff Mode, 1.0s Sniff Mode, 2.0s Hold Mode Inquiry Scan Mode, 1.28s interval Page Scan Mode, 1.28s interval Inquiry Page Scan Mode, 1.28s interval Power Supply Current Transmit, slot Transmit, slot Transmit, slot Transmit, Transmit, Transmit, Transmit, Continuous Receive, slot Receive, slot Receive, slot Receive, Receive, Receive, Receive, Continuous Standby Mode activity) Sniff Mode, 0.5s Sniff Mode, 1.0s Sniff Mode, 2.0s Hold Mode Inquiry Scan Mode, 1.28s interval Page Scan Mode, 1.28s interval Inquiry Page Scan Mode, 1.28s interval Symbol Typical Average Peak Unit ICCBBtx1 ICCBBtx3 ICCBBtx5 ICCBBtxHV1 ICCBBtxHV2 ICCBBtxHV3 ICCBBtxc ICCBBrx1 ICCBBrx3 ICCBBrx5 ICCBBrxHV1 ICCBBrxHV2 ICCBBrxHV3 ICCBBrxc ICCBBstby ICCBBs0.5 ICCBBs1.0 ICCBBs2.0 ICCBBhold ICCBBis ICCBBps ICCBBips ICCIOtx1 ICCIOtx3 ICCIOtx5 ICCIOtxHV1 ICCIOtxHV2 ICCIOtxHV3 ICCIOtxc ICCIOrx1 ICCIOrx3 ICCIOrx5 ICCIOrxHV1 ICCIOrxHV2 ICCIOrxHV3 ICCIOrxc ICCIOstby ICCIOs0.5 ICCIOs1.0 ICCIOs2.0 ICCIOhold ICCIOis ICCIOps ICCIOips
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ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 Table shows overall current consumed MC72000 many well-known scenarios well detailed current real-time specific modes.
first Table shows maximum peak typical average total current consumed device most scenarios used PDAs, cell phone design, other audio-capable devices such headsets. current specified this total current consumed through three power groups MC72000 (i.e., voltage relationship between three different supply voltages these three groups ignored). Power dissipated MC72000 may, therefore, different than direct power consumption calculated total current consumption. order find current values special scenarios covered typical values total current consumption, current consumed each three power groups also defined variety usages. Each value represents current consumed between repeatedly symmetrical timeframe, example, power supply current transmitting one-slot packets defined time from start burst start burst, same current consumption repeated again next slot. This also applies currents defined receiving packets regardless packet type. example below Figure repeatedly symmetrical pattern definition listed scenarios shown Table
Table Real-time Current Consumption Definitions
Scenario ACL, Continuous Standby Mode Sniff Mode Hold Mode Inquiry and/or Page Scan Mode Defined From burst burst vice versa Absolute value there repeated pattern Absolute value there repeated pattern sniff cycle with defined length seconds Total hold time from start finish page/inquiry scan interval with defined length seconds
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3-SLOT Actual peak current
3-SLOT Actual average current
Figure Power Consumption Characteristics
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Electrical Characteristics
Table Receiver Electrical Specifications
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, unless otherwise noted, Desired RFin 2.441 fdev 157.5 kHz, Interferer fdev kHz, Modulation GFSK, 0.5, Rate Mbps, Modulating payload data desired signal PRBS9, Modulating data interfering signal PRBS15 continuously modulated, Measured 0.1%, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Measurements made from LNAin Recovered Data out. Figure Characteristics Receiver Sensitivity Symbol SENSmin SENSmax Spec Unit
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Maximum Usable Signal Level
Co-Channel Interference Adjacent Interference Adjacent MHz) Interference Adjacent MHz) Interference Adjacent MHz) Interference Image Frequency Interference Adjacent Interference In-Band Image Frequency Spurious Response Frequencies Intermodulation Performance1 Receiver Spurious Emissions Bluetooth 12.75 GSM/DCS UMTS downlink 2110 2170 (WCDMA-FDD)2 2010 2025 (WCDMA-TDD)2 1900 1920 (WCDMA-TDD)2 (GSM 850)3 (GSM 900)3 1805 1880 (DCS1800)3 1930 1990 (PCS1900)3
1MHz 2MHz =3MHz Image Image
dBm/ 100kHz
-186 -184 -184 -177 -177 -177 -174
-180 -180 -180 -163 -163 -170 -168
dBm/Hz
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Table Receiver Electrical Specifications (Continued)
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, unless otherwise noted, Desired RFin 2.441 fdev 157.5 kHz, Interferer fdev kHz, Modulation GFSK, 0.5, Rate Mbps, Modulating payload data desired signal PRBS9, Modulating data interfering signal PRBS15 continuously modulated, Measured 0.1%, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Measurements made from LNAin Recovered Data out. Figure Characteristics Receiver Blocking Performance4 (See Figure Bluetooth 1.999 2.399 2.498 2.999 12.75 GSM/DCS UMTS uplink5 1920 1980 (WCDMA-FDD) 2010 2025 (WCDMA-TDD) 1900 1920 (WCDMA-TDD) (GSM 850) (GSM 900) 1710 1785 (DCS1800) 1850 1910 (PCS1900) RSSI Conversion Value, (R4/6 R9/8 level input maintain conversion value 1000 (binary) 1111 RSSI Resolution, (R4/6 R9/8 RSSI Dynamic Range RSSI Average Supply Current, (R4/6 R9/8 RSSI Symbol Spec Unit
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RSSIres
dB/bit
Measured accordance with Bluetooth specification. Equivalent noise floor bandwidth Equivalent noise floor bandwidth allowed Bluetooth specification, five exceptions taken spurious response. Measured according Bluetooth Specification, using correct modulated bursting GSM/DCS/ UMTS interfering signal, based timeslot.
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Electrical Characteristics
Table Transmitter Electrical Specifications
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, unless otherwise noted, Modulation GFSK, 0.5, Rate Mbps, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Measurements made PAout. Figure Symbo Pout -3.5 -3.5 -3.5 OccBW -1.0 1000 1000 dBm/ 100kHz Bluetooth Specificati
Characteristics
Unit
Transmit Output Power Occupied Bandwidth
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In-Band Spurious Emissions Adjacent Channel Offset Adjacent Channel Offset Adjacent Channel Offset In-Band Spurious Emission Exceptions Band Spurious Emissions Bluetooth 12.75 (2nd Harmonic) 5.15 GSM/DCS UMTS downlink 2110 2170 (WCDMA-FDD)1 2010 2025 (WCDMA-TDD)1 1900 1920 (WCDMA-TDD)1 (GSM 850)2 (GSM 900)2 1805 1880 (DCS1800)2 1930 1990 (PCS1900)2 Average Frequency Deviation Minimum Frequency Deviation High Frequency Modulation Percentage Initial Frequency Accuracy Transmitter Center Frequency Drift One-slot packet Three-slot packet Five-slot packet Maximum Drift Rate Output Impedance
Inb2 Inb3 Inbg3 Inbex
Outb1 Outb2 Outb3 Outb4
dBm/ 100kHz
DevMin ModIn
-177 -190 -190 -175 -175 -175 -175
-168 -178 -182 -153 -156 -165 -167
dBm/Hz
InitFA
Dmax
Table
kHz/ 50µs
Equivalent noise floor bandwidth Equivalent noise floor bandwidth
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Table MC72000 Receive Characteristics
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Interfering access code minimum Hamming distance according Bluetooth specifications. Figure Characteristics False Detection Rate Presence Noise Presence Interfering Access Code Actual Sensitivity Actual Sensitivity Missed Detection Rate Actual Sensitivity Actual Sensitivity Actual Sensitivity Symbol Unit
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Table Reference Oscillator Electrical Specifications
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Crystal Frequency Range External Drive Frequency Range Oscillator Drive Level External Reference Crystal Reference Symbol fRefXTAL fRefXTAL Unit
Crystal Load Capacitance (Resonant Parallel) Maximum Crystal Equivalent Series Resistance (ESR) Typical Crystal Adjustment Range Recommended Crystal Tolerance over Temperature (-40 +85° Electronic Parallel Trim Capacitance Range
Figure
Electronic Parallel Trim Capacitance Resolution Oscillator Bias Current (R11/0) (R11/4) (R11/0) (R11/4) (R11/0) (R11/4)
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Electrical Characteristics
Table Reference Oscillator Electrical Specifications (Continued)
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Input Impedance XBASE (Reference Frequency MHz, R11/0 Parallel Capacitance Symbol Unit
Parallel Trim Capacitance
Parallel Resistance Input Phase Noise XBASE (Reference Frequency MHz, R11/0 Duty Cycle External Reference Input Bias Voltage (XBASE) Start-up Time (using Crystal)
dBc/ TWAIT
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-105 -110 -130
Table Power Oscillator Electrical Specifications
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Crystal Frequency External Drive Frequency Range Oscillator Drive Level coupled) External Reference Crystal Reference Crystal Load Capacitance (Resonant Parallel) XTAL Transconductance XTAL Output Resistance (XTAL_BB) Maximum Crystal Equivalent Series Resistance (ESR) Recommended Crystal Tolerance over Temperature (-40 +85°C) Oscillator Bias Current gmLP
RoLP
Symbol fLPXTAL fLPXTAL
32.768 32.768
Unit
VDD_BB mA/V
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Table Power Oscillator Electrical Specifications (Continued)
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Input Impedance EXTAL_BB Parallel Capacitance Parallel Resistance Duty Cycle External Reference Start-up Time (using Crystal) TLPWAIT Symbol Unit
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Table Data Clock Electrical Specifications
Note: (VCC_RF VDC, VDD_BB VDC, VDD_IO VDC, Reference Crystal MHz, Register settings according Figure unless otherwise noted. Figure Characteristics Internal Reference Frequency Data Clock Output Frequency Counter (R6/9-0) (Base Counter (R7/10-0) (Base Loop Filter Bandwidth Phase Detector Gain Constant Gain Constant
KVCO
Symbol
1200 15.9
4000 1023 2047
Unit
MHz/
Start-up Time External Reference Crystal Reference
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Electrical Characteristics
ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 following figure shows typical test circuit schematic.
VDD_CORE VDD_IO 3.3pF 10.5 deg, deg, 1.8pF deg, 15pF 15pF VCC_RF mounted 270pF 2.7nH 22pF Mounted VCC_RF
Female
PAOUT+ VDD_BB VDD_BB VDD_BB VDD_BB VDD_BB VDD_BB VDDINT VDD_IO RESET_BB CLK1 SSI_SCK SSI_FS SSI_STD SSI_SRD UART_TxD UART_RxD UART_CTS UART_RTS SPI1-MOSI SPI1-MISO SPI1-SCK SPI1-SS MODE_1 REFCTRL EXTAL_BB MNLF DCLF1
10.5 deg,
PAOUT-
100nF
100nF 100nF 100nF
RFIN
Female
33nF
Freescale Semiconductor, Inc.
BASEBAND
RADIO
XBASE XEMIT EPAEN EPADRV RFTEST+ RFTEST-
VCC_RF 100nF 15pF 15pF
13.000MHz Part W-168-179
VDD_CORE
10pF 32.768KHz 10pF 100K
VCC_RF_XTAL NC_1
VCC_RF
XTAL_BB OSC32k GPIO_BB_B10 GPIO_BB_B12 GPIO_BB_C9 TRST RTCK
VCC_PA VCC_LNA VCC_LIM VCC_DEMO VCC_PRE VDD_RF VCC_MOD VCC_MIX VCC_CP VCC_VCO VCC_DC NC_2 NC_3 NC_4 GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF
6.8pF 100nF 100nF 100nF 6.8pF 2.2nF 100nF
GND_BB GND_BB GND_BB GND_BB GND_BB GND_BB GND_BB GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF
MC72000
Figure Typical Test Circuit Schematic
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Package Pinout
Package Pinout
NOTE:
power small footprints critical certain applications. Therefore, input pins used must pulled high using internal pull-ups avoid floating nodes need external pull-up resistors. Unused pins also tied external appropriate logic voltage level (for example, either GND). Weak pull-ups available internally pins (100k ohms typical case), pull-downs available RESET_BB, TCK, TRST_B pins. Internal level-shifters used accommodate difference between voltages. This provides glueless interface peripherals.
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Assignment Listing
following table (Table shows assignment listing MC72000 pins organized into functional groups. Name Functionality columns show actual name brief description each pin, with respect ball assignment column Ball Power Group column lists Supply Power Group assignment. Type column shows type internal circuitry chip. Reset State column lists input/output direction chip RESET_BB. Alternate Function column lists each GPIO port alternate input output selections available. Some selections test- development-mode specific.
Table Names Functions
Ball Name VDD_BB GND_BB UART_TXD Functionality connected Baseband interface supply Baseband ground UART Transmit data Power Group CORE CORE Type Power line Power line Digital tri-state output Digital Reset State Alternate Function GPIO_C0 CSPI0_REQ XACK
GPIO_BB_C CLK1
General purpose
Programmable clock output
Digital
GPIO_C8 TIM_0_O
VDD_IO GND_IO VCC_DC DCLF1
port supply ground Data clock supply Data clock loop filter
Power line Power line Power line Analog output
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Package Pinout
Table Names Functions (Continued)
VDD_RF REFCTRL VDD_BB
logic supply reference clock control Baseband miscellaneous supply Baseband core supply UART Clear send
CORE CORE
Power line Digital output Power line
VDD_BB UART_CTS
CORE
Power line Digital tri-state output Digital
GPIO_C1 CSPI1_REQ GPIO_C6 ABORT GPIO_C2 TIM_0_I GPIO_B2 BT_TP2 GPIO_B5 BT_TP5
SPI1_MISO
SPI1 Master in/Slave
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UART_RXD
UART Receive data
Digital
SSI_STD
Serial transmit data
Digital
SSI_SRD
Serial receive data
Digital
VCC_CP GND_RF GND_BB
connected Frac-N charge pump supply front ground Baseband miscellaneous ground Buffered power 32.768 clock SPI1 Slave select
CORE
Power line Power line Power line
OSC32K
Digital
GPIO_C10 TIM_1_O GPIO_C4 SYSCLK GPIO_C5 SH_STROB GPIO_C7 REFCLK GPIO_B0/ GPIO_B3 BT_TP0/ BT_TP3 GPIO_B1/ GPIO_B4 BT_TP1/ BT_TP4 UART_TXD
SPI1_SS
Digital output
SPI1_SCK
SPI1 Serial clock
Digital output
SPI1_MOSI
SPI1 Master out/Slave
Digital
SSI_SCK
Serial clock
Digital
SSI_FS
Frame sync
Digital
GPIO_BB_B MNLF
General purpose
Digital
Main Frac-N loop filter
Analog output
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Table Names Functions (Continued)
GND_RF GND_RF GND_RF GND_RF GND_RF UART_RTS front ground front ground front ground front ground front ground UART Request send Power line Power line Power line Power line Power line Digital
Package Pinout
GPIO_C3 TIM_1_I UART_RXD
GPIO_BB_B VCC_RF_XT XEMIT VCC_VCO VCC_PRE GND_RF GND_RF GND_RF GND_RF GND_BB VCC_DEMO XBASE GND_BB VDD_BB GND_RF GND_RF GND_RF GND_RF GND_RF VDD_BB VCC_LIM MODE1
General purpose
Digital
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crystal oscillator supply
Power line
crystal oscillator emitter supply Frac-N prescaler supply front ground front ground front ground front ground Baseband ground connected demodulator supply Crystal oscillator base Baseband ground Baseband core supply front ground front ground front ground front ground front ground Baseband core supply limiter supply Baseband boot mode select
CORE CORE CORE CORE CORE
Analog output Power line Power line Power line Power line Power line Power line Power line Power line Analog input Power line Power line Power line Power line Power line Power line Power line Power line Power line Digital input
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Package Pinout
Table Names Functions (Continued)
VCC_MOD GND_BB VDD_BB GND_RF GND_RF GND_RF RTCK RESET_BB
modulation supply Baseband ground Baseband supply front ground front ground front ground JTAG Test clock output Baseband reset
CORE CORE CORE CORE
Power line Power line Power line Power line Power line Power line Digital output Digital Schmitt Trigger input Digital input Analog output
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RFTEST-
JTAG Test select negative differential monitor output (Reserved production factory test only. Leave open) mixer supply Baseband ground front ground front ground front ground front ground front ground positive differential monitor output (Reserved production factory test only. Leave open) JTAG Test mode select input connected supply power amplifier supply Baseband core supply front ground front ground front ground front ground
CORE
VCC_MIX GND_BB GND_RF GND_RF GND_RF GND_RF GND_RF RFTEST+
CORE
Power line Power line Power line Power line Power line Power line Power line Analog output
VCC_LNA VCC_PA VDD_BB GND_RF GND_RF GND_RF GND_RF
CORE CORE
Digital input Power line Power line Power line Power line Power line Power line Power line
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Table Names Functions (Continued)
XTAL_BB 32.768 baseband crystal clock output JTAG Test data input JTAG Test clock input CORE Digital output
Package Pinout
CORE CORE
Digital input Digital Schmitt Trigger input input ESD) Digital output
RFIN EPAEN
input External power amplifier enable positive differential output negative differential output General purpose output external driver output logic ground 32.768 baseband external crystal clock input JTAG Test reset
PAOUT+
output ESD) output ESD) Digital output Analog output
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PAOUT-
EPADRV
GND_RF EXTAL_BB
CORE
Power line Digital input
TRST_B
CORE
Digital Schmitt Trigger input Digital tri-state output
JTAG Test data output
CORE
Descriptions
following table provides detailed descriptions clock, reset, JTAG; Bluetooth; UART; UART, SPI1, including GPIO shared package pins. following table, general-purpose input/output (GPIO) designed share package pins with other peripheral modules chip. peripheral, which normally controls given pin, required, then programmed general-purpose input/output (GPIO) alternate function with programmable pull-up. GPIO module design available ports (Port Port individual control each normal functional mode, alternate function mode GPIO mode. individual direction control each GPIO mode. individual pull-up enable control each normal function mode, alternate function mode GPIO mode. Normal mode. peripheral module controls output enable output data input data from passed peripheral. Alternate function mode (GPIO). GPIO module controls output enable supplies data output. Alternate function mode. peripheral module controls output enable output data input data from passed peripheral.
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Package Pinout
ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 power supply pins including ground pins described following description list these pins share same name within three power groups. Refer Section "Applications Information," details isolate identify correct configuration power supply pins.
Table Descriptions
Signals DCLF1 MNLF Data Clock Loop Filter charge pump output external loop filter. Main Frac-N Loop Filter (Charge Pump). external loop filter referenced VCC_RF order minimize transmit phase noise. Reference oscillator emitter. bias current supplied internally emitter. This must left open external (not crystal) reference frequency used. Reference oscillator base. base reference oscillator input. on-chip capacitor trim network also included allow user relatively inexpensive crystals. This also feed-point case using external (not crystal) reference frequency. This factory only. must left open. This factory only. must left open. RFIN input LNA. bipolar cascode design. input base common emitter transistor. Minimum external matching required optimize input return loss gain. cascode output drives primary on-chip balun single-ended. Positive differential output. external differential-to-single-ended matching network desired. Negative differential output. external differential-to-single-ended matching network desired. External enable digital output which used enable external normally placed under sequence manager control. This output also used control external Rx/Tx switch requiring complementary drive. External driver output. Analog output ranges from 0.02 VCC_RF 0.02. EPADRV linearly scaled maximum VCC_RF General Purpose Output digital output. normally controlled internal sequence manager also programmable. This signal typically used control external Rx/Tx switch. Baseband Clock, Reset, JTAG Signals EXTAL_BB 32.768 baseband external crystal clock input. case using external clock, signal must this pin, while leaving XTAL open. 32.768 baseband crystal clock output. This must left open case using external clock. test data input provides serial input data stream controllers. sampled rising edge TCK. Leave open JTAG unused. test data output tri-statable, providing serial output data from Master Core controller. actively driven shift-IR shift-DR controller states controller state machine. changes falling edge TCK.
XEMIT
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XBASE
RFTEST+ RFTEST-
RFIN
PAOUT+ PAOUT-
EPAEN
EPADRV
XTAL_BB
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Table Descriptions (Continued)
TRST_B
Package Pinout
This active Schmitt trigger input provides asynchronously reset signal controllers initialize test controller. Leave open pull-down JTAG unused. test mode select input used sequence controllers. control module device port determine sequenced. sampled rising edge TCK. Leave open pull-up JTAG unused. test clock input used synchronize JTAG test logic. provides clock synchronize test logic shift serial data from controllers. Leave open JTAG unused. return test clock output returns synchronization test clock development tools entered from serial debug input line. test select input directly controls multiplexing logic select between chip core TAP. logic applied select input will select chip TAP. Leave open JTAG unused. Test/boot mode select pins. order support flexible development system, system must able boot from different memories during system reset power-up. This select four different memory maps, MODE0 hardwired internally. different boot modes start reading data address 0x0000_0000, since this where ARM7 reset vector located. reset active Schmitt trigger input that provides reset internal circuitry. RESET input will qualified valid will asserted least three cycles. Bluetooth Signals REFCTRL reference control dedicated output from clock reset module (CRM) which enables/ disables reference clock. UART Signals SSI_SCK Normal mode serial transmit clock signal used transmitter either continuous gated. normally used synchronous mode. signals internally connected chip this pin. precautions when configuring these signals, internal signals must configured comply with each other. GPIO_0 GPIO_3 Port signals internally connected chip this pin. precautions when configuring these signals, internal signals must configured comply with each other. Bluetooth test port signal. signals internally connected chip this pin. precautions when configuring these signals, internal signals must configured comply with each other.
RTCK
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MODE1
RESET_BB
GPIO_B0/ GPIO_B3
Alternate Function (GPIO)
BT_TP0/ BT_TP3
Alternate Function
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Package Pinout
Table Descriptions (Continued)
SSI_FS
Normal mode
serial transmit frame sync signal used transmitter synchronize transfer data. frame sync signal word length. signals internally connected chip this pin. precautions when configuring these signals, internal signals must configured comply with each other. GPIO_1 GPIO_4 Port signals internally connected chip this pin. precautions when configuring these signals, internal signals must configured comply with each other. Bluetooth test port signal. signals internally connected chip this pin. precautions when configuring these signals, internal signals must configured comply with each other.
GPIO_B1/ GPIO_B4
Alternate Function (GPIO)
BT_TP1/ BT_TP4
Alternate Function
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SSI_STD/GPIO_B2/BT_TP2 SSI_STD GPIO_B2 BT_TP2 Normal mode Alternate Function (GPIO) Alternate Function serial transmit data signal used transmit serial data. GPIO_2 Port Bluetooth test port signal.
SSI_SRD/GPIO_B5/BT_TP5 SSI_SRD GPIO_B5 BT_TP5 Normal mode Alternate Function (GPIO) Alternate Function serial receive data signal used receive serial data. GPIO_5 Port Bluetooth test port signal.
GPIO_B10/UART_TXD GPIO_B10 UART_TXD Alternate Function (GPIO) Alternate Function Note: Note: GPIO_10 Port Transmit data serial (output signal).
GPIO_B12/UART_RXD GPIO_B12 UART_RXD Alternate Function (GPIO) Alternate Function GPIO_12 Port Receive data serial (input signal). UART, SPI1, Signals UART_TXD/GPIO_C0 UART_TXD GPIO_C0 Normal mode Alternate Function (GPIO) UART transmit data serial (output signal). GPIO_0 Port
UART_CTS/GPIO_C1/SPI1_REQ UART_CTS Normal mode UART clear send (CTS) output signal, when asserted, indicates that MC72000 ready accept data remote device transmit when data send.
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Table Descriptions (Continued)
GPIO_C1 SPI1_REQ Alternate Function (GPIO) Alternate Function GPIO_1 Port External data transfer rate control SPI1.
Package Pinout
UART_RXD/GPIO_C2/TIM_0_I UART_RXD GPIO_C2 TIM_0_I Normal mode Alternate Function (GPIO) Alternate Function UART receive data serial (input signal). GPIO_2 Port Input signal timer
UART_RTS/GPIO_C3/TIM_1_I UART_RTS Normal mode UART ready send (RTS) input signal, when asserted, indicates that remote device ready accept data that MC72000 transmit when data send. GPIO_3 Port Input signal timer
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GPIO_C3 TIM_1_I
Alternate Function (GPIO) Alternate Function
SPI1_SS/GPIO_C4/SYSCLK SPI1_SS Normal mode Slave Select: This bi-directional signal output master mode input slave mode. GPIO_4 Port System clock used entire ARM7 platform peripherals attached bus. Some peripherals (for example, UART) will also this clock signal generate their module clock.
GPIO_C4 SYSCLK
Alternate Function (GPIO) Alternate Function
SPI1_SCK/GPIO_C5/SH_STROBE SPI1_SCK Normal mode This bi-directional signal clock output master mode. slave mode, SPI1_SCK input clock signal SPI. GPIO_5 Port Indicates data valid external when show cycle used.
GPIO_C5 SH_STROB
Alternate Function (GPIO) Alternate Function
SPI1_MISO/GPIO_C6/ABORT SPI1_MISO Normal mode Master Slave (MISO): master mode, this bi-directional signal input signal. slave mode, MISO output signal. GPIO_6 Port Indicates current memory access cannot completed.
GPIO_C6 ABORT
Alternate Function (GPIO) Alternate Function
SPI1_MOSI/GPIO_C7/REFCLK SPI1_MOSI Normal mode Master Slave (MOSI): master mode, this bi-directional signal output signal. slave mode, MOSI input signal.
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Package Pinout
Table Descriptions (Continued)
GPIO_C7 REFCLK
Alternate Function (GPIO) Alternate Function
GPIO_7 Port reference clock input (12-32 MHz).
CLK1/GPIO_C8/TIM_0_O CLK1 Normal mode Output external devices generated integer divider. CLK1 programmable clock derivative REFCLK. Frequencies programmable range REFCLK/64 REFCLK. CLK1 used feed external USB, CODEC, whatever device applications need. integer divider should divide REFCLK with 64). value disables timer. GPIO_8 Port Output signal from timer
GPIO_C8
Alternate Function (GPIO) Alternate Function
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TIM_0_O
GPIO_C9/XACK GPIO_C9 XACK Alternate Function (GPIO) Alternate Function GPIO_9 Port External acknowledge signal.
OSC32K/GPIO_C10/TIM_1_O OSC32K GPIO_C10 TIM_1_O Normal mode Alternate Function (GPIO) Alternate Function Buffered output from 32.768 on-chip oscillator. GPIO_10 Port Output signal from timer
VDD_RF VCC_CP MNLF VCC_VCO GND_BB VCCMOD VCC_MIX VCC_LNA RFIN
VDD_BB REFCTRL GND_RF GND_RF VCC_PRE VDD_BB GND_BB GND_BB VCC_PA EPAEN
GND_BB VDD_BB GND_BB GND_RF GND_RF GND_RF VDD_BB GND_RF VDD_BB PAOUT+
CLK1 SPI1_MISO SPI1_SCK GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF EPADRV
VDD_IO UART_RXD SPI1I_MOSI UART_RTS GND_BB GND_RF RTCK GND_RF GND_RF GND_RF
GND_BB SSI_STD SSI_SCK
VCC_DC SSI_SRD SSI_FS
DCLF1
GPIO_BB_B10
UART_TXD GPIO_BB_C9 VDD_BB OSC32K GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF PAOUT4 UART_CTS SPI1_SS GND_RF GND_RF GND_RF GND_RF GND_RF GND_RF
GPIO_BB_B12 VCC_RF_XTAL
XEMIT XBASE MODE1 RFTESTN/C
VDD_BB RESET_BB RFTEST+ XTAL_BB EXTAL_BB
VCCDEMO VCC_LIM TRST_B
Baseband pins
pins
Figure MC72000 Package Pinout (Top View)
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System Description
System Description
This section describes MC72000 system more detail than Section "System Overview." also includes section listing other documents relevance (see Section 5.2, "Document References").
MC72000 System Description
detailed MC72000 design shown block diagram Figure Note that voltages figure recommended setup MC72000, input frequencies clocks crystals Figure
VCC_RF VDD_BB 1.65 1.95 VDD_IO GPIO B10, MOSI, MISO,
Freescale Semiconductor, Inc.
MC72000
match
CMPLX
Limiter Demod
FILTER
Signal Processing Timing ARM7
GPIO Voice Processor UART
Rx/Tx switch
Data
CLK1
Microstrip balun External JTAG
Main
TXD, RXD,
Frac-N Synthesizer
Synthesizer Data
REFCTRL
Wakeup
filter
12-26 Ref.
filter
32.768
Figure MC72000 Block Diagram
following sections describe different blocks MC72000.
5.1.1 ARM7 Processor
MC72000 Bluetooth Baseband Controller architecture based 32-bit ARM7TDMI microprocessor. industry-standard processor recognized efficient MIPS/WATT benchmark, along with excellent code efficiency when working 16-bit THUMB mode. architecture based RISC principles supports instruction sets: 32-bit instruction 16-bit THUMB instruction
ARM7 processor handles high speed processing data link control management. MC72000 embedded containing full Bluetooth baseband upper stacks. ARM7 processor primarily executing code from handles device initialization, power control, protocol behavior, packet formatting.
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System Description
ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 program execution MC72000 Bluetooth Baseband Controller predominantly ROM-based, with internal data storage, application code, code patching. However, necessary download application software configuration data into from external interface. This done either individual files when needed, complete image power containing files from host system, from low-cost serial EEPROM (four-wire connection) connected serial peripheral interface (SPI).
5.1.2 Baseband Processor
baseband processor digitally demodulates signal output radio discriminator. Rather than immediately making threshold decision based amplitude signal, analyzes waveform shape over more than symbol before makes decision. This feature allows Maximum Likelihood Sequence Estimation Joint Detection algorithms (JD/MLSE) improve adjacent channel rejection signal acquisition. Without joint detection MLSE algorithms, possible have high sensitivity throughput because false/missing acquisitions high interference. Joint detection provides simultaneous frequency timing acquisition entire header rather than relying just synchronization portion.
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5.1.2.1 Bluetooth Link Controller
Bluetooth link controller module (BTLC) handles link controller specific functions. data read from/written module, BTLC takes care transmission-related timing, well data signal processing functions like encryption cyclic redundancy check (CRC)/header error correction (HEC) generation. Embedded BTLC also dedicated Bluetooth timers, which maintain accurate estimate time both native remote module. small, dedicated Bluetooth serial peripheral interface controller handles serial communication with radio part MC72000 Integrated Bluetooth Radio. functionality baseband will elaborated Section "Bluetooth Baseband Functionality Overview."
5.1.3 Bluetooth Radio
design based Motorola's third-generation Bluetooth architecture that industry standard interoperability, complete functionality, compliance with Bluetooth specification. radio portion MC72000 exhibits superior performance with small size cost. minimum external components required complete link Bluetooth system, while maintaining superior performance.
5.1.3.1 Receiver
receiver low-IF frequency type using analog image cancellation. either high-side low-side injection that image will fall within band when frequency received edge band. integrated Bluetooth baseband automatically decides high-side low-side injection receiver, based active receive channel. low-power integrated exhibits excellent sensitivity noise rejection performance, which further improved total system solution using JD/MLSE baseband signal processing.
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5.1.3.2 Transmitter
System Description
shape transmit pulse required Bluetooth specification controlled look-up table that directly modulates high frequency accuracy main fractional VCO. gain transmitter adjustable, connections controlling external provided Class operation. output differential and, therefore, requires balun that implemented stripline using discrete balun. controls external antenna switch, which automatically internal sequence manager, therefore requires baseband interruption. transmitter section direct launch transmitter operating directly transmit frequency, out-of-band spurious emissions reduced minimum comply with sensitive environments strict requirements other applications like cell phones, PDAs, computer accessories.
5.1.4 Clock Reset Module
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clock reset module (CRM) dedicated handling clock, reset, power management features MC72000 Bluetooth Baseband Controller.
ensures that different clock reset signals stable before they internal logic MC72000 Bluetooth Baseband Controller. designed make full facilities supplied Bluetooth standard conserve power, while still maintaining Bluetooth link. reference clocks used drive MC72000: power mode (32.768 kHz), accurate transmit, receive, timing operation. Reference frequency chosen cover great variety typical reference frequencies used cell phones, PDAs, other equipment. This internal data clock ensuring that ARM7 processor always runs correct frequency. internal crystal oscillator that feeds clock data clock radio portion covers full supply temperature range with very low-noise trimable reference frequency based external crystal. oscillator also driven using external reference clock from other applications with minimum load external application. module also includes watchdog safeguard against potential software failures.
5.1.5 High-Speed UART
universal asynchronous receiver/transmitter (UART) module provides main interfaces MC72000 Bluetooth Baseband Controller. generated baud rate based configurable divisor input clock. UART transmit receive buffer sizes bytes each.
5.1.6 High-Speed CSPI
MC72000 Bluetooth Baseband Controller contains configurable serial peripheral interface (CSPI) module, CSPI1. CSPI1 connected variety SEEPROM serial flash devices. They described Section 10.8.7, "Possible EEPROM Types." CSPI module master/slave configurable, equipped with byte data buffers (transmit receive FIFOs), allows MC72000 Bluetooth Baseband Controller interface with external CSPI master slave devices. enables fast data communication with fewer number software interrupts incorporating SPIRDY control signals.
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System Description
5.1.7 High-Speed
synchronous serial interface module (SSI) full-duplex serial port allowing digital signal processors (DSPs) communicate with variety serial devices, including industry-standard CODECs, other DSPs, microprocessors, peripherals. typically used transfer samples periodic manner consists variety registers that handle port, status, control, transmit receive, serial clock generation, frame synchronization.
5.1.8 Bluetooth Audio Signal Processor
High audio quality great importance user. Section 10.9, "Audio," describes audio features. dedicated Bluetooth audio signal-processing module (BTASP) been designed give users superior audio performance. BTASP module handles filtering, interpolation, well encoding/decoding with minimum processor intervention.
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internal voice-processing unit converts 16-bit voice data compressed voice data uncompressed voice. Compression modes A-Law, µ-Law, CVSD. performs filtering accepts CODEC rates kbits/sec. external CODEC connected synchronous serial interface (SSI) required voice processing, needed.
5.1.9 Timer
dual timer module (TMR) general purpose module, used timing control application-specific tasks. also configured perform pulse width modulation (PWM) into quadrature-count mode needed. contains identical 16-bit counter/timer groups, each which supports counting, prescaling, comparing, loading, capturing, holding options.
5.1.10 General Purpose Input/Output
MC72000 Bluetooth Baseband Controller supports maximum GPIO lines grouped ports. Port contains lines, Port contains lines. These ports configured GPIO pins dedicated peripheral interface pins.
5.1.11 JTAG Test Interface Controller
JTIC interface offers full JTAG boundary scan capabilities debug production test purposes, well access JTAG interface ARM.
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Document References
following list documents providing additional information implementation guidance different systems. MC72000-related documents: Motorola Bluetooth File System, Overview Application Note (document number 94001481001) Motorola Bluetooth File System, Host-based General Application Note (document number 94001481003) Motorola Bluetooth File System, Host Based File Application Note (document number 94001481004) Motorola Bluetooth File System, Embedded File System Application Note (document number 94001481002)
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Motorola Bluetooth Solutions, Bluetooth Qualification Application Note (document number AN2386/D) UART/SSI Configuration Guide (document number 94001481900) Vendor-Specific Reference (public) (document number 79000001800). Specification Bluetooth System Feb. 2001, v.1.1)-official book available from: http://www.bluetooth.com. Implementation-related documents: Bluetooth File System File Formats Application Note (document number 94001481200). MC72000 Implementation Cellular Phones Application Note (document number 94001481800) MC71000/MC72000 Wake-Up, Reset, Host Clock Request Sequences Application Note (document number AN2340/D) Production Test Application Note (document number 94001481100)
Radio Functional Description
NOTE:
following description, control bits contained MC72000 Radio Register various functions will identified register number number(s). example, R4/8 references register while R5/9-3 identifies bits through inclusive, register (decimal notation). Unless otherwise noted, default register configuration listed Figure assumed. information contained this section will describe detail calculate find appropriate values MC72000 Radio Register your specific setup. information that concerns radio performance ability function, consisting MC72000 Radio Register Main Synthesizer Channel Table, gathered assembled File410x.vfs Motorola Bluetooth File System. Refer Section 5.2, "Document References," details file system.
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Radio Functional Description
Receive Chain
MC72000 placed into receive mode from idle mode asserting internal RXTXEN master signal after setting Radio Receive Enable (R2/13), clearing Radio Transmit Enable (R2/14), clearing Radio Narrow Bandwidth Enable (R2/12). data represents 6-Bit, 2's-complement digital value sampled four times every data bit. Once receive cycle complete, RXTXEN master signal radio deasserted MC72000 begins internal power down sequence. This controlled internal baseband processor. receive chain optimized provide high adjacent channel rejection, which most important specification high interference environment. This accomplished setting bandpass filter then using Maximum Likelihood Sequence Estimation (MLSE) baseband processing remove effects intersymbol interference. voltage interface used between radio baseband processor. baseband synchronizes radio timing through master RXTXEN signal radio. logic transition this signal indicates beginning idle state, while logic high transition indicates either transmit receive cycle.
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Transmit Chain
MC72000 placed into transmit mode from idle mode setting Radio Transmit Enable (R2/14), setting Radio Narrow Bandwidth Enable (R2/12), clearing Radio Receive Enable (R2/13) Radio Register Map, then asserting RTXEN device. Once data stream been transmitted, RTXEN deasserted MC72000 begins internal power down sequence. Since power still present output, operations additional cycles between radio baseband processor performed until certain amount time passed after deassertion RXTXEN. this time, power substantially enough level produce undesired emissions. internal baseband processor also handles this timing.
Receiver
MC72000 receiver intended used Time Division Duplex (TDD), Frequency Hopping Spread Spectrum (FHSS) Bluetooth applications. receiver uses intermediate frequency (IF) capable receiving Mbit/s Gaussian Frequency Shift Keyed (GFSK) serial data through entire Industrial, Scientific, Medical (ISM) band. output receiver demodulated, serial stream Mbit/s data. This data represents over sample 6-bit actual demodulated analog data recovered from desired channel. detailed discussion each functional blocks within receiver provided following sections.
6.3.1
first portion receiver chain Noise Amplifier (LNA). bipolar cascode design provides gain with noise frequencies. designed with single-ended (unbalanced) input converted differential (balanced) output means on-chip, integrated balun. optimum performance, input impedance must matched complex conjugate source impedance (usually MC72000 exhibits distinctly different impedances depending upon whether active disabled. During receive cycle, shown Table
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Table During Receive
Frequency 2.45 (dB) Angle (degree)
matched simple capacitor/inductor network shown Figure
CBlock Cmatch Lmatch
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Figure Simple Capacitor/Inductor Network
When disabled device Idle Transmit mode, impedance becomes value shown Table
Table Disabled
Frequency 2.45 (dB) Angle (degree)
antenna switch interface with antenna preferred circuit configuration shown Figure this implementation, true Single-Pole, Double-Throw (SPDT) switch used isolate output from input during receive transmit modes. wavelength trace required. result, this implementation highest performance (due lowest loss) smallest size penalty increased system cost. external switch must used Class Bluetooth devices input will become overloaded sufficiently isolated from external output. provides nominal power gain when properly matched. enabled approximately after assertion RTXEN when programmed Receive mode. disabled immediately after deassertion RTXEN during Idle Transmit mode.
6.3.2 High/Low Image Reject Mixer (I/R Mixer)
mixer used convert desired channel Intermediate Frequency (IF). mixer completely balanced ports, local oscillator (LO) derived from buffered output on-chip voltage controlled oscillator (VCO). general, desirable keep image frequencies in-band. Therefore, when receiving lowest channels, mixer programmed high-side injection will programmed above desired channel frequency. When receiving highest channels, mixer programmed low-side injection, will programmed below desired channel frequency. This shown Figure Selection high side injection accomplished R2/11 register map. other in-band channels, choice high side injection arbitrary. baseband uses high-side injection frequencies 2.441-GHz inclusive low-side injection thereafter.
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Radio Functional Description
Image
High-side injection (R2/11=1) Image
Low-side injection (R2/11
Figure High-Side Low-Side Mixer Injection
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mixer delivers approximately 15.8 voltage gain image rejection.
mixer enabled approximately after assertion RTXEN when programmed Receive mode. disabled immediately after deassertion RTXEN during Idle Transmit mode.
6.3.3 Bandpass Filter (BPF)
bandpass filter used block undesired channels. filter self-adjusting calibrated during each receive cycle, based internally generated signal. gain filter fixed nominal pass band filter kHz. This deliberately pass band cause significant intersymbol interference (ISI) issues GFSK modulated signal with Mbit/s data rate. advantages increased sensitivity, adjacent channel interference performance, ease manufacture. this pass band, digitally implemented decoder scheme utilized eliminate ISI. This referenced JD/MLSE incorporated into Motorola Bluetooth basebands. enabled approximately after assertion RTXEN while programmed Receive mode automatic tuning complete after approximately disabled immediately after deassertion RTXEN during Idle Transmit mode.
6.3.4 Limiter with Received Signal Strength Indicator (RSSI)
received signal strength indicator (RSSI) integrated into limiter. RSSI converts RSSI current into 4-bit digital signal. When RSSI enable (R4/6) RSSI Read Enable (R9/8) both set, 4-bit RSSI conversion value read from MC72000 Radio Register (R29/3-0) while Idle mode. RSSI updated approximately after receiving first receive cycle. Enabling RSSI will result additional current consumption noted Receiver Electrical Specifications shown Table Figure shows RSSI conversion value versus level input various temperatures. Figure shows RSSI conversion versus level different power supplies.
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LEVEL RFIN (dB)
85°C 55°C
LEVEL RFIN (dB)
25°C
-20°C
25°C
-40°C
RSSI CONVERSION VALUE
RSSI CONVERSION VALUE
Freescale Semiconductor, Inc.
Figure Level RSSI Temperature
Figure Level RSSI VCCRF
6.3.5 Demodulator
receiver MC72000 down converts signal demodulates demodulator takes signal from limiter delivers baseband signal converter (ADC). 6-bit uses Redundant Sign Digit (RSD) Cyclic architecture that samples analog input Msamples/s. resulting demodulated data MC72000 Mbit/s, 2's-complement serial stream. start each 6-bit data stream indicated frame sync (FS) signal internal baseband processor. clock output accompanies demodulated data.
6.3.5.1 Receiver Characteristics
optimum intermodulation performance, MC72000 GND_RF pins require good conduction ground layer. Figure through Figure show typical performance receiver various conditions.
CONTINUOUS WAVE INTERFERING SIGNAL POWER LEVEL (dBm)
CONTINUOUS WAVE INTERFERING SIGNAL FREQUENCY (GHz)
Figure Receive Sensitivity Temperature
Figure Blocking Performance Continuous Wave Interfering Signal
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Radio Functional Description
INTERFERER LEVEL (dBc) INTERFERER FREQUENCY DELTA (MHz)
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Figure Performance Channel (2.405 GHz, High-Side Injection)
INTERFERER LEVEL (dBc) INTERFERER FREQUENCY DELTA (MHz)
Figure Performance Channel (2.477 GHz, Low-Side Injection)
INTERFERER LEVEL (dBc) INTERFERER FREQUENCY DELTA (MHz)
Figure Performance Channel (2.405 GHz, High-Side Injection)
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INTERFERER LEVEL (dBc) INTERFERER FREQUENCY DELTA (MHz)
Figure Performance Channel (2.405 GHz, High-Side Injection)
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INTERFERER LEVEL (dBc) INTERFERER FREQUENCY DELTA (MHz)
-40°
Figure Performance Temperature
Transmitter
MC72000 uses direct launch transmitter taken from output local oscillator (LO). During transmit cycle automatically trimmed. Following output power stages, sequenced proper order. minimize splattering, output programmable power amplifier (LPA) drives balanced ramp up/ramp down generator, which "Balun" provide single-ended output external antenna switch. transmit start up/warm down sequences shown Figure
6.4.1 Transmit Synchronization Delay
programmable delay exists between rising edge RTXEN first available on-the-air data during transmit cycle. This delay range TXsync Radio Register bits Transmit Synchronization Time Delay Value (R8/15-8) where decimal value represents delay microseconds. Packet data seen antenna approximately after this delay. Bluetooth packets require minimum four preamble bits pattern 0101 1010. minimum power consumption, delay TXsync minimum. additional settling time preamble bits required, manipulate delay necessary, TXsync maximum.
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Radio Functional Description
6.4.2 Main Synthesizer Operation
internal local oscillator (LO) MC72000 derived from external reference frequency means 3-accumulator, fractional-N synthesizer. external pass filter (C14/R1 Figure corner frequency approximately kHz. external pass filter requires three passive components, dependent reference frequency. fdev nominal transmit frequency deviation (typically 157500 Hz). integer portion fractional synthesizer. numerator portion fractional synthesizer. frefExternal external reference frequency. desired local oscillator frequency then, (LO/frefExternal fdev/frefExternal) REM(LO/frefExternal fdev/frefExternal) where function integer portion result remainder portion result.
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example shown below: fdev 157500 2.441 frefExternal then, INT(2.441 GHz/13 157.5 kHz/13 MHz) 18410 REM(2.441 GHz/13 157.5 kHz/13 MHz) 4961810 Accuracy least decimal places suggested.
6.4.3 Transmit Operation
MC72000 uses look-up table (LUT Transmit ROM) shape incoming transmit data bits produce Gaussian filtered mask with BT=0.5. value current data bit, along with knowledge previous bits, determines unique trajectory shaping. Only four unique trajectories required implement this filter, symmetrical nature Gaussian response, these trajectories reduced single quadrant. Furthermore, without compromising accuracy, this table reduced only values. output accumulators fractional synthesizer. seven MSBs eventually second port main during transmit operation (see Figure 17). receive operation, output constantly held value contained R1C1. These trajectory constants listed Table (see also Figure Radio Register Map). actual value place calculated RxCxb10 (fdev/frefExternal) (RxCx constant) This number then rounded converted binary: RxCxb2 INT((LUT RxCxb10+2)/4) where function integer portion result. example calculating value R4C2 frefExternal MHz: R4C2b10 (157.5 kHz/13.0 MHz) 0.5229292198 415.2
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ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 R4C2b2 INT((415.2+2)/4) INT(104.3) 011010000 68b16
following table lists values RxCx supported reference.
Table RxCx Constants
R1C1 R2C2 R2C3 R2C4 R3C1 R3C2 0.9999739537 0.9980246857 0.9911665663 0.9678427310 0.1881990082 0.5249014674 0.7660791186 0.9043672052 0.5229292198 0.7572459756 0.8722099597
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R3C3
R3C4 R4C2 R4C3 R4C4
6.4.4 M-Dual Port Multiplier B-Dual Port Multiplier
proper operation dual-port synthesizer, necessary maintain constant deviation injection input Port VCO. appears from Transmit operation Figure output digital multiplier prior being presented input modulation DAC. Since values decrease proportionately with input reference frequency, multiplier must scale these values achieve constant deviation. This scaling linear. programmable constants used form equation line, dual-port multipliers. M-Dual Port Digital Multiplier Value (R17/ 15-8), determines slope, B-Dual Port Digital Multiplier Value (R8/7-0), determines intercept. M-Dual Port Digital Multiplier (frefExternal) 10810 B-Dual Port Digital Multiplier (frefExternal) 9710 Table contains slope intercept point values across supported input reference frequencies.
6.4.5 Dual-Port Programmable Delay (R7/15-11)
necessary maintain constant deviation Port2 VCO. Likewise, necessary maintain constant phase inputs main charge pump. total delay from output input charge pump given follows: delay 10.5 (frefExternal) Likewise, total delay from input charge pump follows: delay Delay where delay programmed delay value shown Table Therefore, given external reference frequency: Delay 10.5 (frefExternal)
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Radio Functional Description
ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 Consult Table closest available value.
Table lists values programmable delay supported reference frequencies.
Table Dual-Port Programmable Delay Values
R7/15-11 (decimal) Delayb10 (ns) R7/15-11 (decimal) Delayb10 (ns)
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Table Register Settings Component Values Reference Frequency
Note: Fref= Fref= Fref= 14.40 Fref= 15.26 Fref= 16.80 Fref= 19.22 Fref= 19.44 Fref= 19.68 Fref= 19.88
(All register setting values notation) Fref=
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Register
Data (R6/9-0)
Data (R7/10-0)
R1C1 (R12/7-0)
R2C2 (R12/15-8)
R2C3 (R13/7-0)
R2C4 (R13/15-8)
R3C1 (R14/7-0)
R3C2 (R14/15-8)
R3C3 (R15/7-0)
R3C4 (R15/15-8)
R4C2 (R16/7-0)
R4C3 (R16/15-8)
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R4C4 (R17/7-0)
M-Dual Port Multiplier (R17/15-8)
B-Dual Port Multiplier (R8/7-0)
Dual Port Programmable Delay (R7/15-11)
(pF)
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Table Register Settings Component Values Reference Frequency (Continued)
Fref= Fref= Fref= 14.40 Fref= 15.26 Fref= 16.80 Fref= 19.22 Fref= 19.44 Fref= 19.68 Fref= 19.88
Note:
(All register setting values notation) Fref=
Register
Radio Functional Description
(pF)
MC72000 Advance Information Data Sheet More Information This Product, Preliminary www.freescale.com Figure Main Synthesizer Block Diagram
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6.4.6 Programmable
output power varied programming Bias Adjust (R5/2-0) register map. Table displays response output power, current consumption Harmonic power level with respect programmable settings. Class operations supported through external power amplifier shown here. Refer Section 10.6, "Class Operation," more detail. Figure Figure provide additional characteristic data. also includes ramp generator which exponential ramp up/ramp down function with maximum settling time Increasing output power exponentially useful avoid splattering minimize load pulling.
6.4.7 External Balun
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provides differential output that converted single-ended signal through inexpensive printed circuit board balun. Optionally, external discrete balun used. Figure Figure show physical dimensions characteristics this network. Table shows output impedance, during active inactive cycles.
Table Power Bias Adjust
Bias Adjust R5/2 R5/1 R5/0 Output Power (dBm) Current Consumption (Continuous Transmit)(mA) Harmonic (dBc)
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Figure Output Power Carrier Frequency
Figure Output Power Temperature
Figure Balun Physical Dimensions Table During Transmit
Note: (R5/2-0 010)(Measured Differential-Ended) Operation Mode Active Inactive Frequency (GHz) 2.45 2.45 (dB) Angle (degree)
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Crystal Oscillator
crystal oscillator provides reference data clock main PLL. configured Colpitts type (negative resistance) oscillator utilize external parallel resonant crystal driven from external source. oscillator circuit on-chip capacitor trim network that provides capability compensate crystal and/or load capacitor tolerances. This allows relatively inexpensive crystals with much tolerance. oscillator also provides three bias current modes. Xtal Enable (R11/0) enables/disables bias current Xtal Boost Enable (R11/4) enables/ disables high current mode. Refer Reference Oscillator Electrical Characteristics Table available current modes. Table gives examples parallel trim capacitances that programmed register location Xtal Trim (R6/14-10). Typical stray capacitance order drive oscillator with external source, program Xtal Enable (R11/0) zero AC-couple external signal into oscillator base with capacitor. also recommended Radio Xtal Trim (R6/14-10) zero reduce load external source. external source either sine square long AC-coupled keeps requirements phase noise, amplitude, duty cycle Table Additional characteristic data shown following figures.
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Table Examples Programmable XTAL Trim Capacitances XTAL Trim (R6/14-10) Setting (MSB left) 00000 00100 10000 10101 11111 Electronic Parallel Crystal Trim Capacitance (CPT)
OSCILLATOR NEGATIVE RESISTANCE
OSCILLATOR OPEN LOOP GAIN (dB)
-100 -150 -200 -250 -300 -350 25°C -20°C 85°C
Figure 25°C Open Loop Gain Measurements Crystal Load Capacitance Electronic Trim (R6/14-10) (decimal)
Figure 25°C Curve Measured with Crystal Reference Crystal Load Capacitance Ratio (C15/C16)
CRYSTAL CAPACITOR RATIO (C5/C8)
ELECTRONIC PARALLEL CRYSTAL TRIM (R6/14-10)
Figure Oscillator Open Loop Gain Capacitor Ratio
Figure Oscillator Negative Resistance Electronic Parallel Crystal Trim (CPT) (Crystal Boost Enable R11/4)
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Radio Functional Description
-100 -110 -120 -130
OSCILLATOR NEGATIVE RESISTANCE
-200 -400 -600 -800 -1000 -1200 -1400 85°C 25°C -20°C
OSCILLATOR NEGATIVE RESISTANCE
Figure 25°C Curve Measured with Crystal Reference Parallel Crystal Trim (R6/14-10) (decimal)
Figure 25°C Curve Measured with Crystal Reference Crystal Load Capacitance Ratio (C15/C16)
ELECTRONIC PARALLEL CRYSTAL TRIM (R6/14-10)
CAPACITOR RATIO (C5/C8)
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Figure Oscillator Negative Resistance Electronic Parallel Crystal Trim (CPT) (Crystal Boost Enable R11/4)
Figure Oscillator Negative Resistance Crystal Capacitor Ratio (Crystal Boost Enable R11/4)
CRYSTAL FREQUENCY PULLING (Hz)
CRYSTAL START-UP TIME (ms)
Figure 25°C Crystal Reference
-200 -400 -600
Figure 25°C Crystal Frequency Delta measured relative initial frequency R/14-10 (decimal).
CAPACITOR RATIO (C5/C8)
ELECTRONIC PARALLEL TRIM VALUE (R6/14-10)
Figure Crystal Start-up Time Capacitor Ratio
Figure Crystal Frequency Pulling Electronic Parallel Trim Value
Data Clock Operation
data clock phase lock loop responsible providing constant reference throughout device. MC72000 uses simple integer-N synthesizer derive clock (CLK) from reference frequency. This allows MC72000 adapt external reference oscillator crystal range MHz. counter values must always appropriate values generate this clock frequency. general model phase lock loop (PLL) shown Figure circuit Figure external pass filter loop filter bandwidth (LBW) kHz. This proves adequate value external reference frequency that integral multiple kHz. external pass filter requires capacitor. More details about loop filters obtained from Improved Design Method Application Note (document number AN1253/D). R-counter synthesizer (R6/9-0) value which will internal reference frequency frefInternal kHz; thus, frefInternal/20 kHz. N-counter synthesizer (R7/10-0) multiply frefInternal MHz; thus MHz/frefInternal. case external reference, 65010 =120010.
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ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 applications utilizing frefInternal MHz, external pass filter with corner frequency still usable. However, counter limitations, counter programmed generate frefInternal (recommended). case external reference other frequencies above MHz, 65010 60010.
counters only divide integer values greatest common divider must found represent frefInternal achieve CLK. Table provides appropriate values various frefInternal. applications requiring faster data clock response time, refer data clock electrical characteristics Improved Design Method Application Note (document number AN1253/D) Additional data clock characteristic data shown Figure Figure
Table Data Clock Counter Values frefInternal with
frefExternal (MHz) frefInternal (kHz) Counter (Decimal) Counter (Decimal) 1200 1200 1200 1200 1200 1200 1200 (kHz)
Freescale Semiconductor, Inc.
14.4 16.8 19.22 19.68 19.88
frefExternal
frefInternal
Phase Detector (Kpd)
Filter (Kf)
(KVCO)
Divider (Kn)
Figure General Model
Where: Phase Detector Gain Constant Loop filter transfer function KVCO Gain Constant Divide Ratio (1/N) frefInternal Input Frequency Output frequency fo/N Feedback frequency divided
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DATA CLOCK START-UP TIME (ms)
Externally Driven frefExternal 25°C
DATA CLOCK START-UP TIME (ms)
Figure 25°C frefExternal Crystal frefInternal
frefInternal (MHz)
CAPACITOR RATIO (C5/C8)
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Figure Data Clock Start-up Time frefInternal
Figure Data Clock Start-up Time Capacitor Ratio Crystal Reference
External Antenna Switch
external antenna switch, shown Figure provides isolation between output input subsequently enables transmit receive cycles. controls switch EPAEN, pins respectively, MC72000 device. When high, switch transmit mode. EPAEN serves complementary driver this configuration. Section "Applications Information," further information.
General Purpose Output (GPO)
MC72000 general purpose output (GPO) located device. output programmed general setting R2/8 Radio Register Map. serve control line external antenna switch.
External Power Amplifier Enable (EPAEN)
External Power Amplifier Enable (EPAEN) output MC72000 located device. EPAEN used applications. assist Class Operation driving external power amplifier; serve complementary driver dual port antenna switch shown Figure EPAEN required desired application, disabled setting R11/6 zero.
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RTXEN
EPADAC (R9/7 (Antenna Switch)
EPAEN (R11/6
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Internal Enable
Power Ramp Transmit Sync Delay (R8/15-8 18410) 18410
Figure Ramp Generator (Transmit Cycle) Timing Diagram
Hardware Functional Description
These hardware blocks will described following sections: Clock reset module (CRM) UART Interface Interface interface
Clock Reset Module (CRM)
Clock Reset Module (CRM) dedicated module handle clock reset functions MC72000. assures that different clock reset signals stable synchronized before they internal logic MC72000.
7.1.1 Features
following features: Controls system reset Sleep mode management Timer recording sleep mode active period initiating wake
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Watchdog (COP) surveillance Clock control generation Software-initiated system reset
7.1.2 Modes Operation
Power After module will delay release oscillator clock rest system until oscillator time stabilize. After core begins operating, will control switch over REFCLK signal. Normal Operation MC72000 system clock operates 12-32 reference clock (REFCLK) from radio. Sleep Operation During sleep mode, high frequency reference clock from radio will turned off, only clock will used clock vital parts module. Sleep mode initiated setting Wake Control register. Sleep mode ended either internal wake timer four external wake interrupts.
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7.1.2.1 External Clock Control Register
module generates derivatives REFCLK. frequencies these clocks programmable range ~500 REFCLK. resulting clocks named CLK0 (fractional divided), CLK1 (integer divided) output pads. These clocks used feed external devices such USB, CODEC, whatever final system application needs. duty cycle CLK0 CLK1 cannot expected 50/50 because nature REFCLK from well additional changes introduced clock divider circuitry. external device using CLK0 CLK1 should held reset whenever frequency these clocks changed because periods unstable some time immediately after change request. Because external clocks operate independently, there implied phase relationship between CLK0 CLK1 their divisors same integer multiples. These clocks will stopped sleep mode because they derivatives REFCLK which also stopped sleep mode. CLK1_DIV[3:0] Clock1 Divisor CLK1_CNTRL register controls integer division REFCLK generate CLK1 output signal. CLK1 output will when CLK1_DIV disabled.
Table CLK1_DIV Values
Value Divisor CLK1 Disabled (Low) divide divide divide divide divide divide divide refclk Duty Cycle REFCLK dependent 50/50 50/50 50/50 50/50 50/50 50/50
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Universal Asynchronous Receiver/Transmitter (UART)
7.2.1 Overview
UART transmits receives character length eight bits. transmission, data passed transmitter FIFO (first first out), bytes/characters depth, from peripheral data bus. This data passed shift register shifted serially pin. reception, data received serially from stored receiver FIFO bytes/characters depth. received data retrieved from receiver FIFO peripheral data bus. receiver transmitter FIFOs contain maskable interrupt that configured interrupt when reaches certain level. UART-generated baud rate based upon configurable divisor input clock. configured send stop bits well odd, even, parity. receiver detects framing errors, start errors, breaks, parity errors, overrun errors.
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fractional divider writing INCrement MODulo value registers. important that UART disabled (RXE equal before writing values INC/MOD registers. After writing registers, receiver and/or transmitter enabled (RXE equal
NOTE:
When UART disabled (RXE equal both buffers flushed, status register updated. test purposes, pins connected internally each other loop-back test.
7.2.2 Features
UART provides following features: data bits stop bits Programmable parity (even, odd, none) Four-wire serial interface (RXD, TXD, RTS, CTS) Hardware flow control support signals Sense programmable RTS/CTS pins (high true/low true) Status flags various flow control FIFO states Voting logic improved noise immunity (16X/8X oversampling) maskable interrupts (IPI_RXRDY, IPI_TXRDY) Time-out interrupt timer, which times after eight non-present characters (interrupt RXRDY) 32-byte receive FIFO 32-byte transmit FIFO Receiver transmitter enable/disable Low-power modes Fractional divider generate baud rate between 1,200 baud 1,843.2 kbaud Software reset
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7.2.3 Fractional Divider
high-speed UART clocked with clock MC72000 typically MHz). This high frequency clock plus internal fractional divider enables wide range frequencies that calculated using following equations: times oversampling mode (xTIM=0 UART control register), following equation used calculate baud rate.
audrateX16 ipsclk -MOD baudrate baudrateX16
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times oversampling mode (xTIM=1 UART control register), following equation used calculate baud rate.
baudrateX8 ipsclk -MOD baudrate baudrateX8
internal baud rate generator shown Figure
Fractional Divider
UBRINC
IPG_CLK
Divide UBRMOD
Baud Rate Sample Clock
Figure UART Baud Rate Generator
Values that yield standard baud rates input clock MHz/12 shown Table
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Table Standard Baud Rates1
IPSCLK Baud Rate 1,200 2,400 4,800 9,600 19,200 28,800 38,400 57,600 115,200 230,400 460,800 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 1535 3071 6143 61432 FREQ 1,200 2,400 4,800 9,600 19,200 28,800 38,400 57,600 115,200 230,400 460,800 921,600 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 14000 1,535 3,071 6,143 86013 FREQ 1,200 2,400 4,800 9,600 19,200 28,800 38,400 57,600 115,200 230,400 460,800 921600 1843285.7
IPSCLK
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921,600 1,843,200
Fractional divider values shown times oversampling mode. this baud rate, only oversampling possible because MHz/921600) this baud rate, only oversampling possible because MHz/1843200)
7.2.4 General UART Definitions
These general UART definitions will help understanding following sections. Start start logic zero which indicates beginning data frame. start must begin with zero transition preceded least time logic one. Stop stop logic which indicates data frame. stop follows data parity bit. They mark unit transmission (normally byte character). Break frame longer with RX/TX held logic zero. This kind frame generally sent signal message beginning message. Frame frame consists start followed specified number data information bits terminated stop bit. number data information bits depends format specified must agree between transmitting device receiving device. most common frame format start followed eight data bits (LSB first) terminated stop bit. Framing Error error condition which stop received frame missing. framing error results when frame boundaries received stream synchronized with receiver counter. Framing errors always detected: data expected stop time happens logic one, framing error undetected. framing error always present receiver side, when transmitter sending breaks. However, UART expect stop bits, only first stop received, then this framing error. Parity Error error condition which calculated parity received data bits frame different from parity received line. Parity error only calculated after entire frame received.An additional stop parity also included.
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MC71000 Remote
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NOTE:
above signals assume control (FCe) (enabled control) (FCp) (active RTS/CTS signals).
Figure General UART Connection
7.2.4.1 Request Send
This input used control transmitter. asserting RTS, far-end device signals UART that ready receive. Normally, transmitter waits until this signal active (low) before character transmitted. Flow Control Enable (FCE) disabled, transmitter sends character whenever character ready transmit. When flow control enabled, signal configured either stop transmission upon assertion enable transmission upon deassertion.
7.2.4.2 Clear Send
This output used control transmitter remote device. Normally, receiver indicates that ready receive data asserting this (low). When enabled, this signal controlled watermarks RXFIFO.
7.2.4.3 Transmitter
transmitter accepts parallel character transmits serially. When transmitter enabled, start, stop, parity enabled) bits added character. used flow-control serial data desired. negated (high), transmitter finishes sending character progress any) then stops waits again become asserted (low).
7.2.4.4 Receiver
receiver accepts serial data stream converts into parallel character.When enabled, searches start bit, qualifies then samples succeeding data bits bit-center. Jitter tolerance noise immunity provided sampling rate using voting techniques clean samples. Once start been found, data bits, parity enabled), stop bits shifted parity enabled, checked status reported USTAT register. Similarly, frame errors breaks checked reported. CTS_LEVEL zero, receiver ready interrupt flag (RXRDY) will
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7.2.4.5 Receiving Break Condition
Receiving break condition detecting zeros including zero during stop time. When break condition detected receiver, UART will interpret this framing error.
7.2.4.6 Voting Logic
vote logic block provides jitter tolerance noise immunity sampling with respect peripheral clock using voting techniques clean samples. voting implemented sampling incoming signal constantly rising edge clock. receiver provided with majority vote value, which three samples.
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Table Majority Vote Results
Samples
Vote
vote logic captures sample every rising edge clock, receiver takes value middle sample frame using oversampling. idle character longer shorter than counts, receiver looks transition. Then starts count start does capture FIFO. start validated upon receiving zeros seven consecutive times following transition. Once counter reaches hex, starts counting next captures middle sampling frame. data bits captured same manner. Once stop detected, receiver shift register data parallel shifted receiver FIFO.
7.2.5 UART Registers
following paragraphs provide detailed descriptions UART registers.
7.2.5.1 UART Control Register (UCON)
UCON used specify transmission parameters, such flow control, stop bits, parity,
UCONBase $000
TX_OEN_ CONT MTXR XTIM writes have effect terminate without transfer error exception
TST-Test Loop-Back: This sets whether MC72000 placed into test loop-back mode where signals connected.
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Test (loop-back) mode Normal operation
MRXR-Mask RXRDY Interrupt This active enables interrupt when receiver data RXFIFO above watermark, there data FIFO UART idle more than frames. fill level RXFIFO which interrupt generated controlled RXLEVEL bits. While negated, this interrupt disabled (masked). RXRDY interrupt masked RXRDY interrupt enabled MTXR-Mask TXRDY Interrupt This active enables interrupt when transmitter data TXFIFO below watermark completely empty. fill level TXFIFO which interrupt generated controlled TXLEVEL bits. While negated, this interrupt disabled (masked). TXRDY interrupt masked TXRDY interrupt enabled FCE-Flow Control Enable This controls whether MC72000 will flow control. When flow control disabled, UART will ignore input assert low. Enabled Disabled FCP-Flow Control When flow control used, this indicates polarity RTS/CTS bits. Assert stop transmission Deassert enable transmission xTIM-Times Oversampling xTIM indicates much oversampling will used. times oversampling times oversampling SEL-GPIO Input Select indicates which MC72000 GPIO pins will used RTS/RXD output signals from UART. RTS_2/RXD_2 RTS_1/RXD_1 TX_OEN_B- Tri-state enable TXD/CTS indicates: Tri-state output pads Enable output pads CONTX-Continuous (Test Mode) Only used test mode, when this enabled, UART will continuously transmit characters. Enable Disable SB-Set Break When set, pulled signal break.
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break break
ST2-Stop Bits This controls number stop bits transmitted after character. While HIGH, stop bits sent. While LOW, stop sent. This effect receiver which expects more stop bits. stop bits stop EP-Even Parity This controls sense parity generator checker. While LOW, parity generated expected. While HIGH, even parity generated expected. This function low. Even parity parity
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PEN-Parity Enable This active HIGH controls parity generator transmitter parity checker receiver. While asserted, they enabled. While negated, they disabled. Enable parity Disable parity RXE-RX Enable This active HIGH enables receiver. When receiver enabled, line already low, receiver does recognize break characters, since requires valid one-to-zero transition before accept character. disabled during reception, receiver will complete current reception then disable. Receiver enabled Receiver disabled TXE-TX Enable This active HIGH enables transmitter. disabled during transmission, UART will immediately return idle (1). transmitter FIFO cannot written when this cleared. Transmitter enabled Transmitter disabled
NOTE:
used select between using RTS_2/RXD_2 RTS_1/RXD_1 ports UART module. MC72000, these ports connected GPIO ports RTS_2/RXD_2 connected alternate functions GPIO port (GPIO_B11 GPIO_B12) called UART-RTS/UART-RXD. GPIO_B11 GPIO_B12 must alternate function mode order RTS_2/RXD_2. RTS_1/RXD_1 connected pins RTS_/RXD GPIO port configuration necessary these pins.
7.2.5.2 UART Status Register (USTAT)
USTAT indicates interrupts errors that have been detected during transmission, such FIFO buffer overflow underflow, parity error, frame, start, stop error.
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Hardware Functional Description
NOTE:
Bits[7:6] cleared when respective condition allows Status bits[5:0] cleared when register read.
USTATBase $004
TXRD RXRD
writes have effect terminate without transfer error exception
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TXRdy-Transmitter Causing Interrupt Interrupt pending interrupt RXRDY-Receiver Causing Interrupt Interrupt pending interrupt RUE-RX FIFO Underrun Error This read-only indicates, while HIGH, that RXFIFO underrun error occurred. This occurs when software reads more from FIFO than actually present. This updated valid each received character. This last character written FIFO indicating that characters following this character will ignored write performed software. cleared UART reset reading USTAT register. Error occurred error ROE-RX FIFO Overrun Error This read-only indicates, while HIGH, that RXFIFO ignored data prevent overwriting data FIFO. Under normal circumstances, this should never set. indicates that user's software keeping with incoming data rate. This updated valid each received character. This last character written FIFO indicating that characters following this character will ignored read performed software. cleared UART reset reading USTAT register. Error occurred error TOE-TX FIFO Overrun Error This flag when UDATA register filled ready transfer TXFIFO register register already full. This error occurs when software writes more data than room FIFO. transmit data transferred this case. transmit overrun error does cause interrupts. cleared UART reset reading USTAT register. Error occurred error
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ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 FE-Frame/Stop Error This read-only indicates, while HIGH, that current character framing error (missing stop break condition). data possibly corrupted. This updated each character read from FIFO. cleared UART reset reading USTAT register. Framing error occurred framing error
PE-Parity Error This read-only indicates, while HIGH, that current character detected with parity error. data possibly corrupted. This updated each character read from FIFO. While parity disabled, this always reads zero. cleared UART reset reading USTAT register. Parity error occurred parity error
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SE-Start Error This read-only indicates, while HIGH, that current character framing error (missing start bit.) data possibly corrupted. This occur when start (RXD found, verified center (for example, glitch). This updated each character read from FIFO. cleared UART reset reading USTAT register. Start error occurred start error
7.2.5.3 UART Data Register (UDATA)
UDATA fills UART transmit FIFO buffer with bytes that transmitted, read received bytes from UART receive FIFO buffer. possible read/write byte access.
UDATABase $008
writes have effect terminate without transfer error exception
RXDATA TXDATA Undefined
RXDATA[7:0]-Received Byte This field contains 8-bit data that been received. TXDATA[7:0]-Byte Transmit This field contains 8-bit data transmitted.
7.2.5.4 UART Buffer Control Registers
UART buffers threshold values generate interrupts. These thresholds used specify that interrupt should generated before transmit FIFO become completely empty, some time
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7.2.5.4.1
UART RXBUFFER Control Register (URXCON)
RXLEVEL register used threshold interrupt that generated when receive buffer full. RXFULLCNT register contains number bytes that currently buffered receive FIFO.
URXCONBase $00C
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writes have effect terminate without transfer error exception
RXFULLCNT RXLEVEL
RXFULLCNT[5:0]-Receive buffer full level This value indicates number bytes currently buffered receive FIFO buffer. number bytes between (empty) (full) bytes. RXLEVEL[5:0]-Receive buffer level When number bytes receive FIFO exceeds value specified RXLEVEL, interrupt generated.
7.2.5.4.2
UART TXBUFFER Control Register (UTXCON)
UTXCON sets threshold interrupt that generated when transmit buffer becomes empty. TXEMPTYCNT register contains number bytes that still written UART transmit FIFO. Data written transmit buffer while this number non-zero.
UTXCON
Base $010
writes have effect terminate without transfer error exception
TXEMPTYCNT TXLEVEL
TXEMPTYCNT[7:0]-Transmit Buffer Empty Level This value indicates number empty bytes currently available transmit FIFO buffer. number free bytes between (full) (empty) bytes.
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7.2.5.4.3
UART Level Control Register (UCTS)
UCTS sets threshold control flow signal. remote UART continues send limited amounts data after detecting deasserted signal, local receive buffer handle additional data CTS_LEVEL suitable value.
UCTSBase $014
Freescale Semiconductor, Inc.
writes have effect terminate without transfer error exception
CTS_LEVEL CTS_LEVEL
CTS_LEVEL[7:0]-CTS Buffer Level When number bytes receiver (RX) FIFO exceeds this value, signal deasserted.
7.2.5.5 UART Baud Rate Divider Register (UBR)
fractional divider registers used select receive transmit baud rate. following sections describe fractional divider registers. FRACDIV_DIV register used select divisor fractional division divider. Section 7.2.3, "Fractional Divider," explanation value written register. FRACDIV_INC register used select modulus value fractional division divider. Section 7.2.3, "Fractional Divider," explanation value written register.
Base $018
UBRINC UBRINC
UBRMOD UBRMOD writes have effect terminate without transfer error exception
UBRINC Value This value used select baud rate. Section 7.2.3, "Fractional Divider," more information. UBRMOD Value This value used select baud rate. Section 7.2.3, "Fractional Divider," more information.
MOTOROLA
MC72000 Advance Information Data Sheet More Information This Product, Preliminary www.freescale.com
Hardware Functional Description
7.2.6 FIFO Operation
operation transmit receive FIFOs shown Figure
TXFIFO
Empty
RXFIFO
Empty
Asserted
TXLEVEL (Write only)
Asserted
CTSLEVEL (Write only)
Asserted
RXLEVEL (Write only)
TXCNT (Read only)
RXCNT (Read only)
Freescale Semiconductor, Inc.
Full
Full
Figure FIFO-Related Levels
7.2.7 Flow Control
operation transmit receive Flow Control shown Figure
NOTE:
Ready Send (RTS) means that MC72000 allowed send because remote unit ready. Clear Send (CTS) means that MC72000 ready accept data, remote unit transmit when data. polarity RTS/CTS changed changing control [FCP] bit. When control[FCE]=0, flow control disabled. This causes UART ignore input asserting (that when control[FCP]=0).
MC72000 Advance Information Data Sheet More Information This Product, Preliminary www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc. Functional Description Hardware
MC71000
Please stop full ready more data Please stop
Remote
NOTE:
above signals assume control (FCe) (enabled control) (FCp) (active RTS/CTS signals).
Freescale Semiconductor, Inc.
Figure Flow Control
Configurable Serial Peripheral Interface (CSPI)
CSPI master/slave configurable serial peripheral interface module which allows full-duplex, synchronous, serial communications with other peripheral devices. CSPI equipped with RXFIFO TXFIFO. CSPI incorporates DATAREADY_B SS_B control signals enables fast data communication with fewer number software interrupts.
7.3.1 Features
CSPI following features: Full-duplex operation Master slave modes Separate transmit receive FIFO registers Eight master mode frequencies Maximum frequency frequency Minimum frequency frequency Slave mode frequencies Maximum frequency less than frequency Minimum frequency Selectable transmit receive word lengths from bits Serial clock with programmable polarity phase Interrupts Receiver full (programmable level) Transmitter empty (programmable level) Overflow error, RXFIFO, count
7.3.2 Modes Operation
Master mode
MOTOROLA
MC72000 Advance Information Data Sheet More Information This Product, Preliminary www.freescale.com
Hardware Functional Description
Transfer control Immediate Data ready input signal
Period control (baud rate clock clock) Slave mode
7.3.3 Block Diagram
Figure shows CSPI block diagram.
Interface
Freescale Semiconductor, Inc.
Clock Generator
Control
DATAREADY_B SS_B SPI_CK MISO MOSI
Shift Register
Figure CSPI Block Diagram
MC72000 Advance Information Data Sheet More Information This Product, Preliminary www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc. Functional Description Hardware
7.3.4 Signal Description
Table shows signals used control serial peripheral interface master.
Table Serial Peripheral Interface Master Control Signals
Signal MOSI Description Master slave Function This bidirectional signal output signal from data shift register master mode. slave mode, MOSI input data shift register. This bidirectional signal input signal data shift register master mode. slave mode, MISO output from data shift register. This bidirectional signal CSPI clock output master mode. slave mode, SPI_CK input clock signal CSPI. This bidirectional signal output master mode input slave mode. This input signal used only master mode. will edge level trigger CSPI burst used.
MISO
Master slave
SPI_CK SS_B
CSPI clock Slave select ready
Freescale Semiconductor, Inc.
DATAREADY_B
7.3.5 Detailed Signal Descriptions
following section provides detailed signal descriptions.
7.3.5.1 SPI_CK CLOCK
serial clock synchronizes data transmission between master slave devices. master MCU, SPI_CK clock output. slave MCU, SPI_CK clock input. full duplex operation, master slave CSPIs exchange data BITCOUNT serial clock cycles. When enabled GPIO function select register, CSPI controls data direction SPI_CK regardless state GPIO data direction register shared port.
7.3.5.2 MISO Master In/Slave
MISO CSPI module pins that transmits serial data. full duplex operation, MISO master CSPI module connected MISO slave module. master CSPI simultaneously receives data MISO transmits data from MOSI pin. Slave output data MISO enabled only when configured slave. CSPI configured slave when MODE logic zero SS_B logic zero. support multiple-slave system, logic SS_B puts MISO high-impedance state. When enabled GPIO function select register CSPI controls data direction MISO regardless state GPIO data direction register shared port.
7.3.5.3 MOSI Master Out/Slave
MOSI CSPI module pins that transmit serial data. full duplex operation, MOSI master CSPI module connected MOSI slave CSPI module. master CSPI simultaneously transmits data from MOSI receives data MISO pin. When enabled GPIO function select register CSPI controls data direction MOSI regardless state GPIO data direction register shared port.
MOTOROLA
MC72000 Advance Information Data Sheet More Information This Product, Preliminary www.freescale.com
Hardware Functional Description
7.3.5.4 SS_B Slave Select
SS_B various functions depending current state CSPI CONTROLREG. CSPI configured slave, SS_B used select slave. When CSPI configured slave, SS_B always configured input. cannot used general purpose I/O. When CSPI configured master, SS_B used define start word transmission. However, remain between word transmissions format. When enabled GPIO function select register, CSPI controls data direction SS_B regardless state GPIO data direction register shared port.
7.3.5.5 DATAREADY_B Data Ready
DATAREADY_B used master mode allow slave device signal master that slave ready deliver some data master.
Freescale Semiconductor, Inc.
When enabled GPIO function select register, CSPI controls data direction DATAREADY_B regardless state GPIO data direction register shared port.
7.3.6 Memory Registers
Table shows CSPI memory map. There user programmable registers which bits. registers aligned 32-bit word address width always return zeros upper bits whenever read. AIPI enable either transfers. registers byte halfword accessible. base address CSPI0 CSPI1 modules MC72000 32'h8000_8000 32'h8000_9000.
Table CSPI Memory
Address Base 0x00 Base 0x04 Base 0x08 Base 0x0C Base 0x10 Base 0x14 Base 0x18 Base 0x1c Data Register (RXDATAREG) Data Register (TXDATAREG) Control Register (CONTROLREG) Interrupt Control/Status Register (INTREG) CSPI Test Register (TESTREG) CSPI Sample Period Control Register (PERIODREG) Reserved CSPI Soft Reset Register (RESETREG) Access
following sections provide detailed descriptions each CSPI registers. readable registers will return after reset unless otherwise specifically stated. reserved bits read zero should written with zero future compatibility.
MC72000 Advance Information Data Sheet More Information This Product, Preliminary www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc. Functional Description Hardware
7.3.7 Register Descriptions
7.3.7.1 Data Register (RXDATAREG)
Register address: BASE 0x00 Reset Reset Reserved Data[15:0]
Unimplemented Reserved
Freescale Semiconductor, Inc.
Figure Data Register (RXDATAREG)
RXDATAREG 32-bit read-only register. lower bits hold RXFIFO received from external CSPI device during data transaction. upper bits reserved bits always read Bits beyond current setting BITCOUNT register invalid should masked user software. DATA[15:0] CSPI Data RXFIFO DATA meaning interrupt control/status register clear.
7.3.7.2 Data Register (TXDATAREG)
Register address: Base 0x04 Reset Reset Reserved
SPIEN Data[15:0], else 0x0000 Data[15:0]
Figure Data Register (TXDATAREG)
TXDATAREG 32-bit write-only data register. lower bits TXFIFO. Writing TXFIFO permitted long full, even though set, that user could write TXFIFO during CSPI data exchange process. Writes this register ignored while SPIEN clear. upper bits reserved bits always read DATA[15:0] CSPI data loaded 8x16 TXFI
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