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MC71000 Package Information Plastic Package Case 1347 (MAPBGA-100


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MC71000TB/D Rev. 8/2002 MC71000 Bluetooth Baseband Controller
MC71000
Package Information Plastic Package Case 1347 (MAPBGA-100)
Freescale Semiconductor, Inc.
Ordering Information
Device MC71000 Operating Temperature Range Package MAPBGA
Contents
Applications Typical Bluetooth Solution Using MC71000 Overview Architectural Overview Assignment Listing General Characteristics Mechanical Specifications Functionality Overview Supported Commands
MC71000 Bluetooth Baseband Controller part Bluetoothchipset from Motorola that provides complete, low-power Bluetooth radio system. design based Motorola's third-generation Bluetooth architecture that industry standard interoperability, complete functionality, compliance with Bluetooth specification. MC71000 Bluetooth Baseband Controller from Motorola implements baseband host controller interface (HCI) Bluetooth protocol. operates with core voltage I/Os between MC71000 ideal solution low-power, short-range Bluetooth applications includes superior performance features like dedicated Bluetooth audio processor module on-chip memory. Debug production test fully supported through joint test action group (JTAG) interface. MC71000 provides zero-glue logic interface companion MC13180 Bluetooth Integrated Circuit (IC), allowing implementation two-chip Bluetooth Class radio. addition MRFIC2408 External Power Amplifier provides Class solution.
This document contains information product under development. Motorola reserves right change discontinue this product without notice. Motorola, Inc., 2002. rights reserved.
Preliminary
More Information This Product, www.freescale.com
Applications
MC71000 IPBC Watchdog Wakeup Reset Bluetooth Link Controller Bluetooth Audio Processor UART SPI0 SPI1 TIMER GPIO
JTAG
JTIC
ARM7
Freescale Semiconductor, Inc.
emCTRL
256K
Figure MC71000 Block Diagram
Applications
Mobile phone connectivity Personal digital assistant (PDA) connectivity Internet appliance connectivity Mobile phone headsets
Typical Bluetooth Solution Using MC71000
following figure shows sample two-chip Bluetooth solution.
Transceiver MC71000 XTAL XTAL 12-15
UART
Baseband Controller MC71000
Transceiver MC13180
Figure Sample Two-Chip Bluetooth Solution
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MOTOROLA
Overview
Overview
This section describes overall system architecture MC71000 Bluetooth Baseband Controller. highlights main features requirements, well provides overview operational blocks MC71000 Bluetooth Baseband Controller system level. subsequent sections describe detailed design requirements major blocks functions. MC71000 Bluetooth Baseband Controller implements baseband host controller interface (HCI) Bluetooth protocol specifically designed meet immediate market needs low-power Bluetooth applications. improve total system throughput reduce component cost board size, MC71000 Bluetooth Baseband Controller integrates Motorola-unique ARM7TDMI platform with intelligent peripheral modules focused communications system integration. MC71000 Bluetooth Baseband Controller includes superior performance features audio power conservation, well debug production test support.
Freescale Semiconductor, Inc.
MC71000 Bluetooth Baseband Controller provides zero glue logic interface MC13180 Bluetooth Integrated CircuitC, 2.4GHz Bluetooth radio implementing Bluetooth Class solution. addition MRFIC2408 External Power Amplifier provides Class solution. power management chip, MC13181, also available headset mobile phone accessory applications. MC13181 integrates power management functions common these applications. architecture MC7100 shown Figure page
MC71000 Bluetooth Features
Bluetooth Specification Compliant Point-to-multipoint (piconet) with slaves connection types packet types power saving modes Master/slave switch Encryption UART transport layer Superior Audio Performance Sample rate synchronization between CODEC Bluetooth clock domains avoid "clicking" effects simultaneous channels supported Bluetooth encoding/decoding schemes supported (CVSD, A-Law, µ-Law) Very audio delay avoid need echo cancellation Support Sample Rate CODECs
MC71000 Hardware Features
MC71000 specifically designed work with Bluetooth protocol supports wide range Bluetooth user profiles applications. MC71000 offers following features: Bluetooth Link Controller Bluetooth Audio Processor ARM7 Processor Complex Peripherals
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Architectural Overview
ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 High-speed UART Mbps)
High-speed Mbps) Dual high-speed Mbps) Embedded Memory SRAM (64K) (256K) External Interface Module (EIM) JTAG Test Interface Controller (JTIC) Oscillator (OSC32k) Power Operation Operating Voltage: 1.65 1.95 Package: 100-pin MAPBGA, 0.65 ball pitch
Freescale Semiconductor, Inc.
Architectural Overview
following sections describe functionality performance MC71000 Bluetooth Baseband Controller.
ARM7 Platform (A7P)
4.1.1 ARM7TDMI
MC71000 Bluetooth Baseband Controller architecture based around 32-bit ARM7TDMI microprocessor. industry-standard processor recognized efficient MIPS/WATT benchmark, along with excellent code efficiency when working 16-bit THUMB mode. architecture based RISC principles supports instruction sets: 32-bit instruction 16-bit THUMB instruction
Memory Sub-System
Program execution MC71000 Bluetooth Baseband Controller predominantly ROM-based, with internal SRAM being used code patching. image uploaded from host system, low-cost serial E2PROM (four-wire connection).
4.2.1 External Interface Module (EIM)
external interface module (EIM) handles interface external devices, well generation chip selects external peripherals memory. contains zero-glue interface external memories (SRAM, E2PROM, FLASH chips).
Peripherals Sub-System
4.3.1 Clock Reset Module (CRM)
clock reset module (CRM) dedicated handling clock, reset, power management features MC71000 Bluetooth Baseband Controller. assures that different clock reset signals stable before they internal logic MC71000 Bluetooth Baseband Controller.
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Freescale Semiconductor, Inc. Architectural Overview
ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 designed make full facilities supplied Bluetooth standard conserve power, while still maintaining Bluetooth link. this purpose, connected on-chip low-power oscillator, which generates frequency using external cost 32.768 crystal. module also includes watchdog safeguard against potential software failures.
4.3.2 Bluetooth Link Controller (BTLC)
Bluetooth link controller module (BTLC) handles link controller specific functions. data read from/written module, BTLC takes care transmission related timing, well data signal processing functions like encryption cyclic redundancy check (CRC)/header error correction (HEC) generation. Embedded BTLC also dedicated Bluetooth timers, which maintain accurate estimate time both native remote module. small dedicated Bluetooth serial peripheral interface controller handles serial communication with MC13180 Bluetooth Integrated Circuit.
Freescale Semiconductor, Inc.
4.3.3 Bluetooth Audio Signal Processor (BTASP)
Special attention been audio quality user. this purpose, dedicated Bluetooth audio signal processing module (BTASP) been designed give users excellent superior audio performance. With minimum processor intervention, this module handles filtering, interpolation, well encoding/decoding (aLaw, uLaw, CVSD).
4.3.4 High-Speed UART Mb/sec MHz)
Universal Asynchronous Receiver/Transmitter (UART) module provides main interfaces MC71000 Bluetooth Baseband Controller. generated baud rate based upon configurable divisor input clock. configured send stop bits well odd, even, parity. UART transmit receive buffer sizes bytes each.
4.3.5 Dual High-speed CSPI Mb/sec MHz)
MC71000 Bluetooth Baseband Controller contains configurable serial peripheral interface (CSPI) modules, CSPI0 CSPI1. CSPI0 connect variety SEEPROM serial flash devices. Both CSPI modules master/slave configurable, equipped with byte data buffers (transmit receive FIFOs), allow MC71000 Bluetooth Baseband Controller interface with external CSPI master slave devices. Incorporating SPIRDY control signals, enables fast data communication with fewer number software interrupts.
4.3.6 High-Speed Mb/sec MHz)
synchronous serial interface module (SSI) full-duplex serial port allowing digital signal processors (DSPs) communicate with variety serial devices, including industry-standard CODECs, other DSPs, microprocessors, peripherals. typically used transfer samples periodic manner consists variety registers that handle port, status, control, transmit receive, serial clock generation, frame synchronization.
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Assignment Listing
4.3.7 Timer (TMR)
dual timer module (TMR) general purpose module, used timing control application-specific tasks. also configured perform pulse width modulation (PWM) into quadrature-count mode needed. contains identical 16-bit counter/timer groups, each supports counting, prescaling, comparing, loading, capturing, holding options.
4.3.8 General Purpose (GPIO)
MC71000 Bluetooth Baseband Controller supports maximum GPIO lines grouped together ports. Port contains lines Port contains other These ports configured GPIO pins dedicated peripheral interface pins.
Test
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4.4.1 JTAG Test Interface Controller (JTIC)
JTIC interface offers full JTAG boundary scan capabilities debug production test purposes, well access JTAG interface ARM.
Assignment Listing
following table (Table 2-1) shows assignment listing MC71000 pins organized into functional groups. Name Description columns show actual name brief description each pin. Drive column lists typical (minimum) drive current required pin. Power Group column lists Supply Power Group assignment. Reset State column lists input/output direction chip RESET. Alternate Functions column lists each GPIO port alternate input output selections available. Some selections test- development-mode specific.
Table MC71000 Bluetooth Baseband Controller Description
Name Description Type Reset Pull Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD Drive Power Group Reset State Alternate Functions
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Table MC71000 Bluetooth Baseband Controller Description (Continued)
Name Description Address line Data line Data line Data line Data line Data line Data line Data line Data line Chip Select Chip Select Output enable Write enable Type MISC EXTAL XTAL TRST RTCK MODE0 MODE1 RESETIN External crystal clock input Crystal output JTAG Test reset JTAG Test data input JTAG Test data output JTAG Test mode select input JTAG Test clock input JTAG Test clock output JTAG Test select Boot mode select Boot mode select Reset input Tri-O
Reset Pull Drive Power Group EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD Reset State Alternate Functions
Freescale Semiconductor, Inc.
MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD
PORT (BLUETOOTH) REFCTRL REFCLK Reference clock control Reference clock input Frame synch/ CSPI_di RXDATA TXDATA RXTXEN/ HOP_STROBE SPI_CLK Tri-O AVDD AVDD AVDD AVDD AVDD AVDD AVDD
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Assignment Listing
Reset Pull Drive PORT Power Group AVDD AVDD AVDD AVDD Reset State Alternate Functions
Table MC71000 Bluetooth Baseband Controller Description (Continued)
Name Description SPI_EN SPI_DO/SPI_DI PWM0/TX_EN/ GPO0 PWM1/PA_EN/ GPO1 Type Tri-O
SSI_STCK
Serial Transmit Clock Serial Transmit Frame Sync Serial Transmit Data Serial Receive Clock Serial Receive Frame Sync Serial Receive Data CSPI Slave Select CSPI Serial Clock CSPI Master Slave CSPI Master Slave General Purpose General Purpose General Purpose Programmable Clock Output
PORT
BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD
GPIO_B0; BT_TP0 GPIO_B1; BT_TP1 GPIO_B2; BT_TP2 GPIO_B3; BT_TP3 GPIO_B4; BT_TP4 GPIO_B5; BT_TP5 GPIO_B6; BT_TP6 GPIO_B7; BT_TP7 GPIO_B8; BT_TP8; GPIO_B9; BT_TP9 GPIO_B10 UART-TXD GPIO_B11 UART-RTS GPIO_B12 UART-RXD GPIO_B13 UART-CTS
Freescale Semiconductor, Inc.
SSI_STFS
SSI_STD SSI_SRCK SSI_SRFS SSI_SRD CSPI_0_SS CSPI_0_SCK CSPI_0_MISO CSPI_0_MOSI GPIO_B10 GPIO_B11 GPIO_B12 CLK0
CTS_ RTS_ CSPI_1_SS
UART UART UART UART CSPI Slave select
Tri-O Tri-O
CVDD CVDD CVDD CVDD CVDD
GPIO_C0; CSPI0_REQ GPIO_C1; CSPI1_REQ GPIO_C2; TIM_0_I GPIO_C3; TIM_1_I GPIO_C4; SYSCLK
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Table MC71000 Bluetooth Baseband Controller Description (Continued)
Name Description Type Reset Pull Drive Power Group CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD Reset State
Alternate Functions GPIO_C5; SH_STROBE GPIO_C6; ABORT GPIO_C7; REFCLK GPIO_C8; TIM_0_O GPIO_C9; XACK GPIO_C10; TIM_1_O GPIO_C11 GPIO_C12
CSPI_1_SCK CSPI_1_MISO CSPI_1_MOSI CLK1 GPIO_C9
CSPI Serial clock CSPI Master Slave CSPI Master Slave Programmable clock output General Purpose Buffered Power Clock Buffered System Clock Buffered Bluetooth Clock
Freescale Semiconductor, Inc.
OSC32K
SYSCLK BTCLK
POWER/GROUND GND_EIM2 GND_EIM3 GND_EIM4 GND_EIM6 GND_EIM7 PWR_EIM2 PWR_EIM3 PWR_EIM4 PWR_EIM6 PWR_EIM7 MISC POWER/GROUND GND_MISC PWR_MISC PORT POWER/GROUND GND_PA PWR_PA PORT POWER/GROUND GND_PB PWR_PB PORT POWER/GROUND GND_PC PWR_PC CORE POWER/GROUND GND_CORE1 GND_CORE2 GND_CORE3 COREVDD COREVDD COREVDD CVDD CVDD BVDD BVDD AVDD AVDD MISCVDD MISCVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD
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Assignment Listing
Reset Pull Drive Power Group COREVDD COREVDD COREVDD COREVDD COREVDD Reset State Alternate Functions
Table MC71000 Bluetooth Baseband Controller Description (Continued)
Name GND_CORE4 Description Type
PWR_CORE1 PWR_CORE2 PWR_CORE3 PWR_CORE4 1.ST Schmitt Trigger input
Descriptions
Freescale Semiconductor, Inc.
following table provides detailed descriptions external interface module (EIM); clock, reset, JTAG; Bluetooth; SSI, SPI0, UART; UART, SPI1, including GPIO shared package pins. following table, general purpose input/output (GPIO) designed share package pins with other peripheral modules chip. peripheral which normally controls given required, then programmed general purpose input/output (GPIO) alternate function with programmable pullup. GPIO module design available ports (Port Port individual control each normal functional mode, alternate function mode GPIO mode. individual direction control each GPIO mode. individual pullup enable control each normal function mode, alternate function mode GPIO mode. Normal mode. peripheral module controls output enable output data input data from passed peripheral. Alternate function mode (GPIO). GPIO module controls output enable supplies data output. Alternate function mode. peripheral module controls output enable output data input data from passed peripheral.
Table Descriptions
Signals Active high, bidirectional inputs/outputs. least significant most significant. These pins provide bidirectional data external memory access. D0-D7 held previous logic state when there external activity. This done with weak "keepers" inside buffers. They also kept their previous state during hardware reset. Active high outputs, specifies address external memory accesses. ADDR0 least significant ADDR11 most significant. minimize power dissipation, ADDR0-ADDR11 change state when external memory being accessed. This output signal active asserted based decode internal address bus. This active-low output signal asserted based decode internal address bus. This active output signal used indicate that access read enables slave devices drive data with read data. negated during hardware reset. This active output signal used indicate that access write enables slave devices drive address with write data.
D0-D7 (Data Bus)
A0-A11 (Address Bus)
(Chip Select (Chip Select
(Output Enable)
(Write Enable)
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Table Descriptions (Continued)
Clock, Reset, JTAG Signals EXTAL XTAL (Test Data Input) external crystal clock input Crystal output test data input provides serial input data stream controllers. sampled rising edge TCK. test data output tri-statable, providing serial output data from Master Core controller. actively driven shift-IR shift-DR controller states controller state machine. changes falling edge TCK. This active Schmitt trigger input provides asynchronously reset signal controllers initialize test controller. test mode select input used sequence controllers. sequenced determined control module device port. sampled rising edge TCK. test clock input used synchronize JTAG test logic. provides clock synchronize test logic shift serial data from controllers. return test clock input returns synchronization test clock development tools entered from serial debug input line. test select input directly controls multiplexing logic select between chip core TAP. logic applied select input will select chip TAP. Test/boot mode select pins. order support flexible development system, system must capable boot from different memories during system reset power-up. four different memory maps selected these pins. different boot modes start reading data address 0x0000_0000, since this where ARM7 reset vector located. reset active Schmitt trigger input that provides reset internal circuitry. RESET input will qualified valid will asserted least cycles. Bluetooth Signals REFCTRL (Reference Control) REFCLK (Reference Clock) reference control dedicated output from which enables/disables reference clock. reference clock dedicated input into from interface. (12-32 MHz) Input from front end. Frame sync MC13180 CSPI_din Silicon Wave RXDATA: Input from MC13180 Silicon Wave Front TXDATA: Output MC13180 Silicon Wave Front Dedicated control output Front Ends. RXTX_EN MC13180 Radio HOP_STROBE Silicon Wave Radio. CSPI_CLK: three CSPI signals which program MC13180 Radio four CSPI signals which program Silicon Wave Radio. CSPI_EN: three CSPI signals which program MC13180 Radio four CSPI signals which program Silicon Wave Radio. CSPI_DOUT/CSPI_DIN: three CSPI signals which program MC13180 Radio (CSPI_DIN CSPI_DOUT) four CSPI signals which program Silicon Wave Radio (CSPI_DOUT)
(Test Data Output)
TRST (Test Reset)
(Test Mode Select)
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(Test Clock) RTCK (Return Test Clock)
(Test select)
MODE[1:0]
RESETIN (Reset
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Assignment Listing
Table Descriptions (Continued)
control output which programmed different purposes, such TX_EN, PWM0 (Pulse Width modulator output), GPO0. control output which programmed different purposes, such PA_EN (power amplifier enable), PWM1 (pulse width modulator output) GPO1. SSI, SPI0, UART Signals
SSI_STCK/GPIO_B0/BT_TP0 Normal Mode Alternate Function (GPIO) Alternate Function SSI_STCK GPIO_B0 BT_TP0 serial transmit clock signal used transmitter either continuous gated. GPIO Port Bluetooth test port
Freescale Semiconductor, Inc.
SSI_STFS/GPIO_B1/BT_TP1
Normal Mode Alternate Function (GPIO) Alternate Function SSI_STD/GPIO_B2/BT_TP2 Normal Mode Alternate Function (GPIO) Alternate Function SSI_SRCK/GPIO_B3/BT_TP3 Normal Mode Alternate Function (GPIO) Alternate Function SSI_SRFS/GPIO_B4/BT_TP4 Normal Mode Alternate Function (GPIO) Alternate Function SSI_SRD/GPIO_B5/BT_TP5 Normal Mode Alternate Function (GPIO) Alternate Function CSPI_0_SS/GPIO_B6/BT_TP6
SSI_STFS GPIO_B1 BT_TP1
serial transmit frame sync signal used transmitter synchronize transfer data. frame sync signal word length. GPIO Port Bluetooth test port signal
SSI_STD GPIO_B2 BT_TP2
serial transmit data signal used transmit serial data. GPIO Port Bluetooth test port signal
SSI_SRCK GPIO_B3 BT_TP3
serial receive clock signal used receiver always continuous, however, used synchronous mode. GPIO Port Bluetooth test port signal
SSI_SRFS GPIO_B4 BT_TP4
serial receive frame sync signal used receiver synchronize transfer data. frame sync signal word length. GPIO Port Bluetooth test port signal
SSI_SRD GPIO_B5 BT_TP5
serial receive data signal used receive serial data. GPIO Port Bluetooth test port signal
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Table Descriptions (Continued)
Normal Mode Alternate Function (GPIO) Alternate Function CSPI_0_SCK/GPIO_B7/BT_TP7 Normal Mode Alternate Function (GPIO) Alternate Function CSPI_0_MISO/GPIO_B8/BT_TP8 CSPI0 Clock GPIO_B7 BT_TP7 This bidirectional signal CSPI0 clock output master mode. slave mode, CSPI_0_SCK input clock signal CSPI. GPIO Port Bluetooth test port signal CSPI_0_SS GPIO_B6 BT_TP6
CSPI0 slave select bidirectional signal output master mode input slave mode. GPIO Port Bluetooth test port signal
Freescale Semiconductor, Inc.
Normal Mode Alternate Function (GPIO) Alternate Function CSPI_0_MOSI/GPIO_B9/BT_TP9 Normal Mode Alternate Function (GPIO) Alternate Function GPIO_B10/UART_TxD Alternate Function (GPIO) Alternate Function GPIO_B11/UART_RTS Alternate Function (GPIO)
CSPI0 GPIO_B8 BT_TP8
Master Slave Out: master mode, this bidirectional signal input signal. slave mode, MISO output signal. GPIO Port Bluetooth test port signal
CSPI0 GPIO_B9 BT_TP9
Master Slave master mode, this bidirectional signal output signal. slave mode, MOSI input signal. GPIO Port Bluetooth test port signal; Bluetooth clock
GPIO_B10 UART_TxD
GPIO Port Transmit data serial (output signal)
GPIO_B11
GPIO Port UART ready send (RTS) This input signal, when asserted, indicates that remote device ready accept data that MC71000 Bluetooth Baseband Controller transmit when data send.
Alternate Function
UART_RTS
GPIO_B12/UART_RxD Alternate Function (GPIO) Alternate Function CLK0/GPIO_B13/UART_CTS Output external devices generated fractional clock divider CRM. CLK0 programmable clock derivative REFCLK. Frequencies programmable range REFCLK/127 REFCLK. CLK0 used feed external USB, CODEC, whatever applications need. fractional divider 16-bit resolution; writing 0x000 divisor disables timer. GPIO_B12 UART_RxD GPIO Port Receive data serial (input signal)
Normal Mode
CLK0
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Assignment Listing
Table Descriptions (Continued)
GPIO Port UART clear send (CTS) This output signal, when asserted, indicates that MC71000 Bluetooth Baseband Controller ready accept data remote device transmit when data send.
Alternate Function (GPIO)
GPIO_B13
Alternate Function
UART_CTS
UART, SPI1, Signals TXD/GPIO_C0/CSPI0_REQ Normal Mode Alternate Function (GPIO) Alternate Function CTS/GPIO_C1/CSPI1_REQ GPIO_C0 CSPI0_REQ UART transmit data serial (output signal) GPIO Port External data transfer rate control CSPI0
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Normal Mode
UART clear send (CTS) output signal, when asserted, indicates that MC71000 ready accept data remote device transmit when data send. GPIO Port External data transfer rate control CSPI1
Alternate Function (GPIO) Alternate Function RXD/GPIO_C2/TIM_0_I Normal Mode Alternate Function (GPIO) Alternate Function RTS/GPIO_C3/TIM_1_I
GPIO_C1 CSPI1_REQ
GPIO_C2 TIM_0_I
UART receive data serial (input signal) GPIO Port Input signal timer
Normal Mode
UART ready send (RTS) input signal, when asserted, indicates that remote device ready accept data that MC71000 transmit when data send. GPIO Port Input signal timer
Alternate Function (GPIO) Alternate Function CSPI_1_SS/GPIO_C4/SYSCLK Normal Mode Alternate Function (GPIO)
GPIO_C3 TIM_1_I
CSPI1 GPIO_C4
Slave Select: This bidirectional signal output master mode input slave mode. GPIO Port System clock used entire ARM7 platform peripherals attached bus. Some peripherals (for example, UART) will also this clock signal generate their module clock.
Alternate Function
SYSCLK
CSPI_1_SCK/GPIO_C5/SH_STROBE Normal Mode Alternate Function (GPIO) CSPI Clock GPIO_C5 This bidirectional signal CSPI clock output master mode. slave mode, CSPI1_SCK input clock signal CSPI. GPIO Port
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Table Descriptions (Continued)
Alternate Function CSPI_1_MISO/GPIO_C6/ABORT Normal Mode Alternate Function (GPIO) Alternate Function CSPI_1_MOSI/GPIO_C7/REFCLK Normal Mode CSPI1 GPIO_C7 REFCLK Master Slave (MOSI): master mode, this bidirectional signal output signal. slave mode, MOSI input signal. GPIO Port reference clock input (12-32 MHz) CSPI1 GPIO_C6 ABORT Master Slave (MISO): master mode, this bidirectional signal input signal. slave mode, MISO output signal. GPIO Port Indicates current memory access completed. SH_STROBE
Indicates data valid external when show cycle used.
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Alternate Function (GPIO) Alternate Function CLK1/GPIO_C8/TIM_0_O
Normal Mode
CLK1
Output external devices generated integer divider. CLK1 programmable clock derivative REFCLK. Frequencies programmable range REFCLK/64 REFCLK. CLK1 used feed external USB, CODEC, whatever device applications need. integer divider should divide REFCLK with 64). value disables timer. GPIO Port Output signal from timer
Alternate Function (GPIO) Alternate Function GPIO_C9/XACK Alternate Function (GPIO) Alternate Function OSC32K/GPIO_C10/TIM_1_O Normal Mode Alternate Function (GPIO) Alternate Function SYSCLK/GPIO_C11/A20
GPIO_C8 TIM_0_O
GPIO_C9 XACK
GPIO Port External acknowledge signal
OSC32K GPIO TIM_1_O
Buffered output from chip oscillator GPIO Port Output signal from timer
Normal Mode
SYSCLK
System clock used processor well most peripherals attached bus. Some peripherals (for example, BTLC) will derive their internal clock based SYSCLK. GPIO Port Address line signal used debugging
Alternate Function (GPIO) Alternate Function BTCLK/GPIO_C12/A21
GPIO_C11
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General Characteristics
Table Descriptions (Continued)
Bluetooth system clock, used internally Bluetooth-related calculations. GPIO Port Address line signal used debugging
Normal Mode Alternate Function (GPIO) Alternate Function
BTCLK GPIO_C12
5.1.1 Power Ground
following table shows power ground supplies.
Table Power Ground Supplies
Name COREVDD Description Core Supply Port Noise Sensitive Bluetooth Supply Port Supply Port Supply Clock JTAG Supply Supply Value
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AVDD
BVDD CVDD MISCVDD EIMVDD
1.Can with degraded performance timing pull-ups
NOTE:
pads tolerant ground supplies tied together.
Functional Grouping Signals Polaris
Port Bluetooth
Core
Port SSI, SPI0, TIM, GPIO
MISC
Port UART, SPI1, TIM, GPIO
Core
Figure Functional Grouping Signals
General Characteristics
Absolute maximum ratings given Table stress ratings only, functional operation maximum guaranteed. Stress beyond these ratings affect device reliability cause permanent damage device.
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ARCHIVED FREESCALE SEMICONDUCTOR, INC. 2005 MC71000 DC/AC electrical specifications preliminary from design simulations analysis. These specifications fully tested guaranteed this early stage product life cycle. Finalized specifications will published after complete characterization device qualifications have been completed.
WARNING:
This device contains protective circuitry guard against damage high static voltage electrical fields. However, normal precautions advised avoid application voltages higher than maximum rated voltages high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (for example, either GND).
Table Absolute Maximum Ratings (GND
Freescale Semiconductor, Inc.
Rating
Symbol TSTG
Value (GND-0.3) (GND 0.3)
Unit
Core supply voltage other input voltages Storage temperature range
Table Recommended Operating Conditions
Characteristic Core supply voltage Ambient temperature Symbol 1.65 1.95 Unit
Table Package Thermal Characteristics
Thermal Resistance Junction-to-ambient (estimated)1 Junction-to-case (estimated)2 Symbol 181-pin 105.38 28.76 100-pin MAPBGA Unit
1.Junction-to-ambient thermal resistance based measurements horizontal single-sided Printed Circuit Board. 2.Junction-to-case thermal resistance based measurements using cold plate with exception that cold plate temperature used case temperature.
Electrical Characteristics
Table
Characteristics supply voltage MISC supply voltage Bluetooth supply voltage (Port
Electrical Characteristics
Unit
Symbol EIMVDD MISCVDD AVDD
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General Characteristics
Table Electrical Characteristics (Continued)
Symbol BVDD CVDD
Unit
Characteristics Supply voltage (level shift I/O) High-level input voltage EIMVDD (2.7 MISCVDD AVDD BVDD CVDD
1.90 MISCVDD AVDD BVDD CVDD
Freescale Semiconductor, Inc.
High-level output voltage
(2.7 EIMVDD MISCVDD AVDD BVDD CVDD Low-level output voltage Low-level input voltage Current drain (run mode) MHz, 1.8V Current drain (stop mode) 1.8V Input capacitance (estimated)
MISCVDD AVDD BVDD CVDD
AVDD BVDD CVDD
IDDACTIVE IDDSLEEP
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Freescale Semiconductor, Inc.General Characteristics
REFCTRL REFCLK Ground Port Frame Synch/SPI_di EXTAL XTAL RESETIN Clock Reset Port RxData TxData RxTxEn/Hop_strobe CSPI_clk CLK0 (GPIO_B13) CLK1 (GPIO_C8) CSPI_en Programmable Clock Output GPIO CSPI_do/CSPI_di PWM0/Tx_en/GPO0 PWM1/PA_en/GPO1 SSI_STCK (GPIO_B0) SSI_STFS (GPIO_B1) A[11:0] D[7:0] External Address External Data Port GPIO SSI_STD (GPIO_B2) SSI_SRCK (GPIO_B3) SSI_SRFS (GPIO_B4) SPI0 Port GPIO SSI_SRD (GPIO_B5) CSPI_0_SS (GPIO_B6) External Control CSPI_0_SCK (GPIO_B7) CSPI_0_MISO (GPIO_B8) CSPI_0_MOSI (GPIO_B9) TRST GPIO RTCK MODE0 MODE1 SPI1 Port GPIO JTAG Port UART_TXD (GPIO_C0) UART Port GPIO UART_CTS (GPIO_C1) UART_RXD (GPIO_C2) UART_RTS (GPIO_C3) CSPI_1_SS (GPIO_C4) CSPI_1_SCK (GPIO_C5) CSPI_1_MISO (GPIO_C6) CSPI_1_MOSI (GPIO_C7) GPIO_B10 GPIO_B12, GPIO
Power Port
Freescale Semiconductor, Inc.
OSC32K (GPIO_C10)
SYSCLK (GPIO_C11) BTCLK (GPIO_C12)
CS[1:0]
MODE Pins
Figure MAPBGA Standard Configuration
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Mechanical Specifications
Mechanical Specifications
Packaging
MAPBGA, 100-pin 1.35 0.65 pitch
Table MC71000 Bluetooth Baseband Controller MAPBGA Ball Signal Name List
Signal Name Signal Name Signal Name
SPI1_SCK SSI_STCK SSI_SRCK SPI1_MISO PWR_PC3 SPI0_SS SSI_STD SSI_SRD PWR_CORE4 GPIO_C9 SPI1_MOSI GND_PC3 PWR_PB2 SSI_STFS SSI_SRFS GND_CORE4
OSC32K SPI1_SS BTCLK GND_PB2 SPI0_SCK SPI0_MOSI PWR_EIM2 GND_EIM2 PWR_EIM7 CLK1 SYSCLK GPIO_B11 SPI0_MISO CLK0 GPIO_B12 PWR_CORE1 GND_CORE1 GND_EIM7 MODE1 GPIO_B10 PWR_CORE3/ GND_CORE3/ RESETIN GND_PA1 GND_MISC1
MODE0 PWR_IO_I1_MISC GND_CORE2 PWR_PA1 RTCK GND_EIM3 GND_EIM4 GND_CORE2 PWR_CORE2 REFCLK EXTAL PWR_EIM3 PWR_EIM4 PWR_CORE2 REFCTRL XTAL TRST
Freescale Semiconductor, Inc.
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MOTOROLA
Freescale Semiconductor, Inc. Functionality Overview
Freescale Semiconductor, Inc.
Figure MAPBGA Package Diagram 1.35
Functionality Overview
following section describes link control link manager features detail provides information when those features will supported supported this version).
Link Control Features
following table lists, detail, supported link controller features MC71000. With only slight modification, table been prepared that closely parallels Bluetooth SIG's PICS Proforma Annex Version 0.91.
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Functionality Overview
Table Overview Link Controller Features
V0.92 V2.01 Frequency Hopping Systems Planned Future Features Support Currently Planned
Feature
79-channel frequency hopping system 23-channel frequency hopping system
Link Types
link support link support
Piconet Capabilities
Freescale Semiconductor, Inc.
simultaneous links3 Point-to-point connection Point-to-multipoint connections
Scatternet Capabilities
Master piconet slave another Slave more than piconet
Link Capabilities
simultaneous links3 Multiple links same slave Multiple links different slaves Multiple links from same master Multiple links from different masters
Common Packet Types
packet type NULL packet type POLL packet type packet type packet type
Packet Types
packet type packet type packet type packet type packet type AUX1 packet type
Packet Types
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MOTOROLA
Freescale Semiconductor, Inc. Functionality Overview
Table Overview Link Controller Features (Continued)
V0.92 V2.01 Planned Future Features
Support Currently Planned
Feature
packet type packet type packet type packet type
Paging Procedures
Paging, 79-channel system Page scan, 79-channel system
Freescale Semiconductor, Inc.
Paging, 23-channel system2
Page scan, 23-channel system
Paging Schemes
Paging scheme (Mandatory) Paging scheme (Optional
Page Scanning Modes
Paging mode Paging mode Paging mode
Paging Train Repetition
Npage Npage Npage
Inquiry Procedures
Inquiry, 79-channel system Inquiry scan, 79-channel system Inquiry, 23-channel system2 Inquiry scan, 23-channel system Inquiry support IACs Inquiry scan, simultaneous IACs
Other Link Controller Features
Transparent data pass-through Adaptive Frequency Hopping Antenna diversity 1.ROM V2.0 label assigned production-ready, qualified iteration Version 0.92. There plan "ROM V1.0". 2.The 23-channel frequency hopping system fully implemented Version 0.92, being discontinued Bluetooth SIG, extensive testing been performed.
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Functionality Overview
3.This value adjusted down reduce amount consumed MC71000.
Link Manager Features
Table lists Link Manager features MC71000. table parallels Bluetooth SIG's PICS Proforma Annex Version 0.91.
Table Overview Link Manager Features
V0.92 V2.01 Supported Features (General Statement) Planned Future Features Support Currently Planned
Feature
3-slot packets
Authentication
Freescale Semiconductor, Inc.
5-slot packets
Encryption Slot offset Timing accuracy Role switch (master/slave) Hold mode Sniff mode Park mode Power control Channel quality driven data rate RSSI
Initiate authentication before connection completed Initiate authentication after connection completed Respond authentication request
Pairing
Initiate pairing before connection completed Initiate pairing after connection completed Respond pairing request fixed request responder-to-initiator switch variable Accept initiator-to-responder switch
Link Keys
Link creation using unit (local device configured with unit key) Link creation using unit (remote device configured with unit key)
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MOTOROLA
Freescale Semiconductor, Inc. Functionality Overview
Table Overview Link Manager Features (Continued)
V0.92 V2.01 Planned Future Features
Support Currently Planned
Feature
Link creation using combination Initiate change link Accept change link Change temporary (i.e., master link key) Make semi-permanent link current link (i.e., exit master link key)
Encryption
Freescale Semiconductor, Inc.
Initiate encryption
Information Requests/Status Requests
Accept encryption requests Point-to-point encryption Point-to-point broadcast encryption size negotiation bit) Start encryption Accept start encryption Stop encryption Accept stop encryption
Request clock offset information Respond clock offset requests Send slot offset information Request timing accuracy information Respond timing accuracy requests Request version information Respond version requests Request supported features Respond supported features requests Request name information Respond name requests link quality Read RSSI
Role Switch
Request master/slave switch Accept master/slave switch requests
Detach
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Functionality Overview
V0.92 V2.01 Planned Future Features Support Currently Planned
Table Overview Link Manager Features (Continued)
Feature
Detach connection
Hold Mode
Request hold mode Respond hold mode requests Force hold mode Accept forced hold mode
Sniff Mode
Freescale Semiconductor, Inc.
Request sniff mode
Park Mode
Respond sniff mode requests Request un-sniff Accept un-sniff requests
Request park mode Respond park mode request broadcast scan window Accept change broadcast scan window Modify beacon parameters Accept modification beacon parameters Request unpark using PM_ADDR Request unpark using BD_ADDR Slave requested unpark Accept unpark using PM_ADDR Accept unpark using BD_ADDR
Power Control
Request increase power Request decrease power Respond when power reached Respond when minimum power reached
Link Supervision Timeout
link supervision timeout value Accept link supervision timeout setting
Quality Service
Channel quality driven change between packet types
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Freescale Semiconductor, Inc. Supported Commands
Table Overview Link Manager Features (Continued)
V0.92 V2.01 Planned Future Features
Support Currently Planned
Feature
Force/accept forced change Quality Service (QoS) Request/accept change
Multi-Slot Packages
Allow maximum number slots used Request maximum number slots used Accept request maximum number slots used
Freescale Semiconductor, Inc.
Paging Scheme
Request page mode Accept suggested page mode Request page scan mode Accept suggested page scan mode
Test Mode
Activate test mode tester) Enable test mode DUT) ability accept activation test mode Ability reject activation test mode test mode disabled Control test mode Ability reject test mode control commands test mode disabled
1.ROM V2.0 label assigned production-ready, qualified iteration Version 0.92. There plan V1.0. 2.ROM Version 0.92 supports Best-Effort Quality Service (QoS) only. Guaranteed Traffic types features planned Version 3.0.
Supported Commands
provides command interface baseband controller link manager, access hardware status control registers. This interface provides uniform method accessing Bluetooth baseband capabilities. Table shows currently supported commands. commands divided into following major groupings: link control, link policy, host/baseband, events, informational parameters, status parameters, testing. following list shows some features HCI: 79-channel frequency hopping Supports connection types Supports packet types Host controller flow control
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Supported Commands
Authentication pairing Change packet type Encryption Master/slave role switch Hold/sniff modes Radio power status control Test modes
Table Commands Events
Command Name Currently Supported Supported
Link Control Commands
Freescale Semiconductor, Inc.
HCI_Inquiry
Link Policy Commands
HCI_Inquiry_Cancel HCI_Periodic_Inquiry_Mode HCI_Exit_Periodic_Inquiry_Mode HCI_Create_Connection HCI_Disconnect HCI_Accept_Connection_Request HCI_Reject_Connection_Request HCI_Add_SCO_Connection HCI_Remote_Name_Request HCI_Read_Clock_Offset HCI_Authentication_Requested HCI_Link_Key_Request_Reply HCI_Pin_Code_Request_Reply HCI_Change_Connection_Link_Key HCI_Master_Link_Key HCI_Set_Connection_Encryption
HCI_Read_Link_Policy_Settings HCI_Write_Link_Policy_Settings HCI_Switch_Role HCI_Role_Discovery HCI_Read_Link_Policy_Settings HCI_Write_Link_Policy_Settings HCI_Hold_Mode HCI_Sniff_Mode
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MOTOROLA
Freescale Semiconductor, Inc. Supported Commands
Table Commands Events (Continued)
Command Name Currently Supported
Supported
HCI_Exit_Sniff_Mode HCI_Park_Mode HCI_Exit_Park_Mode HCI_QoS_Setup
Host/Baseband Commands
HCI_Read_Scan_Enable HCI_Write_Scan_Enable HCI_Read_Page_Scan_Activity HCI_Write_Page_Scan_Activity
Freescale Semiconductor, Inc.
HCI_Read_Inquiry_Scan_Activity
HCI_Write_Inquiry_Scan_Activity HCI_Read_Current_IAC_LAP HCI_Write_Current_IAC_LAP HCI_Read_Page_Timeout HCI_Write_Page_Timeout HCI_Flush HCI_Set_Event_Mask HCI_Set_Event_Filter HCI_Reset HCI_Read_Class_of_Device HCI_Write_Class_of_Device HCI_Read_Voice_Setting HCI_Write_Voice_Setting HCI_Host_Buffer_Size HCI_Read_Authentication_Enable HCI_Write_Authentication_Enable HCI_Read_PIN_Type HCI_Write_PIN_Type
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Supported Commands
Currently Supported Supported
Table Commands Events (Continued)
Command Name
HCI_Read_Stored_Link_Key HCI_Write_Stored_Link_Key HCI_Delete_Stored_Link_Key HCI_Read_Encryption_Mode HCI_Write_Encryption_Mode HCI_Read_Hold_Mode_Activity HCI_Write_Hold_Mode_Activity HCI_Read_Transmit_Power_Level HCI_Read_Page_Scan_Mode HCI_Write_Page_Scan_Mode
Freescale Semiconductor, Inc.
HCI_Read_Page_Scan_Period_Mode HCI_Write_Page_Scan_Period_Mode
Informational Parameters
HCI_Read_BD_ADDR HCI_Read_Buffer_Size HCI_Read_Country_Code
Status Parameters
HCI_Read_Failed_Contact_Counter HCI_Get_Link_Quality HCI_Read_RSSI
Testing
HCI_Read_Loopback_Mode HCI_Read_RSSI
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MOTOROLA
Freescale Semiconductor, Inc. Supported Commands
Freescale Semiconductor, Inc.
MOTOROLA
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Freescale Semiconductor, Inc.
REACH USA/EUROPE/LOCATIONS LISTED: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE:
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MC71000TB/D
Preliminary
More Information This Product, www.freescale.com

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