MC68HC11KW1 TECHNICAL DATA MC68HC11KW1 TECHNICAL DATA M
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MC68HC11KW1/D
MC68HC11KW1 TECHNICAL DATA
MC68HC11KW1
TECHNICAL DATA
MC68HC11KW1
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
Conventions
Where abbreviations used text, explanation found glossary, back this manual. Register mnemonics defined paragraphs describing them. overbar used designate active-low signal, RESET. Because bits register necessarily linked common function, description register appear several sections referring different aspects device operation. full description given only section which relevance. Elsewhere, appears shaded register diagram only briefly described. When state reset described `x', this means that state depends factors such operating mode selected. indicates that bit's state reset undefined.
TABLE CONTENTS
Paragraph Number TITLE Page Number
INTRODUCTION
Features.1-1 Mask option .1-2
DESCRIPTIONS
RESET.2-2 Crystal driver external clock input (XTAL, EXTAL).2-3 .2-4 clock output .2-4 XOUT.2-4 Interrupt request (IRQ) .2-4 Nonmaskable interrupt (XIRQ) .2-5 MODA MODB (MODA/LIR MODB/VSTBY) .2-5 .2-6 2.10 R/W.2-6 2.11 Port signals .2-6 2.11.1 Port .2-6 2.11.2 Port .2-8 2.11.3 Port .2-8 2.11.4 Port .2-8 2.11.5 Port .2-9 2.11.6 Port .2-9 2.11.7 Port G.2-9 2.11.8 Port .2-10 2.11.9 Port J.2-10 2.11.10 Port .2-10
MC68HC11KW1
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CENTRAL PROCESSING UNIT
Registers .3-1 3.1.1 Accumulators D.3-2 3.1.2 Index register (IX) .3-2 3.1.3 Index register (IY) .3-2 3.1.4 Stack pointer (SP).3-2 3.1.5 Program counter (PC).3-4 3.1.6 Condition code register (CCR).3-4 3.1.6.1 Carry/borrow .3-5 3.1.6.2 Overflow .3-5 3.1.6.3 Zero .3-5 3.1.6.4 Negative .3-5 3.1.6.5 Interrupt mask (I).3-5 3.1.6.6 Half carry (H).3-6 3.1.6.7 interrupt mask .3-6 3.1.6.8 Stop disable (S).3-6 Data types .3-6 Opcodes operands .3-7 Addressing modes.3-7 Immediate (IMM) .3-7 3.5.1 Direct (DIR).3-7 3.5.2 Extended (EXT) .3-8 3.5.3 Indexed (IND, IND, Y).3-8 3.5.4 Inherent (INH) .3-8 3.5.5 Relative (REL).3-8 Instruction .3-8
OPERATING MODES ON-CHIP MEMORY
Operating modes .4-1 4.1.1 Single chip operating mode .4-1 4.1.2 Expanded operating mode.4-1 4.1.3 Special test mode .4-2 4.1.4 Special bootstrap mode .4-2 On-chip memory.4-3 4.2.1 Mapping allocations .4-3 4.2.1.1 .4-4 4.2.1.2 Bootloader .4-4 4.2.2 Registers.4-4 System initialization .4-10 4.3.1 Mode selection.4-10 4.3.1.1 HPRIO Highest priority I-bit interrupt misc. register .4-11
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4.3.2 Initialization .4-12 4.3.2.1 CONFIG System configuration register .4-12 4.3.2.2 INIT mapping register .4-13 4.3.2.3 INIT2 EEPROM mapping register.4-15 4.3.2.4 OPTION System configuration options register 1.4-15 4.3.2.5 OPT2 System configuration options register .4-17 4.3.2.6 BPROT Block protect register.4-18 4.3.2.7 TMSK2 Timer interrupt mask register .4-20 4.3.2.8 TCTL4 TCTL6 Timer control registers .4-21 Memory expansion .4-22 4.4.1 Memory expansion logic .4-22 4.4.2 Extended addressing .4-23 4.4.3 Memory expansion examples .4-24 4.4.4 MMSIZ Memory mapping window size register.4-29 4.4.5 MMWBR Memory mapping window base register .4-30 4.4.6 MM1CR, MM2CR Memory mapping window control registers .4-31 4.4.7 PGAR Port assignment register .4-32 Chip selects .4-32 4.5.1 Chip select priorities.4-33 4.5.2 Program chip select .4-33 4.5.3 chip select .4-33 4.5.4 CSCTL Chip select control register .4-34 4.5.5 General-purpose chip selects .4-35 4.5.5.1 GPCS1A General-purpose chip select address register .4-35 4.5.5.2 GPCS1C General-purpose chip select control register .4-36 4.5.5.3 GPCS2A General-purpose chip select address register .4-37 4.5.5.4 GPCS2C General-purpose chip select control register .4-37 4.5.6 chip select driving another .4-38 4.5.7 Clock stretching .4-39 4.5.7.1 CSCSTR Chip select clock stretch register .4-39 EEPROM CONFIG register .4-41 4.6.1 EEPROM .4-41 4.6.1.1 PPROG EEPROM programming control register .4-41 4.6.1.2 EEPROM bulk erase .4-43 4.6.1.3 EEPROM erase .4-43 4.6.1.4 EEPROM byte erase .4-44 4.6.2 CONFIG register programming .4-44 4.6.3 EEPROM security .4-45
RESETS INTERRUPTS
Resets .5-1 5.1.1 Power-on reset .5-1 5.1.2 External reset (RESET) .5-2
MC68HC11KW1
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5.1.3 reset .5-2 5.1.3.1 COPRST Arm/reset timer circuitry register.5-3 5.1.4 Clock monitor reset .5-3 5.1.5 OPTION System configuration options register .5-4 5.1.6 CONFIG Configuration control register .5-5 Effects reset.5-6 5.2.1 Central processing unit .5-7 5.2.2 Memory map.5-7 5.2.3 Parallel .5-7 5.2.4 Timer 1.5-7 5.2.5 Timers 3.5-8 5.2.6 Real-time interrupt (RTI) .5-8 5.2.7 Pulse accumulator .5-8 5.2.8 Computer operating properly (COP).5-8 5.2.9 Serial communications interface (SCI).5-8 5.2.10 Serial peripheral interface (SPI).5-9 5.2.11 Analog-to-digital converter.5-9 5.2.12 System.5-9 Reset interrupt priority .5-9 5.3.1 HPRIO Highest priority I-bit interrupt misc. register .5-10 Interrupts .5-13 5.4.1 Interrupt recognition register stacking.5-13 5.4.2 Nonmaskable interrupt request (XIRQ) .5-14 5.4.3 Illegal opcode trap .5-14 5.4.4 Software interrupt .5-14 5.4.5 Maskable interrupts .5-15 5.4.6 Reset interrupt processing.5-15 power operation .5-15 5.5.1 WAIT .5-15 5.5.2 STOP .5-16
PARALLEL INPUT/OUTPUT
6.1.1 6.1.2 6.2.1 6.2.2 6.3.1 6.3.2 6.4.1 Port A.6-2 PORTA Port data register .6-2 DDRA Data direction register port .6-2 Port B.6-3 PORTB Port data register .6-3 DDRB Data direction register port .6-3 Port .6-4 PORTC Port data register.6-4 DDRC Data direction register port C.6-4 Port .6-5 PORTD Port data register.6-5
TABLE CONTENTS
MC68HC11KW1
Paragraph Number 6.4.2 6.5.1 6.6.1 6.6.2 6.7.1 6.7.2 6.7.3 6.8.1 6.8.2 6.9.1 6.9.2 6.10 6.10.1 6.10.2 6.11 6.11.1 6.12 6.12.1 6.12.2
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DDRD Data direction register port D.6-5 Port E.6-6 PORTE Port data register .6-6 Port .6-7 PORTF Port data register.6-7 DDRF Data direction register port F.6-7 Port .6-8 PORTG Port data register .6-8 DDRG Data direction register port .6-9 PGAR Port assignment register .6-9 Port H.6-10 PORTH Port data register.6-10 DDRH Data direction register port H.6-10 Port .6-11 PORTJ Port data register .6-11 DDRJ Data direction register port .6-11 Port K.6-12 PORTK Port data register .6-12 DDRK Data direction register port .6-12 Internal pull-up resistors .6-13 PPAR Port pull-up assignment register .6-13 System configuration .6-14 OPT2 System configuration options register 2.6-14 CONFIG System configuration register .6-15
SERIAL COMMUNICATIONS INTERFACE
7.4.1 7.4.2 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7.1 Data format .7-2 Transmit operation .7-2 Receive operation.7-2 Wake-up feature .7-4 Idle-line wake-up .7-4 Address-mark wake-up .7-4 error detection .7-5 registers .7-5 SCBDH, SCBDL baud rate control registers .7-6 SCCR1 control register .7-7 SCCR2 control register .7-9 SCSR1 status register 1.7-10 SCSR2 status register 2.7-11 SCDRH, SCDRL data high/low registers .7-12 Status flags interrupts.7-12 Receiver flags .7-13
MC68HC11KW1
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SERIAL PERIPHERAL INTERFACE
8.2.1 8.3.1 8.3.2 8.3.3 8.3.4 8.5.1 8.5.2 8.5.3 8.5.4 Functional description .8-1 transfer formats.8-2 Clock phase polarity controls.8-3 signals .8-3 Master slave out.8-4 Master slave in.8-4 Serial clock .8-4 Slave select.8-4 system errors .8-5 registers .8-5 SPCR control register.8-6 SPSR status register .8-8 SPDR data register .8-9 OPT2 System configuration options register 2.8-9
TIMING SYSTEM
Timer .9-1 9.1.1 Timer structure.9-3 9.1.2 Input capture.9-4 9.1.2.1 TCTL2 Timer control register 2.9-6 9.1.2.2 TIC1-TIC3 Timer input capture registers .9-7 9.1.2.3 TI4/O5 Timer input capture 4/output compare register.9-7 9.1.3 Output compare .9-8 9.1.3.1 TOC1-TOC4 Timer output compare registers.9-9 9.1.3.2 CFORC Timer compare force register .9-9 9.1.3.3 OC1M Output compare mask register.9-10 9.1.3.4 OC1D Output compare data register.9-10 9.1.3.5 TCNT Timer counter register .9-11 9.1.3.6 TCTL1 Timer control register 1.9-11 9.1.3.7 TMSK1 Timer interrupt mask register 1.9-12 9.1.3.8 TFLG1 Timer interrupt flag register .9-13 9.1.3.9 TMSK2 Timer interrupt mask register 2.9-14 9.1.3.10 TFLG2 Timer interrupt flag register .9-15 Timer .9-15 9.2.1 Output compare .9-18 9.2.2 Input capture.9-18 9.2.3 F23FRC Compare force register Timers .9-18 9.2.4 T2C4 Timer channel register.9-19 9.2.5 T2OC1-T2OC3 Timer output compare registers .9-19 9.2.6 TCNT2 Timer counter register.9-20
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9.2.7 TCTL3 Timer control register (Timer .9-20 9.2.8 TCTL4 Timer control register (Timer .9-21 9.2.9 T2MSK Timer interrupt mask register.9-22 9.2.10 T2FLG Timer interrupt flag register .9-23 Timer .9-24 9.3.1 T3C4 Timer channel register .9-24 9.3.2 T3OC1-T3OC3 Timer output compare registers .9-26 9.3.3 TCNT3 Timer counter register.9-26 9.3.4 TCTL5 Timer control register (Timer .9-27 9.3.5 TCTL6 Timer control register (Timer .9-27 9.3.6 T3MSK Timer interrupt mask register.9-29 9.3.7 T3FLG Timer interrupt flag register .9-30 Real-time interrupt .9-31 9.4.1 TMSK2 Timer interrupt mask register 2.9-31 9.4.2 TFLG2 Timer interrupt flag register .9-32 9.4.3 PACTL Pulse accumulator control register .9-33 Computer operating properly watchdog function .9-33 Pulse accumulator .9-33 9.6.1 PACTL Pulse accumulator control register .9-35 9.6.2 PACNT Pulse accumulator count register .9-36 9.6.3 Pulse accumulator status interrupt bits .9-36 9.6.3.1 TMSK2 Timer interrupt mask register .9-36 9.6.3.2 TFLG2 Timer interrupt flag register .9-36 Pulse-width modulation (PWM) timer .9-37 9.7.1 timer block diagram .9-38 9.7.2 PWCLK clock prescaler 16-bit select register.9-38 9.7.2.1 16-bit function .9-38 9.7.2.2 Clock prescaler selection .9-40 9.7.3 PWPOL timer polarity clock source select register .9-41 9.7.4 PWSCAL timer prescaler register.9-41 9.7.5 PWEN timer enable register .9-42 9.7.6 PWCNT1-4 timer counter registers 4.9-43 9.7.7 PWPER1-4 timer period registers 4.9-43 9.7.8 PWDTY1-4 timer duty cycle registers 4.9-44 9.7.9 Boundary cases .9-44
ANALOG-TO-DIGITAL CONVERTER
10.1 Conversion process .10-2 10.2 Channel assignments .10-2 10.3 Single channel operation .10-3 10.3.1 4-conversion, single scan.10-4 10.3.2 4-conversion, continuous scan.10-4 10.3.3 8-conversion, single scan.10-4
MC68HC11KW1
TABLE CONTENTS
Paragraph Number 10.3.4 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.6 10.7 10.7.1 10.7.2 10.7.3
TITLE
Page Number
8-conversion, continuous scan .10-4 Multiple channel operation.10-4 4-channel single scan .10-5 4-channel continuous scan .10-5 8-channel single scan .10-5 8-channel continuous scan .10-5 Power-up clock select.10-5 Operation STOP WAIT modes.10-6 Registers .10-6 ADCTL control status register .10-6 ADFRQ converter frequency select register .10-7 ADR1 ADR8 result registers .10-8
ELECTRICAL SPECIFICATIONS
A.5.1 A.5.2 A.5.3 A.5.4 Maximum ratings Thermal characteristics power considerations Test methods electrical characteristics Control timing Peripheral port timing. Analog-to-digital converter characteristics. A-10 Serial peripheral interface timing A-11 Non-multiplexed expansion timing A-14 EEPROM characteristics A-15
MECHANICAL DATA
Packaging
DEVELOPMENT SYSTEMS
Evaluation system. MMDS11 Motorola modular development system SPGMR11 Serial peripheral system
TABLE CONTENTS viii
MC68HC11KW1
LIST FIGURES
Figure Number TITLE Page Number
MC68HC11KW1 block diagram.1-3 MC68HC11KW1 100-pin TQFP.2-1 External reset circuitry.2-2 Oscillator connections .2-3 stand-by connections.2-5 Programming model .3-1 Stacking operations .3-3 MC68HC11KW1 memory .4-3 register overlap.4-14 Memory example memory expansion.4-25 Schematic example memory expansion .4-26 Memory example memory expansion.4-27 Schematic example memory expansion .4-28 Processing flow reset .5-17 Processing flow reset .5-18 Interrupt priority resolution .5-19 Interrupt priority resolution .5-20 Interrupt priority resolution .5-21 Interrupt source resolution within subsystem .5-22 baud rate generator circuit diagram.7-1 block diagram .7-3 Interrupt source resolution within SCI.7-14 block diagram.8-2 transfer format.8-3 Timer clock divider chains .9-2 Timer capture/compare block diagram .9-5 Timer capture/compare block diagram .9-17 Timer capture/compare block diagram .9-25 Pulse accumulator block diagram.9-34 timer block diagram.9-39 duty cycle.9-44 Test methods Timer inputs.
MC68HC11KW1
LIST FIGURES
Figure Number A-10 A-11 A-12 A-13 A-14
TITLE
Page Number
Reset timing .A-6 Interrupt timing .A-6 STOP recovery timing .A-7 WAIT recovery timing .A-7 Port read timing diagram .A-8 Port control timing.A-8 Port write timing diagram.A-9 master timing (CPHA .A-12 master timing (CPHA .A-12 slave timing (CPHA .A-13 slave timing (CPHA .A-13 Expansion timing .A-15 100-pin TQFP .B-1 100-pin TQFP mechanical dimensions.B-2
LIST FIGURES
MC68HC11KW1
LIST TABLES
Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 TITLE Page Number
Port signal functions .2-7 Reset vector comparison.3-4 Instruction .3-9 Example bootloader baud rates.4-2 Register control assignments .4-5 Registers with limited write access.4-10 Hardware mode select summary.4-11 register remapping.4-14 EEPROM remapping .4-15 XCLK frequencies.4-18 EEPROM block protect.4-19 address address expansion signals.4-24 Window size select .4-29 Memory expansion window base address.4-30 Chip select priorities .4-33 Program chip select size .4-34 General purpose chip select priority.4-35 General-purpose chip select size control .4-37 General-purpose chip select size control .4-38 chip select driving another .4-39 Chip select control parameter summary.4-40 Erase mode selection .4-42 timer rate select .5-2 Reset cause, reset vector operating mode .5-6 Highest priority interrupt selection .5-11 Interrupt reset vector assignments .5-12 Stacking order entry interrupts .5-13 Port configuration .6-1 Example baud rate control values .7-7 clock rates.8-7 Timer resolution capacity.9-3 periodic rates .9-31 Pulse accumulator timing .9-34
MC68HC11KW1
LIST TABLES xiii
Table Number 10-1
TITLE
Page Number
Clock clock prescalers 9-40 Channel assignments. 10-3 M68HC11 development tools
LIST TABLES
MC68HC11KW1
INTRODUCTION
MC68HC11KW1 8-bit microcontroller member M68HC11 family HCMOS microcontrollers. bytes EEPROM bytes RAM. Making 100-pin TQFP package, non-multiplexed expanded feature this device. main timer system includes three input captures, four output compares software selectable input capture output compare. There additional 16-bit timers, each with three output compares software selectable input capture output compare. Other major features this device are: 10-channel, 10-bit resolution converter, four timer channels, (serial peripheral interface) enhanced (serial communications interface). common with other family members, MC68HC11KW1 also includes 8-bit pulse accumulator circuit, real time interrupt facility, computer operating properly watchdog system. This device intended expanded memory applications.
Features
power, high performance M68HC11 core with 4MHz internal frequency bytes bytes byte-erasable EEPROM, with on-chip charge pump bytes boot general purpose lines, plus input-only lines Non-multiplexed address data buses, permitting direct access full byte address Memory expansion unit, with address extension lines, allowing (for example) sixteen byte banks external memory addressed either bank windows Four external chip selects 16-bit timer with input captures output compares; pulse accumulator watchdog timer Real-time interrupt circuit
MC68HC11KW1
INTRODUCTION
additional 16-bit timers, each with output compares input capture output compare (may externally clocked, required, external event counter operation) subsystem (NRZ type compatibility with standard RS232 systems) with parity modulus prescaler subsystem, with software selectable MSB/LSB first option increased baud rate selection range 10-channel, 10-bit analog-to-digital converter Four 8-bit timer channels Available 100-pin TQFP package
Mask option
There single mask option MC68HC11KW1, which programmed during manufacture must specified order form: Security option (available/unavailable). Section 4.6.3
INTRODUCTION
MC68HC11KW1
Periodic interrupt watchdog OC4/IC1 ECIN
Port
Port
OC4/IC1 ECIN
Pulse accumulator
Timer
Timer
OC1/PAI OC1/OC2 OC1/OC3 OC1/OC4 IC4/OC1/OC5
VDDAD VSSAD
Port
SPI+ SCI+
bytes EEPROM 10-channel, 10-bit converter
bytes
XIRQ RESET LIR/MODA VSTBY/MODB XTAL EXTAL XOUT
Memory expansion M68HC11 Chip selects
Oscillator
CSPROG CSGP2 CSGP1 CSIO
Non-multiplexed address data buses
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR0 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Port
Port
Port
Figure MC68HC11KW1 block diagram
MC68HC11KW1
INTRODUCTION
Port
Port
Interrupts mode select
XA18 XA17 XA16 XA15 XA14 XA13
Port
Port
Timer
MOSI MISO
THIS PAGE LEFT BLANK INTENTIONALLY
INTRODUCTION
MC68HC11KW1
DESCRIPTIONS
MC68HC11KW1 available packaged 100-pin thin quad flat pack (TQFP), shown Figure 2-1. Most pins this serve more functions, described following paragraphs.
PK4/OC1 PK3/ECIN PH0/PWM1 PH1/PWM2 PH2/PWM3 PH3/PWM4 PH4/CSIO PH5/CSGP1 PH6/CSGP2 PH7/CSPROG XIRQ PG0/XA13 PG1/XA14 PG2/XA15 PG3/XA16 PG4/XA17 PG5/XA18 PG6/AN0 PG7/AN1
PK5/OC2 PK6/OC3 PK7/C4 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 PA0/IC3/OC1 PA1/IC2/OC1 PA2/IC1/OC1 PA3/IC4/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 PD5/SS PD4/SCK
PD3/MOSI PD2/MISO PD1/TXD PD0/RXD MODA/LIR MODB/VSTBY RESET XTAL EXTAL XOUT PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 PF0/ADDR0 PF1/ADDR1 PF2/ADDR2
Figure MC68HC11KW1 100-pin TQFP
MC68HC11KW1
VDDAD PE7/AN9 PE6/AN8 PE5/AN7 PE4/AN6 PE3/AN5 PE2/AN4 PE1/AN3 PE0/AN2 VSSAD PJ3/ECIN PJ4/OC1 PJ5/OC2 PJ6/OC3 PJ7/C4 PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3
DESCRIPTIONS
RESET
active-low, bidirectional control signal, RESET acts input initialize known start-up state. also acts open-drain output indicate that internal failure been detected either clock monitor watchdog circuit. distinguishes between internal external reset conditions sensing whether reset rises logic less than four clock cycles after internal reset been released. therefore advisable connect external resistor-capacitor (RC) power-up delay circuit reset M68HC11 devices because circuit charge time constant cause device misinterpret type reset that occurred. Refer Section further information. Figure illustrates typical reset circuit that includes external switch together with voltage inhibit circuit, prevent power transitions, EEPROM corruption.
RESET MC34064
M68HC11 RESET
Manual reset
RESET MC34164
Figure External reset circuitry
DESCRIPTIONS
MC68HC11KW1
Crystal driver external clock input (XTAL, EXTAL)
These pins provide interface either crystal CMOS compatible clock control internal clock generator circuitry. frequency applied these pins must four times higher than desired clock rate. Refer Figure 2-3. XTAL normally left unconnected when external CMOS compatible clock input connected EXTAL pin. XTAL output normally intended drive only crystal. XTAL output buffered with high-impedance buffer, used drive EXTAL input another M68HC11 family device. cases, caution when designing circuitry associated with oscillator pins.
EXTAL Common crystal connections M68HC11 XTAL crystal
EXTAL External oscillator connections M68HC11 XTAL
External oscillator
EXTAL M68HC11 XTAL crystal
EXTAL
M68HC11
XTAL
crystal driving MCUs Note: capacitor values include stray capacitance.
Figure Oscillator connections
MC68HC11KW1
DESCRIPTIONS
Power supplied microcontroller these pins. positive supply ground. operates from (nominal) power supply. nature CMOS designs that very fast signal transitions occur pins. These short rise fall times place very high short-duration current demands power supply. prevent noise problems, special care must taken provide good power supply bypassing MCU. Bypass capacitors should have good high-frequency characteristics close possible. Bypassing requirements vary, depending heavily pins loaded. MC68HC11KW1 four pins four pins. pair these pins reserved supplying power analog-to-digital converter (VDDAD, VSSAD); remaining pins used internal logic, supply power port logic either half chip.
clock output
output connection internally generated clock. signal from used timing reference. frequency clock output quarter that input frequency XTAL EXTAL pins. When clock output low, internal process taking place; when high, data being accessed. clocks, including clock, halted when STOP mode. clock output turned single-chip modes reduce effects (see Section 4.3.2.5).
XOUT
XOUT outputs buffered CLKX signal, enabled XCLK CONFIG register. frequency CLKX selected using bits OPT2 register (XDV1 XDV2). reset, CLKX same frequency EXTAL (4E). Section Note that phase relationship between CLKX EXTAL cannot predicted.
Interrupt request (IRQ)
input provides means applying asynchronous interrupt requests MCU. Either falling-edge-sensitive triggering level-sensitive triggering program selectable (OPTION register). always configured level-sensitive-triggering reset.
Note:
Connect external pull-up resistor, typically when used level sensitive wired-OR configuration. also Section 2.7.
DESCRIPTIONS
MC68HC11KW1
Nonmaskable interrupt (XIRQ)
XIRQ input provides means requesting nonmaskable interrupt after reset initialization. During reset, condition code register (CCR) interrupt masked until software enables XIRQ often used power loss detect interrupt. Whenever XIRQ used with multiple interrupt sources (IRQ must configured level-sensitive operation there more than source interrupt), each source must drive interrupt input with open-drain type driver avoid contention between outputs. There should single pull-up resistor near interrupt input (typically There must also interlock mechanism each interrupt source that source holds interrupt line until recognizes acknowledges interrupt request. more interrupt source still pending after services request, interrupt line will still held will interrupted again soon interrupt mask cleared (normally upon return from interrupt). Refer Section
MODA MODB (MODA/LIR MODB/VSTBY)
During reset, MODA MODB select four operating modes. Refer Section After operating mode been selected, provides open-drain output (driven low) indicate that execution instruction begun. order detect consecutive instructions high-speed application, this signal drives high short time prevent false triggering. series clock cycles occurs during execution each instruction. signal goes during first clock cycle each instruction (opcode fetch). This output provided assistance program debugging, operation controlled LIRDV OPT2 register. VSTBY used input stand-by power. powered from unless difference between level VSTBY greater than threshold (about volts). When these voltages differ more than volts, internal part reset logic powered from VSTBY rather than VDD. This allows contents retained without power applied MCU. Reset must driven before removed must remain until been restored valid level.
NiCd BATT VOUT 4.7k MODB/VSTBY
Figure stand-by connections
MC68HC11KW1
DESCRIPTIONS
These pins provide reference voltages analog-to-digital converter.
2.10
expanded test modes, performs read/write function. signals direction transfers external data bus. high this indicates that read cycle progress. single chip mode signal driven low.
2.11
Port signals
MC68HC11KW1 includes pins that arranged into 8-bit ports port pins bidirectional, except PG7, port pins [7:0]; these input only. Most bidirectional ports serve purpose other than I/O, depending operating mode peripheral function selected. input-only pins used general-purpose inputs, inputs converter. Note that ports available functions only single chip bootstrap modes. Refer Table details port signals' functions different operating modes.
Note:
When using information about port functions, confuse function with electrical state reset. general purpose pins configured inputs reset high-impedance state. Port data registers reflect functional state port reset. function mode dependent.
2.11.1
Port
Port 8-bit, general-purpose port with data register (PORTA) data direction register (DDRA). Port pins share functions with main 16-bit timer system, Timer (see Section further information). PORTA read time always returns level. written, PORTA stores data internal latches. pins driven only they configured outputs. Writes PORTA change state when pins configured timer output compares. reset, port pins [7:0] general purpose high-impedance inputs. When functions associated with these pins disabled, bits DDRA govern state associated pin. further information, refer Section
DESCRIPTIONS
MC68HC11KW1
Table Port signal functions
Single chip Expanded multiplexed bootstrap mode special test mode PA7/PAI and/or PA6/OC2 and/or PA5/OC3 and/or PA4/OC4 and/or PA3/OC5/IC4 and/or PA2/IC1 PA1/IC2 PA0/IC3 PB[7:0] ADDR[15:8] PC[7:0] DATA[7:0] PD[7, PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TXD PD0/RXD Input only analog inputs PF[7:0] ADDR[7:0] Input only analog inputs PG[5:0] PG[5:0] XA[18:13] CSPROG CSGP2 CSGP1 CSIO PH[3:0] PWM[4:1] ECIN PJ[2,0] ECIN PK[2,0]
Port/bit PB[7:0] PC[7:0] PD[7,6] PE[7:0] PF[7:0] PG[7,6] PG[5:0] PH[3:0] PJ[2,0] PK[2,0]
MC68HC11KW1
DESCRIPTIONS
2.11.2
Port
Port 8-bit, general-purpose port with data register (PORTB) data direction register (DDRB). single chip mode, port pins general purpose pins (PB[7:0]). expanded mode, port pins high-order address lines (ADDR[15:8]) address bus. PORTB read time always returns level. PORTB written, data stored internal latches. pins driven only they configured outputs single chip bootstrap mode. further information, refer Section Port pins include on-chip pull-up devices which enabled disabled port pull-up assignment register (PPAR).
2.11.3
Port
Port 8-bit, general-purpose port with data register (PORTC) data direction register (DDRC). single chip mode, port pins general purpose pins (PC[7:0]). expanded mode, port pins configured data pins (DATA[7:0]). PORTC read time; inputs return level outputs return driver input level. PORTC written, data stored internal latches. pins driven only they configured outputs single chip bootstrap mode. Port pins general purpose inputs reset single chip bootstrap modes. expanded test modes, these pins data lines reset. CWOM control OPT2 register disables port p-channel output drivers. Because n-channel driver affected CWOM, setting CWOM causes port become open-drain-type output port suitable wired-OR operation. wired-OR mode (PORTC bits logic level zero), pins actively driven n-channel driver. When port logic level one, associated high impedance state neither n-channel p-channel devices active. customary have external pull-up resistor lines that driven open-drain devices. Port only configured wired-OR operation when single chip mode. further information, refer Section
2.11.4
Port
Port 8-bit, general-purpose port, data register (PORTD) data direction register (DDRD). port pins used general purpose I/O, pins [5:0] also used serial peripheral interface (SPI, pins [5:2]) serial communications interface (SCI, pins [1,0]). PORTD read time; inputs return level outputs return driver input level. PORTD written, data stored internal latches. pins driven only port configured general purpose output.
DESCRIPTIONS
MC68HC11KW1
DWOM SPCR disables p-channel output drivers pins D[5:2], WOMS SCCR1 disables those pins D[1,0]. Because n-channel driver affected DWOM WOMS, setting either causes corresponding port pins become open-drain-type outputs suitable wired-OR operation. wired-OR mode (PORTD bits logic level zero), pins actively driven n-channel driver. When port logic level one, associated high impedance state neither n-channel p-channel devices active. customary have external pull-up resistor lines that driven open-drain devices. Port configured wired-OR operation when single chip expanded mode. further information, refer Section Section (SCI) Section (SPI).
2.11.5
Port
Port pins used analog inputs analog-to-digital converter, general-purpose inputs. further information, refer Section Section (A/D).
2.11.6
Port
Port 8-bit, general-purpose port with data register (PORTF) data direction register (DDRF). single chip mode, port pins general purpose pins (PF[7:0]). expanded mode, port pins low-order address lines (ADDR[7:0]) address bus. PORTF read time always returns level. PORTF written, data stored internal latches. pins driven only they configured outputs single chip bootstrap mode. Port pins include on-chip pull-up devices that enabled disabled port pull-up assignment register (PPAR). further information, refer Section
2.11.7
Port
normal modes, Port 8-bit general-purpose port with lines (PG[5:0]), input only lines (PG[7, 6]). Associated with port data register (PORTG), data direction register (DDRG) assignment register (PGAR). Pins used general-purpose inputs, inputs analog-to-digital converter. functions pins [5:0] controlled bits port assignment register (PGAR), which select whether pins used general purpose I/O, expanded mode, memory expansion lines XA[18:13]. PORTG read time always returns level. PORTG written, data stored into internal latch. driven only configured output. Pins [5:0] have on-chip pull-up devices that enabled disabled port pull-up assignment register (PPAR). Refer Section Section (A/D) Section
MC68HC11KW1
DESCRIPTIONS
2.11.8
Port
Port 8-bit general-purpose port with data register (PORTH) data direction register (DDRH). Port lines used general-purpose I/O, chip select lines (PH[7:4]), pulse width modulation timer (PWM, PH[3:0]). PORTH read time always returns level. PORTH written, data stored into internal latch. driven only configured output. Port pins include on-chip pull-up devices that enabled disabled port pull-up assignment register (PPAR). further information, refer Section Section (Timing system) Section
2.11.9
Port
Port 8-bit, general-purpose port with data register (PORTJ) data direction register (DDRJ). Port lines used general-purpose I/O, pins [7:3] share functions with 16-bit timers, Timer PORTJ read time always returns level. written, PORTJ stores data internal latches. pins driven only they configured outputs. Writes PORTJ change state when pins configured timer output compares. reset, port pins [7:0] general purpose high-impedance inputs. When functions associated with these pins disabled, bits DDRJ govern state associated pin. further information, refer Section Section (Timing system).
2.11.10
Port
Port 8-bit general-purpose port with data register (PORTK) data direction register (DDRK). Port lines used general-purpose I/O, pins [7:3] share functions with 16-bit timers, Timer PORTK read time always returns level. written, PORTK stores data internal latches. pins driven only they configured outputs. Writes PORTK change state when pins configured timer output compares. reset, port pins [7:0] general purpose high-impedance inputs. When functions associated with these pins disabled, bits DDRK govern state associated pin. further information, refer Section Section (Timing system).
DESCRIPTIONS 2-10
MC68HC11KW1
CENTRAL PROCESSING UNIT
This section discusses M68HC11 central processing unit (CPU) architecture, addressing modes instruction set. more detailed information instruction set, refer M68HC11 Reference Manual (M68HC11RM/AD). designed treat peripheral, memory locations identically, addresses 64Kbyte memory map. This referred memory-mapped I/O. There special instructions that separate from those used memory. This architecture also allows accessing operand from external memory location with execution-time penalty.
Registers
M68HC11 registers integral part addressed they were memory locations. seven registers shown Figure discussed following paragraphs.
Accumulator Accumulator Double accumulator Index register Index register Stack pointer Program counter
Carry Overflow Zero Negative Interrupt mask Half carry (from Interrupt mask Stop disable
Condition code register
Figure Programming model
MC68HC11KW1
CENTRAL PROCESSING UNIT
3.1.1
Accumulators
Accumulators general purpose 8-bit registers that hold operands results arithmetic calculations data manipulations. some instructions, these accumulators treated single double-byte (16-bit) accumulator called accumulator Although most operations accumulators interchangeably, following exceptions apply: instructions contents 8-bit accumulator contents 16-bit register there equivalent instructions that instead instructions transfer data from accumulator condition code register, from condition code register accumulator however, there equivalent instructions that rather than decimal adjust accumulator (DAA) instruction used after binary-coded decimal (BCD) arithmetic operations, there equivalent instruction adjust accumulator add, subtract, compare instructions associated with both (ABA, SBA, CBA) only operate direction, making important plan ahead ensure correct operand correct accumulator.
3.1.2
Index register (IX)
register provides 16-bit indexing value that added 8-bit offset provided instruction create effective address. register also used counter temporary storage register.
3.1.3
Index register (IY)
16-bit register performs indexed mode function similar that register. However, most instructions using register require extra byte machine code extra cycle execution time because opcode implemented. Refer Section further information.
3.1.4
Stack pointer (SP)
M68HC11 automatic program stack. This stack located anywhere address space size amount memory available system. Normally initialized first instructions application program. stack configured data structure that grows downward from high memory memory. Each time byte pushed onto stack, decremented. Each time byte pulled from stack, incremented. given time, holds 16-bit address next free location stack. Figure summary operations.
CENTRAL PROCESSING UNIT
MC68HC11KW1
JSR, Jump subroutine
Main program
DIRECT Next instruction
BSR, Branch subroutine
Main program
Next instruction SP-2 SP-1
Stack
Main program
IND, Next instruction
SWI, Software interrupt
Stack
SP-2 SP-1
Stack
SP-9 SP-8 SP-7 SP-6 SP-5 SP-4 SP-3 SP-2 SP-1 Condition Code Accumulator Accumulator Index register (IXH Index register (IXL) Index register (IYH Index register (IYL)
Main program
Main program
IND, Next instruction
WAI, Wait interrupt
Main program
Main program
EXTEND Next instruction
RTI, Return from interrupt
Interrupt program
SP+1 SP+2 SP+3 SP+4 SP+5 SP+6 SP+7 SP+8 SP+9
Stack
Condition Code Accumulator Accumulator Index register (IXH Index register (IXL) Index register (IYH Index register (IYL)
RTS, Return from subroutine
Main program
Stack
SP+1 SP+2
LEGEND Address next instruction main program, executed return from subroutine RTNH More significant byte return address RTNL Less significant byte return address Shaded cells show stack pointer position after operation complete 8-bit direct address ($0000-$00FF); high byte assumed 8-bit positive offset ($00 256)) added index register contents High order byte 16-bit extended address order byte 16-bit extended address Signed relative offset ($80 (-128 +127)); offset relative address following offset byte
Figure Stacking operations
MC68HC11KW1
CENTRAL PROCESSING UNIT
When subroutine called jump subroutine (JSR) branch subroutine (BSR) instruction, address instruction after automatically pushed onto stack, less significant byte first. When subroutine finished, return from subroutine (RTS) instruction executed. pulls previously stacked return address from stack, loads into program counter. Execution then continues this recovered return address. When interrupt recognized, current instruction finishes normally, return address (the current value program counter) pushed onto stack, registers pushed onto stack, execution continues address specified vector interrupt. interrupt service routine, instruction executed. instruction causes saved registers pulled stack reverse order. Program execution resumes return address. There instructions that push pull accumulators index registers. These instructions often used preserve program context. example, pushing accumulator onto stack when entering subroutine that uses accumulator then pulling accumulator stack just before leaving subroutine, ensures that contents register will same after returning from subroutine before starting subroutine.
3.1.5
Program counter (PC)
program counter, 16-bit register, contains address next instruction executed. After reset, program counter initialized from possible vectors, depending operating mode cause reset.
Table Reset vector comparison
RESET $FFFE, $FFFF $BFFE, $BFFF Clock monitor $FFFC, $FFFD $BFFE, $BFFF watchdog $FFFA, $FFFB $BFFE, $BFFF
Normal Test Boot
3.1.6
Condition code register (CCR)
This 8-bit register contains five condition code indicators interrupt masking bits, (IRQ XIRQ) stop disable (S). M68HC11 CPU, condition codes automatically updated most instructions. example, load accumulator (LDAA) store accumulator (STAA) instructions automatically clear condition code flags. Pushes, pulls, (ABX), (ABY), transfer/exchange instructions affect condition codes. Refer Table 3-2, which shows condition codes that affected particular instruction.
CENTRAL PROCESSING UNIT
MC68HC11KW1
3.1.6.1
Carry/borrow
C-bit arithmetic logic unit (ALU) performs carry borrow during arithmetic operation. C-bit also acts error flag multiply divide operations. Shift rotate instructions operate with through carry facilitate multiple-word shift operations.
3.1.6.2
Overflow
overflow operation causes arithmetic overflow. Otherwise, V-bit cleared.
3.1.6.3
Zero
Z-bit result arithmetic, logic, data manipulation operation zero. Otherwise, Z-bit cleared. Compare instructions internal implied subtraction condition codes, including reflect results that subtraction. operations (INX, DEX, INY, DEY) affect Z-bit other condition flags. these operations, only conditions determined.
3.1.6.4
Negative
N-bit result arithmetic, logic, data manipulation operation negative; otherwise, N-bit cleared. result said negative most significant (MSB) (MSB quick test whether contents memory location load into accumulator then check status N-bit.
3.1.6.5
Interrupt mask
interrupt request (IRQ) mask (I-bit) global mask that disables maskable interrupt sources. While I-bit set, interrupts become pending, operation continues uninterrupted until I-bit cleared. After reset, I-bit default only cleared software instruction. When interrupt recognized, I-bit after registers stacked, before interrupt vector fetched. After interrupt been serviced, return from interrupt instruction normally executed, restoring registers values that were present before interrupt occurred. Normally, I-bit zero after return from interrupt executed. Although I-bit cleared within interrupt service routine, `nesting' interrupts this should only done when there clear understanding latency arbitration mechanism. Refer Section
MC68HC11KW1
CENTRAL PROCESSING UNIT
3.1.6.6
Half carry
H-bit when carry occurs between bits arithmetic logic unit during ADD, ABA, instruction. Otherwise, H-bit cleared. Half carry used during operations.
3.1.6.7
interrupt mask
XIRQ mask disables interrupts from XIRQ pin. After reset, default must cleared software instruction. When XIRQ interrupt recognized, I-bits after registers stacked, before interrupt vector fetched. After interrupt been serviced, instruction normally executed, causing registers restored values that were present before interrupt occurred. interrupt mask only hardware RESET XIRQ acknowledge). cleared only program instruction (TAP, where associated RTI, where value loaded into from stack been cleared). There hardware action clearing
3.1.6.8
Stop disable
Setting STOP disable prevents STOP instruction from putting M68HC11 into low-power stop condition. STOP instruction encountered while S-bit set, treated no-operation (NOP) instruction, processing continues next instruction. reset STOP disabled default.
Data types
M68HC11 supports following data types: data 8-bit 16-bit signed unsigned integers 16-bit unsigned fractions 16-bit addresses
byte eight bits wide accessed byte location. word composed consecutive bytes with most significant byte lower value address. Because M68HC11 8-bit CPU, there special requirements alignment instructions operands.
CENTRAL PROCESSING UNIT
MC68HC11KW1
Opcodes operands
M68HC11 family microcontrollers uses 8-bit opcodes. Each opcode identifies particular instruction associated addressing mode CPU. Several opcodes required provide each instruction with range addressing capabilities. Only opcodes would available range values were restricted number able expressed 8-bit binary numbers. four-page opcode been implemented expand number instructions. additional byte, called prebyte, directs processor from page opcode other three pages. name implies, additional byte precedes opcode. complete instruction consists prebyte, any, opcode, zero, one, two, three operands. operands contain information needs executing instruction. Complete instructions from five bytes long.
Addressing modes
addressing modes; immediate, direct, extended, indexed, inherent, relative, detailed following paragraphs, used access memory. modes except inherent mode effective address. effective address memory address from which argument fetched stored, address from which execution proceed. effective address specified within instruction, calculated.
Immediate (IMM)
immediate addressing mode argument contained byte(s) immediately following opcode. number bytes following opcode matches size register memory location being operated There two, three, four prebyte required) byte immediate instructions. effective address address byte following instruction.
3.5.1
Direct (DIR)
direct addressing mode, low-order byte operand address contained single byte following opcode, high-order byte address assumed $00. Addresses $00-$FF thus accessed directly, using two-byte instructions. Execution time reduced eliminating additional memory access required high-order address byte. most applications, this 256-byte area reserved frequently referenced data. M68HC11 MCUs, memory configured combinations internal registers, RAM, external memory occupy these addresses.
MC68HC11KW1
CENTRAL PROCESSING UNIT
3.5.2
Extended (EXT)
extended addressing mode, effective address argument contained bytes following opcode byte. These three-byte instructions four-byte instructions prebyte required). bytes needed opcode effective address.
3.5.3
Indexed (IND, IND,
indexed addressing mode, 8-bit unsigned offset contained instruction added value contained index register effective address. This addressing mode allows referencing memory location 64Kbyte address space. These two- five-byte instructions, depending whether prebyte required.
3.5.4
Inherent (INH)
inherent addressing mode, information necessary execute instruction contained opcode. Operations that only index registers accumulators, well control instructions with arguments, included this addressing mode. These two-byte instructions.
3.5.5
Relative (REL)
relative addressing mode used only branch instructions. branch condition true, 8-bit signed offset included instruction added contents program counter form effective branch address. Otherwise, control proceeds next instruction. These usually two-byte instructions.
Instruction
Refer Table 3-2, which shows M68HC11 instructions possible addressing modes. each instruction, table shows operand construction, number machine code bytes, execution time clock cycles.
CENTRAL PROCESSING UNIT
MC68HC11KW1
Table Instruction (Page
Instruction Opcode Operand Cycles Condition codes
Mnemonic ADCA (opr)
Operation accumulators with carry
Description A+BA (00:B) (00:B) A+M+CA
Addressing mode IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND,
ADCB (opr)
with carry
B+M+CB
ADDA (opr)
memory
A+MA
ADDB (opr)
memory
B+MB
ADDD (opr)
16-bit
(M:M+1)
ANDA (opr)
with memory
ANDB (opr)
with memory
(opr)
Arithmetic shift left
ASLA ASLB ASLD
Arithmetic shift left Arithmetic shift left Arithmetic shift left Arithmetic shift right
ASRA ASRB (rel) BCLR (opr) (msk) (rel) (rel) (rel) (rel) (rel)
Arithmetic shift right Arithmetic shift right Branch carry clear Clear bit(s)
C=0? (MM)
Branch carry Branch equal zero Branch zero Branch zero Branch higher
C=1? Z=1? C+Z=0?
MC68HC11KW1
CENTRAL PROCESSING UNIT
Table Instruction (Page
Instruction Opcode Operand Cycles Condition codes
Mnemonic (rel)
Operation Branch higher same Bit(s) test with memory
Description C=0?
Addressing mode IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND,
BITA (opr)
BITB (opr)
Bit(s) test with memory
(rel) (rel) (rel) (rel) (rel) (rel) BPL(rel) (rel) BRCLR(opr) (msk) (rel) (rel) BRSET(opr) (msk) (rel) BSET (opr) (msk) (rel) (rel) (rel) (opr)
Branch zero Branch lower Branch lower same Branch zero Branch minus Branch zero Branch plus Branch always Branch bit(s) clear
C=1? C+Z=1? N=1? Z=0? N=0? 1=1?
Branch never Branch bit(s)
1=0?
bit(s)
Branch subroutine Branch overflow clear Branch overflow Compare with Clear carry Clear interrupt mask Clear memory byte
Figure V=0? V=1?
CLRA CLRB CMPA (opr)
Clear accumulator Clear accumulator Clear overflow flag Compare with memory
CMPB (opr)
Compare with memory
(opr)
Ones complement memory byte
COMA COMB
Ones complement Ones complement
CENTRAL PROCESSING UNIT 3-10
MC68HC11KW1
Table Instruction (Page
Instruction Opcode Operand Cycles Condition codes
Mnemonic (opr)
Operation Compare with memory (16-bit)
Description (M:M+1)
Addressing mode IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND,
(opr)
Compare with memory (16-bit)
(M:M+1)
(opr)
Compare with memory (16-bit)
(M:M+1)
(opr)
Decimal adjust Decrement memory byte
adjust M-1M
DECA DECB EORA (opr)
Decrement accumulator Decrement accumulator Decrement stack pointer Decrement index register Decrement index register Exclusive with memory
A-1A B-1B
EORB (opr)
Exclusive with memory
FDIV IDIV (opr)
Fractional divide, Integer divide, Increment memory byte
M+1M
INCA INCB (opr)
Increment accumulator Increment accumulator Increment stack pointer Increment index register Increment index register Jump
A+1A B+1B Figure
(opr)
Jump subroutine
Figure
LDAA (opr)
Load accumulator
MC68HC11KW1
CENTRAL PROCESSING UNIT 3-11
Table Instruction (Page
Instruction Opcode Operand Cycles Condition codes
Mnemonic LDAB (opr)
Operation Load accumulator
Description
Addressing mode IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND,
(opr) Load double accumulator (opr) Load stack pointer
M:M+1
(opr)
Load index register
M:M+1
(opr)
Load index register
M:M+1
(opr)
Logical shift left
LSLA LSLB LSLD (opr)
Logical shift left Logical shift Left Logical shift left Logical shift right
LSRA LSRB LSRD (opr)
Logical shift right Logical shift right Logical shift right Multiply, Twos complement memory byte
A*BD 0-MM
NEGA NEGB ORAA
Twos complement Twos complement operation accumulator (inclusive)
0-AA 0-BB operation A+MA
ORAB
accumulator (inclusive)
B+MB
PSHA PSHB PSHX PSHY
Push onto stack Push onto stack Push onto stack (low first) Push onto stack (low first)
Stack; SP-1 Stack; SP-1 Stack; SP-2 Stack; SP-2
CENTRAL PROCESSING UNIT 3-12
MC68HC11KW1
Table Instruction (Page
Instruction Opcode Operand Cycles Condition codes
Mnemonic PULA PULB PULX PULY (opr)
Operation Pull from stack Pull from stack Pull from stack (high first) Pull from stack (high first) Rotate left
Description SP+1; Stack SP+1; Stack SP+2; Stack SP+2; Stack
Addressing mode IND, IND,
ROLA ROLB (opr)
Rotate left Rotate left Rotate right
IND, IND,
RORA RORB SBCA (opr)
Rotate right Rotate right Return from interrupt Return from subroutine Subtract from Subtract with carry from
Figure Figure A-BA A-M-CA
IND, IND, IND, IND,
SBCB (opr)
Subtract with carry from
B-M-CB
STAA (opr)
carry interrupt mask overflow flag Store accumulator
IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND, IND,
STAB (opr)
Store accumulator
(opr)
Store accumulator
STOP (opr)
Stop internal clocks Store stack pointer
M:M+1
(opr)
Store index register
M:M+1
(opr)
Store index register
M:M+1
MC68HC11KW1
CENTRAL PROCESSING UNIT 3-13
Table Instruction (Page
Instruction Opcode Operand Cycles Condition codes
Mnemonic SUBA (opr)
Operation Subtract memory from
Description A-MA
Addressing mode IND, IND, IND, IND, IND, IND, IND, IND,
SUBB (opr) Subtract memory from SUBD (opr) Subtract memory from
B-MB
M:M+1
TEST (opr)
Software interrupt Transfer Transfer register Transfer Test (only test modes) Transfer register Test zero minus
Figure address increments
TSTA TSTB XGDX XGDY
Test zero minus Test zero minus Transfer stack pointer Transfer stack pointer Transfer stack pointer Transfer stack pointer Wait interrupt Exchange with Exchange with
stack registers WAIT
Operators transferred Boolean Arithmetic addition, except where used inclusive-OR symbol Boolean formulae Exclusive-OR Multiply Concatenation Arithmetic subtraction, negation symbol (Twos complement)
Operands 8-bit direct address ($0000-$00FF); high byte assumed zero 8-bit positive offset ($00 256)) added contents index register High order byte 16-bit extended address byte immediate data High order byte 16-bit immediate data order byte 16-bit immediate data order byte 16-bit extended address 8-bit mask (set bits affected) Signed relative offset ($80 (-128 +127)); offset relative address following offset byte
Cycles Infinite, until reset occurs cycles used, beginning with opcode fetch. wait state entered, which remains effect integer number clock cycles until interrupt recognised. Finally, additional cycles used fetch appropriate interrupt vector. total).
Condition Codes changed always cleared always cleared, depending operation cleared, cannot become defined
CENTRAL PROCESSING UNIT 3-14
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY
This section contains information about modes that define MC68HC11KW1 operating conditions, about on-chip memory that allows configured various applications.
Operating modes
values mode select inputs MODB MODA during reset determine operating mode (See Table 4-4). Single chip expanded modes normal modes. single chip mode only on-board memory available. Expanded mode, however, allows access external memory. Each these normal modes paired with special mode. Bootstrap, variation single chip mode, special mode that executes bootloader program internal bootstrap ROM. Test special expanded mode that allows privileged access internal resources.
4.1.1
Single chip operating mode
single chip operating mode, MC68HC11KW1 microcontroller external address data bus. Ports available general-purpose parallel I/O.
4.1.2
Expanded operating mode
expanded operating mode, access byte physical address space. address space includes same on-chip memory addresses used single chip mode, addition external memory peripheral devices.The expansion made ports expanded mode, high order address bits output port pins, order address bits port pins, data port signals direction data transfer port bus. MC68HC11KW1 includes additional memory expansion feature, available expanded modes, which allows access pages memory windows within byte physical memory space. This extend memory space more than byte. Section 4.4.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY
information about four programmable chip selects available expanded modes, refer Section 4.5. security feature protect EEPROM data when expanded mode (see Section 4.6.3).
4.1.3
Special test mode
Special test, variation expanded mode, used during Motorola's internal production testing, intended recommended other purpose. specification subject change without notice.
4.1.4
Special bootstrap mode
When reset special bootstrap mode, small on-chip enabled address $BE40-$BFFF. contains reset vector bootloader program. fetches reset vector, then executes bootloader. normal bootloader program, send synchronization byte receiver either clock ÷256, clock ÷1664 (15624 2400 baud respectively, clock MHz). Then download bytes program data (which into starting $00A0). These characters echoed through transmitter. bootloader program ends download after timeout four character times bytes. When loading complete, program jumps location $00A0 begins executing code. external pull-up resistor required when using transmitter (TXD) because port pins configured wired-OR operation bootloader. bootstrap mode, interrupt vectors point RAM. This allows interrupts through jump table. Further baud rate options available MC68HC11KW1 using different value synchronization byte, shown Table 4-1. Refer also Motorola application note AN1060, M68HC11 Bootstrap Mode (the bootloader mode similar that used MC68HC11K4).
Table Example bootloader baud rates
Sync. byte Timeout delay char. 17.3 Baud rates clock 4.00MHz 2400 10416 7812
OPERATING MODES ON-CHIP MEMORY
MC68HC11KW1
On-chip memory
MC68HC11KW1 includes bytes on-chip bytes EEPROM. bootloader occupies byte block memory map. CONFIG register implemented separate EEPROM byte.
Start address $0000 $00A0 $03A0 $0D80 $1000
Register block
bytes $x39F using INIT register. EEPROM $xD80 bytes $xFFF
$x000 Each these blocks $x09F mapped $x0A0 page boundary,
This block remapped page, using INIT2.
$BE40 $C000
BootROM $BE40 Vectors
$BFFF
Special bootstrap mode only. Special modes only.
$FFC0 -$FFFF
Vectors Single chip Expanded Special bootstrap Special test
$FFC0 $FFFF
Normal mode vectors.
Figure MC68HC11KW1 memory
4.2.1
Mapping allocations
Memory locations on-chip resources same both expanded single chip modes. 160-byte register block originates $0000 reset placed other boundary ($x000) after reset writing appropriate value INIT register. Refer Figure 4-1, which shows memory map. on-board byte block initially located $00A0 after reset. divided into sections bytes bytes. registers both mapped same boundary, starts $x0A0 bytes remapped $x300-$x39F. Otherwise, starts $x000. Figure 4-2. Remapping accomplished writing appropriate values into nibbles INIT register. Section 4.3.2.2. 640-byte EEPROM initially located $0D80 after reset, when EEPROM enabled memory CONFIG register. EEPROM placed other page ($xD80) writing INIT2 register.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY
special bootstrap mode, bootloader enabled locations $BE40-$BFFF. vectors special bootstrap mode contained bootloader program.
4.2.1.1
MC68HC11KW1 bytes fully static that used storing instructions, variables temporary data during program execution. placed boundary byte address space writing appropriate value INIT register. default, initially located $00A0 memory map. Direct addressing mode access first locations using one-byte address operand. Direct mode accesses save program memory space execution time. Registers moved other boundaries allow bytes located direct addressing space. Figure 4-2. on-chip fully static memory. contents preserved during periods processor inactivity either methods, both which reduce power consumption: During software-based STOP mode, clocks stopped, continues draw power from VDD. Power supply current directly related operating frequency CMOS integrated circuits there very little leakage when clocks stopped. These factors reduce power consumption while STOP mode. reduce power consumption minimum, turned off, MODB/VSTBY used supply power from either battery back-up second power supply. Although this method requires external hardware, very effective. Refer Section information about connect stand-by power supply Section description power operation.
4.2.1.2
Bootloader
bootloader enabled address $BE40-$BFFF during special bootstrap mode. reset vector fetched from this executes bootloader firmware. normal modes, bootloader disabled.
4.2.2
Registers
Table 4-2, summary registers control bits, registers shown ascending order within 160-byte register block. addresses shown default block mapping ($0000-$009F), however INIT register remaps block page ($x000-$x09F). Section 4.3.2.2.
OPERATING MODES ON-CHIP MEMORY
MC68HC11KW1
Table Register control assignments (Page
Register name Port data (PORTA) Data direction (DDRA) Data direction (DDRB) Data direction (DDRF) Port data (PORTB) Port data (PORTF) Port data (PORTC) Data direction (DDRC) Port data (PORTD) Data direction (DDRD) Port data (PORTE) Timer compare force (CFORC) Output compare mask (OC1M) Output compare data (OC1D) Timer count (TCNT) high Timer count (TCNT) Timer input capture (TIC1) high Timer input capture (TIC1) Timer input capture (TIC2) high Timer input capture (TIC2) Timer input capture (TIC3) high Timer input capture (TIC3)
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B
State reset undefined
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0000 0000 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 0000 0000 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 0000 0000 undefined undefined undefined
DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000 undefined
DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 0000 0000 (10) (10) (10) (10) (10) (10) (10) (10) (10) undefined 0000 0000 0000 0000 0000 0000
FOC1 FOC2 FOC3 FOC4 FOC5
$000C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 $000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit (14) (14) (14) (14) (14) (14) (14) (14) (14) (13) (13) (13) (13) (13) (13) (13) (13) (13) (12) (12) (12) (12) (12) (12) (12) (12) (12) (11) (11) (11) (11) (11) (11) (11) (11) (11)
(bit 0000 0000 (bit 0000 0000 (bit (bit (bit (bit (bit (bit undefined undefined undefined undefined undefined undefined
Timer output compare (TOC1) high $0016 Timer output compare (TOC1) $0017
(bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 0000 0000
Timer output compare (TOC2) high $0018 Timer output compare (TOC2) $0019
Timer output compare (TOC3) high $001A Timer output compare (TOC3) $001B
Timer output compare (TOC4) high $001C (bit Timer output compare (TOC4) Capture 4/compare (TI4/O5) high Capture 4/compare (TI4/O5) Timer control (TCTL1) Timer control (TCTL2) Timer interrupt mask (TMSK1) $001D $001E $001F $0020 (bit (bit (bit
$0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000 $0022 OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I 0000 0000
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY
Table Register control assignments (Page
Register name Timer interrupt flag (TFLG1) Timer interrupt mask (TMSK2) Timer interrupt flag (TFLG2)
Address $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030
IC1F I4/O5
IC2F
IC3F
State reset 0000 0000 0000 0000 0000 0000
OC1F OC2F OC3F OC4F I4/O5F (bit SPIE RTII PAOVI PAII
RTIF PAOVF PAIF PAEN PAMOD PEDGE
Pulse accumulator control (PACTL) Pulse accumulator count (PACNT) control (SPCR) status (SPSR) data (SPDR) Reserved Port pull-up assignment (PPAR) Port assignment (PGAR) Reserved Reserved control status (ADCTL)
RTR1 RTR0 0000 0000 (bit undefined
DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu MODF (bit 0000 0000 undefined
SPIF WCOL (bit
HPPUE GPPUE FPPUE BPPUE 0000 1111
PGAR5 PGAR4 PGAR3 PGAR2 PGAR1 PGAR0 0000 0000
CONV8 SCAN MULT
0000 0000
Compare force timers (F23FRC) $0031
FT3C1 FT3C2 FT3C3 FT3C4 FT2C1 FT2C2 FT2C3 FT2C4 0000 0000 ADER 0000 0000
frequency select (ADFRQ) Reserved Reserved Block protect (BPROT) Reserved EEPROM mapping (INIT2) System config. options (OPT2) System config. options (OPTION) timer arm/reset (COPRST) EEPROM programming (PPROG) Highest priority interrupt (HPRIO) mapping (INIT) Factory test (TEST1) Configuration control (CONFIG) result (ADR1) high result (ADR1) result (ADR2) high result (ADR2)
$0032 $0033 $0034
$0035 BULKP BIT6 BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1111 1111 $0036 $0037 $0038 $0039 $003A $003B IRQE 0000 0000
LIRDV CWOM ADPU CSEL (bit EVEN
IRVNE LSBF SPR2 XDV1 XDV0 000x 0000 BYTE FCME (bit 0001 0000 undefined
ERASE EELAT
EEPG 0000 0000
$003C RBOOT SMOD PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110 $003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000 $003E $003F $0040 $0041 $0042 $0043 TILOP (Bit (Bit (14) (14) OCCR CBYP DISR FCOP 0000 x000
NOCO CLKX PAREN NOSEC (13) (13) (12) (12) (11) (11) (10) (10)
EEON 11xx xx1x undefined uu00 0000 undefined uu00 0000
OPERATING MODES ON-CHIP MEMORY
MC68HC11KW1
Table Register control assignments (Page
Register name result (ADR3) high result (ADR3) result (ADR4) high result (ADR4) result (ADR5) high result (ADR5) result (ADR6) high result (ADR6) result (ADR7) high result (ADR7) result (ADR8) high result (ADR8) Reserved Reserved Reserved Reserved Reserved Reserved Memory mapping window size (MMSIZ)
Address $0044 $0045 $0046 $0047 $0048 $0049 (Bit (Bit (Bit
(14) (14) (14) (14) (14) (14)
(13) (13) (13) (13) (13) (13)
(12) (12) (12) (12) (12) (12)
(11) (11) (11) (11) (11) (11)
(10) (10) (10) (10) (10) (10)
State reset undefined uu00 0000 undefined uu00 0000 undefined uu00 0000 undefined uu00 0000 undefined uu00 0000 undefined uu00 0000
$004A (Bit $004B
$004C (Bit $004D
$004E (Bit $004F $0050 $0051 $0052 $0053 $0054 $0055
$0056 MXGS2 MXGS1 W2SZ1 W2SZ0
W1SZ1 W1SZ0 0000 0000 0000 0000 0000 0000 0000 0000
Memory mapping window base (MMWBR) $0057 W2A15 W2A14 W2A13 Memory mapping window control (MM1CR) Memory mapping window control (MM2CR)
W1A15 W1A14 W1A13
$0058 $0059 $005A $005B
IOSA IOEN
X1A18 X1A17 X1A16 X1A15 X1A14 X1A13 X2A18 X2A17 X2A16 X2A15 X2A14 X2A13
Chip select clock stretch (CSCSTR) Chip select control (CSCTL)
IOSB GP1SA GP1SB GP2SA GP2SB PCSA PCSB 0000 000x IOPL IOCSA IOSZ GCSPR PCSEN PCSZA PCSZB 0000 0100
Gen. purpose chip select addr. (GPCS1A) $005C G1A18 G1A17 G1A16 G1A15 G1A14 G1A13 G1A12 G1A11 0000 0000 Gen. purpose chip select con. (GPCS1C) $005D G1DG2 G1DPC G1POL G1AV G1SZA G1SZB G1SZC G1SZD 0000 0000 Gen. purpose chip select addr. (GPCS2A) $005E Gen. purpose chip select con. (GPCS2C) $005F
G2A18 G2A17 G2A16 G2A15 G2A14 G2A13 G2A12 G2A11 0000 0000 G2DPC G2POL G2AV G2SZA G2SZB G2SZC G2SZD 0000 0000 PCKB3 PCKB2 PCKB1 0000 0000
Pulse width clock select (PWCLK) Pulse width polarity select (PWPOL) Pulse width scale (PWSCAL) Pulse width enable (PWEN) Pulse width count (PWCNT1)
$0060 CON34 CON12 PCKA2 PCKA1
$0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000 $0062 (bit (bit 0000 0000
$0063 TPWSL DISCP $0064 (bit
PWEN4PWEN3PWEN2PWEN1 0000 0000 (bit 0000 0000
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY
Table Register control assignments (Page
Register name Pulse width count (PWCNT2) Pulse width count (PWCNT3) Pulse width count (PWCNT4)
Address $0065 $0066 $0067 $0068 $0069 $006A $006B $006C $006D $006E $006F $0070 $0071 (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit
State reset
(bit 0000 0000 (bit 0000 0000 (bit 0000 0000 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111
Pulse width period (PWPER1) Pulse width period (PWPER2) Pulse width period (PWPER3) Pulse width period (PWPER4) Pulse width duty (PWDTY1) Pulse width duty (PWDTY2) Pulse width duty (PWDTY3) Pulse width duty (PWDTY4) baud rate high (SCBDH) baud rate (SCBDL) control (SCCR1) control (SCCR2) status (SCSR1) status (SCSR2) data high (SCDRH) data (SCDRL) Reserved Reserved Reserved Reserved Port data (PORTH) Data direction (DDRH) Port data (PORTG) Data direction (DDRG) Timer control register (TCTL3) Timer control register (TCTL4)
BTST BSPL SYNC SBR12 SBR11 SBR10 SBR9 SBR8 0000 0000 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0000 0100 RDRF R5T5 ILIE IDLE R4T4 WAKE R3T3 R2T2 R1T1 R0T0 0000 0000 0000 0000 1100 0000 0000 0000 undefined undefined
$0072 LOOPS WOMS $0073 $0074 $0075 $0076 $0077 $0078 $0079 $007A $007B $007C $007D $007E $007F $0080 $0081 TDRE R7T7 TCIE R6T6
undefined
DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 0000 0000 undefined
DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000 0000 0000 0000 0000
EDGB EDGA PR2B PR2A ECEB ECEA T2STP I1/04 (bit (bit (bit (bit (bit (14) (14) (14) (13) (13) (13) (12) (12) (12) (11) (11) (11) (10) (10) (10)
Timer counter register (TCNT2) high $0082 Timer counter register (TCNT2) Timer output compare 1(T2OC1) high $0083 $0084
(bit 0000 0000 (bit 0000 0000 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111
Timer output compare (T2OC1) $0085 Timer output comp. (T2OC2) high $0086
OPERATING MODES ON-CHIP MEMORY
MC68HC11KW1
Table Register control assignments (Page
Register name Timer output comp. (T2OC2) Timer output comp. (T20C3) high Timer output comp. 3(T20C3) Timer channel (T2C4) high Timer channel (T2C4) Timer mask (T2MSK) Timer flag (T2FLG) Port data (PORTJ) Data direction (DDRJ) Timer control register (TCTL5) Timer control register (TCTL6) Timer counter (TCNT3) high Timer counter (TCNT3) Timer output compare (T30C1) high
Address $0087 $0088 $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 (bit (bit (bit (bit (bit OC1I
(14) (14) OC2I
(13) (13) OC3I
(12) (12) DDJ4
(11) (11) TO2I TO2F DDJ3
(10) (10) DDJ2
DDJ1
State reset
(bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 0000 0000 0000 0000 undefined
OC1F OC2F OC3F DDJ7 DDJ6 DDJ5
DDJ0 0000 0000 0000 0000
EDGB EDGA PR3B PR3A ECEB ECEA T3STP I1/O4 0000 0000 (bit (bit (bit (bit (bit (bit (bit (bit (bit (bit OC1I (14) (14) (14) (14) (14) OC2I (13) (13) (13) (13) (13) OC3I (12) (12) (12) (12) (12) (11) (11) (11) (11) (11) TO3I TO3F (10) (10) (10) (10) (10) (bit 0000 0000 (bit 0000 0000 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 (bit 1111 1111 0000 0000 0000 0000 undefined
Timer output compare (T30C1) $0095 Timer output compare (T30C2) high $0096
Timer output compare (T30C2) $0097 Timer output comp. (T3OC3) high $0098 Timer output comp. (T3OC3) Timer channel (T3C4) high Timer channel (T3C4) Timer mask (T3MSK) Timer flag (T3FLG) Port data (PORTK) Data direction (DDRK) $0099 $009A $009B $009C $009D $009E $009F
OC1F OC2F OC3F
DDK7 DDK6 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 0000 0000
State reset depends mode selected State reset undefined
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY
System initialization
Registers bits that control initialization basic operation protected against writes except under special circumstances. following table lists registers that written only once after reset, that must written within first cycles after reset. Table Registers with limited write access
Register address $x024 $x035 $x037 $x038 $x039 $x03D $x081 $x091
Register name Timer interrupt mask register (TMSK2) Block protect register (BPROT) EEPROM mapping register (INIT2) System configuration options register (OPT2) System configuration options register (OPTION) register (INIT) Timer control register (Timer TCTL4 Timer control register (Timer TCTL6
Must written first cycles
Write once only
When SMOD bits written only once, during first cycles, after which they become read-only. When SMOD however, these bits written time. other bits written time. Bits written zero once only first cycles special modes. Bits time. (IRVNE) written only once. When SMOD bits written once only first cycles. When SMOD however, bits written time. other bits written time. When SMOD bits written only once, during first cycles, after which register becomes read-only. When SMOD bits written time. Bits written only once.
4.3.1
Mode selection
four mode variations selected logic states mode (MODA) mode (MODB) pins during reset. MODA MODB logic levels determine logic state special mode (SMOD) mode (MDA) control bits highest priority I-bit interrupt miscellaneous (HPRIO) register. After reset released, mode select pins longer influence operating mode. single chip operating mode, MODA connected logic zero. expanded mode, MODA normally connected through pull-up resistor MODA also functions load instruction register (LIR) when reset. open-drain active output drives during first cycle each instruction. MODB also functions stand-by power input (VSTBY), which allows contents maintained absence VDD.
OPERATING MODES ON-CHIP MEMORY 4-10
MC68HC11KW1
Refer Table 4-4, which summary mode operation, mode control bits four operating modes. normal mode selected when MODB logic during reset. three reset vectors fetched from address $FFFA-$FFFF, program execution begins from address indicated this vector. MODB logic zero during reset, special mode reset vector fetched from addresses $BFFA-$BFFF software access special test features. Refer Section
4.3.1.1
HPRIO Highest priority I-bit interrupt misc. register
Address State reset
Highest priority interrupt (HPRIO)
$003C RBOOT SMOD PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
Note:
RBOOT, SMOD bits depend power-up initialization mode only written special modes when SMOD Refer Table 4-4.
RBOOT Read bootstrap (set) Bootloader enabled, $BE40-$BFFF. Bootloader disabled map.
(clear)
SMOD Special mode select (set) Special mode variation effect. Normal mode variation effect.
(clear)
Once cleared, cannot again. Mode select (set) Normal expanded special test mode. (Expanded buses active.) Normal single chip special bootstrap mode. (Ports active.) Table Hardware mode select summary
Inputs MODB MODA Control bits HPRIO (latched reset) RBOOT SMOD Single chip Expanded Special bootstrap Special test Mode
(clear)
PSEL[4:0] Priority select bits (refer Section
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-11
4.3.2
Initialization
Because bits following registers control basic configuration MCU, accidental change their values could cause serious system problems. protection mechanism, overridden special operating modes, requires write protected bits only within first cycles after reset, only once after each reset. Table 4-3.
4.3.2.1
CONFIG System configuration register
Address NOCO State reset
Configuration control (CONFIG)
$003F
CLKX PAREN NOSEC
EEON 11xx xx1x
CONFIG controls presence EEPROM memory enables watchdog system. CLKX enables XOUT output XCLK signal, PAREN enables pull-ups certain ports. Refer Section 4.6.3. security feature that protects data EEPROM available, controlled NOSEC (refer Section 4.6.3). CONFIG made EEPROM cells static working latches. operation controlled directly these latches EEPROM byte. When programming CONFIG register, EEPROM byte accessed. When CONFIG register read, static latches accessed. These bits read time. value read latched into register from EEPROM cells during last reset sequence. value programmed into this register readable until after subsequent reset sequence. Bits CONFIG written time SMOD (bootstrap special test mode). SMOD (single chip expanded mode), these bits only written using EEPROM programming sequence, none bits readable active until latched next reset. Bits implemented; always read one. CLKX XOUT enable (set) XCLK signal driven XOUT pin. XOUT disabled.
(clear)
frequency XCLK signal controlled bits OPT2 register (see Section 4.3.2.5). PAREN Pull-up assignment register enable (refer Section (set) Pull-ups enabled using PPAR. pull-ups disabled (not controlled PPAR).
(clear)
OPERATING MODES ON-CHIP MEMORY 4-12
MC68HC11KW1
NOSEC EEPROM security disabled (refer Section 4.6.3) (set) Disable security. Enable security.
(clear)
NOCOP system disable (refer Section (set) system disabled. system enabled (forces reset timeout).
(clear)
EEON EEPROM enable (set) EEPROM included memory map. EEPROM excluded from memory map.
(clear)
4.3.2.2
INIT mapping register
Address State reset
mapping (INIT)
$003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000
internal registers used control operation relocated boundaries within memory space with INIT. This 8-bit special-purpose register change default locations control registers within memory map. written only once within first clock cycles after reset. then becomes read-only register. RAM[3:0] position These four bits, which specify upper hexadecimal digit address, control position memory map. positioned beginning page memory map. Refer Table 4-5. REG[3:0] 160-byte register block position These four bits specify upper hexadecimal digit address 160-byte block internal registers. register block positioned beginning page memory map. Refer Table 4-5.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-13
Table register remapping
RAM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Location $0000-$02FF $1000-$12FF $2000-$22FF $3000-$32FF $4000-$42FF $5000-$52FF $6000-$62FF $7000-$72FF $8000-$82FF $9000-$92FF $A000-$A2FF $B000-$B2FF $C000-$C2FF $D000-$D2FF $E000-$E2FF $F000-$F2FF REG[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Location $0000-$009F $1000-$109F $2000-$209F $3000-$309F $4000-$409F $5000-$509F $6000-$609F $7000-$709F $8000-$809F $9000-$909F $A000-$A09F $B000-$B09F $C000-$C09F $D000-$D09F $E000-$E09F $F000-$F09F
When memory 160-byte register block mapped same location RAM, registers have priority relocated memory space immediately following register block. This mapping feature keeps available use. Refer Figure 4-2, which illustrates overlap.
$x000 $x09F $x0A0
$x000 $x09F $x0A0
Register block
$x2FF
$x2FF $x300 $x39F
Register mapped different boundaries.
Register mapped same boundary.
Figure register overlap
OPERATING MODES ON-CHIP MEMORY 4-14
MC68HC11KW1
4.3.2.3
INIT2 EEPROM mapping register
Address State reset 0000 0000
EEPROM mapping (INIT2)
$0037
This register determines location EEPROM memory map. INIT2 read time bits written only once after reset normal modes. EE[3:0] EEPROM position EEPROM located $xD80-$xFFF, where hexadecimal digit represented EE[3:0]. Refer Table 4-6.
Table EEPROM remapping
EE[3:0] 0000 0001 0010 0011 Location $0D80-$0FFF $1D80-$1FFF $2D80-$2FFF $3D80-$3FFF EE[3:0] 0100 0101 0110 0111 Location $4D80-$4FFF $5D80-$5FFF $6D80-$6FFF $7D80-$7FFF EE[3:0] 1000 1001 1010 1011 Location $8D80-$8FFF $9D80-$9FFF $AD80-$AFF $BD80-$BFF EE[3:0] 1100 1101 1110 1111 Location $CD80-$CFF $DD80-$DFF $ED80-$EFF $FD80-$FFFF
Bits [3:0] implemented; always read zero.
4.3.2.4
OPTION System configuration options register
Address IRQE State reset 0001 0000
System config. options (OPTION)
$0039
ADPU CSEL
FCME
8-bit special-purpose OPTION register sets internal system configuration options during initialization. time protected control bits IRQE, DLY, FCME CR[1:0] written only once first cycles after reset then they become read-only bits. This minimizes possibility accidental changes system configuration. They written time special modes.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-15
ADPU power-up (refer Section (set) system power enabled. system disabled, reduce supply current.
(clear)
After enabling power, least 100µs should allowed system stabilization. CSEL Clock select (refer Section
(set)
EEPROM internal clock source (about 1.5MHz). EEPROM system clock (must least 1MHz).
(clear)
This selects clock source on-chip EEPROM charge pumps. on-chip clock should used when clock frequency falls below 1MHz. IRQE Configure falling-edge-sensitive operation (set) Falling-edge-sensitive operation. Low-level-sensitive operation.
(clear)
Enable oscillator start-up delay (set) stabilization delay around 4064 cycles imposed started from STOP mode power-on reset). oscillator start-up delay bypassed resumes processing within about four cycles. stable external oscillator required this option selected.
(clear)
reset, delay always imposed started from power-on reset. Clock monitor enable (refer Section (set) Clock monitor enabled. Clock monitor disabled.
(clear)
order both STOP clock monitor, should cleared before executing STOP, then after recovering from STOP. FCME Force clock monitor enable (refer Section (set) Clock monitor enabled; cannot disabled until next reset. Clock monitor follows state bit.
(clear)
When FCME set, slow stopped clocks will cause clock failure reset sequence. utilize STOP mode, FCME should always cleared.
OPERATING MODES ON-CHIP MEMORY 4-16
MC68HC11KW1
CR[1:0] timer rate select bits (refer Section These control bits determine scaling factor watchdog timer.
4.3.2.5
OPT2 System configuration options register
Address State reset
System config. options (OPT2)
$0038
LIRDV CWOM
IRVNE LSBF SPR2 XDV1 XDV2 000x 0000
LIRDV driven (set) Enable drive high pulse. driven high MODA/LIR pin.
(clear)
single-chip bootstrap modes, this meaning effect. driven indicate that execution instruction begun. normally configured wired-OR operation (only pulls low). order detect consecutive instructions high-speed application, this signal made drive high quarter cycle prevent false triggering (LIRDV set). CWOM Port wired-OR mode (refer Section (set) Port outputs open-drain. Port operates normally.
(clear)
Bits implemented; always read zero. IRVNE Internal read visibility/not IRVNE written once normal modes, written often desired bootstrap special test modes. special test modes, IRVNE reset one. normal bootstrap modes, IRVNE reset zero. IRVNE should only used room temperature nominal. expanded modes, IRVNE determines whether internal read visibility (IRV) off. (set) Data from internal reads driven external data bus. visibility internal reads external bus.
(clear)
single chip modes this determines whether clock drives from chip. (set) driven low. clock driven from chip.
(clear)
Refer following table summary operation immediately following reset.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-17
Mode Single chip Expanded Boot Special test
IRVNE after reset
clock IRVNE IRVNE after reset after reset affects only written Once Once Unlimited Unlimited
LSBF LSB-first enable (refer Section
(set)
Data transferred first. Data transferred first.
(clear)
SPR2 clock rate select (refer Section This adds divide-by-four clock chain. XDV[1, XOUT clock divide select These bits control frequency XCLK signal, which output XOUT enabled CLKX CONFIG. Table shows some example frequencies. Once clock rate been selected, maximum time clock cycles should allowed signal stabilize. Note that reset, both bits cleared XCLK signal runs same frequency EXTAL.
Note:
phase relationship between XOUT EXTAL cannot predicted.
Table XCLK frequencies
XDV2
EXTAL divided
XCLK with EXTAL
4.3.2.6
BPROT Block protect register
Address State reset
Block protect (BPROT)
$0035 BULKP BIT6 BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1111 1111
BPROT prevents accidental writes EEPROM CONFIG register, enables voltage EEPROM protect circuit. bits this register written zero only once during
OPERATING MODES ON-CHIP MEMORY 4-18
MC68HC11KW1
first clock cycles after reset normal modes; they time. Once bits cleared, EEPROM array CONFIG register programmed erased. Setting bits BPROT register logic protects EEPROM CONFIG register until next reset. Refer Table 4-8. BULKP Bulk erase EEPROM protect (set) EEPROM cannot bulk erased. EEPROM bulk erased normally.
(clear) BIT6
BIT6 programmed first cycles, although meaning. PTCON Protect CONFIG register (set) CONFIG register cannot programmed erased. CONFIG register programmed erased normally.
(clear)
Note that, special modes, CONFIG written regardless state PTCON. BPRT[4:0] Block protect bits EEPROM (set) Protection enabled associated block; cannot programmed erased. Protection disabled associated block.
(clear)
Each these five bits protects block EEPROM against writing erasure, follows: Table EEPROM block protect
name BPRT0 BPRT1 BPRT2 BPRT3 BPRT4 Block protected $xD80-$xD9F $xDA0-$xDDF $xDE0-$xE5F $xE60-$xF7F $xF80-$xFFF
Block size bytes bytes bytes bytes bytes
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-19
4.3.2.7
TMSK2 Timer interrupt mask register
Address RTII PAOVI PAII State reset 0000 0000
Timer interrupt mask (TMSK2)
$0024
PR[1:0] time-protected control bits changed only once then only within first cycles after reset normal modes.
Note:
Bits [7:4] TMSK2 correspond with flag bits TFLG2. Ones bits [7:4] TMSK2 enable corresponding interrupt sources.
Timer overflow interrupt enable (refer Section (set) Interrupt requested when set. interrupts disabled.
(clear)
RTII Real-time interrupt enable (refer Section (set) Interrupt requested when RTIF set. RTIF interrupts disabled.
(clear)
PAOVI Pulse accumulator overflow interrupt enable (refer Section (set) Intdrrupt requested when PAOVF set. PAOVF interrupts disabled.
(clear)
PAII Pulse accumulator interrupt enable (refer Section (set) Interrupt requested when PAIF set. PAIF interrupts disabled.
(clear)
Bits implemented; always read zero. PR[1:0] Timer prescaler select These bits select prescale rate main 16-bit free-running timer system, Timer These bits written only once during first clock cycles after reset normal modes, time special modes. Refer following table:
PR[1:0] Prescale factor
OPERATING MODES ON-CHIP MEMORY 4-20
MC68HC11KW1
4.3.2.8
TCTL4 TCTL6 Timer control registers
Address State reset 0000 0000 State reset 0000 0000
Timer control register (TCTL4)
$0081
EDGB EDGA PR2B PR2A ECEB ECEA T2STP I1/04
Address Timer control register (TCTL6) $0091
EDGB EDGA PR3B PR3A ECEB ECEA T3STP I1/04
Bits [5:2] both these registers written only once after reset. following paragraphs describe Timer control bits TCTL4; Timer control bits TCTL6 described Section EDGB EDGA Input capture edge control (Refer Section This pair bits configures input capture edge detector circuits IC1. functions only I1/O4 set. PR2A PR2B Timer prescaler select These bits used select prescaler divide-by ratio Timer They written only once after reset.
PR2B
PR2A
Prescaler
PR3A PR3B Timer prescaler select These bits used select prescaler divide-by ratio Timer They only written once after reset. PR3B PR3A both cleared, then Timer synchronized prescaled Timer rate.
PR3B
PR3A
Prescaler Timer rate
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-21
ECEB ECEA Event counter edge control These control bits configure input clock source Timer counter. They written only once after reset.
(set)
ECEB
ECEA
Configuration Timer uses internal clock prescaler Count rising edges external clock only Count falling edges external clock only Count edge external clock
T2STP Stop Timer counter (Refer Section Timer counter prescaler stopped counter reset $0000. Timer counter operates normally.
(clear)
I1/O4 Input capture 1/output compare (Refer Section (set) Input capture function enabled OC4). Output compare function enabled IC1).
(clear)
4.4.1
Memory expansion Memory expansion logic
MC68HC11KW1 ability extend address range M68HC11 beyond physical byte limit address lines. extra addressing capability provided register-based paging scheme using expansion address lines physical bytes address space. additional on-chip blocks provided with MC68HC11KW1. first block implements additional address lines that become active only when required CPU. second block provides chip-select signals that simplify interface external peripheral devices. Both these blocks fully programmable values written associated control registers.
OPERATING MODES ON-CHIP MEMORY 4-22
MC68HC11KW1
4.4.2
Extended addressing
Memory expansion achieved manipulating address lines such that, even though cannot distinguish more than bytes physical memory, byte accessed through paged memory scheme. Additional address lines XA[18:13] provided alternative functions port pins. Bits port assignment register (PGAR) define which port pins used memory expansion address lines which used general-purpose I/O. order access expanded memory, user must first allocate range byte address space used window(s) through which external, expanded memory viewed CPU. size placement window(s) depend values written MMSIZ MMWBR registers, respectively. Which bank page expanded memory that present window(s) given time dependent values written MM1CR MM2CR registers. windows designated each programmed (disabled), 16K, bytes. base address each window must integer multiple window size, with exception byte window, which base address $0000, $4000, $8000. windows defined such that they overlap, bank window priority part window that overlapped bank window remains active. window defined such that overlaps internal registers, RAM, EEPROM, then portion registers, RAM, EEPROM that overlapped repeated banks associated with that window. Coming reset, reset vector fetched from external memory. Since memory expansion lines disabled coming reset internally pulled logic level one, external system that uses these expansion address lines sees them ones. this case, reset vector fetched from $7FFFE-$7FFFF. Systems using external expanded memory still fetch reset vector from $FFFE-$FFFF. This reset vector's normal position M68HC11 CPU's conventional byte address space. Expanded memory addressed using combination CPU's normal address lines ADDR[15:0] expansion address lines XA[18:13]. Window size number banks associated with window determine exactly which address lines used. additional address lines (XA[18:13]) determine which bank present window given time. lower three expansion address lines (XA[15:13]) used only when needed replace CPU's equivalent address lines (ADDR[15:13]). Table shows which address lines used various configurations expanded memory. special case exists when bank size bytes window base address $4000. Normally, when bank size bytes bank address $0000 $8000, address lines ADDR[14:0] select individual bytes within byte space ADDR[14:0] pins connected address lines (A[14:0]) memory device. When base address $4000, address signal ADDR14 must inverted allow bytes contiguous memory. MC68HC11KW1 drives inverted ADDR14 signal onto XA14 when window active. this case, XA14 signal must connected address line memory device. When window active, XA14 driven with non-inverted ADDR14 signal.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-23
Table address address expansion signals
Window size bytes ADDR[14:0] XA15 ADDR[14:0] XA[16:15] ADDR[14:0] XA[17:15] ADDR[14:0] XA[18:15]
Number banks
bytes ADDR[12:0] XA13 ADDR[12:0] XA[14:13] ADDR[12:0] XA[15:13] ADDR[12:0] XA[16:13] ADDR[12:0] XA[17:13] ADDR[12:0] XA[18:13]
bytes ADDR[13:0] XA14 ADDR[13:0] XA[15:14] ADDR[13:0] XA[16:14] ADDR[13:0] XA[17:14] ADDR[13:0] XA[18:14]
bytes (window based $4000) ADDR[13:0] XA[15:14] ADDR[13:0] XA[16:14] ADDR[13:0] XA[17:14] ADDR[13:0] XA[18:14]
neither bank uses particular expansion address bit, corresponding available general-purpose I/O. PGAR register selects which pins used memory expansion address lines.
4.4.3
Memory expansion examples
Consider example system which external memory used user wishes allocate single byte window through which access total bytes external memory. provide byte address range needed window, only address lines ADDR[12:0] need used provide bytes (213) address locations. Expansion address lines XA[15:13] replace address lines ADDR[15:13] provide additional eight times (23) number address locations provided ADDR[12:0], total bytes address space). ADDR[12:0] provide byte window XA[15:13] provide additional eight bank-select signals that determine which bank present window. This illustrated inFigure Figure 4-4. Figure shows memory Figure shows schematic single byte window with banks external memory.
OPERATING MODES ON-CHIP MEMORY 4-24
MC68HC11KW1
$0000 $1000
Registers, EEPROM $00000 $02000 $04000
Window
$06000 $08000 $0A000 $0C000 $0E000
$4000
Bank Bank Bank Bank Bank Bank Bank Bank Chip select
XA[15:13] 0:0:0 XA[15:13] 0:0:1 XA[15:13] 0:1:0 XA[15:13] 0:1:1 XA[15:13] 1:0:0 XA[15:13] 1:0:1 XA[15:13] 1:1:0 XA[15:13] 1:1:1
$6000
$01FFF
$03FFF
$05FFF
$07FFF
$09FFF
$0BFFF $0DFFF $0FFFF
PGAR MMWBR $FFC0 $FFFF MMSIZ Vectors CSCTL GPCS1A GPSC1C GPCS2A GPCS2C
XA[15:13] window $4000, window disabled window bytes, window disabled program chip selects general purpose chip select from $00000 byte range general purpose chip select disabled
Figure Memory example memory expansion
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-25
MC68HC11KW1 XA15 XA14 XA13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
27C512
XA18 XA17 XA16 XA15 XA14 XA13 ADDR15 CSGP2 CSGP1 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Figure Schematic example memory expansion
OPERATING MODES ON-CHIP MEMORY 4-26
MC68HC11KW1
another example user wishes allocate windows. first window organized previous example, banks bytes each. second window organized banks bytes each. logical addresses window determined address lines ADDR[13:0]. Note that XA13 replaces ADDR13 each memory device this example since ADDR13 driven XA13. Expansion address lines XA[17:14] another (24) times number address locations provided ADDR[13:0] (256K bytes total address space). ADDR13 also used instead XA13 6226 memory devices designer chooses. This illustrated Figure Figure 4-6. Figure shows memory Figure shows schematic byte window with banks external memory, byte window with banks external memory.
$0000
Registers, EEPROM
Window
$00000 $02000 $04000 $06000 $08000 $0A000 $0C000 $0E000
$4000
Bank Bank Bank Bank Bank Bank Bank Bank Chip select
XA[15:13] 0:0:0 XA[15:13] 0:0:1 XA[15:13] 0:1:0 XA[15:13] 0:1:1 XA[15:13] 1:0:0 XA[15:13] 1:0:1 XA[15:13] 1:1:0 XA[15:13] 1:1:1
$6000
$01FFF
$03FFF
$05FFF
$07FFF
$09FFF
$0BFFF $0DFFF $0FFFF
Window
$00000 $04000 $08000 $0C000 $10000 $3C000
$8000
Bank Bank Bank Bank Bank Chip select
XA[15:13] 0:0:0:0 XA[15:13] 0:0:0:1 XA[15:13] 0:0:1:0 XA[15:13] 0:0:1:1 XA[15:13] 0:1:0:0
Bank15
XA[15:13] 1:1:1:1
$C000
$FFC0 $FFFF
$03FFF Vectors
$07FFF
$0BFFF $0FFFF
$13FFF
$3FFFF
PGAR MMWBR MMSIZ
XA[17:13] window $4000, window $8000 window bytes, window bytes
CSCTL GPCS1A GPSC1C GPCS2A GPCS2C
program chip selects general purpose chip select from $00000 byte range general purpose chip select from $00000 256K byte range 16K)
Figure Memory example memory expansion
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-27
MC68HC11KW1 XA18 XA17 XA16 XA15 XA14 XA13 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 XA17 XA16 XA15 XA14 XA13 XA15 XA14 XA13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 27C512
CSGP1 CSGP2
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
XA17 XA16 XA15 XA14 XA13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 6226 (High)
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
XA17 XA16 XA15 XA14 XA13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
6226 (Low)
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Figure Schematic example memory expansion
OPERATING MODES ON-CHIP MEMORY 4-28
MC68HC11KW1
4.4.4
MMSIZ Memory mapping window size register
Address State reset
Memory mapping window size (MMSIZ)
$0056 MXGS2 MXGS1 W2SZ1 W2SZ0
W1SZ1 W1SZ0 0000 0000
MMSIZ register sets size windows selects whether on-board general-purpose chip selects active addresses expansion addresses. MXGS[2:1] Memory expansion select general-purpose chip select (set) General-purpose chip select based expansion address. General-purpose chip select based byte address.
(clear)
W2SZ[1:0] Window size These bits select bank size window window starting address depends contents MMWBR register continues same number bytes selected window size. Refer Table 4-10. Bits implemented; always read zero. W1SZ[1:0] Window size These bits select bank size window window starting address depends contents MMWBR register continues same number bytes selected window size. Refer Table 4-10.
Table 4-10 Window size select
WxSZ[1:0] Window size Window disabled window have byte banks window have byte banks window have byte banks
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-29
4.4.5
MMWBR Memory mapping window base register
Address State reset 0000 0000
Memory mapping window base (MMSIZ)
$0057 W2A15 W2A14 W2A13
W1A15 W1A14 W1A13
MMWBR register defines starting address each windows within byte address range. windows normally begin boundary related their size byte window begin byte boundary, beginning $0000). W2A[15:13] Window base address These bits select three most significant bits (MSB) base address memory mapping window Note that W2A13 ignored bank size bytes. Refer Figure 4-11. Bits implemented; always read zero. W1A[15:13] Window base address These bits select three MSBs base address memory mapping window Note that W1A13 ignored bank size bytes. Refer Table 4-11.
Table 4-11 Memory expansion window base address
bits WxA[15:13] Window base address bytes bytes bytes $0000 $0000 $0000 $2000 $0000 $0000 $4000 $4000 $4000 $6000 $4000 $4000 $8000 $8000 $8000 $A000 $8000 $8000 $C000 $C000 $8000 $E000 $C000 $8000
OPERATING MODES ON-CHIP MEMORY 4-30
MC68HC11KW1
4.4.6
MM1CR, MM2CR Memory mapping window control registers
Address State reset 0000 0000
Memory mapping window control (MM1CR)
$0058
X1A18 X1A17 X1A16 X1A15 X1A14 X1A13
Address
Memory mapping window control (MM2CR)
State reset 0000 0000
$0059
X2A18 X2A17 X2A16 X2A15 X2A14 X2A13
These window registers indicate which bank window active. Each contains value output when selects addresses within extended memory window. change banks, write address bank into appropriate window register. Bits implemented; always read zero. MM1CR Memory mapping window control register When byte address falls within window value MM1CR driven from corresponding expansion address lines enable specified bank window. MM2CR Memory mapping window control register When byte address falls within window value MM2CR driven from corresponding expansion address lines enable specified bank window. Overlap guidelines: On-chip registers, RAM, EEPROM have higher priority than expansion windows. window overlaps RAM, registers EEPROM, they appear banks their address. Window higher priority than window therefore overlapped portion window inaccessible.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-31
4.4.7
PGAR Port assignment register
Address State reset
Port assignment (PGAR)
$002D
PGAR5 PAGR4 PGAR3 PGAR2 PGAR1 PGAR0 0000 0000
PGAR selects which pins used memory expansion address lines, defining which extended address lines used. memory expansion address lines shared with port pins. Selecting address these pins causes port lost. Therefore, allow unused lines serve general-purpose I/O, select only those address lines that needed expansion logic. neither bank uses particular expansion address bit, corresponding available general-purpose I/O. address line required, clear appropriate PGAR. special case exists address lines that overlap address lines XA[15:13]. these lines selected address lines PGAR, used either window, corresponding address line output appropriate port pin.) Bits [7:6] implemented; always read zero. PGAR[5:0] Port assignment (set) Corresponding port expansion address line (XA[18:13]). Corresponding port general-purpose I/O.
(clear)
Chip selects
function chip selects minimize amount external glue logic needed interface external devices. Such factors polarity, address block size, clock stretching controlled using chip-select registers. When enabled, chip select signal asserted whenever makes access designated range addresses. control signals chip select signals synchronous with external clock signal. Refer section expansion timing (Section A.5.4) electrical specifications chapter. length external clock cycle which external device synchronized stretched accommodate devices that slower than MCU. There chip select control registers. Chip select functions enabled control bits CSCTL register. When used chip select functions, used general-purpose I/O. MC68HC11KW1 four software configured chip selects that enabled expanded modes. chip select (CSIO) used expansion. program chip select (CSPROG) used with external memory that contains reset vectors program. general-purpose chip selects, CSGP1 CSGP2, used enable external devices. These external devices byte memory space expanded memory space.
OPERATING MODES ON-CHIP MEMORY 4-32
MC68HC11KW1
4.5.1
Chip select priorities
minimize conflict between chip selects with another with internal memory registers, priority determined GPSPR CSCTL register. Refer Figure 4-12.
Table 4-12 Chip select priorities
GCSPR On-chip registers On-chip Bootloader On-chip EEPROM chip select Program chip select chip select chip select GCSPR On-chip registers On-chip Bootloader On-chip EEPROM chip select chip select chip select Program chip select
4.5.2
Program chip select
program chip select (CSPROG) active range memory where main program exists. Other chip selects active when their respective memory areas used. Refer Table 4-13. CSPROG enabled reset normal expanded mode when there internal memory reset vector address $FFFE-$FFFF. After reset normal mode, stretch select CSCSTR register provide cycle stretch that slow memory devices used. special test mode CSPROG enabled without stretch reset. Program chip select fixed with address valid timing active low.
4.5.3
chip select
chip select (CSIO) programmable byte size located addresses $1000 $1FFF, byte size located addresses $0000 $1FFF. Polarity active state programmable active high active low. Clock stretching from zero three cycles. Refer Section 4.5.4 descriptions bits IOEN, IOPL, IOCSA, IOSZ.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-33
4.5.4
CSCTL Chip select control register
Address IOEN State reset
Chip select control (CSCTL)
$005B
IOPL IOCSA IOSZ GCSPR PCSEN PCSZA PCSZB 0000 0100
IOEN chip select enable
(set)
CSIO enabled uses port CSIO disabled port general-purpose pin.
(clear)
IOPL chip select polarity select (set) CSIO active high. CSIO active low.
(clear)
IOCSA chip select address valid (set) CSIO valid during address valid time. CSIO valid during E-clock high time.
(clear)
IOSZ chip select size select (set) CSIO size $0000-$1FFF. CSIO size $1000-$1FFF.
(clear)
GCSPR General-purpose chip select priority (refer Table 4-12) (set) General-purpose chip selects have priority over program chip select. Program chip select priority over general-purpose chip selects.
(clear)
PCSEN Program chip select enable (set) CSPROG enabled reset uses port CSPROG disabled port general-purpose pin.
(clear)
PCSZA PCSZB Program chip select size Table 4-13 Program chip select size
PCSZA PCSZB Size (bytes) Address range $0000 $FFFF $8000 $FFFF $C000 $FFFF $E000 $FFFF
OPERATING MODES ON-CHIP MEMORY 4-34
MC68HC11KW1
4.5.5
General-purpose chip selects
general-purpose chip selects most flexible programmable have most control bits. Polarity active state, valid address valid, size, starting address programmable. Clock stretching from zero three cycles. Each general-purpose chip select registers. One, control register GPCSxC, determines logical output required when area memory selected range memory over which chip select active. Each chip select programmed become active whenever address enters memory expansion window, regardless actual bank selected. This known following window. second, address register GPCSxA, allows starting address chip select programmed. bits this register that valid determined size chip select range selected control register. Refer descriptions associated registers starting address control information. cases where general-purpose chip select programmed drive other general-purpose chip select program chip select, determine priority from Table 4-14.
Table 4-14 General purpose chip select priority
Condition GPCS1 drives GPCS2 GPCS1 drives GPCS2 drives GPCS1 GPCS2 drive Priority GPCS1 GPCS1 GPCS2 GPCS1
4.5.5.1
GPCS1A General-purpose chip select address register
Address State reset
Gen. purpose chip select addr. (GPCS1A) $005C G1A18 G1A17 G1A16 G1A15 G1A14 G1A13 G1A12 G1A11 0000 0000
G1A[18:11] General-purpose chip select address These bits select starting address general-purpose chip select range. Refer Table 4-15.
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-35
4.5.5.2
GPCS1C General-purpose chip select control register
Address State reset
Gen. purpose chip select con. (GPCS1C) $005D G1DG2 G1DPC G1POL G1AV G1SZA G1SZB G1SZC G1SZD 0000 0000
G1DG2 General-purpose chip select drives general-purpose chip select
(set)
CSGP1 CSGP2 OR'ed driven CSGP2. CSGP1 does affect CSGP2.
(clear)
G1DPC General-purpose chip select drives program chip select (set) CSGP1 CSPROG OR'ed driven CSPROG. CSGP1 does affect CSPROG.
(clear)
G1POL General-purpose chip select polarity select (set) CSGP1 active high. CSGP1 active low.
(clear)
G1AV General-purpose chip select address valid select (set) CSGP1 valid during address valid time. CSGP1 valid during high time.
(clear)
G1SZA-G1SZD chip select size These bits select size general-purpose chip select Refer Table 4-15.
OPERATING MODES ON-CHIP MEMORY 4-36
MC68HC11KW1
Table 4-15 General-purpose chip select size control
G1SZx 1100-1111
Size (bytes) Disabled Follow window Follow window Default
Valid bits (MXGS1 None G1A[15:11] G1A[15:12] G1A[15:13] G1A[15:14] None None None None None None None
Valid bits (MXGS1 None G1A[18:11] G1A[18:12] G1A[18:13] G1A[18:14] G1A[18:15] G1A[18:16] G1A[18:17] G1A18 None None None None
4.5.5.3
GPCS2A General-purpose chip select address register
Address State reset
Gen. purpose chip select addr. (GPCS2A) $005E
G2A18 G2A17 G2A16 G2A15 G2A14 G2A13 G2A12 G2A11 0000 0000
G2A[18:11] General-purpose chip select address These bits select starting address general-purpose chip select range. Refer Table 4-16.
4.5.5.4
GPCS2C General-purpose chip select control register
Address State reset
Gen. purpose chip select con. (GPCS2C) $005F
G2DPC G2POL G2AV G2SZA G2SZB G2SZC G2SZD 0000 0000
implemented; always reads zero. G2DPC General-purpose chip select drives program chip select (set) CSGP2 CSPROG OR'ed driven CSPROG pin. Does affect program chip select.
(clear)
MC68HC11KW1
OPERATING MODES ON-CHIP MEMORY 4-37
G2POL General-purpose chip select polarity select (set) CSGP2 active high. CSGP2 active low.
(clear)
G2AV General-purpose chip select address valid select (set) CSGP2 valid during address valid time. CSGP2 valid during high time.
(clear)
G2SZA-G2SZD General-purpose chip select size These bits select size general-purpose chip select Refer Table 4-16. Table 4-16 General-purpose chip select size control
G2SZx 11100 1111 Valid bits (MXGS2 None G2A[15:11] G2A[15:12] G2A[15:13] G2A[15:14] G2A15 None None None None None None None Valid bits (MXGS2 None G2A[18:11] G2A[18:12] G2A[18:13] G2A[18:14] G2A[18:15] G2A[18:16] G2A[18:17] G2A18 None None None None
Size (bytes) Disabled 128K 256K 512K Follow Window Follow Window Default 512K
4.5.6
chip select driving another
general-purpose chip selects programmed drive program chip select well each other. General-purpose chip select drives general-purpose chip select only. There eight combinations bits G1DG2, G1DPC, G2DPC. Although possible combinations allowed, some combinations cause operations which perform might expect. results combinations defined following table. priorities defined previous sections still apply. following table assumes that none chip select ranges overlap.
OPERATING MODES ON-CHIP MEMORY 4-38
MC68HC11KW1
Table 4-17 chip select driving another
G1DG G2DP Program asserted when General asserted General asserted G1DPC address when address when address valid program area valid general area valid general area valid program general area Never asserted valid general area valid program general area valid general area Never asserted valid program general area Never asserted Never asserted valid program area valid general general area Never asserted valid program general area Never asserted valid general area valid program general area valid general area Never asserted valid program general area Never asserted Never asserted
4.5.7
Clock stretching
Each chip select bits that enable clock stretching from zero three cycles. clock stretch programmed occur only during accesses addresses that chip select's address range. During clock stretch period clock held high additional full peri
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