Advance Information 8-BIT MICROPROCESSOR MCl@05E2 Microproce

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Advance Information 8-BIT MICROPROCESSOR MCl@05E2 Microproce

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8-BIT MICROPROCESSOR
MCl@05E2 Microprocessor Unit Family Microcomputers. This 8-bit microprocessor contains CPU, on-chip low-power, low-cost processor designed
MC146805E2
CMOS
`.!*$
(HIGH PERFORMANCE
SILICONe$~
UNIT
(MPU) belongs M6805 fully static expandable RAM, 1/0, TIMER. low-end mid-range
Freescale Semiconductor, Inc.
plications consumer, automotive, industrial, communications markets where very power consumption constitutes important factor. following major features MC146805E2 MPU:
HARDWARE FEATURES
Typical Full Speed Operating Power Typical WAIT Mode Power Typical STOP Mode Power
.112
Bytes On-Chip Lines
Bidirectional
~:1, ~.,l ~!,$&
.,i.~:: Internal 8-Bit Timer with Software Programmable 7-Bit Pres&i~eX:t .,,1 *\<jy, External Timer Input .?,+ .,,. .*>, `$~,, ~!~:~ .3.,$$ Full External Timer Interrupts ,.'~$, >tt?l\,.,v,,l .~.l~l Multiplexed Address/Data .~., $:,$?, Master Reset Power-On Reset
Capable Addressing Bytes E~:$~RQlMemory Single 6-Volt Supply On-Chip Oscillator W-Pin Dual-In-Line
Package
Chip Carrier Also Available
~h>-,+ .,.\*. .:,~ ,,!, :?.\\w
it:t~. "*:,, .i$$,-if.s<::,~.+, ,J:;, ",,, ~:,`*I, "i${J! **;J?," .,.$}. t.,.,.~+.l .v.>M4\. /~\:/l\.,\ :.+.
ASSIGNMENTS
SUFFIX
CHIP CARRIER CASE
SOFTWARE FEATURES ,.~-'~qa;$ .,.~%. Similar MC68~ ,~d>. a+$,y$.i,.
Efficient Prog%,#pace Versatile lnterrup$~a~ting True Ma~@ulatrbti
]VDD
]Oscl
]OSC2 ]TIMER ]P80 ]P81 ]PB2 ]PB3 ]PB4 ]PB5
]PB6
.;:*
~.**,{
Addressin@~@ with Indexed Addressing Tables
i\,!~'
PA4[ PA3[ PA2~
Efficie~%u&tion Memq,$~apped +.,.' T$&$Fo&er *,,~\.?
Saving Standby Modes
]PB7
RoHS-compliant and/or free versions Freescale products have functionality electrical characteristics their non-RoHS-compliant and/or non-Pb- free counterparts. further information, http://www.freescale.com contact your Freescale sales representative.
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contains
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product.
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More Information This Product, Specifications Goand information herein www.freescale.comMOTOROLA
INC.,
1982
ADl~R:
Freescale Semiconductor, Inc.
Data
Address
Address Data
Strobe (@Z)
Strobe
Read/Wtite
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rucls Inc,
ELECTRICAL
CHARACTERISTICS
(VDD=3.O Vdc, unless otherwise noted) Charactetiatica Symbol
"!$,?<<
VDD:O,,
Ma&*~#
.,"y: +$,,,<< ,.,,,,'. .!),:.
Output Voltage (1Load< 10,0
Total Supply Current (CL=50 Loads, tcYc=5 (VIL=O.2 VIH=VDD- Wait (Test Conditions Stop (Test Conditions Note Below) Note Below)
,,,., $:$+$.,' ,+,+ *.7.
Va@&i$<
.$.,,?$, `~"$'" $,$}~ ~)~$ -~t:t,,, ,_}<:j X,*.,,$<
Output High Voltage (lLoad=0.25 A8-A12, BO-B7,
~y.,Y~., \.:~y@~'""~ $~,,J<.)K.,* .,!.\? ,,-' ~ii~$ `~OL ~t,3~* ,:,,, .,:~:y. `,8:,>. "~+';+.
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(lLoad=O.l
pAO-pA7, pBO-pB7
Output Voltage (lLoad=0.25 A8-A12, BO-B7, PBO-PB7, R/~, PAO-PA7 Input High Voltage PAO-PA7, PBO-PB7, BO-B7 TIMER, RESET
Oscl
Input Voltage (All Inputs) Frequency Operation Crystal External Clock Input Current RESET, IRQ, TIMER, OSCI Hi-Z Output Leakage PAO-PA7, PBO-PB7, BO-B7 Capacitance
\\+. ,,~1 .,::$ f!:l:,>,,
~?.~$' .*.;. \i,y .:q.,, $.~.,ft!~ ,+.,. x),. .},r `~:i,. .$iJ\. t{,~. ,rt, ,>., ~1:,
fosc fosc ITSL
,.,$,,., ,,\kp, .,~,, ~j>> a$i~?+ ,,,y,, ,<\\, .,:.'.,
NOTE: Test conditions Quiew~&ent
values are:
Port prog@m@d inputs. PBO-PB7, BO-B7. vIL=O.2 fo$:~%~?, vlH=vDQ-&~,~Or RESET, IRQ, TIMER OSC1 in~,js $~uarewave from +0,2 OSC2 ~'h~.~ad (including tester) maximum, 4,,, W~r@e~DD affected linearly this capacitance. i.:ih,
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TABLE CONTROL TIMING (VSS= TA=TL VDD=3.O fo~c Characteristics Port Timing Input Setup Time (Figure Input Hold Time (Figure Output Delay Time (Figure Interrupt Setup Time (Figure Crystal Oscillator Startup Time (Figure Wait Recovery Startup Time (Hgure Required Interrupt Release (Figure Timar Pulse Width (Figure Reset Pulse Width (Figure Timer Period (Figure Interrupt Pulse Width (Figure Interrupt Pulse Period "(Figure Oscillator Cycle Petiod [1/5 tcyc) OSCI Pulse Width High Symbol tpVASL tASLpX tlLASL toxov tlVASH tDSLIH tTH, tlLIH tlLIL tOLOL VDD=5.O
fo~c
.!,.
Stop Recovery Startup Time (Crystal Oscillator) (Figure tlLASH
,.`1Ii?'&\ ,.,+J. ,.*,* .,./' -,3?:;,. ~,,~. ~y~y: \?.$ .,&,,,! ,.>, -<l?s,!:
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.<,,J
,,M'>ia.a+
.,,.
tr,,fl "r#s tcyc tcyc tcyc
~$li$ ,,*:*;>.,:
-!.:$,?,, ,,.,\>N,;5 ~:,,.:!
.s.%!,,s ~:?: {t;.
1000
,#b*
.?:> "'*'
kti<.
OSCI Pulse Width
3gg:''~'?i**
CMOS Equivalent
`estpoint
C=50 PAO-PA7, PBO-PB7 A8-A12, BO-B7, with VDD=5
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A8-AI
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Internal/External Clock TCRb7
~tTL
,',.
Routine Starting Addr SP-11 5P-2 SP-3 SP-4
PCti
Unmux A8-A12 Address
BO-B7
Address/Data
b///////;////////////////N
Addr+
tine
Code
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FUNCTIONAL DESCRIPTION BO-B7 (ADDRESS/DATA provide power chip. provides power ground. (MASKABLE INTERRUPT REQUEST)
BUS)
both level-sensitive edge-sensitive input which used request interrupt sequence. completes current instruction before responds request, interrupt mask (1bit) condition code register clear, begins interrupt sequence current instruction, interrupt circuit recognizes both "wire ORed" level well pulses line (see Interrupt section more details). requires external resistor "wire operation. RESET
BO-B7 bidirectional lines constitute lower order addresses data. These lines multiplexed, with address present address strobe time data present data strobe time, When data mode, these lines bidirectional, transferring data from memory peripheral devices indicated R/~pin. outputs either data address modes, these lines capable driving standard load
A),,),, .:$Y:,.,k., .,,i~ ,.':t.:.,)i,' MC146805E2 provides types o~$~!~qtor inputs crystal circuit external clock. T~$~$$bscillator pins used interface crystal CLFmIN+aSshown $t~,,,!*\.\ Figure external clock used, it~B%t@ connected OSCI. input these pins div~@{~five form cycle rate seen D~:~f~.me frequency range specified fosc. OS~l `?~,,,@~sransitions relationt ships provided FigU{~ system designs using oscillators slower than ~!?$$ ,.~,~.~ ,-1, `,,.,:.*:: CRYSTAL Theq[@~@Shown Figure recommended when using wta.~he internal oscillator designed interface wit~.s~,,n AT-cut parallel resonant quartz crystal resonator in-ttigtif$equency range specified fosc electrical~$ti~eristics table. external CMOS oscillator recw,%:~#ed when crystals outside specified ranges $~i:~e used, crystal components should M$unte&as close possible input pins minimize .,~d~ut distortion start-up stabilization time, :@\.T<:i
Oscl,
0SC2
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RESET input required start-up used reset internal state provide orderly software start-up procedure. Refer Reset section detailed description. TIMER TIMER input used clocking on-chip timer, Refer Timer section detailed description. (ADDRESS STROBE)
Address strobe (AS) output strobe used indicate ::!*"!+w$$~ presence address 8-bit multiplexed bus. EXTERNAL CLOCK external clock should apAS line used demultiplex eight least significant `t$~.~$: ~lied OSCI input with 0SC2 input connected, dress bits from data bus, latch controlled address shown Figure strobe should capture addresses negative edge,.+Thi@$' output capable driving standard load 4'&I130 (LOAD INSTRUCTION) ,$t,i,;, .Ki?:'~ %,$,\: 1,,.*,,., (DATA STROBE) .1,3 $V.t, !},,,. This output used transfer data t@:~#$&& peripheral memory. occurs anytime M~$U'@8s data read write. also occurs when ,{b'~k data transfer from internal mw@.W,t%efer Table Figure timing charact6ri$J::$This output capablef driving standard T~&k~&and continuous signal fosc,k+ 5~,#n WAIT STOP state. S@&'@bus cycles redundant reads ~:,$:,il~ >y<?$$~ opcode bytes, ,\t+w, `,.:, ,.~-.\.,~. ,,,. (READ~t&~Tt) ~u~ut used indicate direction data trao:,f~fo~@6th internal memory registers, exter.ng~{p~.t~heral devices memories. This output used .:,J ,<to@&ate selected peripheral whether going `~k~d write data next data strobe (R/~ I&_= processor write; high processor read). output capable driving standard load normal standby state read (high). A8-A12 (HIGH ORDER ADDRESS LINES)
~L,,,:@$~
This output used indicate tha~ fetch next opcode progress. remains during external timer interrupt. output used only certain debugging test systems. normal operations this connected. output capable driving standard LSTTL loads This signal overlaps data strobe,
PAO-PA7 These eight pins constitute input/output port Each line individually programmed either input output under software control data direction register shown Figure Ii(b). programmed output when corresponding "l", input when "O'. output mode bits latched appear corresponding output pins. read port bits programmed outputs reflects last value written that location, When programmed input, input data Mt(s) latched. read port bits programmed inputs reflects current status corresponding input pins. port timing shown Figure typical port circuitry Figure During power-on reset external reset, lines configured inputs (zero data direction register). output port register initialized reset. compatible three-state output buffers capable driving standard load re~d/write register.
A8-A12 output lines constitute higher order nonmultiplexed addresses. Each output line capable driving standard load
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,,,.,
Freescale Semiconductor, Inc. FIGURE"9 -.OSCI TRANSITIONS'
,,.j,.~:,,
L'.,
,'-,.,,
,,.,
,,"" .,:~., ,.,'
."., r.,,
Freescale Semiconductor, Inc.
,,,,
.,-,'
BO-B7
q,',
.'., Oscl ,,,,r.y%ii,~f ~iq;:,
inter~al `memory spade located within first bytes ,rnemory (first half page zero) comprised "1/0 port locations, flmer locations, bytes RAM. read from write of,these loca~ ,tions. p~ogra,m write on-chip locations repeated external permit off-chip"'memory duplicate content on-chip me,mory. Program reads on-chip ioca` tions also appear theextern"al bus, accepts data only from addressed on-chip location, read
data appearing the''input bus. ignored. stack pointer used' address data stored stack. Data stored stack during interrupts subroutine calls. power-up, stack pointer "$O07F decremented data pushed onto
stack. When data removed from stack, stack pointar incremented. maximum bytes
~.,' `:},:;',
available
stack usage, Since most programs
only
`MEMOR~'ADDRESSING,
,small part allotted stack locations interrupts and/or
,,subrouti,ne stacking purposes,' unused bytes usable
CI%805E2 `capable of'addressing 8192 bytes rn,amory registers, address s"pace:is di~ded into internal memory space `and' external' memory: spacej as!"
shown Figure .";., ,,., .,-. :.,'
program data storage. memory locations above location $007F:are part
externalmemory map. addition, ten'locations portion lower bytes memory space, shown
`,'.
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FIGURE TYPICAL PORT CIRCUITRY
Data Direction Register
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Data Direction Register DDA7
DDA6
DDA5
DDA4
DDA3
~+~:$$;::"~+
DDAO $0004
Port Register
s,i.,
$0000
TABLE FUNCTIONS
Functions input mode. Data written into output data latch. Data written into output data latch output pin. state read. output mode, output data latch read.
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FIGURE PROGRAMMING MODEL
Accumulator
Index Register
INZC
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stack#~;$s?],$ollowed
PCH, etc. Pulling from stack
`The stack pointer 13-bit r~&~,{3~ontaining -address next free location on~he ,fack. When accessing memory, seven most sig@%~$&lts permanently 00~001. They app~n~d.~k least significant register bits produce ~,,,a~ress within range $O07F $0040, stack ~fea bf&R'AM used store return address subrou&@ealls machine state during in,,~,.)'.,,v~, terrupts. Durin~%@~t&@b) power-on reset, during "reset stack ~t~.' instruction, stack pointer upper li,,m~W7F). Nested interrupts and/or subroutines u~,,.ti~ts~ (decimal) locations, beyond which stack &oin@t'r'wraps around" points th:@~y~w.$&sing previously stored ,:uB~@&*$fie call occupies upper limit, information,
carry occurs between bits duting instruction. useful binarv coded decimal addition subroutines. INTERRUPT MASK When set, both external interrupt timer interrupt disabled. Clearing this enables above interrupts, interrupt occurs while set, interrupt latched will processed when next cleared.
NEGATIVE When set, this indicates that result last arithmetic, logical, data manipulation negative (bit result logical one). ZERO When last arithmetic, CARRY set, this indicates that result zero,
bvtes stack, while
.;,,
CONDITION CODE REGISTER (CC)
logical,
data manipulation
when duting
carry borinstruction,
occurs
arithmetic
condition code register 5-bit register which each used indicate results instruction just executed. These bits individually tested program specific action taken result their state. Each five bits explained below, HALF CARRY when
also modified during test, shift,. rotate, branch types instruction, RESETS
MC146805E2 reset modes: active external reset power-on reset function; refer Figure
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,.-~
-.,,
,"'.:
:.:,.~.,,:,,
-;,,,.,
!,,:,.'
.!,, '.,,.:
.,,,,,~.,,,-
.;,~-."~.
.~.,!
(piN'#l)
"':,, ,:,,,
RESET input used orderly' s'oftware start-up proc~ external reset mode, RESET must sta~:low tRL. ,Thl trigger improve
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then
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FIGURE RESET INTERRUPT PROCESSING FLOWCHART
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07F+S O+DDRS Logic FF+Timer 7F;~Ts&ler
Clear
lFFE Address
Load From: SWI: 1FFC/1 lFFA/1 TIMER: lFF8/1 rimer Wait: lFF6/l FF71
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multiplexed address/data goes data input state shown Figure high order address lines remain address next instruction, remains STOP mode until external interrupt reset occurs, During quests STOP mode, remove timer control pending timer register timer (TCR) bits interrupt reExternal altered which allowed count normal sequence, line goes high state, multiplexed address/data goes data input state, lines state shown Figure high order address lines remain address next instruction. remains this state until external interrupt, timer interrupt, reset occurs, During WAIT mode, condi~o~+,code register cleared enable interrupts. oth~{~'rws?~rs, memory, mode. FIGURE STOP FUNCTION FLOWCHART time, lines remain allow interrupt external external their last st~.t%~'timer exit ~b@&IW'e WAIT same timer tb~n, enabled petiodic
disable
further
interrupts,
interrupts enabled condition code other registers memory remain unaltered, remain unchanged.
register, lines
timer interru,pt~-~at serviced~r~t;
stop
interrupt request cleared,::~:~t,}~,~j~xternal interrupt routine, normal timer interrupt~$oo}ltie timer WAIT interrupt) serviced mode. since ,q>y:; ,<;$MER Is:#o longer WAIT
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Stop Oscillator Clocks Clear Mask
timer co~*,&& single 8-bit software programmable counter wf~:~blt software selectable prescaler. Figure sho~,,~ b~&k diagram timer. counter pre~:~der program control decrements towards @i~When counter decrements zero, timer ~t~u~ request bit, i.e., timer control regis@gF/~C~), set. Then timer interrupt
~@ke&X~.e., ,,~o~,,register Nrupt. After
condition both cleared, processor receives
completion current instruction,
pro-
stack, then fetches timer interrupt vector from locations order begin servicing interrupt, were interrupted vector fetch would while WAIT mode, interrupt from locations
$IFF7. counter continues count after reaches zero, allowing software determine number internal external input clocks since timer interrupt request set. counter read time processor without disturbing count. content counter becomes stable prior read portion cycle does change during read. timer interrupt request remains until cleared software. read occurs before timer interrupt serviced, interrupt lost. TCR7 also used scanned status noninterrupt mode operation (TCR6= prescaler 7-bit divider which used extend maximum length timer. programmed choose appropriate prescaler output which used counter input. processor cannot write into read from prescaler; however, contents cleared "OS" write operation into when written data equals which allows truncation-free counting. timer input configured three different operating modes, plus disable mode, depending value written TCR4, TCR5 control bits. Refer Timer TIMER Control INPUT Register MODE section.
Turn Oscillator Wait Time Delay Stabilize
Fetch External Interrupt Reset Vector
WAIT WAIT instruction places MC146805E2 power consumption mode, WAIT mode consumes
somewhat more power than STOP mode; refer Table WAIT function, internal clock disabled from internal Thus, circuitry internal except timer circuit; refer Figure except timer processing halted
"U', inand external mode
TCR4 TCR5 both programmed timer from internal clock TIMER input disabled. internal
clock
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External Input
FIGURE19 TIMER BLOCK DIAGRAM Selected TCR4, TCR5 Selected TCRO,
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Internal Clock Cleared TCR3
.~:.>$,
TIMER CONTROL REGISTER (TCR) 7654 TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCRI
,$'.\JeR5 .:,. ~:,':,. .'>$(.!i<\; .,.*) t:."t:-.~,,+?, to-.\,.?:* TCRO "'~; ,.*':
TCR4 Internal clock (AS) timer internal clock (AS) TIMER timer Inputs timer disabled TIMER timer
whenever counter dqc~ `"$:,,* program control. ,:~t: ,,/$ym Cleared external rese$:lp~er-on struction, progra~''w~bl
zero, unreset, STOP
TCR3 Timer Prescaler Reset bit: wtiting this resets prescaler zero. read this location always indicates (unaffected RESET).
TCR2, TCRI, TCRO- Prescaler address bits: decoded select eight outputs prescaler (unaffected RESET).
TCR2
TCR1
TCRO Result
Select external clock source. Select internal clock source (AS).
+128
INSTRUCTION
TCR4 External enable bit: control used enable external TIMER (unaffected RESET). Enable external TIMER pin. Disable external TIMER pin.
basic instructions. They divided into five different types: register/memory, readmodify-write, branch, manipulation, control. following paragraphs briefly explain each type. instructions within given type presented individual tables.
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processor indicate "contents replace-d colon indi.
information-necessary
:.r6aiSteror acct)mulator,
ex~the opcode. Operations
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registers
chip ROM, Direct addressing
addrassof the"two bytes following opextended addressing modes urnents anywhere memory with ction. When using Motorola specify whether instruction addressing, assembler
nest efficient addressing mode,
mode, theeffective
(PC+2);PC+PC+3
Address Low-(PC
:addressing mode, effective contained 8-bit index addressing mode access first instructions only byte move pointer through table erenced location.
)y,adding th,e contents byte index register; therefore, nywhere, within lowest mple, thi,s mode addressing element element table. vtes. contents index ntents (PC+I) bvte "offset indexing permits either ROM,
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INDEXED, 16-BIT OFFSET opcode. clear instructions occupy bytes, opcode (including number) second address byte which contains interest. EA=(PC+I); PC~PC+2 Address High Address Low+(PC TEST BRANCH
`.!$>,
indexed, 16-bit offset addressing mode effective address contents unsiged 8-bit index register unsigned bytes following opcode. This addressing mode used manner similar indexed 8-bit offset, except that this three byte instruction allows tables anywhere memory (e.g., jump tables ROM). with direct extended, M6805 assembler determines most efficient form indexed offset bit. content index register changed. EA=X+[(PC+ I):(PC+2)]; PC+PC+3 Address High-( Address Low+K+ (PC+2) where: carry from addition RELATIVE
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Relative addressing used only branch instructions. relative addressing content 8-bit signed byte following opcode (the offset) added only branch condition true, Otherwise, control proceeds next instruction. span relative addressing limited range bytes from branch instruction opcode location, Motorola assembler calculates proper offset checks within span branch.
test branch combination direct ad~$$$~g, addressing, relative addressing. ,@d~% condition (set clear) tested part ~f,%$<~pcode. address byte tested tQ@:~&byte immediately following opcode byte,<JP&$P&The signed relative 8-bit offset third byte .#~&2)~&fiNd added specified set,?@:$~@]n specified memory location. This single thr#~$@ instruction allows program branch based3$~Jthe'~ondition first locations m~$r 541+*'(R Address Hig~:<~q@8dress Low~(PC+ EA2= 3+$~Q); PC~EA2 branch taken; ,s~,oth&Wise, .{.}.\\ \i\,,,>~ \\*f\i.
CONFIGURATION f":$~sTEM Figu~,*~firough show general terms C~468~52 structure utilized. Specified interEA= PC+2+ (PC+ PC~EA branch taken; fat~{~etails vary with various peripheral memory otherwise, #~&c~k emnloved. :%~t,i~$.$able11 pro~ides detailed description information SET/CLEAR ~t~'!~$,present bus, read/write (R/~) load inDirect addressing addressing combined in`":S struction (Ll) during each cycle each instruction. structions which clear individual memory This information useful comoaring actual with expetted results during debug both softw~re hardware control,, program executed. information categorized groups according addressing mode number cycles instruction.
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Branch Always Branch Never
TABLE6-
BRANCH INSTRUCTIONS Relative Addressing Mode Cycles "!$,?<< skr.\:27,, `~,;:": ,?*., ,,$''" ~.,, .;3>::> ~t.,.?: ~i:\, ~<$.it ,,l.,.,~,i,.,. ,y.,.1. ,.,,.
Function
Mnemonic (BHS) BHCC BHCS
Code
Bytes
Branch Higher Branch Lower Same Branch CarrV Clear (Branch Higher Same) Branch lFFCarrV (Branch Lower) Branch Equal Branch Equal Branch Half CarrV Clear
:;~:*'&"""
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Branch Half CarrV Branch Plus Branch Minus
k~%$>, +$ci'y<;& ~:w~ `::$2:Y*I
~.{. ,,:$:
,.~k.;,
Function Branch Branch Clear Clear qR~3:&'rh +,,B'%$F%n[n= O.7) ,l:t~ %@~R O.7) ,.,:,1 ~.t. `*?t Mne~'~J$k$ Set/Clear Code 10+2*n ll+2*n Bytes
Addressing Modes Test Branch CVcles Code 01+2*n Bytes Cvcles
Function Transfer Transfer CarrV Clear CarrV Interrupt Mask Clear Interrupt Mask Software Interruot
Mnemonic
Code
Bytes
Cycles
Wait
WAIT
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TABLE MCI=5 CMOS INSTRUCTION OPCODE
Manipulation 0321 0310 ET05 BRCLR05 BRSET15 BSETO BCLRO BSET1 BCLR1 BSET2 BCLR2
Branch
Read-Modify-Wtite
Control 0110
0111
0101
1011
,.>S%&T ./::.
!s,,
1101
1170
1111
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`?#&,; lhlM,. ~!!a ,*`"'~$ ~Y%c ,J~>
":\. `$?*
0310 0311 0101
COMA LSRA
BRCLR15 ET25
COMX LSRX
0101
BRCLR25 ET35
RORA
RORX
0110 0111
fy;$; ~;$<+ ,',,, ":$>.,; `~Q;A ,,,if,,?:~, .~tl ?,.>,, fj;>\ ~.,,,, ~:b:,
:BRc~ SET45 BRCLR45 ET55
:BcL~: BSET45 BCLR45 BSET55 BCLR55 BSET65 BCLR65
`E~:: BHCC BHCS
`s~;
`sR~; LSLA
`sR~; LSLX
`SR;
<:'?.
:TA~N;
`T{;
1032
2:,. ~,:,.+<"?
`T~:
`TAT
ROLA
ROLX
~.?.::
1021 1010 1o11 1102
1031 1010
DECA
1o11
BRCLR55 ET65
INCA TSTA
I,:t`1 ,*~.~ .\$.,, ~',::i>., \:~\Y .$,:$,,:! INCX (p~, DECX TSTX$$: t:~,x&T
ORA'
STOP
1101 1110
BRCLR65 SET75
BCLR75
~%,, ~'l:;.,t, ,:<=. "'kc' .'., .:~{.
JSRIX;
JSRIX;
BRCLR75
A@+'
!:,> .,.! ,,~'$$}:/,.)
1111
CLRIX:
WA';:
`xl,:
STX:::
STC!
STX2
STX!
Abbreviations
Address
LEGEND
Inherent
Index Register
Accumulator Immediate Direct Extended `ne.:-
Opcode
Hexadecimal
Opcode Binary
Indexed,
Bfie
(16-Bit)
Offset
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FIGURE CONNECTION M~OO PERIPHERALS Address Decode
A8-A12
Chip Select
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NOTE:
)0-Q7 CMOS Non-Muxed ~o-A7 Memory
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Address Mode Instructions
Inh-r-nt
TABLE SUMMARY Cycles Cycle
CYCLE-BY-CYCLE
OPERATION
Address
Data
Code Address Code Address Code Address
Code Next Instruction ~levant Data #rrelevant Data Irrelevant Data Code Code Code Next Instruction Return Address Byte) Return Address Byte) Contents Index Register Contents Accumulator Contents Register Address Int. Routine Byte Address Int. Routine BytE Interrupt Routine First Opcode Code Code Next Instruction Irrelevant Data Irrelevant Data Irrelevant Data Irrelevant Data Irrelevant Data Irrelevant Data Code
STOP
WAIT
Code Address Code Address Code Address Code Address Stack Pointer Stack Pointer Stack Pointer Code Address
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Code Address .@~' Code Address `:., !t~,tt.+ ft,:t,,> .kp,\Q Stack Pointer .}.>,:;:+}* Stack Pointer ,,*. /!,,8 .,,. .:/, Stack Pointar *\,~,*ii,.,,>:. Stack Pointer .,$*, \$,,/l,::$' Stack Pointer Vector Address 1FFC (He~'P'''s$:yqJ Vector Address 1FFD (fi[x)'k~ Interrupt Routine StaF~&~Mress *$$x{!, Code Address
nmediate
Code Address Code Address
Code Operand Data
,,i\. ,,:. `*:*::. :\., BSET ~i.a, BCLR .'$.,.!.,, .,!,W., ,.,, .,',:}~ie. .,,.::,<.~ "?\.,. Test and, ~,@'ch- ~:i* ,,,$: .t~.,'+;<:j,+;~ BRS&Y,@t:A,. B~C:&;$ ";.::T&h,
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Code Address Code Address Address Operand Address Operand Address Operand Code Address Code Address Address Operand Code Address Code Address
Code Address Operand Operand Data Operand Data Manipulated Data Code Address Operand Operand Data Brench Offset Branch Offset
.,i.' ,,,.
Relative BHCC BHCS Code Address Code Address Code Address
Code Branch Offset Branch Offset Code Branch Offset Branch Offset First Subroutine Code Return Address Byte) Return Address Byte)
Code Address Code Address Code Address Subroutine Starting Address Stack Pointer Stack Pointer
1010
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A~dress Address Address
Operand Operand Operand
Byte) Byte) Bvte)
Address Subroutine Byte: Address Subroutine Byte Subroutine Code
Code Next
Instruction
Code Next Instruction
Code Next Instruction Code Next Instruction
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TABLE
SUMMARY
CYCLE-BY-CYCLE
OPERATION
(CONTINUED)
Indexed
Address Mode Instructions 8-Bit Offset
Cycles
Cvcle
Address
Data
Code Address Code Address Code Address
Code Address Code Address Code Address Index Register Offset Code Address Code Address Code Address Code Address Index Register
,$~,:: yi:~{l
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Offset
@*et Operand Data
Code Address Code Address Code Address Index Register Code Address Code Address Code Address Code Address
,,;$" Code Offset Offset Operand Data Instruction Code Next
Offset
`:$,pd<+~>v ">+?*, ,,,t.Fti.J.,,, `~$i*<:,.ii,bt **,)$ :.;l) ,.~{.~$ .!,$~. :,), ,,t<.\$i<;$ .t:?t :\\? ,.,,~th" ~.];,}
Code Offset Offset Current Operand Data Current Operand Data ODerand Data Code Offset
Offset Subroutine Return Return Address Address
Code Bvte Bvte
Indexed,
16-Bit
Offset
,!,*~
`.+.,O
~$$%~
Address
Code Offset Offset Offset Offset Offset Offset Operand BVte) BVtel Byte) Byte) BVte) Byte) Data
,~,~bde Address Code Address
`bpCode
Address
Code Address Code Address Code Address Code Address Index Register Code Address Code Address Code Address Code Address
Code
Offset
Code Address Index Register Code Address Code Address Code Address Code Address
Offset
Index Register Offset Stack Pointer Stack Pointer
Code Offset BVte) Offset Offset BVte) BVte)
Offsat Byte) Operand Data Code Offset Offset Offset Return Return BVte) BVte) Bvtel Code Byte) BVte) Address Address
Subroutine
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PACKAGE DIMENSIONS
NOTES: DIMENSION~lS
DATUM.
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,?:::! ~(i,ti~,,, ,,.<, $~,* ~:$:,, .r?p,i:\.,\t.,*,,
POSITIONAL TOLERANCE LEAOS (0), SHALL WITHIN 0.25 (O.O1OI MAXIMUM MATERIAL CONOITION,
OIMENSION OIMENSION `ow;TE:':NEAND ;°FLAsH"
CENTER LEADS DOES INCLUOE
SUFFIX
PLANE
pLAsTIc PAcKAGE CASE 711-01
1.02 1.52 2.54 1.65 2.16 0.20 0.3B 2.92 3.43 15.24 0.51 1.02
0.040 0.060 0.100 0.065 0.085 0.00B 0.015 0.115 0.135. 0,600 0,0201 0.040
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NOTES: DIMENSIONS RARE DATUMS. GAUGE PLANE, POSITIONAL TOLERANCE TERMINALS (0): PLACES: ~@10.25(0,010] lA@l DIMENSIONING ANOTOLERANCING ANSI Y14.5, 1973,
SUFFIX
CHIP CARRIER CASE 761-01
MILLIMETERS 11.94 12,57 11.05 11.30 1.60 2.OB 0,33 0,69 1.07 1.47 1.02 0,S4 1.19 1.27 1,79 11.94 12.57
INCHES 0,470 0.495 0.435 0.445 0.063 O.OS2 0.013 0,027 0.042 0.05S 0,040 0.033 0.047 0.050 0.070 0.470 0.495
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PARTICULAR' M6805" FAMILY VERSION *Q+: .,'"';, `%;r;;lAGE ~k,v;~ie, .Iij MC~870~P3 N:.$t ~\,;?!$$,''&': ,.$=* ,,v,$:k~ $s,}, `~c146805G~ ,+.$>s.b~i,, ,\:,*~> ,.~,.h. .:*., -%,2> \-,~h?iitli,+.w, MC6805P2P2,, ~>t\.\ ,:{{,
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Motorola reserves rightto make changes.to prod ucts,herein improve ieliabilitv, function ordesign. Motorola does assume Iiabilitvarising application product-or circuit described herein; neither doesit convevanv licenseunder.ts patentrights rightsof others.
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INC.
A13322-3
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18,000 ,.-.,
RD1-850-R2

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