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HC908JB8AD/D Rev. 4/2002 Addendum MC68HC908JB8 Technical Data
This addendum provides additional information MC68HC908JB8 Technical Data, Rev. (Motorola document number MC68HC908JB8/D),
MC68HC08JB8A
MC68HC08JB8A part equivalent MC68HC908JB8. entire MC68HC908JB8 data book apply this device, with exceptions outlined this addendum. Table Summary MC68HC08JB8A MC68HC908JB8 Differences
MC68HC08JB8A Memory ($DC00-$FBFF) User vectors ($FFF0-$FFFF) Registers $FE08 $FF09 8,192 bytes bytes used; locations reserved. $FC00-$FDFF: used. $FE10-$FFDF: Used testing purposes only. level logic) MC68HC908JB8 8,192 bytes FLASH bytes FLASH FLASH related registers. $FE08 FLCR $FF09 FLBPR Used testing FLASH programming/erasing. VREG level (3.3V logic)
Monitor ($FC00-$FDFF $FE10-$FFDF) OSC1 OSC2 pins
Block Diagram
Figure shows block diagram MC68HC08JB8A.
Memory
MC68HC08JB8A 8,192 bytes user from $DC00 $FBFF, bytes user vectors from $FFF0 $FFFF. MC68HC908JB8, these memory locations FLASH memory. Figure shows memory MC68HC08JB8A.
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INTERNAL M68HC08 PTA7/KBA7 PTA0/KBA0 ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE DDRB PTB7-PTB0 DDRA
HC908JB8AD/D
REGISTERS
CONTROL STATUS REGISTERS BYTES TIMER INTERFACE MODULE
USER 8,192 BYTES
MONITOR BYTES VOLTAGE INHIBIT MODULE DDRD
USER VECTORS BYTES
DDRC
USER BYTES BREAK MODULE
PTC7-PTC0
PTD7-PTD6 PTD5-PTD2 PTD1-PTD0 PTE4/D-
OSC1 OSCILLATOR POWER-ON RESET MODULE
OSC2
(1),
SYSTEM INTEGRATION MODULE
PTE3/D+ DDRE COMPUTER OPERATING PROPERLY MODULE PTE2/TCH1 PTE1/TCH0 PTE0/TCLK MODULE
(1),
MODULE
POWER
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INTERNAL VOLTAGE REGULATOR Pins have logic. Pins have integrated pullup device. Pins have software configurable pull-up device. Pins open-drain when configured output. Pins have 10mA sink capability. Pins have 25mA sink capability.
VREG (3.3
Shaded blocks indicate differences MC68HC908JB8
Figure MC68HC08JB8A Block Diagram
TRANSCEIVER ENDPOINT
Addendum MC68HC908JB8 Technical Data
HC908JB8AD/D MC68HC08JB8A
$0000 $003F $0040 $013F $0140 $DBFF $DC00 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFDF $FFE0 $FFEF $FFF0 $FFFF
Registers Bytes Bytes Unimplemented 56,000 Bytes 8,192 Bytes Unimplemented Bytes Break Status Register (BSR) Reset Status Register (RSR) Reserved Break Flag Control Register (BFCR) Interrupt Status Register (INT1) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Break Address High Register (BRKH) Break Address Register (BRKL) Break Status Control Register (BRKSCR) Reserved Monitor Bytes Reserved Bytes Vectors Bytes
Figure MC68HC08JB8A Memory
Addendum MC68HC908JB8 Technical Data
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HC908JB8AD/D
Reserved Registers
registers $FE08 $FE09 reserved locations MC68HC08JB8A. MC68HC908JB8, these locations FLASH control register FLASH block protect register respectively.
Monitor
monitor program (monitor ROM: $FE10-$FFDF) MC68HC08JB8A device testing only. $FC00-$FDFF unused.
Electrical Specifications Electrical Characteristics
Electrical specifications MC68HC908JB8 apply MC68HC08JB8A, except parameters indicated below.
Table Electrical Characteristics
Characteristic(1) Regulator output voltage Output high voltage (ILoad -2.0 PTA0-PTA7, PTB0-PTB7, PTC0-PTC7, PTE0-PTE2 Output voltage (ILoad pins (ILoad PTD0-PTD1 ILDD mode (ILoad PTE3-PTE4 with disabled Input high voltage ports, OSC1 IRQ, Input voltage ports, OSC1 IRQ, Output current (VOL PTD2-PTD5 mode supply current, 5.25V, 3MHz Run, with speed USB(3) Run, with suspended(3) Wait, with speed USB(4) Wait, with suspended(4) Stop(5) 70°C (5.0) (4.5) (3.0) (2.5) Symbol VREG VREG -0.8 Typ(2) Unit
VREG (17)
(22)
VREG VREG (27)
Addendum MC68HC908JB8 Technical Data
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HC908JB8AD/D MC68HC08JB8A
Table Electrical Characteristics
Characteristic(1) ports Hi-Z leakage current Input current Capacitance Ports input output) re-arm voltage(6) rise-time ramp rate(7) Symbol COut VPOR RPOR VDD+VHI 0.035 (2.4) (2.7) Typ(2) Unit
(3.0)(8)
V/ms
Monitor mode entry voltage Pullup resistors Port port port PTE0-PTE2, RST, PTE3-PTE4 (with module disabled) (with module enabled) reset
VLVR
Vdc, Vdc, unless otherwise noted. Typical values reflect average measurements midpoint voltage range, only. (operating) measured using external square wave clock source (fXCLK MHz). inputs from rail. loads. Less than outputs. OSC2. ports configured inputs. OSC2 capacitance linearly affects IDD. Measured with modules enabled. Wait measured using external square wave clock source (fXCLK MHz); inputs from rail; loads; less than outputs. OSC2; termination resistors pins; ports configured inputs; OSC2 capacitance linearly affects wait STOP measured with suspend mode; OSC1 grounded; transceiver pullup resistor between VREG pins termination resistor pin; port pins sourcing current. Maximum highest voltage that guaranteed. minimum VREG reached before internal reset released, must driven externally until minimum VREG reached. numbers parenthesis MC68HC08JB8 (non-A part) values.
Memory Characteristics Table Memory Characteristics
Characteristic data retention voltage Symbol VRDR Unit
Notes: Since MC68HC08JB8A device, FLASH memory electrical characteristics apply.
Addendum MC68HC908JB8 Technical Data
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HC908JB8AD/D
MC68HC08JB8A Order Numbers
These part numbers generic numbers only. place order, code must submitted Processing Center (RPC). Table MC68HC08JB8A Order Numbers
order number MC68HC08JB8AJP MC68HC08JB8AJDW MC68HC08JB8AADW Package 20-pin PDIP 20-pin SOIC 28-pin SOIC 44-pin Operating temperature range
MC68HC08JB8AFB
MC68HC08JB8A MC68HC08JB8 Differences
MC68HC08JB8A MC68HC08JB8 identical devices, except following: Table MC68HC08JB8A MC68HC08JB8 Differences
MC68HC08JB8A OSC1 OSC2 pins Output current PTD2-PTD5 mode Operating currents trip points level logic) MC68HC08JB8 VREG level (3.3V logic)
Table Electrical Characteristics. numbers parenthesis MC68HC08JB8 values.
Addendum MC68HC908JB8 Technical Data
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HC908JB8AD/D NOTES
NOTES
Addendum MC68HC908JB8 Technical Data
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HC908JB8AD/D Rev. 4/2003

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