56F800 16-bit Digital Signal Controllers DSP56F803 Rev. 09/2007
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56F803
56F800 16-bit Digital Signal Controllers
DSP56F803 Rev. 09/2007
freescale.com
Document Revision History
Version History Rev. Description Change Added revision history. Added this text footnote Table 3-8: "However, high pulse width does have particular percent pulse width."
56F803 General Description
MIPS 80MHz core frequency functionality unified, C-efficient architecture Hardware loops MCU-friendly instruction supports both controller functions: MAC, manipulation unit, addressing modes 31.5K 16-bit words (64KB) Program Flash 16-bit words (1KB) Program 16-bit words (8KB) Data Flash 16-bit words (4KB) Data 16-bit words (4KB) Boot Flash 16-bit words each external Program Data memory 6-channel module 4-channel 12-bit ADCs Quadrature Decoder module Serial Communication Interface (SCI) Serial Peripheral Interface (SPI) General Purpose Quad Timers JTAG/OnCEport debugging shared GPIO lines 100-pin LQFP package
Outputs Current Sense Inputs Fault Inputs
PWMA
RESET IRQA
EXTBOOT IRQB JTAG/ OnCE Port VCAPC Digital Analog VDDA VSSA
A/D1 A/D2 VREF
Interrupt Controller
Voltage Supervisor
Quadrature Decoder Quad Timer
Program Controller Hardware Looping Unit
Address Generation Unit
Data 36-Bit Three 16-bit Input Registers 36-bit Accumulators
Manipulation Unit
Program Memory 32252 Flash SRAM Quad Timer Quad Timer Quad Timer 2.0A/B GPIO COP/ Watchdog Data Memory 4096 Flash 2048 SRAM Boot Flash 2048 Flash
IPBB CONTROLS
CLKO
XDB2 CGDB XAB1 XAB2
16-Bit 56800 Core
XTAL Clock EXTAL
INTERRUPT CONTROLS RESET MODULE CONTROLS ADDRESS [8:0] DATA [15:0]
GPIO
Application-Specific Memory Peripherals
IPBus Bridge (IPBB)
External Interface Unit
External Address Switch External Data Switch Control
A[00:05] Select Select Enable Enable A[06:15] GPIO-E2:E3 GPIO-A0:A7 D[00:15]
56F803 Block Diagram
*includes which reserved factory tied
56F803 Technical Data, Rev. Freescale Semiconductor
Part Overview
56F803 Features
1.1.1
Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture many Million Instructions Second (MIPS) 80MHz core frequency Single-cycle 16-bit parallel Multiplier-Accumulator (MAC) 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction with unique processor addressing modes Hardware loops Three internal address buses external address Four internal data buses external data Instruction supports both controller functions Controller style addressing modes instructions compact code Efficient compiler local variable support Software subroutine interrupt stack with depth limited only memory JTAG/OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits many three simultaneous accesses Program Data memory On-chip memory including low-cost, high-volume Flash solution 31.5K 16-bit words Program Flash 512K 16-bit words Program 16-bit words Data Flash 16-bit words Data 16-bit words Boot Flash
Off-chip memory expansion capabilities programmable wait states much bits Data memory much bits Program memory
1.1.3
Peripheral Circuits 56F803
Pulse Width Modulator module (PWM) with outputs, three Current Sense inputs, three Fault inputs, fault-tolerant design with dead time insertion, supports both center- edge- aligned modes, supports Freescale's patented dead time distortion correction 12-bit Analog-to-Digital Converters (ADCs), which support simultaneous conversions; modules synchronized Quadrature Decoder with four inputs (shares pins with Quad Timer)
56F803 Technical Data, Rev. Freescale Semiconductor
56F803 Description
Four General Purpose Quad Timers: Timer (sharing pins with Quad Dec0), Timers without external pins Timer with pins module with 2-pin ports transmit receive Serial Communication Interface (SCI) with pins additional GPIO lines) Serial Peripheral Interface (SPI) with configurable 4-pin port four additional GPIO lines) Computer Operating Properly (COP) Watchdog timer dedicated external interrupt pins Sixteen multiplexed General Purpose (GPIO) pins External reset input hardware reset JTAG/On-Chip Emulation (OnCETM) unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer controller core clock
1.1.4
Energy Information
Fabricated high-density CMOS with 5V-tolerant, TTL-compatible digital inputs Uses single 3.3V power supply On-chip regulators digital analog circuitry lower cost reduce noise Wait Stop modes available
56F803 Description
56F803 member 56800 core-based family processors. combines, single chip, processing power functionality microcontroller with flexible peripherals create extremely cost-effective solution. Because cost, configuration flexibility, compact program code, 56F803 well-suited many applications. 56F803 includes many peripherals that especially useful applications such motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply control, automotive control, engine management, noise suppression, remote utility metering, industrial control power, lighting, automation. 56800 core based Harvard-style architecture consisting three execution units operating parallel, allowing many operations instruction cycle. MCU-style programming model optimized instruction allow straightforward generation efficient, compact device control code. instruction also highly efficient compilers enable rapid development optimized control applications. 56F803 supports program execution from either internal external memories. data operands accessed from on-chip Data instruction cycle. 56F803 also provides external dedicated interrupt lines, General Purpose Input/Output (GPIO) lines, depending peripheral configuration. 56F803 controller includes 31.5K words (16-bit) Program Flash words Data Flash (each programmable through JTAG port) with words Program words Data RAM. also supports program execution from external memory. total words Boot Flash incorporated easy customer-inclusion field-programmable
56F803 Technical Data, Rev. Freescale Semiconductor
software routines that used program main Program Data Flash memory areas. Both Program Data Flash memories independently bulk-erased erased page sizes words. Boot Flash memory also either bulk- page-erased. application-specific feature 56F803 inclusion Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable signal outputs (the module also capable supporting three independent functions, total outputs) enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction current sensing software, separate bottom output polarity control. up-counter value programmable support continuously variable frequency. Edge- center-aligned synchronous pulse width control 100% modulation) supported. device capable controlling most motor types: ACIM Induction Motors), both BLDC (Brush Brushless motors), (Switched Variable Reluctance Motors), stepper motors. incorporates fault protection cycle-by-cycle current limiting with sufficient output drive capability directly drive standard opto-isolators. "smoke-inhibit", write-once protection feature parameters patented waveform distortion correction circuit also provided. double-buffered includes interrupt controls permit integral reload rates programmable from module provides reference output synchronize ADC. 56F803 incorporates separate Quadrature Decoder capable capturing four transitions two-phase inputs, permitting generation number proportional actual position. Speed computation capabilities accommodate both fast slow moving shafts. integrated watchdog timer Quadrature Decoder programmed with time-out value alarm when shaft motion detected. Each input filtered ensure only true transitions recorded. This controller also provides full standard programmable peripherals that include Serial Communications Interface (SCI), Serial Peripheral Interface (SPI), four Quad Timers. these interfaces used General Purpose Input/Outputs (GPIO) that function required. Controller Area Network interface (CAN Version A/B-compliant) internal interrupt controller also included 56F803.
State Development Environment
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56F803 Technical Data, Rev. Freescale Semiconductor
Product Documentation
Product Documentation
four documents listed Table required complete description proper design with 56F803. Documentation available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, online www.freescale.com
Table 56F803 Chip Documentation
Topic 56800E Family Manual DSP56F801/803/805/807 User's Manual 56F803 Technical Data Sheet 56F803 Errata Description Detailed description 56800 family architecture, 16-bit core processor instruction Detailed description memory, peripherals, interfaces 56F801, 56F803, 56F803, 56F807 Electrical timing specifications, descriptions, package descriptions (this document) Details chip issues that might present Order Number 56800EFM DSP56F801-7UM DSP56F803 DSP56F803E
Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR This used indicate signal that active when pulled low. example, RESET active when low. high true (active high) signal high true (active low) signal low. high true (active high) signal true (active low) signal high. Signal/Symbol Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
"asserted" "deasserted" Examples:
Values VIL, VOL, VIH, defined individual product specifications.
56F803 Technical Data, Rev. Freescale Semiconductor
Part Signal/Connection Descriptions
Introduction
input output signals 56F803 organized into functional groups, shown Table illustrated Figure 2-1. Table through Table 2-17, each table describes signal signals present pin.
Table Functional Group Allocations
Functional Group Power (VDD VDDA) Ground (VSS VSSA) Supply Capacitors Clock Address Bus1 Data Control Interrupt Program Control Pulse Width Modulator (PWM) Port Serial Peripheral Interface (SPI) Port1 Quadrature Decoder Port2 Serial Communications Interface (SCI) Port1 Port Analog Digital Converter (ADC) Port Quad Timer Module Port JTAG/On-Chip Emulation (OnCE)
Alternately, GPIO pins Alternately, Quad Timer pins
Number Pins
Detailed Description Table Table Table Table Table Table Table Table Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17
56F803 Technical Data, Rev. Freescale Semiconductor
Introduction
Power Port Ground Port Power Port Ground Port
VDDA VSSA
PWMA0-5 ISA0-2 FAULTA0-2 PWMA Port
Other Supply Ports Clock
VCAPC
EXTAL XTAL CLKO
SCLK (GPIOE4) MOSI (GPIOE5) MISO (GPIOE6) (GPIOE7) Port GPIO
56F803
A0-A5 External Address GPIO A6-7 (GPIOE2-E3) A8-15 (GPIOA0-A7)
External Data
D0-D15
TXD0 (GPIOE0) RXD0 (GPIOE1)
SCI0 Port GPIO
External Control
MSCAN_RX MSCAN_TX ANA0-7 VREF ADCA Port
PHASEA0 (TA0) Quadrature Decoder Quad Timer PHASEB0 (TA1) INDEX0 (TA2) HOME0 (TA3)
JTAG/OnCEPort TRST
TD1-2
Quad Timer
IRQA IRQB RESET EXTBOOT Interrupt/ Program Control
*includes which reserved factory tied
Figure 56F803 Signals Identified Functional Group1
Alternate functionality shown parenthesis.
56F803 Technical Data, Rev. Freescale Semiconductor
Power Ground Signals
Table Power Inputs
Pins Signal Name VDDA Signal Description Power-These pins provide power internal structures chip, should attached VDD. Analog Power-This dedicated power analog portion chip should connected noise 3.3V supply.
Table Grounds
Pins Signal Name VSSA Signal Description GND-These pins provide grounding internal structures chip, should attached VSS. Analog Ground-This supplies analog ground. TCS-This Schmitt reserved factory must tied normal use. block diagrams, this considered additional VSS.
Table Supply Capacitors
Pins Signal Name VCAPC Signal Type Supply State During Reset Supply Signal Description VCAPC-Connect each greater bypass capacitor order bypass core logic voltage regulator (required proper chip operation). more information, please refer Section 5.2.
56F803 Technical Data, Rev. Freescale Semiconductor
Clock Phase Locked Loop Signals
Clock Phase Locked Loop Signals
Table Clock
Pins Signal Name EXTAL Signal Type Input State During Reset Input Signal Description External Crystal Oscillator Input-This input should connected 8MHz external crystal ceramic resonator. more information, please refer Section 3.5. Crystal Oscillator Output-This output should connected 8MHz external crystal ceramic resonator. more information, please refer Section 3.5. This also connected external clock source. more information, please refer Section 3.5.3. CLKO Output Chip-driven Clock Output-This outputs buffered clock signal. programming CLKOSEL[4:0] bits CLKO Select Register (CLKOSR), user select between outputting version signal applied XTAL version device's master clock output PLL. clock frequency this also disabled programming CLKOSEL[4:0] bits CLKOSR.
XTAL
Input/ Output
Chip-driven
Address, Data, Control Signals
Table Address Signals
Pins Signal Name A0-A5 A6-A7 Signal Type Output Output State During Reset Tri-stated Tri-stated Signal Description Address Bus-A0-A5 specify address external Program Data memory accesses. Address Bus-A6-A7 specify address external Program Data memory accesses. Port GPIO-These pins General Purpose (GPIO) pins that individually programmed input output pins. After reset, default state Address Bus. A8-A15 Output Tri-stated Address Bus-A8-A15 specify address external Program Data memory accesses. Port GPIO-These eight pins General Purpose (GPIO) pins that individually programmed input output pins. After reset, default state Address Bus.
GPIOE2- GPIOE3
Input/O utput
Input
GPIOA0- GPIOA7
Input/O utput
Input
56F803 Technical Data, Rev. Freescale Semiconductor
Table Data Signals
Pins Signal Name D0-D15 Signal Type Input/O utput State During Reset Tri-stated Signal Description Data Bus- D0-D15 specify data external Program Data memory accesses. D0-D15 tri-stated when external inactive. Internal pull-ups active.
Table Control Signals
Pins Signal Name Signal Type Output Output Output State During Reset Tri-stated Tri-stated Tri-stated Signal Description Program Memory Select-PS asserted external Program memory access. Data Memory Select-DS asserted external Data memory access. Write Enable-WR asserted during external memory write cycles. When asserted low, pins D0-D15 become outputs device puts data bus. When deasserted high, external data latched inside external device. When asserted, qualifies A0-A15, pins. connected directly Static RAM. Read Enable-RD asserted during external memory read cycles. When asserted low, pins D0-D15 become inputs external device enabled onto device data bus. When deasserted high, external data latched inside controller. When asserted, qualifies A0-A15, pins. connected directly Static ROM.
Output
Tri-stated
Interrupt Program Control Signals
Table Interrupt Program Control Signals
Pins Signal Name IRQA Signal Type Input (Schmitt) State During Reset Input Signal Description External Interrupt Request A-The IRQA input synchronized external interrupt request indicating external device requesting service. programmed level-sensitive negative-edge- triggered. External Interrupt Request B-The IRQB input external interrupt request indicating external device requesting service. programmed level-sensitive negative-edge-triggered.
IRQB
Input (Schmitt)
Input
56F803 Technical Data, Rev. Freescale Semiconductor
Pulse Width Modulator (PWM) Signals
Table Interrupt Program Control Signals (Continued)
Pins Signal Name RESET Signal Type Input (Schmitt) State During Reset Input Signal Description Reset-This input direct hardware reset processor. When RESET asserted low, controller initialized placed Reset state. Schmitt trigger input used noise immunity. When RESET deasserted, initial chip operating mode latched from EXTBOOT pin. internal reset signal will deasserted synchronous with internal clocks, after fixed number internal clocks. ensure complete hardware reset, RESET TRST should asserted together. only exception occurs debugging environment when hardware device reset required necessary reset OnCE/JTAG module. this case, assert RESET, assert TRST. EXTBOOT Input (Schmitt) Input External Boot-This input tied force device boot from off-chip memory. Otherwise, tied VSS.
Pulse Width Modulator (PWM) Signals
Table 2-10 Pulse Width Modulator (PWMA) Signals
Pins Signal Name PWMA0-5 ISA0-2 Signal Type Output Input (Schmitt) State During Reset Tri-stated Input Signal Description PWMA0-5- These PWMA output pins. ISA0-2- These three input current status pins used top/bottom pulse width correction complementary channel operation PWMA. FAULTA0-2- These three fault input pins used disabling selected PWMA outputs cases where fault conditions originate off-chip.
FAULTA0-2
Input (Schmitt)
Input
56F803 Technical Data, Rev. Freescale Semiconductor
Serial Peripheral Interface (SPI) Signals
Table 2-11 Serial Peripheral Interface (SPI) Signals
Pins Signal Name MISO Signal Type Input/Out State During Reset Input Signal Description Master In/Slave (MISO)-This serial data input master device output from slave device. MISO line slave device placed high impedance state slave device selected. Port GPIO-This General Purpose (GPIO) individually programmed input output pin. After reset, default state MISO. MOSI Input/Out Input Master Out/Slave (MOSI)-This serial data output from master device input slave device. master device places data MOSI line half-cycle before clock edge that slave device uses latch data. Port GPIO-This General Purpose (GPIO) individually programmed input output pin. After reset, default state MOSI. SCLK Input/Out Input Serial Clock-In master mode, this serves output, clocking slaved listeners. slave mode, this serves data clock input. Port GPIO-This General Purpose (GPIO) individually programmed input output pin. After reset, default state SCLK. Input Input Slave Select-In master mode, this used arbitrate multiple masters. slave mode, this used select slave. Port GPIO-This General Purpose (GPIO) individually programmed input output pin. After reset, default state
GPIOE6
Input/Out
Input
GPIOE5
Input/Out
Input
GPIOE4
Input/Out
Input
GPIOE7
Input/Out
Input
56F803 Technical Data, Rev. Freescale Semiconductor
Quadrature Decoder Signals
Quadrature Decoder Signals
Table 2-12 Quadrature Decoder (Quad Dec0) Signals
Pins Signal Name PHASEA0 PHASEB0 INDEX0 HOME0 Signal Type Input Input/Output Input Input/Output Input Input/Output Input Input/Output State During Reset Input Input Input Input Input Input Input Input Signal Description Phase A-Quadrature Decoder PHASEA input TA0-Timer Channel Phase B-Quadrature Decoder PHASEB input TA1-Timer Channel Index-Quadrature Decoder INDEX input TA2-Timer Channel Home-Quadrature Decoder HOME input TA3-Timer Channel
Serial Communications Interface (SCI) Signals
Table 2-13 Serial Communications Interface (SCI0) Signals
Pins Signal Name TXD0 GPIOE0 Signal Type Output Input/Output State During Reset Input Input Signal Description Transmit Data (TXD0)-SCI0 transmit data output Port GPIO-This General Purpose (GPIO) individually programmed input output pin. After reset, default state output. RXD0 GPIOE1 Input Input/Output Input Input Receive Data (RXD0)- SCI0 receive data input Port GPIO-This General Purpose (GPIO) individually programmed input output pin. After reset, default state input.
56F803 Technical Data, Rev. Freescale Semiconductor
2.10 Signals
Table 2-14 Module Signals
Pins Signal Name MSCAN_ MSCAN_ Signal Type Input (Schmitt) Output State During Reset Input Output Signal Description MSCAN Receive Data-This MSCAN input. This internal pull-up resistor. MSCAN Transmit Data-MSCAN output. output open-drain output pull-up resistor needed.
2.11 Analog-to-Digital Converter (ADC) Signals
Table 2-15 Analog Digital Converter Signals
Pins Signal Name ANA0-3 ANA4-7 VREF Signal Type Input Input Input State During Reset Input Input Input Signal Description ANA0-3-Analog inputs channel ANA4-7-Analog inputs channel VREF-Analog reference voltage ADC. Must VDDA-0.3V optimal performance.
2.12 Quad Timer Module Signals
Table 2-16 Quad Timer Module Signals
Pins Signal Name TD1-2 Signal Type Input/Output State During Reset Input Signal Description TD1-2- Timer Channel
56F803 Technical Data, Rev. Freescale Semiconductor
JTAG/OnCE
2.13 JTAG/OnCE
Table 2-17 JTAG/On-Chip Emulation (OnCE) Signals
Pins Signal Name Signal Type State During Reset Signal Description
Input Input, pulled Test Clock Input-This input provides gated clock synchronize (Schmitt) internally test logic shift serial data JTAG/OnCE port. connected internally pull-down resistor. Input (Schmitt) Input, pulled high internally Test Mode Select Input-This input used sequence JTAG controller's state machine. sampled rising edge on-chip pull-up resistor. Note: Always through 2.2K resistor.
Input (Schmitt) Output
Input, pulled high internally Tri-stated
Test Data Input-This input provides serial input data stream JTAG/OnCE port. sampled rising edge on-chip pull-up resistor. Test Data Output-This tri-statable output provides serial output data stream from JTAG/OnCE port. driven Shift-IR Shift-DR controller states, changes falling edge TCK. Test Reset-As input, signal this provides reset signal JTAG controller. ensure complete hardware reset, TRST should asserted power-up whenever RESET asserted. only exception occurs debugging environment when hardware device reset required necessary reset OnCE/JTAG module. this case, assert RESET, assert TRST. Note: normal operation, connect TRST directly VSS. design used debugging environment, TRST tied through resistor.
TRST
Input (Schmitt)
Input, pulled high internally
Output
Output
Debug Event-DE provides pulse recognized debug events.
Part Specifications
General Characteristics
56F803 fabricated high-density CMOS with tolerant TTL-compatible digital inputs. term "5-V tolerant" refers capability pin, built 3.3V-compatible process technology, withstand voltage 5.5V without damaging device. Many systems have mixture devices designed 3.3V power supplies. such systems, carry both 3.3V 5V-compatible voltage levels standard 3.3V designed receive maximum voltage 3.3V during normal operation without causing damage). This 5V-tolerant capability therefore offers power savings 3.3V levels while being able receive levels without being damaged.
56F803 Technical Data, Rev. Freescale Semiconductor
Absolute maximum ratings given Table stress ratings only, functional operation maximum guaranteed. Stress beyond these ratings affect device reliability cause permanent damage device. 56F803 DC/AC electrical specifications preliminary from design simulations. These specifications fully tested guaranteed this early stage product life cycle. Finalized specifications will published after complete characterization device qualifications have been completed.
CAUTION
This device contains protective circuitry guard against damage high static voltage electrical fields. However, normal precautions advised avoid application voltages higher than maximum rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate voltage level.
Table Absolute Maximum Ratings
Characteristic Supply voltage other input voltages, excluding Analog inputs Voltage difference VDDA Voltage difference VSSA Analog inputs ANA0-7 VREF Analog inputs EXTAL XTAL Current drain excluding VDD, VSS, outputs, TCS, VPP, VDDA, VSSA Symbol VSSA- VSSA- 5.5V VDDA+ VSSA+ Unit
Table Recommended Operating Conditions
Characteristic Supply voltage, digital Supply Voltage, analog Voltage difference VDDA Symbol VDDA -0.1 Unit
56F803 Technical Data, Rev. Freescale Semiconductor
General Characteristics
Table Recommended Operating Conditions
Characteristic Voltage difference VSSA reference voltage Ambient operating temperature Symbol VREF -0.1 VDDA Unit
Table Thermal Characteristics6
Value Characteristic
Comments
Symbol 100-pin LQFP
Unit
Notes
Junction ambient Natural convection Junction ambient (@1m/sec) Junction ambient Natural convection Junction ambient (@1m/sec) Junction case Junction center case power dissipation Power dissipation Junction center case Four layer board (2s2p)
RJMA RJMA (2s2p) RJMA PDMAX
41.7
°C/W
37.2 34.2
°C/W °C/W
Four layer board (2s2p)
10.2 User Determined (IDD I/O) /RJA
°C/W °C/W °C/W
Notes:
Theta-JA determined 2s2p test boards frequently lower than would observed application. Determined 2s2p thermal test board. Junction ambient thermal resistance, Theta-JA (RJA) simulated equivalent JEDEC specification JESD51-2 horizontal configuration natural convection. Theta-JA also simulated thermal test board with internal planes (2s2p where number signal layers number planes) JESD51-6 JESD51-7. correct name Theta-JA forced convection with non-single layer boards Theta-JMA. Junction case thermal resistance, Theta-JC (RJC simulated equivalent measured values using cold plate technique with cold plate temperature used "case" temperature. basic cold plate measurement technique described MIL-STD 883D, Method 1012.1. This correct thermal metric calculate thermal performance when package being used with heat sink.
56F803 Technical Data, Rev. Freescale Semiconductor
Thermal Characterization Parameter, Psi-JT "resistance" from junction reference point thermocouple center case defined JESD51-2. useful value estimate junction temperature steady state customer environments.
Junction temperature function on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, flow, power dissipation other components board, board thermal resistance.
Section from more details thermal design considerations. Junction Temperature Ambient Temperature
Electrical Characteristic
Table Electrical Characteristics Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C, 50pF, 80MHz
Characteristic Input high voltage (XTAL/EXTAL) Input voltage (XTAL/EXTAL) Input high voltage (Schmitt trigger inputs)1 Input voltage (Schmitt trigger inputs)1 Input high voltage (all other digital inputs) Input voltage (all other digital inputs) Input current high (pullup/pulldown resistors disabled, VIN=VDD) Input current (pullup/pulldown resistors disabled, VIN=VSS) Input current high (with pullup resistor, VIN=VDD) Input current (with pullup resistor, VIN=VSS) Input current high (with pulldown resistor, VIN=VDD) Input current (with pulldown resistor, VIN=VSS) Nominal pullup pulldown resistor value Output tri-state current Output tri-state current high Symbol VIHC VILC VIHS VILS 2.25 -0.3 -0.3 2.75 Unit
IIHPU IILPU IIHPD IILPD RPU, IOZL IOZH
-210
56F803 Technical Data, Rev. Freescale Semiconductor
Electrical Characteristic
Table Electrical Characteristics (Continued) Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C, 50pF, 80MHz
Characteristic Input current high (analog inputs, VIN=VDDA)2 Input current (analog inputs, VIN=VSSA)2 Output High Voltage IOH) Output Voltage IOL) Output source current Output sink current output source current3 output sink current4 Input capacitance Output capacitance supply current Wait7 Stop Voltage Interrupt, external power supply8 Voltage Interrupt, internal power supply9 Power Reset10
Symbol IIHA IILA IOHP IOLP COUT IDDT5
Unit
VEIO VEIC VPOR
Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, TCS, TCK, TRST, TMS, TDI, MSCAN_RX Analog inputs are: ANA[0:7], XTAL EXTAL. Specification assumes sampling. output source current measured with duty cycle. output sink current measured with duty cycle. IDDT IDDA (Total supply current VDDA) (operating) measured using 8MHz clock source. inputs 0.2V from rail; outputs unloaded. ports configured inputs; measured with modules enabled. Wait measured using external square wave clock source (fosc 8MHz) into XTAL; inputs 0.2V from rail; loads; less than 50pF outputs. 20pF EXTAL; ports configured inputs; EXTAL capacitance linearly affects wait IDD; measured with enabled.
56F803 Technical Data, Rev. Freescale Semiconductor
This low-voltage interrupt monitors VDDA external power supply. VDDA generally connected same potential separate traces. VDDA drops below VEIO, interrupt generated. Functionality device guaranteed under transient conditions when VDDA>VEIO (between minimum specified point when VEIO interrupt generated). This voltage interrupt monitors internally regulated core power supply. output from internal voltage regulator drops below VEIC, interrupt generated. Since core logic supply internally regulated, this interrupt will generated unless external power supply drops below minimum specified value (3.0V). Power-on reset occurs whenever internally regulated 2.5V digital supply drops below 1.5V typical. While power ramping this signal remains active long internal 2.5V below 1.5V typical, matter long ramp-up rate internally regulated voltage typically 100mV less than during ramp-up, until 2.5V reached, which time self-regulates.
Digital Analog Total
(mA)
Freq. (MHz)
Figure Maximum Frequency (see Note Table 3-14)
Electrical Characteristics
Timing waveforms Section tested using levels specified Characteristics table. Figure levels input signal shown.
56F803 Technical Data, Rev. Freescale Semiconductor
Flash Memory Characteristics
Input Signal Midpoint1 Fall Time
Note: midpoint (VIH VIL)/2.
High
Rise Time
Figure Input Signal Measurement References Figure shows definitions following signal states:
Active state, when signal driven, enters impedance state Tri-stated, when signal placed high impedance state Data Valid state, when signal level reached Data Invalid state, when signal level transition between
Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data Active Data3 Valid Data3
Figure Signal States
Flash Memory Characteristics
Table Flash Memory Truth Table
Mode Standby Read Word Program Page Erase Mass Erase PROG5 ERASE6 MAS17 NVSTR8
address enable, rows disabled when address enable, YMUX disabled when Sense amplifier enable Output enable, tri-state Flash data when
56F803 Technical Data, Rev. Freescale Semiconductor
Defines program cycle Defines erase cycle Defines mass erase cycle, erase whole block Defines non-volatile store cycle
Table IFREN Truth Table
Mode Read Word program Page erase Mass erase IFREN Read information block Program information block Erase information block Erase both block IFREN Read main memory block Program main memory block Erase main memory block Erase main memory block
Table Flash Timing Parameters Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF
Characteristic Program time Erase time Mass erase time Endurance1 Data Retention1 Symbol 10,000 20,000 Unit cycles years Figure Figure Figure Figure
Tprog* Terase* Tme*
ECYC DRET
following parameters should only used Manual Word Programming Mode PROG/ERASE NVSTR time
Tnv*
Figure 3-4, Figure 3-5, Figure Figure 3-4, Figure Figure Figure Figure 3-4, Figure 3-5, Figure
NVSTR hold time NVSTR hold time (mass erase) NVSTR program time Recovery time
Tnvh* Tnvh1* Tpgs* Trcv*
56F803 Technical Data, Rev. Freescale Semiconductor
Flash Memory Characteristics
Table Flash Timing Parameters (Continued) Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF
Characteristic Cumulative program period2 Program hold time3 Address/data time3 Address/data hold time3 Symbol Unit Figure Figure
Tpgh Tads Tadh
Figure Figure Figure
cycle equal erase program read. cumulative high voltage programming time same before next erase. same address cannot programmed twice before next erase. Parameters guaranteed design smart programming mode must cycle greater. *The Flash interface unit provides registers control these parameters.
IFREN
XADR
Tadh YADR
Tads PROG Tnvs NVSTR Tpgs Tnvh Trcv Tprog Tpgh
Figure Flash Program Cycle
56F803 Technical Data, Rev. Freescale Semiconductor
IFREN
XADR
YE=SE=OE=MAS1=0
ERASE Tnvs NVSTR Tnvh Terase Trcv
Figure Flash Erase Cycle
IFREN
XADR
MAS1
YE=SE=OE=0
ERASE Tnvs NVSTR Tnvh1 Trcv
Figure Flash Mass Erase Cycle
56F803 Technical Data, Rev. Freescale Semiconductor
External Clock Operation
External Clock Operation
56F803 system clock derived from external crystal external system clock signal. generate reference frequency using internal oscillator, reference crystal must connected between EXTAL XTAL pins.
3.5.1
Crystal Oscillator
internal oscillator also designed interface with parallel-resonant crystal resonator frequency range specified external crystal Table 3-9. Figure recommended crystal oscillator circuit shown. Follow crystal supplier's recommendations when selecting crystal, because crystal parameters determine component values required provide maximum stability reliable start-up. crystal associated components should mounted close possible EXTAL XTAL pins minimize output distortion start-up stabilization time. internal 56F80x oscillator circuitry designed have external load capacitors present. shown Figure external load capacitors should used. 56F80x components internally modeled parallel resonant oscillator circuit provide capacitive load each oscillator pins (XTAL EXTAL) 10pF 13pF over temperature process variations. Using typical value internal capacitance these pins 12pF value typical circuit board trace capacitance parallel load capacitance presented crystal determined following equation:
This value load capacitance that should used when selecting crystal determining actual frequency operation crystal oscillator circuit.
EXTAL XTAL
Recommended External Crystal Parameters: 8MHz (optimized 8MHz)
Figure Connecting Crystal Oscillator
56F803 Technical Data, Rev. Freescale Semiconductor
3.5.2
Ceramic Resonator
also possible drive internal oscillator with ceramic resonator, assuming overall system design tolerate reduced signal integrity. Figure 3-8, typical ceramic resonator circuit shown. Refer supplier's recommendations when selecting ceramic resonator associated components. resonator components should mounted close possible EXTAL XTAL pins. internal 56F80x oscillator circuitry designed have external load capacitors present. shown Figure external load capacitors should used.
EXTAL XTAL
Recommended Ceramic Resonator Parameters: 8MHz (optimized 8MHz)
Figure Connecting Ceramic Resonator
Note: Freescale recommends only terminal ceramic resonators three terminal resonators (which contain internal bypass capacitor ground).
3.5.3
External Clock Source
recommended method connecting external clock given Figure 3-9. external clock source connected XTAL EXTAL grounded.
56F803 XTAL EXTAL External Clock
Figure Connecting External Clock Signal
56F803 Technical Data, Rev. Freescale Semiconductor
External Clock Operation
Table External Clock Operation Timing Requirements3 Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C
Characteristic Frequency operation (external clock driver)1 Clock Pulse Width2, Symbol fosc 6.25 Unit
Figure details using recommended connection external clock driver. high pulse width must smaller than 6.25ns chip will function. However, high pulse width does have particular percent pulse width. Parameters listed guaranteed design.
External Clock
Note: midpoint (VIH VIL)/2.
Figure 3-10 External Clock Timing
56F803 Technical Data, Rev. Freescale Semiconductor
3.5.4
Phase Locked Loop Timing
Table Timing Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C
Characteristic Symbol fosc fout/2 tplls tplls Unit
External reference crystal frequency PLL1 output frequency stabilization time +85oC stabilization time3 -40o
externally supplied reference clock should free possible from phase jitter work correctly. optimized 8MHz input crystal. ZCLK exceed 80MHz. additional information ZCLK fout/2, please refer OCCS chapter User Manual. ZCLK This minimum time required after set-up changed ensure reliable operation.
External Asynchronous Timing
Table 3-10 External Asynchronous Timing1, Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C, 50pF, 80MHz
Characteristic Address Valid Asserted Width Asserted Wait states Wait states Asserted D0-D15 Valid Data Hold Time from Deasserted Data Time Deasserted Wait states Wait states Deasserted Address Valid Address Valid Deasserted Wait states Wait states Symbol tAWR (T*WS) tWRD tDOH tDOS (T*WS) tRDA tARDD 18.7 (T*WS) 18.7 Unit
56F803 Technical Data, Rev. Freescale Semiconductor
External Asynchronous Timing
Table 3-10 External Asynchronous Timing1, (Continued) Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C, 50pF, 80MHz
Characteristic Input Data Hold Deasserted Assertion Width Wait states Wait states Address Valid Input Data Valid Wait states Wait states Address Valid Asserted Asserted Input Data Valid Wait states Wait states Deasserted Asserted Deasserted Asserted Deasserted Asserted Deasserted Asserted Symbol tDRD (T*WS) tARDA tRDD tWRRD tRDRD tWRWR tRDWR 14.1 12.8 (T*WS) -4.4 (T*WS) Unit
56F803 Technical Data, Rev. Freescale Semiconductor
Timing both wait state frequency dependent. formulas listed, number wait states Clock Period. 80MHz operation, 12.5ns. Parameters listed guaranteed design.
calculate required access time external memory frequency 80Mhz, this formula: Clock period desired operating frequency Number wait states Memory Access Time (Top*WS) (Top- 11.5)
A0-A15, (See Note)
tARDA
tARDD tRDA tRDRD
tAWR tWRWR tWRRD
tRDWR
tWRD tDOS tDOH
tRDD tDRD
D0-D15
Data
Data
Note: During read-modify-write instructions internal instructions, address lines change state.
Figure 3-11 External Asynchronous Timing
Reset, Stop, Wait, Mode Select, Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, Interrupt Timing Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF
Characteristic RESET Assertion Address, Data Control Signals High Impedance Minimum RESET Assertion Duration2 RESET De-assertion First External Address Output Symbol tRAZ 275,000T 128T tRDA Figure 3-12 Unit Figure Figure 3-12 Figure 3-12
56F803 Technical Data, Rev. Freescale Semiconductor
Reset, Stop, Wait, Mode Select, Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, Interrupt Timing (Continued)1, Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF
Characteristic Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion External Data Memory Access Valid, caused first instruction execution interrupt service routine IRQA, IRQB Assertion General Purpose Output Valid, caused first instruction execution interrupt service routine IRQA First Valid Interrupt Vector Address recovery from Wait State3 IRQA Width Assertion Recover from Stop State4 Delay from IRQA Assertion Fetch first instruction (exiting Stop) Duration Level Sensitive IRQA Assertion Cause Fetch First IRQA Interrupt Instruction (exiting Stop) Delay from Level Sensitive IRQA Assertion First Interrupt Vector Address Valid (exiting Stop) Symbol tIRW tIDM 1.5T Unit Figure Figure 3-13 Figure 3-14
Figure 3-14
tIRI
Figure 3-15 Figure 3-16 Figure 3-16
tIRQ
275,000T
Figure 3-17
275,000T
Figure 3-17
275,000T
formulas, clock cycle. operating frequency 80MHz, 12.5ns. Circuit stabilization delay required during reset when using external clock crystal oscillator cases: After power-on reset When recovering from Stop state minimum specified duration edge-sensitive IRQA interrupt required recover from Stop state. This minimum required that IRQA interrupt accepted. interrupt instruction fetch visible pins only Mode Parameters listed guaranteed design.
56F803 Technical Data, Rev. Freescale Semiconductor
RESET tRAZ tRDA
A0-A15, D0-D15
First Fetch
First Fetch
Figure 3-12 Asynchronous Reset Timing
IRQA, IRQB
tIRW
Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)
56F803 Technical Data, Rev. Freescale Semiconductor
Reset, Stop, Wait, Mode Select, Interrupt Timing
A0-A15, IRQA, IRQB
First Interrupt Instruction Execution
tIDM
First Interrupt Instruction Execution
General Purpose IRQA, IRQB
General Purpose
Figure 3-14 External Level-Sensitive Interrupt Timing
IRQA, IRQB
tIRI
A0-A15,
First Interrupt Vector Instruction Fetch
Figure 3-15 Interrupt from Wait State Timing
IRQA
A0-A15,
First Instruction Fetch IRQA Interrupt Vector
Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing
56F803 Technical Data, Rev. Freescale Semiconductor
tIRQ
IRQA
A0-A15
First IRQA Interrupt Instruction Fetch
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
Serial Peripheral Interface (SPI) Timing
Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF, 80MHz
Characteristic Cycle time Master Slave Enable lead time Master Slave Enable time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) time Master Slave Data set-up time required inputs Master Slave Data hold time required inputs Master Slave Access time (time data active from high-impedance state) Slave Disable time (hold time high-impedance state) Slave Symbol tELD tELG 17.6 12.5 24.1 15.2 Figure 3-21 Figures 3-18, 3-20, 3-21 Figures 3-18, 3-20, 3-21 Figures 3-18, 3-20, 3-21 Figures 3-18, 3-20, 3-21 Figure 3-21 Figure 3-21 Unit Figure Figures 3-18, 3-20, 3-21 Figure 3-21
Table 3-12 Timing1
56F803 Technical Data, Rev. Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF, 80MHz
Characteristic Data Valid outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave
Parameters listed guaranteed design.
Table 3-12 Timing1
Symbol
20.4 11.5 10.0
Unit
Figure Figures 3-18, 3-20, 3-21 Figures 3-18, 3-20, 3-21 Figures 3-18, 3-20, 3-21 Figures 3-18, 3-20, 3-21
(Input)
held High master
SCLK (CPOL (Output)
SCLK (CPOL (Output)
MISO (Input)
Bits 14-1
tDI(ref)
MOSI (Output)
Master
Bits 14-1
Master
Figure 3-18 Master Timing (CPHA
56F803 Technical Data, Rev. Freescale Semiconductor
(Input)
held High master
SCLK (CPOL (Output)
SCLK (CPOL (Output)
MISO (Input)
tDV(ref)
Bits 14-1
MOSI (Output)
Master
Bits
Master
Figure 3-19 Master Timing (CPHA
56F803 Technical Data, Rev. Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
(Input)
tELG
SCLK (CPOL (Input)
tELD
SCLK (CPOL (Input)
MISO (Output)
Slave
Bits 14-1
Slave
MOSI (Input)
Bits 14-1
Figure 3-20 Slave Timing (CPHA
56F803 Technical Data, Rev. Freescale Semiconductor
(Input)
SCLK (CPOL (Input)
tELD
tELG
SCLK (CPOL (Input)
MISO (Output)
Slave
Bits 14-1
Slave
MOSI (Input)
Bits 14-1
Figure 3-21 Slave Timing (CPHA
Quad Timer Timing
Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF, 80MHz
Characteristic Timer input period Timer input high/low period Timer output period Symbol PINHL POUT 4T+6 2T+3 Unit
Table 3-13 Timer Timing1,
56F803 Technical Data, Rev. Freescale Semiconductor
Quadrature Decoder Timing
Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF, 80MHz
Timer output high/low period
Table 3-13 Timer Timing1,
POUTHL
formulas listed, clock cycle. 80MHz operation, 12.5ns.
Parameters listed guaranteed design.
Timer Inputs
PINHL PINHL
Timer Outputs
POUT POUTHL POUTHL
Figure 3-22 Timer Timing
3.10 Quadrature Decoder Timing
Table 3-14 Quadrature Decoder Timing1,2 Operating Conditions: VSSA VDDA 3.0-3.6V, -40° +85°C, 50pF, 80MHz
Characteristic Quadrature input period Quadrature input high/low period Quadrature phase period Symbol 8T+12 4T+6 2T+3 Unit
formulas listed, clock cycle. 80MHz operation, 3.6V, -40° +85°C, 50pF. Parameters listed guaranteed design.
56F803 Technical Data, Rev. Freescale Semiconductor
Phase (Input)
Phase (Input)
Figure 3-23 Quadrature Decoder Timing
3.11 Serial Communication Interface (SCI) Timing
Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C, 50pF, 80MHz
Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width Symbol RXDPW TXDPW 0.965/BR 0.965/BR (fMAX*2.5)/(80) 1.04/BR 1.04/BR Unit Mbps
Table 3-15 Timing4
fMAX frequency operation system clock MHz. SCI0 named RXD0 SCI1 named RXD1. SCI0 named TXD0 SCI1 named TXD1. Parameters listed guaranteed design.
receive data (Input)
RXDPW
Figure 3-24 Pulse Width
56F803 Technical Data, Rev. Freescale Semiconductor
Analog-to-Digital Converter (ADC) Characteristics
receive data (Input)
TXDPW
Figure 3-25 Pulse Width
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 3-16 Characteristics
Characteristic input voltages Resolution Integral Non-Linearity3 Differential Non-Linearity Monotonicity internal clock5 Conversion range Power-up time Conversion time Sample time Input capacitance Gain Error (transfer gain)5 Offset Voltage5 Total Harmonic Distortion5 Signal-to-Noise plus Distortion5 Effective Number Bits5 Spurious Free Dynamic Range5 Bandwidth fADIC tADPU tADC tADS CADI EGAIN VOFFSET SINAD ENOB SFDR VSSA 0.95 Symbol VADCIN GUARANTEED 1.00 VDDA 1.10 tAIC cycles6 tAIC cycles6 tAIC cycles6 VREF2 Unit Bits LSB4 LSB4
56F803 Technical Data, Rev. Freescale Semiconductor
Table 3-16 Characteristics
Characteristic Quiescent Current (both ADCs) VREF Quiescent Current (both ADCs) Symbol IADC IVREF 16.5 Unit
optimum performance, keep minimum VADCIN value 25mV. Inputs less than 25mV convert digital output code VREF must equal less than VDDA must greater than 2.7V. optimal performance, VREF VDDA-0.3V. Measured 10-90% range. Least Significant Bit. Guaranteed characterization. tAIC 1/fADIC
analog input
Parasitic capacitance package, pin, package base coupling. (1.8pf) Parasitic capacitance chip bond pad, protection devices signal routing. (2.04pf) Equivalent resistance isolation resistor channel select mux. (500 ohms) Sampling capacitor sample hold circuit. (1pf)
Figure 3-26 Equivalent Analog Input Circuit
3.13 Controller Area Network (CAN) Timing
Table 3-17 Timing2
Operating Conditions: VSSA VDDA 3.0-3.6 50pF, MSCAN Clock 30MHz Characteristic Baud Rate Wakeup detection Symbol BRCAN WAKEUP Unit Mbps
56F803 Technical Data, Rev. Freescale Semiconductor
Controller Area Network (CAN) Timing
Wakeup glitch filter enabled during design initialization also into SLEEP mode then, event MSCAN_RX pin) whose duration less than micro seconds filtered away. However, valid wakeup detection takes place wakeup pulse equal greater than microseconds. value microseconds originates from fact that wakeup message consists dominant bits highest possible baud rate 1Mbps. Parameters listed guaranteed design.
MSCAN_RX receive data (Input)
WAKEUP
Figure 3-27 Wakeup Detection
56F803 Technical Data, Rev. Freescale Semiconductor
3.14 JTAG Timing
Operating Conditions: VSSA VDDA 3.0-3.6 -40° +85°C, 50pF, 80MHz
Characteristic frequency operation2 cycle time clock pulse width TMS, data set-up time TMS, data hold time data valid tri-state TRST assertion time assertion time Symbol tTRST 26.6 23.5 Unit
Table 3-18 JTAG Timing1,
Timing both wait state frequency dependent. values listed, clock cycle. 80MHz operation, 12.5ns. frequency operation must less than processor rate. Parameters listed guaranteed design.
(Input) (VIH VIL)/2
Figure 3-28 Test Clock Input Timing Diagram
56F803 Technical Data, Rev. Freescale Semiconductor
JTAG Timing
(Input)
(Input) (Output)
Input Data Valid
Output Data Valid
(Output)
(Output)
Output Data Valid
Figure 3-29 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 3-30 TRST Timing Diagram
Figure 3-31 OnCE-Debug Event
56F803 Technical Data, Rev. Freescale Semiconductor
Part Packaging
Package Pin-Out Information 56F803
This section contains package pin-out information 100-pin LQFP configuration 56F803.
VCAPC SCLK MOSI MISO CLKO RESET EXTBOOT RXD0 TXD0
ORIENTATION MARK
PWMA5 PWMA4 PWMA3 PWMA2 PWMA1 PWMA0 HOME0 INDEX0 PHASEB0 PHASEA0 VDDA VSSA EXTAL XTAL
IRQA IRQB TRST VCAPC ISA0 ISA1 ISA2 FAULTA0 MSCAN_TX FAULTA1 MSCAN_RX FAULTA2 VREF
Figure View, 56F803 100-pin LQFP Package
56F803 Technical Data, Rev. Freescale Semiconductor
Package Pin-Out Information 56F803
Table 56F803 Identification Number
Signal Name Signal Name IRQA IRQB TRST VCAPC ISA0 ISA1 ISA2 FAULTA0 MSCAN_TX FAULTA1 MSCAN_RX FAULTA2 VREF Signal Name XTAL EXTAL VSSA VDDA PHASEA0 PHASEB0 INDEX0 HOME0 PWMA0 PWMA1 PWMA2 PWMA3 PWMA4 PWMA5 Signal Name TXD0 RXD0 EXTBOOT RESET CLKO MISO MOSI SCLK VCAPC
56F803 Technical Data, Rev. Freescale Semiconductor
0.15 (0.006) -TNOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE -AB- LOCATED BOTTOM LEAD COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY BOTTOM PARTING LINE. DATUMS -T-, -U-, DETERMINED DATUM PLANE -AB-. DIMENSIONS DETERMINED SEATING PLANE -AC-. DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.250 (0.010) SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE -AB-. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL CAUSE DIMENSION EXCEED 0.350 (0.014). DAMBAR LOCATED LOWER RADIUS FOOT. MINIMUM SPACE BETWEEN PROTRUSION ADJACENT LEAD 0.070 (0.003). MINIMUM SOLDER PLATE THICKNESS SHALL 0.0076 (0.003). EXACT SHAPE EACH CORNER VARY FROM DEPICTION. MILLIMETERS 13.950 14.050 13.950 14.050 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 0.050 0.150 0.090 0.200 0.500 0.700 0.090 0.160 0.150 0.250 15.950 16.050 15.950 16.050 0.200 1.000 INCHES 0.549 0.553 0.549 0.553 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 0.002 0.006 0.004 0.008 0.020 0.028 0.004 0.006 0.006 0.010 0.628 0.632 0.628 0.632 0.008 0.039
0.15 (0.006)
-AB-AC96X
0.100 (0.004)
(24X SIDE)
SEATING PLANE
0.25 (0.010)
GAUGE PLANE
DETAIL
0.20 (0.008) SECTION AE-AE
0.15 (0.006)
0.15
(0.006)
Figure 100-pin LQPF Mechanical Information
56F803 Technical Data, Rev. Freescale Semiconductor
Thermal Design Considerations
Please www.freescale.com most current case outline.
Part Design Considerations
Thermal Design Considerations
estimation chip junction temperature, obtained from equation:
Equation
Where:
ambient temperature package junction-to-ambient thermal resistance °C/W power dissipation package
Historically, thermal resistance been expressed junction-to-case thermal resistance case-to-ambient thermal resistance:
Equation
Where:
package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W
device-related cannot influenced user. user controls thermal environment change case-to-ambient thermal resistance, RCA. example, user change flow around device, heat sink, change mounting arrangement Printed Circuit Board (PCB), otherwise change thermal dissipation capability area surrounding device PCB. This model most useful ceramic packages with heat sinks; some heat flow dissipated through case heat sink ambient environment. ceramic packages, situations where heat flow split between path case alternate path through PCB, analysis device thermal performance need additional modeling capability system level thermal simulation tool. thermal performance plastic packages more dependent temperature which package mounted. Again, estimations obtained from satisfactorily answer whether thermal performance adequate, system level model appropriate. Definitions: complicating factor existence three common definitions determining junction-to-case thermal resistance plastic packages:
Measure thermal resistance from junction outside surface package (case) closest chip mounting area when that surface proper heat sink. This done minimize temperature variation
56F803 Technical Data, Rev. Freescale Semiconductor
Reach
Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe Locations Listed: Freescale Semiconductor Technical Information Center, CH370 1300 Alma School Road Chandler, Arizona 85224 +1-800-521-6274 +1-480-768-2130 support@freescale.com Europe, Middle East, Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 81829 Muenchen, Germany 1296 (English) 52200080 (English) 92103 (German) (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center King Street Industrial Estate N.T., Hong Kong +800 2666 8080 support.asia@freescale.com Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 5405 Denver, Colorado 80217 1-800-441-2447 303-675-2140 Fax: 303-675-2150
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Freescaleand Freescale logo trademarks Freescale Semiconductor, Inc. other product service names property their respective owners. This product incorporates SuperFlash® technology licensed from SST. Freescale Semiconductor, Inc. 2005. rights reserved. DSP56F803 Rev. 09/2007
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