MC9S12A128 Device Guide V01.01 Original Release Date: March, 2002
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9S12A128DGV1/D 4/2002
MC9S12A128 Device Guide V01.01
Original Release Date: March, 2002 Revised: April, 2002
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
Revision History
Version Revision Effective Number Date Date
V01.00 2002 2002
Author
Initial release
Description Changes
Replaced document order number with version except cover sheet Corrected Table Device Memory entries EEPROM array array V01.01 APRIL 2002 APRIL 2002 Table Operating Conditions Increased 2.35V Table Characteristics Corrected rating column typical value Table Operating Characteristics Updated rating definitions items clarity
additional information, refer MC9S12A128 8-Bit Microcontroller Unit Mask Errata (Motorola document order number, 9S12A128MSE1). errata found World Wide
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Table Contents
Section Introduction
Overview. Features Modes Operation Block Diagram Device Memory Map. Part Assignments.
Section Signal Description
Device Pinout Signal Properties Summary Detailed Signal Descriptions. 2.3.1 EXTAL, XTAL Oscillator Pins 2.3.2 RESET External Reset 2.3.3 TEST Test 2.3.4 VREGEN Voltage Regulator Enable 2.3.5 Loop Filter 2.3.6 BKGD TAGHI MODC Background Debug, High, Mode 2.3.7 PAD15 AN15 ETRIG1 Port Input ATD1 2.3.8 PAD[14:08] AN[14:08] Port Input Pins ATD1 2.3.9 PAD7 AN07 ETRIG0 Port Input ATD0 2.3.10 PAD[06:00] AN[06:00] Port Input Pins ATD0 2.3.11 PA[7:0] ADDR[15:8] DATA[15:8] Port Pins 2.3.12 PB[7:0] ADDR[7:0] DATA[7:0] Port Pins 2.3.13 NOACC XCLKS Port 2.3.14 MODB IPIPE1 Port 2.3.15 MODA IPIPE0 Port 2.3.16 ECLK Port 2.3.17 LSTRB TAGLO Port 2.3.18 Port 2.3.19 Port Input 2.3.20 XIRQ Port Input 2.3.21 KWH7 Port
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56 2.3.57
KWH6 Port KWH5 Port KWH4 Port KWH3 Port KWH2 SCK1 Port KWH1 MOSI1 Port KWH0 MISO1 Port KWJ7 PORT KWJ6 PORT PJ[1:0] KWJ[1:0] Port Pins [1:0] ROMON Port PK[5:0] XADDR[19:14] Port Pins [5:0] Port Port SCK0 Port MOSI0 Port Port MISO0 Port Port Port KWP7 PWM7 Port KWP6 PWM6 Port KWP5 PWM5 Port KWP4 PWM4 Port KWP3 PWM3 Port KWP2 PWM2 SCK1 Port KWP1 PWM1 MOSI1 Port KWP0 PWM0 MISO1 Port Port SCK0 Port MOSI0 Port MISO0 Port TXD1 Port RXD1 Port TXD0 Port RXD0 Port
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
2.3.58 PT[7:0] IOC[7:0] Port Pins [7:0] Power Supply Pins 2.4.1 VDDX, VSSX Power Ground Pins Drivers 2.4.2 VDDR, VSSR Power Ground Pins Drivers Internal Voltage Regulator 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 VDD1, VDD2, VSS1, VSS2 Core Power Pins. VDDA, VSSA Power Supply Pins VREG VRH, Reference Voltage Input Pins VDDPLL, VSSPLL Power Supply Pins VREGEN Chip Voltage Regulator Enable
Section System Clock Description
Overview.
Section Modes Operation
4.2.1 4.2.2 4.2.3 4.3.1 4.3.2 4.3.3 Overview. Modes Operation Normal Operating Modes Special Operating Modes. Test Operating Mode Security. Securing Microcontroller Operation Secured Microcontroller Unsecuring Microcontroller Power Modes
Section Resets Interrupts
Overview. Vectors 5.2.1 Vector Table. Effects Reset 5.3.1 Pins 5.3.2 Memory
Section HCS12 Core Block Description Section Clock Reset Generator (CRG) Block Description
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
Device-Specific Information 7.1.1 XCLKS
Section Enhanced Capture Timer (ECT) Block Description Section Analog Digital Converter (ATD) Block Description Section Inter-IC (IIC) Block Description Section Serial Communications Interface (SCI) Block Description
Section Serial Peripheral Interface (SPI) Block Description Section Pulse Width Modulator (PWM) Block Description Section Flash EEPROM 128K Block Description Section EEPROM Block Description Section Block Description Section Port Integration Module (PIM) Block Description Section Voltage Regulator (VREG) Block Description Appendix Electrical Characteristics
General. A.1.1 Parameter Classification A.1.2 Power Supply A.1.3 Pins A.1.4 Current Injection. A.1.5 Absolute Maximum Ratings A.1.6 Protection Latch-up Immunity A.1.7 Operating Conditions A.1.8 Power Dissipation Thermal Characteristics A.1.9 Characteristics A.1.10 Supply Currents
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
A.2.1 A.2.2 A.2.3 A.3.1 A.3.2 A.5.1 A.5.2 A.5.3 A.6.1 A.6.2 A.7.1 Characteristics Operating Characteristics Factors Influencing accuracy Accuracy NVM, Flash, EEPROM Timing Reliability. Voltage Regulator. Reset, Oscillator PLL. Startup Oscillator Phase Locked Loop Master Mode Slave Mode External Timing General Muxed Timing
Appendix Package Information
General. 112-Pin LQFP Package 80-Pin Package
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
List Figures
Figure Figure Figure Figure Figure Figure Figure 18-1 Figure 18-2 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure MC9S12A128 Block Diagram MC9S12A128 Memory Assignments 112-Pin LQFP Assignments 80-Pin MC9S12A128 Loop Filter Connections Clock Connections. Recommended Layout LQFP. Recommended Layout Accuracy Definitions Basic Functional Diagram Jitter Definitions Maximum Clock Jitter Approximation Master Timing (CPHA Master Timing (CPHA =1). Slave Timing (CPHA Slave Timing (CPHA =1). General External Timing. 112-Pin LQFP Mechanical Dimensions (Case 987) 80-pin Mechanical Dimensions (Case 841B)
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table A-17 Table A-18 Table A-19 Document References Device Memory Assigned Part Numbers Memory Size Registers Signal Properties MC9S12A128 Power Ground Connection Summary Mode Selection Interrupt Vector Locations Absolute Maximum Ratings Latch-up Test Conditions Latch-Up Protection Characteristics. Operating Conditions Thermal Package Characteristics Characteristics Supply Current Characteristics Operating Characteristics Electrical Characteristics Conversion Performance Timing Characteristics Reliability Characteristics. Voltage Regulator Recommended Load Capacitances Startup Characteristics Oscillator Characteristics Characteristics. Master Mode Timing Characteristics. Slave Mode Timing Characteristics Expanded Timing Characteristics
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Preface
Device User Guide provides information about MC9S12A128 device made standard HCS12 blocks HCS12 processor core. This document part customer documentation. complete device manuals also includes CPU12 Reference Manual (Motorola order number, CPU12RM/AD) individual Block Guides implemented modules. effort reduce redundancy module specific information located only respective Block Guide. applicable, special implementation details module given block description sections this document. Table names versions referenced documents throughout Device Guide.
Table Document References
User Guide
HCS12 Core User Guide Block Guide ECT_16B8C Block Guide ATD_10B8C Block Guide Block Guide Block Guide Block Guide PWM_8B8C Block Guide FTS128K Block Guide EETS2K Block Guide VREG Block Guide PIM_9A128 Block Guide
Version
Document Order Number
HCS12COREUG/D S12CRGV3/D S12ECT16B8CV1/D S12ATD10B8CV2/D S12IICV2/D S12SCIV2/D S12SPIV2/D S12PWM8B8CV1/D S12FTS128KV1/D S12EETS2KV1/D S12VREGV1/D S12A128PIMV1/D
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Section Introduction
Overview
MC9S12A128 microcontroller unit (MCU) 16-bit device composed standard on-chip peripherals including 16-bit central processing unit (HCS12 CPU), 128K bytes Flash EEPROM, bytes RAM, bytes EEPROM, asynchronous serial communications interfaces (SCI), serial peripheral interfaces (SPI), 8-channel IC/OC enhanced capture timer, 8-channel, 10-bit analog-to-digital converters (ADC), 8-channel pulse-width modulator (PWM), discrete digital channels (Port Port Port Port discrete digital lines with interrupt wakeup capability Inter-IC Bus. System resource mapping, clock generation, interrupt control interfacing managed System Integration Module (SIM). MC9S12A128 full 16-bit data paths throughout. However, external operate 8-bit narrow mode single 8-bit wide memory interfaced lower cost systems. inclusion circuit allows power consumption performance adjusted suit operational requirements.
Features
HCS12 Core 16-bit HCS12 Upward compatible with M68HC11 instruction Interrupt stacking programmer's model identical M68HC11 iii. Instruction queue Enhanced indexed addressing MEBI (Multiplexed External Interface) (Module Mapping Control) (Interrupt control) (Breakpoints) (Background Debug Mode) (low current oscillator, PLL, reset, clocks, watchdog, real time interrupt, clock monitor) 8-bit 4-bit ports with interrupt functionality Digital filtering Programmable rising falling edge trigger Memory 128K Flash EEPROM byte EEPROM
byte
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
8-channel Analog-to-Digital Converters 10-bit resolution External conversion trigger capability 16-bit main counter with 7-bit prescaler programmable input capture output compare channels 8-bit 16-bit pulse accumulators Programmable period duty cycle 8-bit 8-channel 16-bit 4-channel Separate control each pulse width duty cycle Center-aligned left-aligned outputs Programmable clock select logic with wide range frequencies Fast emergency shutdown input Usable interrupt inputs asynchronous Serial Communications Interfaces (SCI) Synchronous Serial Peripheral Interface (SPI) Compatible with standard Multi-master operation Software programmable different serial clock frequencies lines with input drive capability converter inputs Operation 50MHz equivalent 25MHz Speed Development support Single-wire background debugmode (BDM) On-chip hardware breakpoints
Enhanced Capture Timer
channels
Serial interfaces
Inter-IC (IIC)
112-Pin LQFP 80-pin packages
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Modes Operation
User modes Normal Emulation Operating Modes Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola only) Special Peripheral Mode (Motorola only)
Special Operating Modes
power modes Stop Mode Pseudo Stop Mode Wait Mode
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
Block Diagram
Figure shows block diagram MC9S12A128 device.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Figure MC9S12A128 Block Diagram
128K Byte Flash EEPROM Byte Byte EEPROM
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD VDDPLL VSSPLL EXTAL XTAL RESET TEST
ATD0
VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07
ATD1
VDDA VSSA
VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
Voltage Regulator
PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7
Single-wire Background Debug Module
Clock Reset Generation Module
CPU12
DDRK
PPAGE
Periodic Interrupt Watchdog Clock Monitor Breakpoints
XIRQ System Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS
DDRE
Enhanced Capture Timer
DDRT DDRS
SCI0 SCI1
Multiplexed Address/Data SPI0 DDRA
MISO MOSI
DDRB Module Port Routing
Multiplexed Wide
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI
Internal Logic 2.5V
VDD1,2 VSS1,2
Driver
VDDX VSSX
Multiplexed Narrow
KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DDRP
DDRJ
2.5V
VDDPLL VSSPLL
Converter Voltage Regulator Reference
VDDA VSSA
Voltage Regulator
VDDR VSSR
SPI1
DDRH
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Signals shown Bold available Package
DDRM
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
P
MC9S12A128 Device Guide V01.01
Device Memory
Table Figure show device memory MC9S12A128 after reset. Note that after reset bottom EEPROM ($0000 $03FF) hidden register space. Table Device Memory
Address
$0000 $0017 $0018 $0019
Module
CORE (Ports Modes, Inits, Test) Reserved
Size (Bytes)
2048 8192 16384 16384 16384
$001A $001B Device register (PARTID)
$001C $001F CORE (MEMSIZ, IRQ, HPRIO) $0020 $0027 $0030 $0033 Reserved CORE (PPAGE, Port $0028 $002F CORE (Background Debug Mode) $0034 $003F Clock Reset Generator (PLL, RTI, COP) $0040 $007F Enhanced Capture Timer 16-bit channels $0080 $009F Analog Digital Converter 10-bit channels (ATD0) $00A0 $00C7 Pulse Width Modulator 8-bit channels (PWM) $00C8 $00CF Serial Communications Interface (SCI0) $00D0 $00D7 Serial Communications Interface (SCI1) $00D8 $00DF Serial Peripheral Interface (SPI0) $00E0 $00E7 Inter $00E8 $00EF Reserved $00F0 $00F7 Serial Peripheral Interface (SPI1) $00F8 $00FF Reserved $0100- $010F $0110 $011B Flash Control Register EEPROM Control Register
$011C $011F Reserved $0120 $013F Analog Digital Converter 10-bit channels (ATD1) $0140 $023F Reserved $0240 $027F Port Integration Module (PIM) $0280 $03FF Reserved $0000 $07FF EEPROM array $0000 $1FFF array $4000 $7FFF Fixed Flash EEPROM array incl. 0.5K, Protected Sector start
$8000 $BFFF Flash EEPROM Page Window Fixed Flash EEPROM array $C000 $FFFF incl. 0.5K, Protected Sector bytes Vector Space $FF80 $FFFF
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Figure MC9S12A128 Memory
$0000 $0000 $0400 $0800 $1000 $2000 $03FF $0800 $0FFF $2000 $3FFF $4000 $4000 0.5K, Protected Sector Register Space Mappable Boundary Bytes EEPROM Mappable Boundary Bytes Mappable Boundary
$7FFF $8000 $8000 $BFFF $C000 $C000
Fixed Flash EEPROM
Page Window eight Flash EEPROM Pages
Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
Protected Boot Sector Active)
address does show after reset, useful map. After reset $0000 $03FF: Register Space $0000 $1FFF: $0000 $07FF: EEPROM (not visible) $2000 $3FFF: Flash
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MC9S12A128 Device Guide -Freescale V01.01
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Part Assignments
part located 8-bit registers PARTIDH PARTIDL (addresses $001A $001B after reset). read-only value unique part each revision chip. Table shows assigned part number. Table Assigned Part Numbers
Device MC9S12A128 Mask Number 0L85D Part $0100
NOTES: coding follows: 15-12: Major family identifier 11-8: Minor family identifier 7-4: Major mask revision number including transfers 3-0: Minor full mask revision
device memory sizes located 8-bit registers MEMSIZ0 MEMSIZ1 (addresses $001C $001D after reset). Table shows read-only values these registers. Refer HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) further details.
Table Memory Size Registers
Register name MEMSIZ0 MEMSIZ1 Value
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Section Signal Description
This section describes signals that connect off-chip. includes pinout diagram, table signal properties, detailed discussion signals. built from signal description sections Block Guides individual blocks device.
Device Pinout
MC9S12A128 available 112-pin profile quad flat pack (LQFP) also available 80-pin quad flat pack (QFP). Most pins perform more functions, described Detailed Signal Descriptions. Figure Figure show assignments.
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MC9S12A128 Device Guide -Freescale V01.01
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
PP4/KWP4/PWM4 PP5/KPW5/PWM5 PP6/KWP6/PWM6 PP7/KWP7/PWM7 PK7/ECS VDDX VSSX PM2/MISO0 PM3/SS0 PM4/MOSI PM5/SCK0 PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA
MC9S12A128
VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown Bold available Package
Figure Assignments 112-Pin LQFP
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PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM2/MISO0 PM3/SS0 PM4/MOSI0 PM5/SCK0 PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
MC9S12A128
VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure Assignments 80-Pin MC9S12A128
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
MC9S12A128 Device Guide -Freescale V01.01
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Signal Properties Summary
Table summarizes functionality. Signals shown bold available package. Table Signal Properties
Name Function
EXTAL XTAL RESET TEST VREGEN
Name Function
TAGHI AN15 AN[14:08] AN07 AN[06:00] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC IPIPE1 IPIPE0 ECLK LSTRB XIRQ KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0
Name Function
MODC ETRIG1 ETRIG0 XCLKS MODB MODA TAGLO SCK1 MOSI1 MISO1
Name Function
Powered
VDDPLL VDDR N.A. VDDX VDDPLL VDDR Oscillator Pins
Description
External Reset Test Input Voltage Regulator Enable Input Loop Filter Background Debug, High, Mode Input Port Input, Analog Input ATD1, External Trigger Input ATD1 Port Inputs, Analog Inputs AN[6:0] ATD1 Port Input, Analog Input ATD0, External Trigger Input ATD0 Port Inputs, Analog Inputs AN[6:0] ATD0 Port I/O, Multiplexed Address/Data Port I/O, Multiplexed Address/Data Port I/O, Access, Clock Select Port I/O, Pipe Status, Mode Input Port I/O, Pipe Status, Mode Input Port I/O, Clock Output Port I/O, Byte Strobe, Port I/O, expanded modes
BKGD PAD15 PAD[14:8] PAD07 PAD[06:00] PA[7:0] PB[7:0]
VDDA VDDR
Port Input, Maskable Interrupt Port Input, Maskable Interrupt Port I/O, Interrupt Port I/O, Interrupt Port I/O, Interrupt Port I/O, Interrupt Port I/O, Interrupt, SPI1 Port I/O, Interrupt, SPI1 Port I/O, Interrupt, MOSI SPI1 Port I/O, Interrupt, MISO SPI1
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Name Function
PJ[1:0] PK[5:0]
Name Function
KWJ7 KWJ6 KWJ[1:0] XADDR[19:14] SCK0 MOSI0 MISO0 KWP7 KWP6 KWP5 KWP4 KWP3 KWP2 KWP1 KWP0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0]
Name Function
ROMON
Name Function
Powered
Description
Port I/O, Interrupt, Port I/O, Interrupt,
Port I/O, Interrupts Port I/O, Emulation Chip Select, Enable Port I/O, Extended Addresses Port Port Port I/O, SPI0 Port I/O, MOSI SPI0 Port I/O, SPI0 Port I/O, MISO SPI0 Port Port Port I/O, Interrupt, Channel Port I/O, Interrupt, Channel Port I/O, Interrupt, Channel VDDX Port I/O, Interrupt, Channel Port I/O, Interrupt, Channel PWM, SPI1 Port I/O, Interrupt, Channel PWM, SPI1 Port I/O, Interrupt, Channel PWM, MOSI SPI1 Port I/O, Interrupt, Channel PWM, MISO SPI1 Port I/O, SPI0 Port I/O, SPI0 Port I/O, MOSI SPI0 Port I/O, MISO SPI0 Port I/O, SCI1 Port I/O, SCI1 Port I/O, SCI0 Port I/O, SCI0 Port I/O, Timer channels
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
SCK1 MOSI1 MISO1
PT[7:0]
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MC9S12A128 Device Guide -Freescale V01.01
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Detailed Signal Descriptions
2.3.1 EXTAL, XTAL Oscillator Pins
EXTAL XTAL crystal driver external clock pins. reset device clocks derived from EXTAL input frequency. XTAL crystal output.
2.3.2 RESET External Reset
active bidirectional control signal, acts input initialize known start-up state, output when internal function causes reset.
2.3.3 TEST Test
This input only reserved test. NOTE: TEST must tied applications.
2.3.4 VREGEN Voltage Regulator Enable
This input only enables disables on-chip voltage regulator.
2.3.5 Loop Filter
loop filter, A.5.3 Phase Locked Loop. needed, contact your Motorola representative interactive application note compute loop filter elements. current leakage this must avoided.
VDDPLL VDDPLL
Figure Loop Filter Connections
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2.3.6 BKGD TAGHI MODC Background Debug, High, Mode
BKGD/TAGHI/MODC used pseudo-open-drain background debug communication. expanded modes operation when instruction tagging input this during falling edge E-clock tags high half instruction word being read into instruction queue. used operating mode select during reset. state this latched MODC rising edge RESET.
2.3.7 PAD15 AN15 ETRIG1 Port Input ATD1
PAD15 general purpose input analog input analog digital converter ATD1. external trigger input ATD1.
2.3.8 PAD[14:08] AN[14:08] Port Input Pins ATD1
PAD14 PAD08 general purpose input pins analog inputs AN[6:0] analog digital converter ATD1.
2.3.9 PAD7 AN07 ETRIG0 Port Input ATD0
PAD7 general purpose input analog input analog digital converter ATD0. external trigger input ATD0.
2.3.10 PAD[06:00] AN[06:00] Port Input Pins ATD0
PAD06 PAD00 general purpose input pins analog inputs AN[6:0] analog digital converter ATD0.
2.3.11 PA[7:0] ADDR[15:8] DATA[15:8] Port Pins
PA7-PA0 general purpose input output pins. expanded modes operation, these pins used multiplexed external address data bus.
2.3.12 PB[7:0] ADDR[7:0] DATA[7:0] Port Pins
PB7-PB0 general purpose input output pins. expanded modes operation, these pins used multiplexed external address data bus.
2.3.13 NOACC XCLKS Port
general purpose input output pin. During expanded modes operation, NOACC signal, when enabled, used indicate that current cycle unused "free" cycle. This signal will assert when using bus.
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XCLKS input selects between external clock oscillator configuration. state this latched rising edge RESET. input logic EXTAL configured external clock drive. input logic high oscillator circuit configured EXTAL XTAL. Since this input with pull-up device, left floating, default configuration oscillator circuit EXTAL XTAL.
2.3.14 MODB IPIPE1 Port
general purpose input output pin. used operating mode select during reset. state this latched MODB rising edge RESET. This shared with instruction queue tracking signal IPIPE1. This input with pull-down device which only active when RESET low.
2.3.15 MODA IPIPE0 Port
general purpose input output pin. used operating mode select during reset. state this latched MODA rising edge RESET. This shared with instruction queue tracking signal IPIPE0. This input with pull-down device which only active when RESET low.
2.3.16 ECLK Port
general purpose input output pin. configured drive internal clock ECLK. ECLK used timing reference.
2.3.17 LSTRB TAGLO Port
general purpose input output pin. expanded modes operation, LSTRB used low-byte strobe function indicate type access when instruction tagging TAGLO used half instruction word being read into instruction queue.
2.3.18 Port
general purpose input output pin. expanded modes operations, this drives read/write output signal external bus. indicates direction data external bus.
2.3.19 Port Input
general purpose input maskable interrupt request input that provides means applying asynchronous interrupt requests. This will wake from STOP WAIT mode.
2.3.20 XIRQ Port Input
general purpose input non-maskable interrupt request input that provides means applying asynchronous interrupt requests. This will wake from STOP WAIT mode.
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2.3.21 KWH7 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode.
2.3.22 KWH6 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode.
2.3.23 KWH5 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode.
2.3.24 KWH4 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode.
2.3.25 KWH3 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured slave select Serial Peripheral Interface (SPI1).
2.3.26 KWH2 SCK1 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured serial clock Serial Peripheral Interface (SPI1).
2.3.27 KWH1 MOSI1 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured master output (during master mode) slave input (during slave mode) MOSI Serial Peripheral Interface (SPI1).
2.3.28 KWH0 MISO1 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured master input (during master mode) slave output (during slave mode) MISO Serial Peripheral Interface (SPI1).
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2.3.29 KWJ7 PORT
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured serial clock module.
2.3.30 KWJ6 PORT
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured serial data module.
2.3.31 PJ[1:0] KWJ[1:0] Port Pins [1:0]
general purpose input output pins. They configured generate interrupt causing exit STOP WAIT mode.
2.3.32 ROMON Port
general purpose input output pin. During expanded modes operation, this used emulation chip select output (ECS). During normal expanded modes operation, this used enable Flash EEPROM memory memory (ROMON). rising edge RESET, state this latched ROMON bit.
2.3.33 PK[5:0] XADDR[19:14] Port Pins [5:0]
PK5-PK0 general purpose input output pins. expanded modes operation, these pins provide expanded address XADDR[19:14] external bus.
2.3.34 Port
general purpose input output pin.
2.3.35 Port
general purpose input output pin.
2.3.36 SCK0 Port
general purpose input output pin. configured serial clock Serial Peripheral Interface (SPI0).
2.3.37 MOSI0 Port
general purpose input output pin. configured master output (during master mode) slave input (during slave mode) MOSI Serial Peripheral Interface (SPI0).
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2.3.38 Port
general purpose input output pin. configured slave select Serial Peripheral Interface (SPI0).
2.3.39 MISO0 Port
general purpose input output pin. configured master input (during master mode) slave output (during slave mode) MISO Serial Peripheral Interface (SPI0).
2.3.40 Port
general purpose input output pin.
2.3.41 Port
general purpose input output pin.
2.3.42 KWP7 PWM7 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output.
2.3.43 KWP6 PWM6 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output.
2.3.44 KWP5 PWM5 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output.
2.3.45 KWP4 PWM4 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output
2.3.46 KWP3 PWM3 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output. configured slave select Serial Peripheral Interface (SPI1).
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2.3.47 KWP2 PWM2 SCK1 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output. configured serial clock Serial Peripheral Interface (SPI1).
2.3.48 KWP1 PWM1 MOSI1 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output. configured master output (during master mode) slave input (during slave mode) MOSI Serial Peripheral Interface (SPI1).
2.3.49 KWP0 PWM0 MISO1 Port
general purpose input output pin. configured generate interrupt causing exit STOP WAIT mode. configured Pulse Width Modulator (PWM) channel output. configured master input (during master mode) slave output (during slave mode) MISO Serial Peripheral Interface (SPI1).
2.3.50 Port
general purpose input output pin. configured slave select Serial Peripheral Interface (SPI0).
2.3.51 SCK0 Port
general purpose input output pin. configured serial clock Serial Peripheral Interface (SPI0).
2.3.52 MOSI0 Port
general purpose input output pin. configured master output (during master mode) slave input (during slave mode) MOSI Serial Peripheral Interface (SPI0).
2.3.53 MISO0 Port
general purpose input output pin. configured master input (during master mode) slave output (during slave mode) MOSI Serial Peripheral Interface (SPI0).
2.3.54 TXD1 Port
general purpose input output pin. configured transmit Serial Communication Interface (SCI1).
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2.3.55 RXD1 Port
general purpose input output pin. configured receive Serial Communication Interface (SCI1).
2.3.56 TXD0 Port
general purpose input output pin. configured transmit Serial Communication Interface (SCI0).
2.3.57 RXD0 Port
general purpose input output pin. configured receive Serial Communication Interface (SCI0).
2.3.58 PT[7:0] IOC[7:0] Port Pins [7:0]
PT7-PT0 general purpose input output pins. They configured input capture output compare pins IOC7-IOC0 Enhanced Capture Timer (ECT).
Power Supply Pins
MC9S12A128 power ground pins described below. NOTE: pins must connected together application.
2.4.1 VDDX, VSSX Power Ground Pins Drivers
External power ground drivers. Because fast signal transitions place high, short-duration current demands power supply, bypass capacitors with high-frequency characteristics place them close possible. Bypass requirements depend heavily pins loaded.
2.4.2 VDDR, VSSR Power Ground Pins Drivers Internal Voltage Regulator
External power ground drivers input internal voltage regulator. Because fast signal transitions place high, short-duration current demands power supply, bypass capacitors with high-frequency characteristics place them close possible. Bypass requirements depend heavily pins loaded.
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2.4.3 VDD1, VDD2, VSS1, VSS2 Core Power Pins
Power supplied through VSS. Because fast signal transitions place high, short-duration current demands power supply, bypass capacitors with high-frequency characteristics place them close possible. This 2.5V supply derived from internal voltage regulator. There static load those pins allowed. internal voltage regulator turned off, VREGEN tied ground. NOTE: load allowed except bypass capacitors.
2.4.4 VDDA, VSSA Power Supply Pins VREG
VDDA, VSSA power supply ground input pins voltage regulator analog digital converter. also provides reference internal voltage regulator. This allows supply voltage reference voltage bypassed independently.
2.4.5 VRH, Reference Voltage Input Pins
reference voltage input pins analog digital converter.
2.4.6 VDDPLL, VSSPLL Power Supply Pins
Provides operating voltage ground Oscillator Phased-Locked Loop. This allows supply voltage Oscillator bypassed independently. This 2.5V voltage generated internal voltage regulator. NOTE: load allowed except bypass capacitors.
2.4.7 VREGEN Chip Voltage Regulator Enable
Enables internal 2.5V voltage regulator. this tied low, VDD1,2 VDDPLL must supplied externally.
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Table MC9S12A128 Power Ground Connection Summary
Mnemonic VDD1, VSS1, VDDR VSSR VDDX VSSX VDDA VSSA Number 112-pin Nominal Voltage Description Internal power ground generated internal regulator External power ground, supply drivers internal voltage regulator. External power ground, supply drivers. Operating voltage ground analog-to-digital converters reference internal voltage regulator, allows supply voltage bypassed independently. Reference voltages analog-to-digital converter. Provides operating voltage ground Phased-Locked Loop. This allows supply voltage bypassed independently. Internal power ground generated internal regulator. Internal Voltage Regulator enable/disable
VDDPLL VSSPLL VREGEN
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Section System Clock Description
Overview
Clock Reset Generator provides internal clock signals core peripheral modules. Figure shows clock connections from modules. Consult HCS12 Clock Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D) details clock generation.
S12_CORE core clock
Flash EEPROM EXTAL ATD0, clock oscillator clock XTAL SCI0, SCI1 SPI0,
Figure Clock Connections
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Section Modes Operation
Overview
Eight possible modes determine operating configuration MC9S12A128. Each mode associated default memory external configuration. Three power modes exist device.
Modes Operation
operating mode reset determined states MODC, MODB, MODA pins during reset (Table 4-1). MODC, MODB, MODA bits MODE register show current operating mode provide limited mode switching during operation. states MODC, MODB, MODA pins latched into these bits rising edge reset signal. Table Mode Selection
MODC
MODB
MODA
Mode Description
Special Single Chip, allowed ACTIVE. allowed other modes serial command required make active. Emulation Expanded Narrow, allowed Special Test (Expanded Wide), allowed Emulation Expanded Wide, allowed Normal Single Chip, allowed Normal Expanded Narrow, allowed Peripheral; allowed operations would cause conflicts (must used) Normal Expanded Wide, allowed
There basic types operating modes: Normal modes: Some registers bits protected against accidental changes. Special modes: Allow greater access protected control registers bits special purposes such testing. system development debug feature, background debug mode (BDM), available modes. special single-chip mode, active immediately after reset. Some aspects Port mode dependent. Port general purpose input interrupt input. enabled bits CPU's condition codes register inhibited reset this initially configured simple input with pull-up. Port general purpose input XIRQ interrupt input. XIRQ enabled bits CPU's condition codes register inhibited reset this initially configured simple input with pull-up. ESTR EBICTL register reset user mode. This assures that reset vector fetched
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even located external slow memory device. PE6/MODB/IPIPE1 PE5/MODA/IPIPE0 pins high-impedance mode select inputs during reset. following paragraphs discuss default setup describe which aspects changed after reset mode basis.
4.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debug available three modes, must first enabled some operations means background command, then activated. 4.2.1.1 Normal Single-Chip Mode
There external expansion this mode. pins Ports configured general purpose pins Port bits available general purpose input only pins with internal pull-ups enabled. other pins Port bidirectional pins that initially configured high-impedance inputs with internal pull-ups enabled. Ports configured high-impedance inputs with their internal pull-ups disabled. pins associated with Port bits cannot configured their alternate functions IPIPE1, IPIPE0, LSTRB, while single chip modes. single chip modes, associated control bits PIPOE, LSTRE, RDWE reset zero. Writing opposite state into them single chip mode does change operation associated Port pins. normal single chip mode, MODE register writable time. This allows user program change mode narrow wide expanded mode and/or turn visibility internal accesses. Port configured free-running clock output clearing NECLK=0. Typically only clock output while single chip modes would constant speed clock external application system. 4.2.1.2 Normal Expanded Wide Mode expanded wide modes, Ports configured 16-bit multiplexed address data Port configured clock output signal. These signals allow external memory peripheral devices interfaced MCU. Port pins other than PE4/ECLK configured general purpose pins (initially high-impedance inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, RDWE PEAR register used configure Port pins control outputs instead general purpose pins. possible enable pipe status signals Port bits setting PIPOE PEAR, would unusual this mode. Development systems where pipe status signals monitored would typically special variation this mode. Port reconfigured control signal writing RDWE PEAR. expanded system includes external devices that written, such RAM, RDWE
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would need before attempt write external location. there writable resources external system, left general purpose pin. Port reconfigured LSTRB control signal writing LSTRE PEAR. default condition this general purpose input because LSTRB function needed expanded wide applications. Port initially configured ECLK output with stretch. clock output function depends upon settings NECLK PEAR register, IVIS MODE register ESTR EBICTL register. clock available external select decode logic constant speed clock external application system. 4.2.1.3 Normal Expanded Narrow Mode
This mode used lower cost production systems that 8-bit wide external EPROMs RAMs. Such systems take extra cycles access 16-bit locations this preferred over extra cost additional external memory devices. Ports configured 16-bit address Port multiplexed with data. Internal visibility available this mode because internal cycles would need split into 8-bit cycles. Since PEAR register only written time this mode, care bits desired states during single allowed write. PE3/LSTRB always general purpose normal expanded narrow mode. Although possible write LSTRE PEAR this mode, state LSTRE overridden Port cannot reconfigured LSTRB output. possible enable pipe status signals Port bits setting PIPOE PEAR, would unusual this mode. LSTRB would also needed fully understand system activity. Development systems where pipe status signals monitored would typically special expanded wide mode occasionally special expanded narrow mode. PE4/ECLK initially configured ECLK output with stretch. clock output function depends upon settings NECLK PEAR register, IVIS MODE register ESTR EBICTL register. normal expanded narrow mode, clock available external select decode logic constant speed clock external application system. PE2/R/W initially configured general purpose input with pull-up this reconfigured control signal writing RDWE PEAR. expanded narrow system includes external devices that written such RAM, RDWE would need before attempt write external location. there writable resources external system, left general purpose pin. 4.2.1.4 Internal Visibility Internal visibility available when operating expanded wide modes emulation narrow mode. available single-chip, peripheral normal expanded narrow modes. Internal visibility enabled setting IVIS MODE register.
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internal access made while R/W, LSTRB configured control outputs internal visibility (IVIS=0), will remain cycle, will remain high, address, data LSTRB pins will remain their previous state. When internal visibility enabled (IVIS=1), certain internal cycles will blocked from going external. During cycles when selected, will remain high, data will maintain previous state, address LSTRB pins will updated with internal value. During access cycles when driving, will remain high, address, data LSTRB pins will remain their previous state. 4.2.1.5 Emulation Expanded Wide Mode expanded wide modes, Ports configured 16-bit multiplexed address data Port provides control status signals. These signals allow external memory peripheral devices interfaced MCU. These signals also used logic analyzer monitor progress application programs. control related pins Port (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, PE2/R/W) configured serve their control output functions rather than general purpose I/O. Notice that writes control enable bits PEAR register emulation mode restricted. 4.2.1.6 Emulation Expanded Narrow Mode Expanded narrow modes intended allow connection single 8-bit external memory devices lower cost systems that need performance full 16-bit external data bus. Accesses internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will accessed with 16-bit data Ports Accesses 16-bit external words addresses which normally mapped external will broken into separate 8-bit accesses using Port 8-bit data bus. Internal operations continue full 16-bit data paths. They only visible externally 16-bit information IVIS=1. Ports configured multiplexed address data output ports. During external accesses, address A15, data associated with PA7, address associated with data associated with PA0. During internal visible accesses accesses internal resources that have been mapped external, address data associated with address data associated with PB0. control related pins Port (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, PE2/R/W) configured serve their control output functions rather than general purpose I/O. Notice that writes control enable bits PEAR register emulation mode restricted. main difference between special modes normal modes that some control system control signals cannot written emulation modes.
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4.2.2 Special Operating Modes
There special operating modes that correspond normal operating modes. These operating modes commonly used factory testing system development. 4.2.2.1 Special Single-Chip Mode When reset this mode, background debug mode enabled active. does fetch reset vector execute application code would other modes. Instead active background mode control execution firmware waiting additional serial commands through BKGD pin. When serial command instructs return normal execution, system will configured described below unless reset states internal control registers have been changed through background commands after reset.
There external expansion after reset this mode. Ports initially simple bidirectional pins that configured high-impedance inputs with internal pull-ups disabled; however, writing mode select bits MODE register (which allowed special modes) change this after reset. Port pins (except PE4/ECLK) initially configured general purpose high-impedance inputs with pull-ups enabled. PE4/ECLK configured clock output this mode. pins associated with Port bits cannot configured their alternate functions IPIPE1, IPIPE0, LSTRB, while single chip modes. single chip modes, associated control bits PIPOE, LSTRE RDWE reset zero. Writing opposite value into these bits single chip mode does change operation associated Port pins. Port configured free-running clock output clearing NECLK=0. Typically only clock output while single chip modes would constant speed clock external application system. 4.2.2.2 Special Test Mode expanded wide modes, Ports configured 16-bit multiplexed address data Port provides control status signals. special test mode, write protection many control bits lifted that they thoroughly tested without needing through reset.
4.2.3 Test Operating Mode
There test operating mode which external master, such I.C. tester, control on-chip peripherals. 4.2.3.1 Peripheral Mode This mode intended Motorola factory testing MCU. this mode, inactive external (tester) master drives address, data control signals through Ports effect, whole acts peripheral under control external CPU. This allows faster testing on-chip memory peripherals than previous testing methods. Since mode control register accessible peripheral mode, only change another mode reset into different mode. Background debugging should used while special peripheral mode
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internal conflicts between external master cause improper operation both functions.
Security
device will make available security feature preventing unauthorized read write memory contents. This feature allows: Protection contents FLASH, Protection contents EEPROM, Operation single-chip mode, Operation from external memory with internal FLASH EEPROM disabled.
user must reminded that part security must with user's code. extreme example would user's code that dumps contents internal program. This code would defeat purpose security. same time user also wish back door user's program. example this user downloads through which allows access programming routine that updates parameters stored EEPROM.
4.3.1 Securing Microcontroller
Once user programmed FLASH EEPROM desired), part secured programming security bits located FLASH module. These non-volatile bits will keep part secured through resetting part through powering down part. security byte resides portion Flash array. Check HCS12 128K Flash Block Guide (Motorola document order number, S12FTS128KV1/D) more details security configuration.
4.3.2 Operation Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will most common usage secured part. Everything will appear same part secured with exception operation. operation will blocked. 4.3.2.2 Executing from External Memory user wish execute from external space with secured microcontroller. This accomplished resetting directly into expanded mode. internal FLASH EEPROM will disabled. operations will blocked.
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4.3.3 Unsecuring Microcontroller
order unsecure microcontroller, internal FLASH EEPROM must erased. This done through external program expanded mode. Once user erased FLASH EEPROM, part reset into special single chip mode. This invokes program that verifies erasure internal FLASH EEPROM. Once this program completes, user erase program FLASH security bits unsecured state. This generally done through BDM, user could also change expanded mode writing mode bits through BDM) jumping external program (again through commands). Note that part goes through reset before security bits reprogrammed unsecure state, part will secured again.
Power Modes
Consult respective Block Guide information module behavior Stop, Pseudo Stop, Wait Mode.
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Section Resets Interrupts
Overview
Consult Exception Processing section HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) information resets interrupts.
Vectors
5.2.1 Vector Table
Table lists interrupt sources vectors default order priority. Table Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB
Interrupt Source
Reset Clock Monitor fail reset failure reset Unimplemented instruction trap XIRQ Real Time Interrupt Enhanced Capture Timer channel Enhanced Capture Timer channel Enhanced Capture Timer channel Enhanced Capture Timer channel Enhanced Capture Timer channel Enhanced Capture Timer channel Enhanced Capture Timer channel Enhanced Capture Timer channel Enhanced Capture Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD0 ATD1 Port Port Modulus Down Counter underflow
Mask
None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
Local Enable
None PLLCTL (CME, SCME) rate select None None None IRQCR (IRQEN) CRGINT (RTIE) (C0I) (C1I) (C2I) (C3I) (C4I) (C5I) (C6I) (C7I) TSRC2 (TOF) PACTL (PAOVI) PACTL (PAI) SP0CR1 (SPIE, SPTIE) SC0CR2 (TIE, TCIE, RIE, ILIE) SC1CR2 (TIE, TCIE, RIE, ILIE) ATD0CTL2 (ASCIE) ATD1CTL2 (ASCIE) PTJIF (PTJIE) PTHIF(PTHIE) MCCTL(MCZI)
HPRIO Value Elevate
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$FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FF90 $FFB7 $FF8E, $FF8F $FF8C, $FF8D $FF80 $FF8B Port Interrupt EEPROM FLASH SPI1
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I-Bit I-Bit I-Bit Reserved I-Bit I-Bit Reserved I-Bit I-Bit Reserved I-Bit I-Bit Reserved PTPIF (PTPIE) PWMSDN (PWMIE) EECTL(CCIE, CBEIE) FCTL(CCIE, CBEIE) IBCR (IBIE) SP1CR1 (SPIE, SPTIE) PBCTL(PBOVI) CRGINT(LOCKIE) CRGINT (SCMIE)
Pulse Accumulator Overflow lock Self Clock Mode
Emergency Shutdown
Effects Reset
When reset occurs, registers control bits changed known start-up states. Refer respective module Block User Guides register reset states.
5.3.1 Pins
Refer HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) mode dependent configuration port reset. Refer MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order number, S12A128PIMV1/D) reset configurations peripheral module ports. NOTE: devices assembled 80-pin packages non-bonded pins should configured outputs after reset order avoid current drawn from floating inputs. Refer Table Signal Properties affected pins.
5.3.2 Memory
Refer Table Device Memory locations memories depending operating mode after reset. array automatically initialized reset.
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Section HCS12 Core Block Description
Consult HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) information about HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external interface (MEBI), breakpoint module (BKP) background debug mode module (BDM).
Section Clock Reset Generator (CRG) Block Description
Consult HCS12 Clock Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D) information about Clock Reset Generator module.
Device-Specific Information
7.1.1 XCLKS
XCLKS input signal active (see 2.3.13 NOACC XCLKS Port Refer Figure 2-3. Pierce Oscillator Connections (XCLKS=1) HCS12 Clock Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D).
Section Enhanced Capture Timer (ECT) Block Description
Consult HCS12 16-Bit, 8-Channel Enhanced Capture Timer (ECT) Block Guide (Motorola document order number, S12ECT16B8CV1/D) information about Enhanced Capture Timer module.
Section Analog Digital Converter (ATD) Block Description
There Analog Digital Converters (ATD1 ATD0) implemented MC9S12A128. Consult HCS12 10-Bit, 8-Channel Analog-to-Digital Converter (ATD) Block Guide (Motorola document order number, S12ATD10B8CV2/D) information about each Analog Digital Converter module.
Section Inter-IC (IIC) Block Description
Consult HCS12 Inter-Integrated Circuit (IIC) Block Guide (Motorola document order number, S12IICV2/D) information about Inter-IC module.
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Section Serial Communications Interface (SCI) Block Description
There Serial Communications Interfaces (SCI1 SCI0) implemented MC9S12A128 device. Consult HCS12 Serial Communications Interface (SCI) Block Guide (Motorola document order number, S12SCIV2/D) information about each Serial Communications Interface module.
Section Serial Peripheral Interface (SPI) Block Description
There Serial Peripheral Interfaces (SPI1 SPI0) implemented MC9S12A128. Consult HCS12 Serial Peripheral Interface (SPI) Block Guide (Motorola document order number, S12SPIV2/D) information about each Serial Peripheral Interface module.
Section Pulse Width Modulator (PWM) Block Description
Consult HCS12 8-Bit, 8-Channel Pulse Width Modulator (PWM) Block Guide (Motorola document order number, S12PWM8B8CV1/D) information about Pulse Width Modulator module.
Section Flash EEPROM 128K Block Description
Consult HCS12 128K FLASH Block Guide (Motorola document order number, S12FTS128KV1/D) information about flash module.
Section EEPROM Block Description
Consult HCS12 EEPROM Block Guide (Motorola document order number, S12EETS2KV1/D) information about EEPROM module.
Section Block Description
This module supports single-cycle misaligned word accesses.
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Section Port Integration Module (PIM) Block Description
Consult MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order number, S12A128PIMV1/D) information about Port Integration Module.
Section Voltage Regulator (VREG) Block Description
Consult HCS12 Voltage Regulator Block Guide (Motorola document order number, S12VREGV1/D) information about dual output linear voltage regulator.
Component
Purpose VDD1 filter VDD2 filter VDDA filter VDDR filter VDDPLL filter VDDX filter load load loop filter loop filter
Type ceramic ceramic ceramic X7R/tantalum ceramic X7R/tantalum
Value 220nF 220nF 100nF >=100nF 100nF >=100nF
A.5.3 Phase Locked Loop cutoff loop filter Quartz
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must carefully laid ensure proper operation voltage regulator well itself. following rules must observed: Every supply pair must decoupled ceramic capacitor connected near possible corresponding pins C6). Central point ground star should VSSR pin. ohmic inductance connections between VSS1, VSS2 VSSR. VSSPLL must directly connected VSSR. Keep traces VSSPLL, EXTAL XTAL short possible occupied board area small possible. place other signals supplies underneath area occupied connection area MCU. Central power input should VDDA/VSSA pins.
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Figure 18-1 Recommended Layout LQFP
VREGEN
VDDX
VSSX
VSSA
VDDA
VDD1 VSS1 VSS2 VDD2
VSSR
VDDR
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Figure 18-2 Recommended Layout
VDDX
VREGEN
VSSX
VSSA
VDDA
VDD1
VSS2 VSS1 VDD2
VSSR
VDDR
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VSSPLL VDDPLL
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Appendix Electrical Characteristics
General
NOTE: electrical characteristics given this section preliminary should used guide only. Values cannot guaranteed Motorola subject change without notice.
This supplement contains most accurate electrical information MC9S12A128 microcontroller available time publication. information should considered PRELIMINARY subject change.
This introduction intended give overview several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
electrical parameters shown this supplement guaranteed various methods. give customer better understanding following classification used parameters tagged accordingly tables where appropriate. NOTE: Those parameters guaranteed during production testing each individual device. Those parameters achieved design characterization measuring statistically relevant sample size across process variations. Those parameters achieved design characterization small sample size from typical devices under typical conditions unless otherwise noted. values shown typical column within this category. Those parameters derived mainly from simulations. This classification shown column labeled parameter tables where appropriate.
A.1.2 Power Supply
MC9S12A128 utilizes several pins supply power ports, converter, oscillator well digital core. VDDA, VSSA pair supplies converter resistor ladder internal voltage regulator.
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VDDX, VSSX, VDDR VSSR pairs supply pins, VDDR supplies also internal voltage regulator. VDD1, VSS1, VDD2 VSS2 supply pins digital logic, VDDPLL, VSSPLL supply oscillator PLL. VSS1 VSS2 internally connected metal. VDDA, VDDX, VDDR well VSSA, VSSX, VSSR connected anti-parallel diodes protection. NOTE: following context VDD5 used either VDDA, VDDR VDDX; VSS5 used either VSSA, VSSR VSSX unless otherwise noted. IDD5 denotes currents flowing into VDDA, VDDX VDDR pins. used VDD1, VDD2 VDDPLL, used VSS1, VSS2 VSSPLL. used currents flowing into VDD1 VDD2.
A.1.3 Pins
There four groups functional pins. A.1.3.1 pins Those pins have nominal level This class pins comprised port pins, analog inputs, BKGD RESET pins.The internal structure those pins identical, however some functionality disabled. E.g. analog inputs output drivers, pull-up pull-down resistors disabled permanently. A.1.3.2 Analog Reference This group made pins. A.1.3.3 Oscillator pins XFC, EXTAL, XTAL dedicated oscillator have nominal 2.5V level. They supplied VDDPLL. A.1.3.4 TEST This used production testing only. A.1.3.5 VREGEN This used enable chip voltage regulator.
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A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 range during instantaneous operating maximum current conditions. positive injection current (Vin VDD5) greater than IDD5, injection current flow VDD5 could result external power supply going regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will greatest risk when consuming power; e.g. system clock present, clock rate very which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings stress ratings only. functional operation under outside those maxima guaranteed. Stress beyond those limits affect reliability cause permanent damage device. This device contains circuitry protecting against damage high static voltage electrical fields; however, advised that normal precautions taken avoid application voltages higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either VSS5 VDD5). Table Absolute Maximum Ratings(1)
Rating
I/O, Regulator Analog Supply Voltage Digital Logic Supply Voltage Supply Voltage
Symbol
VDD5 VDDPLL VDDX VSSX VRH, VILV VTEST
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.25
10.0
Unit
Voltage difference VDDR VDDA Voltage difference VSSR VSSA Digital Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single limit digital pins Instantaneous Maximum Current Single limit XFC, EXTAL, XTAL(4) Instantaneous Maximum Current Single limit TEST Storage Temperature Range
NOTES: Beyond absolute maximum ratings device might damaged. device contains internal voltage regulator generate logic supply supply. absolute maximum ratings apply when device powered from external source. digital pins internally clamped VSSX VDDX, VSSR VSSA VDDA. Those pins internally clamped VSSPLL VDDPLL. This clamped VSSPLL, clamped high. This must tied applications.
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A.1.6 Protection Latch-up Immunity
testing conformity with CDF-AEC-Q100 Stress test qualification Automotive Grade Integrated Circuits. During device qualification stresses were performed Human Body Model (HBM), Machine Model (MM) Charge Device Model. device will defined failure after exposure pulses device longer meets device specification. Complete parametric functional testing performed applicable device specification room temperature followed temperature, unless specified otherwise device specification. Table Latch-up Test Conditions
Model Description
Series Resistance Storage Capacitance Human Body Number Pulse positive negative Series Resistance Storage Capacitance Machine Number Pulse positive negative Minimum input voltage limit Latch-up Maximum input voltage limit
Symbol
Value
1500 -2.5
Unit
Table Latch-Up Protection Characteristics
Rating
Symbol
VHBM VCDM ILAT
2000 +100 -100 +200 -200
Unit
Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current 125°C positive negative Latch-up Current 27°C positive negative
ILAT
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A.1.7 Operating Conditions
This chapter describes operating conditions device. Unless otherwise noted those conditions apply following data. NOTE: Please refer temperature rating device with regards ambient temperature junction temperature power dissipation calculations refer A.1.8 Power Dissipation Thermal Characteristics. Table Operating Conditions
Rating
I/O, Regulator Analog Supply Voltage
Symbol
VDD5 VDDPLL VDDX VSSX fosc fbus
2.35 2.25 -0.1 -0.1
5.25 2.75 2.75
Unit
Digital Logic Supply Voltage(1) Supply Voltage(2) Voltage Difference VDDX VDDR Voltage Difference VSSX VSSR VSSA Oscillator Frequency MC9S12A128C Operating Junction Temperature Range Operating Ambient Temperature Range
NOTES: device contains internal voltage regulator generate logic supply supply. absolute maximum ratings apply when this regulator disabled device powered from external source. Please refer A.1.8 Power Dissipation Thermal Characteristics more details about relation between ambient temperature device junction temperature
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A.1.8 Power Dissipation Thermal Characteristics
Power dissipation thermal characteristics closely related. user must assure that maximum operating junction temperature exceeded. average chip-junction temperature (TJ) obtained from:
Junction Temperature, Ambient Temperature, Total Chip Power Dissipation, Package Thermal Resistance, [°C/W]
total power dissipation calculated from:
Chip Internal Power Dissipation,
cases with internal voltage regulator enabled disabled must considered: Internal Voltage Regulator disabled
DDPLL DDPLL
RDSON IIOi
output currents ports associated with VDDX VDDR. RDSON valid:
;for outputs driven DSON
respectively
;for outputs driven high DSON
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Internal voltage regulator enabled
IDDR current shown Table overall current flowing into VDDR, which additionally contains current flowing into external loads with output high.
RDSON IIOi
output currents ports associated with VDDX VDDR.
Table Thermal Package Characteristics(1)
Rating
Symbol
Unit
Thermal Resistance LQFP112, single sided PCB(2) Thermal Resistance LQFP112, double sided with internal planes(3)
Thermal Resistance LQFP single sided Thermal Resistance LQFP double sided with internal planes
NOTES: values thermal resistance achieved package simulations Board according EIA/JEDEC Standard 51-2 Board according EIA/JEDEC Standard 51-7
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A.1.9 Characteristics
This section describes characteristics pins. parameters always applicable, e.g. pins feature pull up/down resistances. Table Characteristics
Conditions shown Table unless otherwise noted
Input High Voltage Input High Voltage Input Voltage Input Voltage Input Hysteresis
Rating
Symbol
0.65*VDD5 VSS5
VDD5 0.35*VDD5
Unit
Input Leakage Current (pins high impedance input mode)(1) VDD5 VSS5 Output High Voltage (pins output mode) Partial Drive -2.0mA Full Drive -10.0mA Output Voltage (pins output mode) Partial Drive +2.0mA Full Drive +10.0mA Internal Pull Device Current, tested Max.
-2.5
VDD5
IPUL IPUH IPDH IPDL IICS IICP tPULSE tPULSE
-130
Internal Pull Device Current, tested Min. Internal Pull Down Device Current, tested Min.
Internal Pull Down Device Current, tested Max.
-2.5
Input Capacitance Injection current(2) Single limit Total Device Limit. injected currents Port Interrupt Input Pulse filtered(3) Port Interrupt Input Pulse passed
NOTES: Maximum leakage current occurs maximum operating temperature. Current decreases approximately one-half each 12°C temperature range from 50°C 125°C. Refer A.1.4 Current Injection, more details Parameter only applies STOP Pseudo STOP mode.
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A.1.10 Supply Currents
This section describes current consumption characteristics device well conditions measurements. A.1.10.1 Measurement Conditions measurements without output loads. Unless otherwise noted currents measured single chip mode, internal voltage regulator enabled 25MHz frequency using 4MHz oscillator Colpitts mode. Production testing performed using square wave signal EXTAL input. A.1.10.2 Additional Remarks
expanded modes currents flowing system highly dependent load address, data control signals well duty cycle those signals. generally applicable numbers given. very good estimate take single chip currents currents external loads. Table Supply Current Characteristics
Conditions shown Table unless otherwise noted
Rating
supply currents Single Chip, Internal regulator enabled Wait Supply current modules enabled, only enabled(1) Pseudo Stop Current (RTI disabled) (1), -40°C 27°C 70°C 85°C Temp Option 100°C 105°C Pseudo Stop Current (RTI enabled)(1) ,(2) -40°C 27°C 70°C 85°C 105°C Stop Current(2)
Symbol
IDD5
Unit
IDDW
1600
IDDPS
IDDPS
-40°C 27°C 70°C 85°C Temp Option 100°C 105°C
IDDS
1200
NOTES: those power dissipation levels assumed
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Characteristics
This section describes characteristics analog digital converter.
A.2.1 Operating Characteristics
Table shows conditions under which operates. following constraints exist obtain full-scale, full range results: VSSA VDDA. This constraint exists since sample buffer amplifier drive beyond power supply levels that ties input level goes outside this range will effectively clipped. Table Operating Characteristics
Conditions shown Table unless otherwise noted
Reference Potential
Rating
High
Symbol VRH-VRL fATDCLK
VSSA VDDA/2 4.50
5.00
VDDA/2 VDDA 5.25
Unit Cycles Cycles
Differential Reference Voltage(1) Clock Frequency 10-Bit Conversion Period
Clock Cycles(2) NCONV10 Conv, Time 2.0MHz Clock fATDCLK TCONV10 8-Bit Conversion Period Clock Cycles(2) Conv, Time 2.0MHz Clock fATDCLK
NCONV8 TCONV8 IREF IREF
Stop Recovery Time (VDDA=5.0 Volts) Reference Supply current (Both blocks Reference Supply current (Only block
0.750 0.375
NOTES: Full accuracy guaranteed when differential voltage less than 4.50V minimum time assumes final sample period clocks cycles while maximum time assumes final sample period clocks.
A.2.2 Factors Influencing accuracy
Three factors source resistance, source capacitance current injection have influence accuracy ATD. A.2.2.1 Source Resistance input leakage current specified Table conjunction with source resistance there will voltage drop from signal source input. maximum source resistance
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specifies results error less than (2.5mV) maximum leakage current. device operating conditions less than worst case leakage-induced error acceptable, larger values source resistance allowed. A.2.2.2 Source Capacitance When sampling additional internal capacitor switched input. This cause voltage drop charge sharing with external capacitance. maximum sampling error input voltage 1LSB, then external filter capacitor, 1024 (CINS- CINN). A.2.2.3 Current Injection There cases consider.
current injected into channel being converted. channel being stressed conversion values $3FF ($FF 8-bit mode) analog inputs greater than $000 values less than unless current higher than specified disruptive condition. Current injected into pins neighborhood channel being converted. portion this current picked channel (coupling ratio This additional current impacts accuracy conversion depending source resistance. additional input voltage error converted channel calculated VERR IINJ, with IINJ being currents injected into pins adjacent converted channel. Table Electrical Characteristics
Conditions shown Table unless otherwise noted
Rating
Symbol
CINN CINS
Unit
input Source Resistance Total Input Capacitance Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
-2.5
10-4 10-2
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A.2.3 Accuracy
Table A-10 specifies conversion performance excluding errors current injection, input capacitance source resistance. Table A-10 Conversion Performance
Conditions shown Table unless otherwise noted VREF 5.12V. Resulting count 20mV count fATDCLK 2.0MHz
10-Bit Resolution
Rating
Symbol
-2.5 -0.5 -1.0 -1.5
Unit
Counts Counts Counts Counts Counts Counts
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute Error(1) 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error(1)
±1.5 ±2.0 ±0.5 ±1.0
NOTES: These values include quantization error which inherently count converter.
following definitions also Figure A-1. Differential Non-Linearity (DNL) defined difference between adjacent switching steps.
1LSB
Integral Non-Linearity (INL) defined DNLs:
1LSB
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Vi-1
$3FF $3FE $3FD $3FC $3FB
10-Bit Absolute Error Boundary 8-Bit Absolute Error Boundary
$3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Resolution
$3F4 $3F3
Ideal Transfer Curve
10-Bit Transfer Curve
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Figure Accuracy Definitions NOTE: Figure shows only definitions, specification values refer Table A-10.
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8-Bit Resolution
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NVM, Flash, EEPROM
NOTE: Unless otherwise noted abbreviation (Non Volatile Memory) used both Flash EEPROM.
A.3.1 Timing
time base program erase operations derived from oscillator. minimum oscillator frequency fNVMOSC required performing program erase operations. modules have means monitor frequency will prevent program erase operation frequencies above below specified minimum. Attempting program erase modules lower frequency full program erase transition assured.
Flash EEPROM program erase operations timed using clock derived from oscillator using FCLKDIV ECLKDIV registers respectively. frequency this clock must within limits specified fNVMOP. minimum program erase times shown Table A-11 calculated maximum fNVMOP maximum fbus. maximum times calculated minimum fNVMOP fbus 2MHz.
A.3.1.1 Single Word Programming programming time single word programming dependant frequency well frequency fNVMOP calculated according following formula.
swpgm NVMOP
A.3.1.2 Burst Programming This applies only Flash where words programmed consecutively using burst programming keeping command pipeline filled. time program consecutive word calculated
bwpgm NVMOP
time program whole
brpgm swpgm bwpgm
Burst programming more than times faster than single word programming.
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A.3.1.3 Sector Erase Erasing byte Flash sector byte EEPROM sector takes:
4000 NVMOP
setup time ignored this operation. A.3.1.4 Mass Erase Erasing block takes:
mass 20000 NVMOP
setup time ignored this operation. A.3.1.5 Blank Check time takes perform blank check Flash EEPROM dependant location first non-blank word starting relative address zero. takes cycle word verify plus setup command.
check location
Table A-11 Timing Characteristics
Conditions shown Table unless otherwise noted
Rating
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck
46(2) 20.4(2) 678.4(2) 20(5)
Unit
External Oscillator Clock frequency Programming Erase Operations Operating Frequency Single Word Programming Time Flash Burst Programming consecutive word Flash Burst Programming Time Words Sector Erase Time Mass Erase Time Blank Check Time Flash block Blank Check Time EEPROM block
74.5(3) 31(3) 1035.5(3) 26.7(3)
tcyc tcyc
11(6) 11(6)
32,778(7) 2058(7)
NOTES: Restrictions oscillator crystal mode apply! Minimum Programming times achieved under maximum operating frequency fNVMOP maximum frequency fbus. Maximum Erase Programming times achieved under particular combinations fNVMOP frequency fbus. Refer formulae A.3.1.1 Single Word Programming- A.3.1.4 Mass Erase guidance. urst Programming operations applicable EEPROM Minimum Erase times achieved under maximum operating frequency fNVMOP. Minimum time, first word array blank Maximum time complete check erased block
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A.3.2 Reliability
reliability blocks guaranteed stress test during qualification, constant process monitors burn-in screen early life failures. failure rates data retention program/erase cycling specified operating conditions noted. program/erase cycle count sector incremented every time sector mass erase event executed. NOTE: values shown Table A-12 target values subject further extensive characterization. Table A-12 Reliability Characteristics
Conditions shown Table unless otherwise noted
Array
Cycles
1000 10,000
Data Retention Lifetime
years years
Flash/EEPROM (-40 85°C) EEPROM (-40 85°C)
NOTE: NOTE: NOTE:
Flash cycling performance 1000 cycles +85°C. Data Retention specified years. EEPROM cycling performance 10,000 cycles +85°C. Data retention specified years. These figures provided commercial quality levels automotive.
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Voltage Regulator
on-chip voltage regulator intended supply internal logic oscillator circuits. external load allowed. Table A-13 Voltage Regulator Recommended Load Capacitances
Rating
Load Capacitance VDD1, Load Capacitance VDDPLL
Symbol
CLVDD CLVDDPLL
Unit
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Reset, Oscillator
This section summarizes electrical characteristics various startup scenarios Oscillator Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained this section. Detailed description startup behavior found HCS12 Clock Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D) Table A-14 Startup Characteristics
Conditions shown Table unless otherwise noted
release level assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS
0.97
2.07
Unit
tosc nosc tcyc
Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, edge-sensitive mode Wait recovery startup time
A.5.1.1 release level VPORR assert level VPORA derived from supply. They also valid device powered externally. After releasing reset oscillator clock quality check started. after time tCQOUT valid oscillation detected, will start using internal self clock. fastest startup time possible given nuposc. A.5.1.2 SRAM Data Retention Provided appropriate external reset signal applied MCU, preventing from executing code when VDD5 specification limits, SRAM contents integrity guaranteed after reset PORF Flags Register been set. A.5.1.3 External Reset When external reset asserted time greater than PWRSTL module generates internal reset, starts fetching reset vector without doing clock quality check, there oscillation before reset.
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A.5.1.4 Stop Recovery STOP controller woken external interrupt. clock quality check after performed before releasing clocks system. A.5.1.5 Pseudo Stop Wait Recovery recovery from Pseudo STOP Wait essentially same since oscillator stopped both modes. controller woken internal external interrupts. After twrs starts fetching interrupt vector.
A.5.2 Oscillator
device features internal Colpitts oscillator. asserting XCLKS input during reset this oscillator bypassed allowing input square wave. Before asserting oscillator internal system clocks quality oscillation checked each start from either power-on, STOP oscillator fail. tCQOUT specifies maximum time before switching internal self clock mode after STOP proper oscillation detected. quality check also determines minimum oscillator start-up time tUPOSC. device also features clock monitor. Clock Monitor Failure asserted frequency incoming clock signal below Assert Frequency fCMFA. Table A-15 Oscillator Characteristics
Conditions shown Table unless otherwise noted
Rating
Symbol
fOSC IOSC nUPOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF VDCBIAS
4100 0.45
8(1)
100(2)
Unit
cycOSC
Crystal oscillator range Startup Current Oscillator start-up time from STOP Oscillator start-up time Clock Quality check time-out Clock Monitor Failure Assert Frequency External square wave input frequency(3) External square wave pulse width External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance (EXTAL, XTAL pins) Operating Bias Colpitts Configuration EXTAL
NOTES: fosc 4MHz, 22pF. Maximum value extreme cases using high frequency crystals XCLKS during reset
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A.5.3 Phase Locked Loop
oscillator provides reference clock PLL. Voltage Controlled Oscillator (VCO) also system clock source self clock mode. A.5.3.1 Component Selection This section describes selection components achieve good filter characteristics.
VDDPLL
Phase fosc refdv+1 fref fcmp Detector Loop Divider synr+1
fvco
Figure Basic Functional Diagram following procedure used calculate resistance capacitance values using typical values from Table A-16. Gain desired output frequency approximated
phase detector relationship given
current tracking mode.
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loop bandwidth should chosen fulfill Gardner's stability criteria least factor typical values ensures good transient response.
finally frequency relationship defined
synr
With above inputs resistance calculated
capacitance calculated
0.516
capacitance should chosen range
stabilization delays shown Table A-16 dependant operational settings external component selection (e.g. crystal, filter). A.5.3.2 Jitter Information basic functionality shown Figure A-2. With each transition clock fcmp, deviation from reference clock fref measured input voltage adjusted accordingly.The adjustment done continuously with abrupt changes clock output frequency. Noise, voltage, temperature other factors cause slight variations control loop resulting clock jitter. This jitter affects real minimum maximum clock periods illustrated Figure A-3.
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tmin1 tnom tmax1 tminN tmaxN Figure Jitter Definitions
relative deviation tnom maximum clock period, decreases towards zero larger number clock periods (N). Defining jitter
100, following equation good maximum jitter:
J(N)
Figure Maximum Clock Jitter Approximation This very important notice with respect timers, serial modules where pre-scaler will eliminate effect jitter large extent.
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Table A-16 Characteristics
Conditions shown Table unless otherwise noted
Rating
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq
-120 38.5
0.13
Unit
%(1) %(1) %(1) %(1) MHz/V
Self Clock Mode frequency locking range Lock Detector transition from Acquisition Tracking mode
Lock Detection Un-Lock Detection Lock Detector transition from Tracking Acquisition mode
PLLON Total Stabilization delay (Auto Mode) PLLON Acquisition mode stabilization delay(2) PLLON Tracking mode stabilization delay Fitting parameter loop gain Fitting parameter loop frequency Charge pump current acquisition mode Charge pump current tracking mode Jitter parameter 1(2) Jitter parameter 2(2)
NOTES: deviation from target frequency fREF 4MHz, fBUS 25MHz equivalent fVCO 50MHz: REFDV #$03, SYNR #$018, 4.7nF, 470pF,
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A.6.1 Master Mode
Figure Figure illustrate master mode timing. Timing values shown Table A-17.
(OUTPUT) (CPOL (OUTPUT)
(CPOL (OUTPUT) MISO (INPUT) MOSI (OUTPUT)
configured output. LSBF LSBF order LSB, MSB.
OUT2
Figure Master Timing (CPHA
(OUTPUT) (CPOL (OUTPUT) (CPOL (OUTPUT) MISO (INPUT) MOSI (OUTPUT) PORT DATA
configured output LSBF LSBF order LSB, MSB.
MASTER OUT2
MASTER
PORT DATA
Figure Master Timing (CPHA
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Table A-17 Master Mode Timing Characteristics1
Conditions shown Table unless otherwise noted, LOAD 200pF outputs
Operating Frequency
Rating
Symbol
tsck tlead tlag twsck
tbus
2048 1024 tbus
Unit
fbus tbus tsck tsck
Period tsck 1./fop Enable Lead Time Enable Time Clock (SCK) High Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid (after Enable Edge) Data Hold Time (Outputs) Rise Time Inputs Outputs Fall Time Inputs Outputs
NOTES: numbers column labeled "Num" missing. This been done purpose consistent between Master Slave timing shown Table A-18.
A.6.2 Slave Mode
Figure Figure illustrate slave mode timing. Timing values shown Table A-18.
(INPUT) (CPOL (INPUT) (CPOL (INPUT) MISO (OUTPUT) SLAVE MOSI (INPUT)
SLAVE
Figure Slave Timing (CPHA
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(INPUT) (CPOL (INPUT) (CPOL (INPUT) MISO (OUTPUT) SLAVE
SLAVE
MOSI (INPUT)
Figure Slave Timing (CPHA
Table A-18 Slave Mode Timing Characteristics
Conditions shown Table unless otherwise noted, CLOAD 200pF outputs
Operating Frequency
Rating
Symbol
tsck tlead tlag twsck tdis
tcyc
2048
Unit
fbus tbus tcyc tcyc tcyc tcyc
Period tsck 1./fop Enable Lead Time Enable Time Clock (SCK) High Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time Slave MISO Disable Time Data Valid (after Edge) Data Hold Time (Outputs) Rise Time Inputs Outputs Fall Time Inputs Outputs
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
External Timing
timing diagram external multiplexed-bus illustrated Figure with actual timing values shown table Table A-19. major signals included diagram. While both data write data read cycle shown, only other would occur particular cycle.
A.7.1 General Muxed Timing
expanded timings highly dependent load conditions. timing parameters shown assume balanced load across outputs.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
ECLK Addr/Data (read) data data Addr/Data (write) data addr data
addr
Non-Multiplexed Addresses PK5:0
LSTRB
NOACC
IPIPO0 IPIPO1, PE6,5
Figure General External Timing
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Table A-19 Expanded Timing Characteristics
Conditions shown Table unless otherwise noted, LOAD 50pF
Rating
Symbol
tcyc PWEL PWEH tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV
25.0
Unit
Frequency operation (E-clock) Cycle time Pulse width, Pulse width, high(1) Address delay time Address valid time rise (PWEL-tAD) Muxed address hold time Address hold data valid Data hold address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEH-tDDW) Address access time(1) (tcyc-tAD-tDSR) high access time(1) (PWEH-tDSR) Non-multiplexed address delay time Non-muxed address valid rise (PWEL-tNAD) Non-multiplexed address hold time Chip select delay time Chip select access time (tcyc-tCSD-tDSR) Chip select hold time Chip select negated time Read/write delay time Read/write valid time rise EL-tRWD) Read/write hold time strobe delay time strobe valid time rise (PWEL-tLSD) strobe hold time NOACC strobe delay time NOACC valid time rise (PWEL-tNOD)
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Table A-19 Expanded Timing Characteristics
Conditions shown Table unless otherwise noted, LOAD 50pF
NOACC hold time IPIPO[1:0] delay time
Rating
Symbol
tNOH tP0D tP0V tP1D tP1V
Unit
IPIPO[1:0] valid time rise EL-tP0D) IPIPO[1:0] delay time1 (PWEH-tP1V) IPIPO[1:0] valid time fall
NOTES: Affected clock stretch: tcyc where N=0,1,2 depending number clock stretches.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
Appendix Package Information
General
This section provides physical dimensions MC9S12A128 packages.
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
112-Pin LQFP Package
IDENT
0.20
TIPS
0.20
VIEW
108X
X=L,
VIEW
0.13
BASE METAL
SECTION J1-J1 ROTATED COUNTERCLOCKWISE
NOTES: DIMENSIONING TOLERANCING ASME Y14.5M, 1994. DIMENSIONS MILLIMETERS. DATUMS DETERMINED SEATING PLANE, DATUM DIMENSIONS DETERMINED SEATING PLANE, DATUM DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. DIMENSIONS INCLUDE MOLD MISMATCH. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE DIMENSION EXCEED 0.46. MILLIMETERS 20.000 10.000 20.000 10.000 -1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 0.090 0.170 0.500 0.325 0.100 0.200 0.100 0.200 22.000 11.000 22.000 11.000 0.250 1.000 0.090 0.160
0.050
VIEW 0.10
112X
SEATING PLANE
0.25
GAGE PLANE
VIEW
Figure 112-Pin LQFP Mechanical Dimensions (Case 987)
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
80-Pin Package
0.05
0.20
0.20
-A-,-B-,-DDETAIL
DETAIL
-D0.20
0.05
0.20 -CSEATING PLANE
DETAIL
DATUM PLANE
0.20
SECTION
VIEW ROTATED
0.10
DATUM PLANE
DETAIL
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE LOCATED BOTTOM LEAD COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY BOTTOM PARTING LINE. DATUMS -A-, DETERMINED DATUM PLANE -H-. DIMENSIONS DETERMINED SEATING PLANE -C-. DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE -H-. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT LOCATED LOWER RADIUS FOOT.
MILLIMETERS 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 -0.25 0.13 0.23 0.65 0.95 12.35 0.13 0.17 0.325 0.13 0.30 16.95 17.45 0.13 -16.95 17.45 0.35 0.45
Figure 80-pin Mechanical Dimensions (Case 841B)
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
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Freescale Semiconductor, Inc. Device Guide V01.01 MC9S12A128
User Guide Sheet
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MC9S12A128 Device Guide -Freescale V01.01
Semiconductor, Inc.
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