MIGRATING FROM XR17D15X XR17V25X Author: INTRODUCTION This applic

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MIGRATING FROM XR17D15X XR17V25X Author: INTRODUCTION This applic

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DATA COMMUNICATIONS APPLICATION NOTE DAN183
MIGRATING FROM XR17D15X XR17V25X
Author: INTRODUCTION This application note describes changes necessary what consider when migrating from XR17D15x XR17V25x. HARDWARE DIFFERENCES Because XR17D15x compliant XR17V25x compliant, there some hardware changes consider when migrating from XR17D15x XR17V25x. addition, there some hardware differences because XR17V25x some enhanced features. Sections 2.1-2.4 below lists hardware differences between XR17D15x XR17V25x. VCC/VIO signals were separate XR17D15x because core voltage (VCC) could operating different voltage than voltage (VIO). add-in card example, could while could either 3.3V depending whether plugged into 3.3V slot slot. There separate signals XR17V25x because 3.3V only UART. XR17V25x 3.3V only because there specifications 3.0. TABLE VOLTAGE REQUIREMENTS
DEVICE FAMILY XR17D15x XR17V25x CORE VOLTAGE 3.3V 3.3V Only VOLTAGE 3.3V 3.3V Only
CLOCK XR17D15x operate with clock while XR17V25x operate with clock MHz. operate MHz, M66EN signal should connected VCC. TABLE MAXIMUM CLOCK FREQUENCY
DEVICE FAMILY XR17D15x XR17V25x CLOCK FREQUENCY
BAUD RATE DATA RATE) XR17V25x operates faster data rate than XR17D15x. With sampling rate, XR17V25x operate more than 8Mbps while XR17D15x could only operate 6.25Mbps. TABLE MAXIMUM BAUD RATE (DATA RATE)
DEVICE FAMILY XR17D15x XR17V25x EXTERNAL CLOCK FREQUENCY BAUD RATE 6.25 Mbps 8.25 Mbps
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DATA COMMUNICATIONS APPLICATION NOTE DAN183
DIFFERENCE TEST# (input used factory test mode) XR17D15x been changed PME# (open-drain output pin) XR17V25x support Power Management. XR17V25x compliant with Power Management Revision Specifications. XR17D15x have Power Management support. Power Management used, then PME# should connected PME# signal interface. Otherwise, PME# should pulled-up left floating. FIRMWARE DIFFERENCES internal register XR17V25x based internal register XR17D15x. However, there were some changes/enhancements XR17V25x that resulted some changes internal register set. Here list changes/enhancements register affected. FRACTIONAL BAUD RATE GENERATOR Traditionally, baud rate divisor value between 32767 that programmed 8-bit registers (DLL DLM). With these divisors, standard baud rates such 9600 115200 could achieved using standard clock/crystal frequencies such 1.8432 14.7456 MHz. following formula calculate baud rate divisor: divisor (decimal)= (clock frequency) (baud rate sampling rate) default sampling rate clock frequency, unless sampling rate enabled 8XMODE register. example, desired baud rate 115200 14.7456 clock used, divisor would Using these standard clock frequencies, standard baud rates were easily achieved. However, when non-standard clock frequencies such were used, some standard baud rates were possible because divisors whole numbers. Using closest whole number divisor still resulted data transmission errors because baud rate deviation greater than deviation tolerated UART (see DAN108 complete details). example, desired baud rate 115200 clock used, approximate divisor would 5.425. table below shows closest divisors corresponding data rate error. TABLE BAUD RATE ERROR XR17D15X
DESIRED BAUD RATE (BPS) 115200 115200 0x00 0x00 0x05 0x06 ACTUAL BAUD RATE 125000 104167 ERROR
XR17V25x, register added allow fractional divisors. value programmed into would divided then added divisor. Using same example above, closest divisor would would This would result divisor 5.4375. below, resulting baud rate would within baud rate deviation tolerated UART. TABLE BAUD RATE ERROR XR17V25X
DESIRED BAUD RATE (BPS) 115200 0x00 0x05 0x07 ACTUAL BAUD RATE 114953 ERROR
addition register allows more flexibility clock frequency that used with XR17V25x generate almost desired baud rate. Also, system clock available, XR17V25x that instead separate crystal.
DATA COMMUNICATIONS APPLICATION NOTE DAN183
DEVICE distinguish between families their capabilities, Device XR17V25x family different. upper nibble Device distinguishes between families. lower nibble indicates many UART channels there device. table below lists Device IDs. TABLE DEVICE
DEVICE XR17D152 XR17D154 XR17D158 DEVICE 0x22 0x24 0x28 DEVICE XR17V252 XR17V254 XR17V258 DEVICE 0x42 0x44 0x48
Windows drivers provided Exar, driver does check Device When migrating from XR17D15x XR17V25x, software driver should updated detect Device IDs. Otherwise, drivers will install properly. POWER MANAGEMENT Power Management registers were added address offsets 0x40 0x44 Local Configuration space support Power Management feature XR17V25x. XR17V25x datasheet complete details. This feature available XR17D15x. EEPROM ADDRESS DEFINITIONS XR17D15x only expects read four 16-bit values from EEPROM. However, XR17V25x expects read eight 16-bit values from EEPROM. Therefore, EEPROM should updated that there 16-bit values programmed into EEPROM instead table below lists 16-bit values that XR17D15x XR17V25x UARTs expect. TABLE 16-BIT EEPROM DATA
EEPROM MEMORY ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 XR17D15X Vendor Device Subsystem Vendor Subsystem Device XR17V25X Vendor Device Class Code Class Code (continued) Subsystem Vendor Subsystem Device Special Register (Lower Word) Special Register (Upper Word)
There EEPROM programming utility available from Exar that program EEPROM through UART Windows 2000 Windows operating system. However, program EEPROM through UART, Windows 2000/XP driver must first installed. This driver available Exar customers after Software License Agreement (SLA) been completed. Windows drivers EEPROM programming utility obtained sending e-mail uarttechsupport@exar.com. TIMER/COUNTER XR17D15x, each first bits TIMERCNTL register function. However, Timer/ Counter functions were enhanced XR17V25x. order prevent simple errors masking correct bits, TIMERCNTL register command driven. 4-bit command used instead each individu-
DATA COMMUNICATIONS APPLICATION NOTE DAN183
bit. table below lists different Timer/Counter functions they controlled XR17D15x XR17V25x. detailed description Timer/Counter, XR17V25x datasheet. TABLE TIMER/COUNTER FUNCTIONS
TIMER/COUNTER FUNCTION Disable Timer/Counter Interrupt Enable Timer/Counter Interrupt Stop Pause Timer/Counter Start Timer/Counter Select Re-Triggerable Mode Select One-Shot Mode Select Internal Crystal Oscillator clock source Timer/Counter Select External Clock (via TMRCK input pin) clock source Timer/Counter De-Route Timer output from MPIO[0] Route Timer output MPIO[0] Reset Timer XR17D15X (BIT DRIVEN) TIMERCNTL[0] TIMERCNTL[0] TIMERCNTL[1] TIMERCNTL[1] TIMERCNTL[2] TIMERCNTL[2] TIMERCNTL[3] TIMERCNTL[3] TIMERCNTL[4] TIMERCNTL[4 XR17V25X (COMMAND DRIVEN) TIMERCNTL[3:0] 0010 TIMERCNTL[3:0] 0001 TIMERCNTL[3:0] 1010 TIMERCNTL[3:0] 1001 TIMERCNTL[3:0] 0100 TIMERCNTL[3:0] 0011 TIMERCNTL[3:0] 0101 TIMERCNTL[3:0] 0110 TIMERCNTL[3:0] 1000 TIMERCNTL[3:0] 0111 TIMERCNTL[3:0] 1011
TRANSMITTER RECEIVER DISABLE Transmitter Receive disabled XR17V25x. This feature available XR17D15x. Transmitter disabled when bit-3 (write-only). When Transmitter disabled, data left written into FIFO will transmitted. will resume transmission when bit-3 been reset. Similarly, Receiver disabled when bit-2 (write-only). When Receiver disabled, will ignore data received during that time pin. will receive data normally when bit-2 been reset. XR17V25x datasheet complete details. TXCHAR IMMEDIATE TXCHAR Immediate another feature XR17V25x. byte data inserted into Transmit Shift Register, ahead data that remaining FIFO, after current byte shifted out. This done writing bit-3 (assuming bit-4 then writing register. This feature only used when Transmitter been disabled. XR17V25x datasheet complete details. XON/XOFF INDICATOR XR17D15x, XCHAR register would indicate which flow control character (XON XOFF) received last particular channel. bit-0 then last flow control character received XOFF. bit-1 then last flow control character received XON. addition that, XR17V25x additional bits indicate whether last flow control character transmitted XOFF character. XCHAR bit-2 then last flow control character transmitted XOFF character. XCHAR bit-3 then last flow control character transmitted character. CONCLUSION XR17V25x enhanced version XR17D15x with faster clock, higher data rate, many features. Because these reasons, some hardware software changes will required take advantage performance 66MHz clock other enhanced features XR17V25x.
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed inaccuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 2005 EXAR Corporation September 2005 Send your UART technical inquiry with technical details hotline: uarttechsupport@exar.com Reproduction, part whole, without prior written consent EXAR Corporation prohibited.

MIGRATING FROM XR17D15X XR17V25X Author: INTRODUCTION This applic

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