Author: INTRODUCTION This application note provides sytem design engin
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MIGRATING EXAR'S FIFTH GENERATION UARTS: XR16L784/788
Author: INTRODUCTION This application note provides sytem design engineers with information necessary migrate Exar's newer more powerful Fifth Generation UARTs. describes hardware software differences between classic four channel UARTs (ST16C454, ST16C554, ST16C654, XR16C854 XR16C864) newer fifth generation UARTs (XR16L784 Quad UART XR16L788 Octal UART) which provide:
easier hardware interface easier software programming higher perfomance interrupt service routine register compatibility industry standard 16550
ADVANTAGES FIFTH GENERATION XR16L784 XR16L788 upgrade path from ST16C454/554/654/854/864 XR16L784 XR16L788 offers following benefits:
Simpler hardware interface with Intel/Motorola Reduction board space (when moving from ST16C454/554/654/854/864's XR16L788) Ability interface with both 3.3V devices Tolerant inputs) Higher baud rate sampling Fifth generation Flat Register Set, shadow/mirror registers Global Interrupt Source Registers easier/faster interrupt handling
noted that fifth generation devices continue offer same advantages classic devices following aspects:
Each channel independent FIFOs Each channel 16550-compatible register Each channel baud rate selection channels XTAL1 clock input clock baud rate generation
HARDWARE DIFFERENCES newer XR16L78x UARTs enable simpler interfacing with and/or programmable logic device. consider common cases:
migrating from ST16C454/554/654/854/864 XR16L784 migrating from ST16C454/554/654/854/864's XR16L788
Tables describe footprint hardware differences both cases. Figures show connections required CPU-UART interface both cases.
EXAR Corporation 48720 Kato Road, Fremont 94538 (510) 668-7000 (510) 668-7017 www.exar.com uarttechsupport@exar.com
TABLE HARDWARE DIFFERENCES BETWEEN ST16C454/554/654/854/864 XR16L784
DESCRIPTION Footprint Tolerant inputs (when Chipselect ST16C454/554/654/854/864 68-PLCC, 64-TQFP 100-QFP Available chipselect channel* (requires external address decoder logic generate chipselects) active Interrupt channel* (cannot wire-ORed; requires external logic combine interrupts into single IRQ) (A2:A0) registers (and shadow registers) XR16L784 64-TQFP chipselect entire chip
Interrupt
open-drain interrupt entire chip (can wire-ORed)
Address Lines
lines (A7:A0) registers channel Device Configuration registers entire device)
TABLE HARDWARE DIFFERENCES BETWEEN ST16C454/554/654/854/864'S XR16L788
DESCRIPTION Footprint Tolerant inputs (when Chipselect ST16C454/554/654/854/864 68-PLCC, 64-TQFP 100-QFP Available chipselect channel* (requires external address decoder logic generate chipselects) active Interrupt channel* (cannot wire-ORed; requires external logic combine interrupts into single IRQ) (A2:A0) registers (and shadow registers) XR16L788 100-QFP chipselect entire chip
Interrupt
open-drain interrupt entire chip (can wire-ORed)
Address Lines
lines (A7:A0) registers channel Device Configuration registers entire device)
*Note that these differences only when device operates Intel mode (16/68# HIGH). Motorola mode (16/68# LOW), each ST16C454/554/654/854/864 device only chipselect (with additional address lines select four channels) open-drain interrupt output, similar XR16L784. However, when using ST16C454/554/654/854/864's, extra chipselect still required, compared XR16L788.
FIGURE CPU-UART INTERFACE WHEN USING ST16C454/554/654/854/864 XR16L784
3.3V
Databus D7:D0
Address
A2:A0
ST16C454 ST16C554 ST16C654 XR16C854 XR16C864
CSA#
A10:A0
Programmable Logic Device*
CSB# CSC# CSD#
INTA
Interrupt Controller Logic*
INTB INTC INTD
Typical Connections between ST16C454/554/654/854/864
Tolerant Inputs 3.3V Data D7:D0
Address A7:A0
XR16L784
ChipSelect
100k
INT#
Typical Connections between XR16L784
Since there four chipselects four interrupts, external glue logic essential.
chipselect outputs from usually used drive XR16L784.
FIGURE CPU-UART INTERFACE WHEN USING ST16C454/554/654/854/864'S XR16L788
3.3V
Data D7:D0
Address
A2:A0
ST16C454 ST16C554 ST16C654 XR16C854 XR16C864
CSA#
A10:A0
Programmable Logic Device*
CSB# CSC# CSD#
INTA
Interrupt Controller Logic*
INTB INTC INTD
3.3V
Data D7:D0
A2:A0
CSA# CSB# CSC# CSD#
ST16C454 ST16C554 ST16C654 XR16C854 XR16C864
INTA INTB INTC INTD
Typical Connections between ST16C454/554/654/854/864's
Tolerant Inputs 3.3V Data D7:D0
Address A7:A0
XR16L788
ChipSelect
100k
INT#
Typical Connections between XR16L788
Since there eight chipselects eight interrupts, external glue logic essential.
chipselect outputs from usually used drive XR16L788.
SOFTWARE DIFFERENCES ST16C454/554/654/854/864 well XR16L784/788 have 16550 compatible registers. addition, XR16L784/788 have following enhancements/additions:
Flat Register Set: Apart from baud rate registers DLM, there shadow registers. enhanced registers ST16C654 XR16C854 shadow registers require that 0xBF before they accessed. This required XR16L784/788. Device Configuration Registers: These newly added registers which provide means configure obtain status from channels. These are:
Global Interrupt Registers INT0 INT3: Provide detailed information channel(s) type interrupt TIMER Registers: Configure general purpose Timer/Counter issue one-time periodic interrupts Mode: Double data rate using sampling clock instead sampling RESET: Software Reset channels SLEEP: Place individual channels sleep mode conserve power consumption DREV DVID Registers: Read Revision Device UART (This feature available through shadow registers XR16C854/864, available ST16C454/554/654) REGB: Write control registers channels simultaneously thereby simplifying initialization routine
advantages these registers newer XR16L784/788 devices best clarified using following software routine examples. These examples show typical receive transmit interrupt routines classic ST16C454/554/654/854/864 fifth generation XR16L784 XR16L788: INTERRUPT SERVICE ROUTINE ST16C454/554/654/854/864:
Disable_Interrupts(); status_channel_A read (ISR_channel_A); switch (status_channel_A) case RXRDY Read bytes RHR; break; case TXRDY Load bytes into THR; break; Other cases case No_Interrupt break; next channel switch statement channel
status_channel_B read (ISR_channel_B); switch (status_channel_B) case Repeat above channels Enable_Interrupts(); Interrupt_Routine switch statement channel
clearly seen above, interrupt routine inefficient since loop through channels determine cause interrupt. Also, only interrupt entire device serviced once. these devices used, scheme becomes even more inefficient. This inherent latency seen interrupt service routine XR16L784/788 because availability global interrupt registers paving servicing multiple interrupting conditions interrupt. INTERRUPT SERVICE ROUTINE XR16L784/788
Interrupt_Routine_788 Disable_Interrupts(); source_channel read (INT0); bit-0 indicates interrupt pending channel 3-bit encoding channel making 12-bits XR16L784 24-bits XR16L788 this encoding, bits channel bits channel etc. read same info from register channel encoding SAME. Please read datasheet XR16L784 XR16L788 more information long interrupt_info (read (INT3) read (INT2)) read (INT1); bits XR16L788 (source_channel 0x01) bit-0 channel bit-7 channel etc. switch (interrupt_info 0x7) case RXRDY Read bytes RHR; break; case TXRDY Load bytes into THR; break; Other cases case No_Interrupt break; next channel switch statement channel (source_channel 0x01)
(source_channel 0x02) switch (interrupt_info 0x38)
bits 24-bit value channel
service channel interrupts similarly
Enable_Interrupts(); Interrupt_Routine()
above scheme provides following advantages:
Global interrupt registers support quicker interrupt source identification. Interrupts from multiple channels serviced interrupt, according priority assigned each channel. Shorter deterministic time inside interrupt service routine fewer reads status registers maximum registers, INT0-INT3 against maximum registers individual channels).
SUMMARY From above discussion, clear that XR16L784/788 devices have many advantages from both hardware software point view. these devices deliver higher performance through following:
higher integration (one chip chips 554/654/854's)
less board space single chipselect single interrupt tolerant inputs (all inputs except XTAL1) Global Interrupt Registers quicker interrupt service
simpler interface with
ability interface with both 3.3V devices
less bandwidth requirement (faster interrupt parsing)
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed inaccuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 2004 EXAR Corporation August 2004 Send your UART technical inquiry with technical details hotline: uarttechsupport@exar.com Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
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