S1C88816 S1C88816 Technical Hardware NOTICE part this m
|
|
|
Top Searches for this datasheet
CMOS 8-BIT SINGLE CHIP MICROCOMPUTER
S1C88816
S1C88816 Technical Hardware
NOTICE
part this material reproduced duplicated form means without written permission Seiko Epson. Seiko Epson reserves right make changes this material without notice. Seiko Epson does assume liability kind arising inaccuracies contained this material application product circuit and, further, there representation that this material applicable products requiring high level reliability, such medical products. Moreover, license intellectual property rights granted implication otherwise, there representation warranty that anything made accordance with this material will free from patent copyright infringement third party. This material portions thereof contain technology subject relating strategic products under control Foreign Exchange Foreign Trade Japan require export license from Ministry International Trade Industry other approval from another government agency.
SEIKO EPSON CORPORATION 2004, rights reserved.
Revisions Additions this manual
Chapter Section 5.10.12 Page Item Table 1.1.1 Main features Layout Diagram Mask Option Programming notes Plastic Package Appendix Contents package changed. Explanation added. Item added. package changed. chapter added.
Appendix
Configuration product number
Devices 88104 0A01
Packing specifications Besides tape reel directions Tape reel BACK directions directions directions Tape reel FRONT directions directions directions directions Tape reel LEFT directions directions directions directions Tape reel RIGHT Specs fixed Specification Package form; Model number Model name microcomputer, digital products Product classification semiconductor
Development tools S5U1 88348
Packing specifications standard packing Version Version Tool type board Peripheral board Flash writer microcomputer writer peripheral board compiler package Assembler package Utility tool model Soft simulator Corresponding model number 88348: S1C88348 Tool classification microcomputer Product classification S5U1: development tool semiconductor products
CONTENTS
Contents
INTRODUCTION
Features Block Diagram Layout Diagram Mask Option
POWER SUPPLY
Operating Voltage Internal Power Supply Circuit Heavy Load Protection Mode
MEMORY CONFIGURATION
Internal Memory
3.2.1 3.2.2 3.2.3 memory 3.2.4 Display memory
Exception Processing Vectors (Customized Condition Flag)
INITIAL RESET
Initial Reset Factors
4.1.1 RESET terminal 4.1.2 Simultaneous level input input port terminals K00-K03 4.1.3 Supply voltage detection (SVD) circuit 4.1.4 Initial reset sequence
Initial Settings After Initial Reset Programming Note
PERIPHERAL CIRCUITS THEIR OPERATION
Memory Watchdog Timer
5.2.1 Configuration watchdog timer 5.2.2 Interrupt function 5.2.3 memory watchdog timer 5.2.4 Programming notes
Oscillation Circuits Operating Mode
5.3.1 Configuration oscillation circuits 5.3.2 Mask option 5.3.3 OSC1 oscillation circuit 5.3.4 OSC3 oscillation circuit 5.3.5 Operating mode 5.3.6 Switching clocks 5.3.7 memory oscillation circuit 5.3.8 Programming notes
S1C88816 TECHNICAL MANUAL
EPSON
CONTENTS
Input Ports ports)
5.4.1 Configuration input ports 5.4.2 Mask option 5.4.3 Interrupt function input comparison register 5.4.4 memory input ports. 5.4.5 Programming note
Output Ports ports)
5.5.1 Configuration output ports 5.5.2 Mask option 5.5.3 High impedance control 5.5.4 output 5.5.5 Special output 5.5.6 memory output ports 5.5.7 Programming notes
Ports ports)
5.6.1 Configuration ports 5.6.2 Mask option 5.6.3 control registers mode 5.6.4 memory ports 5.6.5 Programming note
Serial Interface
5.7.1 Configuration serial interface 5.7.2 Mask option 5.7.3 Transfer modes 5.7.4 Clock source 5.7.5 Transmit-receive control 5.7.6 Operation clock synchronous transfer 5.7.7 Operation asynchronous transfer 5.7.8 Interrupt function 5.7.9 memory serial interface 5.7.10 Programming notes
Clock Timer
5.8.1 Configuration clock timer 5.8.2 Interrupt function 5.8.3 memory clock timer 5.8.4 Programming notes
Stopwatch Timer
5.9.1 Configuration stopwatch timer 5.9.2 Count pattern 5.9.3 Interrupt function 5.9.4 memory stopwatch timer 5.9.5 Programming notes
5.10
Programmable Timer
5.10.1 Configuration programmable timer 5.10.2 Mask option 5.10.3 Count operation setting basic mode 5.10.4 Setting input clock 5.10.5 Timer mode 5.10.6 Event counter mode 5.10.7 Pulse width measurement timer mode 5.10.8 Interrupt function 5.10.9 Setting TOUT output 5.10.10 Transmission rate setting serial interface 5.10.11 memory programmable timer 5.10.12 Programming notes
EPSON
S1C88816 TECHNICAL MANUAL
CONTENTS
5.11
Controller
5.11.1 Configuration controller 5.11.2 Mask option 5.11.3 power supply 5.11.4 driver 5.11.5 Display memory 5.11.6 Display control 5.11.7 memory controller 5.11.8 Programming note
5.12
Sound Generator .103
5.12.1 Configuration sound generator 5.12.2 Mask option 5.12.3 Control buzzer output 5.12.4 Setting buzzer frequency sound level 5.12.5 Digital envelope 5.12.6 One-shot output 5.12.7 memory sound generator 5.12.8 Programming notes
5.13
Melody Generator .109
5.13.1 Features configuration melody generator 5.13.2 Programming melodies 5.13.3 Controlling melody output 5.13.4 Interrupt function 5.13.5 memory melody generator 5.13.6 Programming notes
5.14
Supply Voltage Detection (SVD) Circuit .117
5.14.1 Configuration circuit 5.14.2 Operation circuit 5.14.3 memory circuit 5.14.4 Programming notes
5.15
Converter .121
5.15.1 Characteristics configuration converter 5.15.2 Terminal configuration converter 5.15.3 Mask option 5.15.4 conversion 5.15.5 Interrupt function 5.15.6 memory converter 5.15.7 Programming notes
5.16
Interrupt Standby Status .128
5.16.1 Interrupt generation conditions 5.16.2 Interrupt factor flag 5.16.3 Interrupt enable register 5.16.4 Interrupt priority register interrupt priority level 5.16.5 Exception processing vectors 5.16.6 memory interrupt 5.16.7 Programming notes
5.17
Notes Current Consumption .134
BASIC EXTERNAL WIRING DIAGRAM ELECTRICAL CHARACTERISTICS
Absolute Maximum Rating .136 Recommended Operating Conditions .136 Characteristics .137 Analog Circuit Characteristics .138
S1C88816 TECHNICAL MANUAL
EPSON
CONTENTS
Power Current Consumption .140 Characteristics .141 Oscillation Characteristics .147 Converter Characteristics .148 Characteristics Curves (reference value) .149
PACKAGE
Plastic Package .156 Ceramic Package .157
LAYOUT
Diagram Layout .158 Coordinates .159
PRECAUTIONS MOUNTING
APPENDIX S5U1C88000P1&S5U1C88816P2 MANUAL (Peripheral Circuit Board S1C88816)
Names Functions Each Part .162 Installation .164
A.2.1 Installing S5U1C88816P2 S5U1C88000P1 A2.2 Installing into (S5U1C88000H5)
Connecting Target System .165 Downloading Circuit Data S5U1C88000P1 .167 Precautions .168
A.5.1 Precaution operation A.5.2 Differences from actual
Product Specifications .170
A.6.1 S5U1C88000P1 specifications A.6.2 S5U1C88816P2 specifications
EPSON
S1C88816 TECHNICAL MANUAL
INTRODUCTION
INTRODUCTION
S1C88816 microcomputer features S1C88 (MODEL CMOS 8-bit core along with 116K bytes ROM, bytes RAM, three different timers, serial interface with optional asynchronization clock synchronization, melody generator converter. S1C88816 large capacity fully operable over wide range voltages. Furthermore, perform high speed operations even voltage. Like equipment Family, these microcomputers have power consumption.
Features
Table 1.1.1 lists features S1C88816. Table 1.1.1 Main features
Core S1C88 (MODEL3) CMOS 8-bit core OSC1 Oscillation circuit Crystal oscillation circuit/CR oscillation circuit/external clock input 32.768 (Typ.) OSC3 Oscillation circuit Crystal oscillation circuit/ceramic oscillation circuit/CR oscillation circuit/external clock input (Max.) types (usable multiplication division instructions) Instruction Min. instruction execution time 0.244 µsec/8.2 clock) Internal capacity 116K bytes Internal capacity bytes/RAM, 4224 bits/display memory, bytes/melody Input port bits event counter external clock input) Output port bits (can TOUT, TOUT FOUT output) port bits (P10-P13 P14-P17 serial input/output converter input, respectively) Serial interface (Optional clock synchronous system asynchronous system) Timer Programmable timer bits): (1ch event counter bits programmable timer 1ch) Clock timer bits): Stopwatch timer bits): matrix type (supports fonts) segments common (1/5 bias) segments common (1/5 bias) segments common (1/5 bias) drive power supply circuit built-in (booster/reducer type, potentials/4 potentials) Sound generator Envelope function, equipped with volume control Watchdog timer Built-in Supply voltage detection detect different voltage levels (SVD) circuit Melody generator sound source (scale: octaves, note: types, tempo: types) Note scale data stored into melody (allows read write) converter Successive-approximation type, resolution: bits, input: (shared with P14-P17) systems types) Interrupt External interrupt: Input interrupt systems types) Internal interrupt: Timer interrupt Serial interface interrupt system types) Melody interrupt system type) converter interrupt system type) V-5.5 (Max. MHz) Supply voltage Normal mode: power mode: V-5.5 (Max. kHz) High speed mode: V-5.5 (Max. MHz) driver Current consumption SLEEP mode: HALT mode (32.768 kHz): During running (32.768 kHz): During running MHz): QFP21-176pin chip 0.45 (Typ./normal mode) (Typ./normal mode) (Typ./normal mode) (Typ./normal mode)
Supply form
S1C88816 TECHNICAL MANUAL
EPSON
INTRODUCTION
Block Diagram
Core S1C88
OSC1,
Oscillator
OSC3, RESET
Interrupt Controller
Reset/Test
TEST
Input Port
K00-K07 (EVIN) P00-P07 (SIN) (SOUT) (SCLK) (SRDY) P14-P17 (AD4-AD7) AVDD AGND AVSS AVREF (TOUT (TOUT) (FOUT) (BZ) Selectable mask option MOUT MOUT
Watchdog Timer
Port
Clock Timer
Serial Interface
Stopwatch Timer
Converter
VOSC VC1-VC5 CA-CG
Programmable Timer /Event Counter Power Generator Sound Generator
Supply Voltage Detector
SEG0-SEG71 COM16-COM31 (SEG87-SEG72) COM0-COM15
Output Port
Driver
Melody Generator
116KB
Fig. 1.2.1 S1C88816 block diagram
EPSON
S1C88816 TECHNICAL MANUAL
INTRODUCTION
Layout Diagram
QFP21-176pin
INDEX
name N.C. N.C. SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 N.C. N.C.
name N.C. SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 COM31/SEG72 COM30/SEG73 COM29/SEG74 COM28/SEG75 COM27/SEG76 COM26/SEG77 COM25/SEG78 COM24/SEG79 COM23/SEG80 COM22/SEG81 COM21/SEG82 COM20/SEG83 COM19/SEG84 COM18/SEG85 COM17/SEG86 COM16/SEG87 N.C. N.C.
name N.C. N.C. OSC3 OSC4 VOSC OSC1 OSC2 TEST RESET K10/EVIN P17/AD7 P16/AD6 P15/AD5 P14/AD4 P13/SRDY P12/SCLK P11/SOUT P10/SIN AVDD AGND AVSS AVREF N.C. N.C.
name N.C. N.C. MOUT MOUT R26/TOUT R27/TOUT R34/FOUT R50/BZ R51/BZ COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 N.C. N.C.: Connection
Fig. 1.3.1 S1C88816 layout
S1C88816 TECHNICAL MANUAL
EPSON
INTRODUCTION
Table 1.3.1 S1C88816 description
name VOSC VC1-VC5 CA-CG OSC1 OSC2 OSC3 OSC4 K00-K07 K10/EVIN R26/TOUT R27/TOUT R34/FOUT R50/BZ R51/BZ P00-P07 P10/SIN P11/SOUT P12/SCLK P13/SRDY P14/AD4 P15/AD5 P16/AD6 P17/AD7 MOUT MOUT COM0-COM15 COM16-COM31 /SEG87-SEG72 SEG0-SEG71 RESET TEST AVDD AVSS AGND AVREF 93-91, 84-78 112-105 136, 135, 130-125 144-159 77-62 160-175, 3-42, 46-61 In/out Function Power supply terminal Power supply (GND) terminal Regulated voltage internal circuit Regulated voltage OSC1 oscillation circuit drive voltage output terminals Voltage boost/reduce-capacitor connection terminals OSC1 oscillation input terminal (select crystal oscillation/CR oscillation/external clock input mask option) OSC1 oscillation output terminal OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation/external clock input mask option) OSC3 oscillation output terminal Input terminals (K00-K07) Input terminal (K10) event counter external clock input terminal (EVIN) Output terminal (R26) programmable timer underflow signal inverted output terminal (TOUT) (selectable mask option) Output terminal (R27) programmable timer underflow signal output terminal (TOUT) Output terminal (R34) clock output terminal (FOUT) Output terminal (R50) buzzer output terminal (BZ) Output terminal (R51) buzzer inverted output terminal (BZ) (selectable mask option) terminals (P00-P07) terminal (P10) serial data input terminal (SIN) terminal (P11) serial data output terminal (SOUT) terminal (P12) serial clock terminal (SCLK) terminal (P13) serial ready signal output terminal (SRDY) terminal (P14) converter input terminal (AD4) terminal (P15) converter input terminal (AD5) terminal (P16) converter input terminal (AD6) terminal (P17) converter input terminal (AD7) Melody output terminal Melody inverted output terminal common output terminals common output terminals (when 1/32 duty selected) segment output terminal (when 1/16 duty selected) segment output terminals Initial reset input terminal Test input terminal Analog system power supply terminal Analog system power supply terminal Analog system ground terminal Analog system reference voltage input terminal
TEST terminal used shipping inspection normal operation sure connected VDD.
EPSON
S1C88816 TECHNICAL MANUAL
INTRODUCTION
Mask Option
Mask options shown below provided S1C88816. Several hardware specifications prepared each mask option, them selected according application. Select specifications that meet target system check appropriate box. option selection done interactively screen during function option generator winfog execution, using this option list reference. Mask pattern finally generated based data created winfog. Refer "S5U1C88000C Manual details winfog.
PERIPHERAL CIRCUIT BOARD option list
following shows options configuring Peripheral Circuit Board (S5U1C88000P1 with S5U1C88816P2) installed (S5U1C88000H5). selections affect IC's mask option. OSC1 SYSTEM CLOCK
Internal Clock User Clock When User Clock selected, input clock OSC1 terminal. When Internal Clock selected, clock frequency changed according oscillation circuit selected IC's mask option. When User Clock selected, input clock OSC3 terminal. When Internal Clock selected, clock frequency changed according oscillation circuit selected IC's mask option.
OSC3 SYSTEM CLOCK
Internal Clock User Clock
S1C88816 mask option list
following shows option list generating IC's mask pattern. Note that Peripheral Circuit Board installed does support some options.
OSC1 SYSTEM CLOCK Crystal External Clock Crystal (with Gate Capacity) OSC3 SYSTEM CLOCK Crystal Ceramic External Clock MULTIPLE ENTRY RESET Combination K00, K00, K01, K00, K01, K02, RESET circuit function that generates initial reset signal when supply voltage drops level less. mask option used select whether this function used not. Refer Section 5.14, "Supply Voltage Detection (SVD) Circuit", details. Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct This mask option select whether pull-up resistor input port terminal used not. possible select each input ports. Refer Section 5.4, "Input Ports ports)", details. Furthermore, pull-up option also provided RESET terminal. specification OSC1 oscillation circuit selected from among four types: "Crystal oscillation", oscillation", "Crystal oscillation (gate capacitor built-in)" "External clock input". Refer Section 5.3.3, "OSC1 oscillation circuit", details. specification OSC3 oscillation circuit selected from among four types: "Crystal oscillation", "Ceramic oscillation", oscillation" "External clock input". Refer Section 5.3.4, "OSC3 oscillation circuit", details. This function resets when several keys pressed simultaneously. mask option used select whether this function used not. Further when function used, combination input ports (K00-K03), which connected keys pressed simultaneously, selected. Refer Section 4.1.2, "Simultaneous level input input port terminals K00-K03", details.
INPUT PORT PULL RESISTOR With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor RESET With Resistor
S1C88816 TECHNICAL MANUAL
EPSON
INTRODUCTION
PORT PULL RESISTOR With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor
Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct
This mask option select whether pull-up resistor port terminal works during input mode) used not. possible select each ports. Refer Section 5.6, "I/O Ports ports)", details. Since shared with serial interface terminals, selected terminal configuration applied serial input (SIN) terminal serial clock input terminal (SCLK clock synchronous mode) when serial interface used. Refer Section 5.7, "Serial Interface", details.
DRIVE DUTY 1/32 1/16 Duty Duty POWER SUPPLY Internal TYPE (VC2 Standard, Bias, External Internal TYPE (VC2 Standard, Bias, Internal TYPE (VC2 Standard, Bias, Internal TYPE (VC1 Standard, Bias, OUTPUT (R51) TOUT OUTPUT (R26) MODE Maximum Mode Minimum Mode
drive duty built-in driver selected whether will 1/32 1/16 software-switched fixed 1/8. Refer Section 5.11, "LCD Controller", details. Either internal power supply external power supply selected system power source. Furthermore, when using internal power supply, drive voltage panel panel drive bias 1/4. Refer Section 5.11, "LCD Controller", details. port configured general purpose output port output port inverted output). Refer Section 5.5, "Output Ports ports)" details. port configured general purpose output port TOUT output port (TOUT inverted output). Refer Section 5.5, "Output Ports ports)" details. mode S1C88 core select either maximum mode minimum mode (fixed after selection). maximum mode, since S1C88816 saves program counter (PC), system condition flag (SC) code bank register (CB) values into stack when interrupt generated, program sequence able return previous bank interrupt handler routines change banks without saving. minimum mode selected only when program code size less than bytes "Compact code" model specified using EPSON Compiler. Since subroutine call minimum mode accesses stack area with 2-byte address bytes maximum mode), better RAM-access efficiency process-cycle time than maximum mode. This option allows selection whether heavy load protection mode when buzzer (BZ) signal output. When direct driving piezoelectric buzzer, select Normal mode reduce current consumption. When using external bipolar transistor, select Heavy load protection mode. Refer Section 2.3, "Heavy Load Protection Mode", details. This option allows selection whether heavy load protection mode when melody (MOUT) signal output. When direct driving piezoelectric buzzer, select Normal mode reduce current consumption. When using external bipolar transistor, select Heavy load protection mode. Refer Section 2.3, "Heavy Load Protection Mode", details.
MODE DURING BUZZER OUTPUT Normal Mode Heavy Load Protection Mode
MODE DURING MELODY OUTPUT Normal Mode Heavy Load Protection Mode
EPSON
S1C88816 TECHNICAL MANUAL
POWER SUPPLY
POWER SUPPLY
this section, will explain operating voltage configuration internal power supply circuit S1C88816.
Operating Voltage
S1C88816 operating power voltage follows: Normal mode: power mode: High speed mode: supply voltage drops below level (see Chapter "ELECTRICAL CHARACTERISTICS"), system automatically reset supply voltage detection (SVD) circuit described latter. This function selected mask option.
voltage selected from following three types: low-power mode, normal mode high-speed mode. should selected program switch according supply voltage oscillation frequency. Section 5.3, "Oscillation Circuits Operating Mode", switching operating mode. oscillation system voltage regulator generates operating voltage <VOSC> OSC1 oscillation circuit. system power supply circuit generates drive voltages <VC1> <VC5>. bias mode, generated halving output from system voltage regulator generated boosting VC2. These five voltages supplied from outside mask option. Chapter "ELECTRICAL CHARACTERISTICS" voltage values. S1C88816, drive voltage supplied built-in driver which drives panel connected terminals.
Internal Power Supply Circuit
S1C88816 incorporates power supply circuit shown Figure 2.2.1. When voltage within range described above supplied (GND), voltages needed internal circuit generated internally Roughly speaking, power supply circuit divided into three sections. internal logic voltage regulator generates operating voltage <VD1> driving internal logic circuits OSC3 oscillation circuit.
External power supply
Note: voltages output from internal power supply circuit driving external circuits.
Internal voltage setting circuit
Internal logic voltage regulator
OSC3 oscillation circuit Internal circuit
OSC3, OSC4
VOSC
Oscillation system VOSC voltage regulator system voltage regulator
OSC1 oscillation circuit
OSC1, OSC2
system voltage booster/ reducer circuit
VC1, VC3-VC5
driver
COM0-COM15 COM16-COM31/SEG87-SEG72 SEG0-SEG71
When standard bias selected.
Fig. 2.2.1 Configuration power supply circuit (VC2 standard, bias)
S1C88816 TECHNICAL MANUAL
EPSON
POWER SUPPLY
Heavy Load Protection Mode
S1C88816 heavy load protection function stable operation even when supply voltage fluctuates driving heavy load. heavy load protection mode becomes valid when peripheral circuits following status: When OSC3 oscillation circuit (OSCC SLEEP) When buzzer output (BZON BZSHT "1") When melody output (MBUSY "1") conditions selected mask option. Heavy load protection mode during buzzer output Normal mode Heavy load protection mode Heavy load protection mode during melody output Normal mode Heavy load protection mode When direct driving piezoelectric buzzer with buzzer (BZ, melody signal (MOUT, MOUT), select Normal mode reduce current consumption. When driving external bipolar transistor with MOUT signal, select Heavy load protection mode. When using melody output terminal (MOUT, MOUT) buzzer output, select same option both buzzer melody outputs. details OSC3 oscillation circuit, buzzer output melody output, refer "5.3 Oscillation Circuits Operating Mode", "5.12 Sound Generator" "5.13 Melody Generator", respectively.
SLEEP status OSCC BZON BZSHT MBUSY Mask option Heavy load protection mode
Fig. 2.3.1 Configuration heavy load protection mode control circuit
EPSON
S1C88816 TECHNICAL MANUAL
MEMORY CONFIGURATION
MEMORY CONFIGURATION
this section, will explain memory configuration.
S1C88816 utilize S1C88 8-bit core whose resistor configuration, command set, etc. virtually identical other units family processors incorporating S1C88. "S1C88 Core Manual" S1C88. S1C88816 supports Model 3/minimum mode S1C88 which allows accessing internal memory mapped within physical space from 000000H 01FFFFH.
3.2.1
internal capacity shown below. Capacity: 116K bytes Address: 000000H 00CFFFH 010000H 01FFFFH
3.2.2
internal capacity shown below. Capacity: bytes Address: 00D800H 00F7FFH
Internal Memory
S1C88816 equipped with internal shown Figure 3.2.1.
01FFFFH
3.2.3 memory
memory mapped method employed S1C88816 interfacing with internal peripheral circuit. Peripheral circuit control bits data register arranged data memory space. Control data exchange conducted normal memory access. memory arranged from address 00FF00H address 00FFFFH. Section 5.1, "I/O Memory Map", details memory.
(64K bytes)
010000H 00FFFFH 00FF00H 00FD57H 00F800H 00F7FFH 00D800H 00D7FFH 00D200H 00D1FFH 00D100H 00D0FFH 00D000H 00CFFFH
memory Display memory bytes) Unused area Melody note Melody scale (52K bytes)
3.2.4 Display memory
S1C88816 equipped with internal display memory which stores display data driver. display memory arranged from address 00F800H address 00FD57H (including unused area). Section 5.11, "LCD Controller", details display memory.
Exception Processing Vectors
Address 000000H address 000027H program area S1C88816 assigned exception processing vectors. Furthermore, from address 00002AH address 0000FFH, software interrupt vectors assignable bytes which begin with even address. Table 3.3.1 lists vector addresses exception processing factors which they correspond.
000000H
Fig. 3.2.1 Internal memory
S1C88816 TECHNICAL MANUAL
EPSON
MEMORY CONFIGURATION
Table 3.3.1 Vector addresses exception processing factors
Vector address 000000H 000002H 000004H 000006H 000008H 00000AH 00000CH 00000EH 000010H 000012H 000014H 000016H 000018H 00001AH 00001CH 00001EH 000020H 000022H 000024H 000026H 000028H 00002AH 0000FEH Exception processing factor Reset Zero division Watchdog timer (NMI) Programmable timer interrupt Programmable timer interrupt input interrupt K04-K07 input interrupt K00-K03 input interrupt Serial error interrupt Serial receiving complete interrupt Serial transmitting complete interrupt Stopwatch timer interrupt Stopwatch timer interrupt Stopwatch timer interrupt Clock timer interrupt Clock timer interrupt Clock timer interrupt Clock timer interrupt conversion complete interrupt Melody play complete interrupt System reserved (cannot used) Software interrupt Priority High
(Customized Condition Flag)
S1C88816 does customized condition flag (CC) core CPU. Accordingly, cannot used branching condition conditional branching instruction (JRS, CARS).
priority rating
each vector address address after start address exception processing routine written into subordinate super ordinate sequence. When exception processing factor generated, exception processing routine executed starting from recorded address. When multiple exception processing factors generated same time, execution starts with highest priority item. priority sequence shown Table 3.3.1 assumes that interrupt priority levels same. interrupt priority levels software each system. (See Section 5.16, "Interrupt Standby Status".)
Note: exception processing other than reset, (system condition flag) (program counter) evacuated stack branches exception processing routines. Consequently, when returning main routine from exception processing routines, please RETE instruction.
"S1C88 Core Manual" information operations when exception processing factor generated.
EPSON
S1C88816 TECHNICAL MANUAL
INITIAL RESET
INITIAL RESET
Initial reset S1C88816 required order initialize circuits. This chapter describes initial reset factors initial settings internal registers.
Initial Reset Factors
There three initial reset factors S1C88816 shown below. RESET terminal Simultaneous level input input port terminals K00-K03 Supply voltage detection (SVD) circuit Figure 4.1.1 shows configuration initial reset circuit. peripheral circuits initialized means initial reset factors. When factor canceled, commences reset exception processing. (See "S1C88 Core Manual".) When this occurs, reset exception processing vectors, Bank 000000H-000001H from program memory read program (initialization routine) which begins readout address executed.
Input port Input port Input port Input port Time authorize circuit
SLEEP status Oscillation stability waiting signal
Internal initial reset
RESET Supply voltage detection (SVD) circuit
Mask option
Fig. 4.1.1 Configuration initial reset circuit
4.1.1 RESET terminal
Initial reset done executed externally inputting level RESET terminal. sure maintain RESET terminal level regulation time after power assure initial reset. addition, sure RESET terminal first initial reset after power turned RESET terminal equipped with pull-up resistor. select whether mask option. RESET terminal pull-up resistors RESET With resistor Gate direct
4.1.2 Simultaneous level input input port terminals K00-K03
Another executing initial reset externally input level simultaneously input ports (K00-K03) selected mask option. Since there built-in time authorize circuit, sure maintain designated input port terminal level seconds (when oscillation frequency fOSC1 32.768 kHz) more perform initial reset means this function. However, time authorize circuit bypassed during SLEEP (standby) status oscillation stabilization waiting period, initial reset executed immediately after simultaneous level input designated input ports. combination input ports (K00-K03) that selected mask option follows: Multiple entry reset
S1C88816 TECHNICAL MANUAL
EPSON
INITIAL RESET
instance, mask option "K00 K03" selected, initial reset will take place when input level input ports K00-K03 simultaneously LOW. When using this function, make sure that designated input ports simultaneously switch level while system normal operation.
4.1.4 Initial reset sequence
After cancellation level input RESET terminal, when power turned start-up held back until oscillation stabilization waiting time (8,192/fOSC1 sec.) elapsed. When initial reset circuit been used, initial sampling time (248/fOSC1 sec.) added additional waiting time. Figure 4.1.4.1 shows operating sequence following initial reset release. Also, when using initial reset simultaneous level input into input port, should careful following points. During SLEEP status, since time authorization circuit bypassed, initial reset triggered immediately after level simultaneous input value. this case, starts after waiting oscillation stabilization time circuit initial sampling time (when used with mask option), following cancellation level simultaneous input. Other than during SLEEP status, initial reset will triggered seconds after level simultaneous input. this case, since reset differential pulse (64/fOSC1 sec.) generated within S1C88816, will start even level simultaneous input status canceled.
4.1.3 Supply voltage detection (SVD) circuit
When circuit detects that supply voltage dropped below level four successive times (see Chapter "ELECTRICAL CHARACTERISTICS"), outputs initial reset signal until supply voltage been restored level select whether initial reset according circuit mask option. supply voltage must least level first sampling circuit, when power turned this time, power voltage level less than level initial reset status will canceled instead circuit will continue sampling until supply voltage reaches level more. more information, "5.14 Supply Voltage Detection (SVD) Circuit" this Manual.
fOSC1 RESET Internal initial reset Internal address Internal data Internal read signal
8192/fOSC1 [sec] Oscillation stable waiting time 248/fOSC1 [sec] First sampling time Dummy cycle Reset exception processing
00-0000
Dummy
Dummy
VECL
When initial reset circuit with mask option been used, this cycle inserted waiting time.
Fig. 4.1.4.1 Initial reset sequence
EPSON
S1C88816 TECHNICAL MANUAL
INITIAL RESET
Initial Settings After Initial Reset
internal registers initialized follows during initial reset. Table 4.2.1 Initial settings
Register name Data register Data register Index (data) register Index (data) register Index register Index register Program counter Stack pointer Base register Zero flag Carry flag Overflow flag Negative flag Decimal flag Unpack flag Interrupt flag Interrupt flag code bank register Code bank register Expand page register Expand page register Expand page register
Code length Setting value
Programming Note
interrupts including masked until value written both addresses "00FF00H" "00FF01H". release interrupt mask, data must written addresses 00FF00H 00FF01H initial routine. Write 00FF00H change value after writing. value written from 00FF00H bits 00FF01H.
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Reset exception processing loads preset values stored bank, 000000H-000001H into same time, initial value loaded into Initialize registers which initialized initial reset using software. Since internal display memory initialized initial reset, sure initialize using software. respectively stipulated initializations done internal peripheral circuits. necessary, initialization should done using software. initial value initial reset, sections memory peripheral circuit descriptions following chapter this Manual.
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
PERIPHERAL CIRCUITS THEIR OPERATION
peripheral circuits S1C88816 interfaced with means memory mapped method. this reason, just with other memory access operations, peripheral circuits controlled manipulating memory. Below description operation control method each individual peripheral circuit.
Memory
Table 5.1.1(a) Memory (00FF00H-00FF10H)
Address Name 00FF00 BSMD1 BSMD0 CEMD1 CEMD0 00FF01 SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0 00FF02 CLKCHG OSCC VDC1 Function General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register operating clock switch OSC3 oscillation On/Off control Operating mode selection VDC1 VDC0 Operating mode High speed (VD1=3.3V) power (VD1=1.3V) Normal (VD1=2.2V)
dots 1/16 duty dots 1/32 duty
OSC3
OSC1
Comment Reserved register Reserved register Reserved register
VDC0
00FF10
LCCLK LCFRM DTFNT LDUTY SGOUT
General-purpose register General-purpose register font selection drive duty selection General-purpose register
Constantly when being read
Reserved register Reserved register
When duty been selected mask option, setting this register becomes invalid. Always BSMD1 BSMD0 "0".
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(b) Memory (00FF11H-00FF22H)
Address Name Function
Comment
when being read
00FF11 DSPAR display memory area selection LCDC1 display control LCDC1 LCDC0 display LCDs LCDs Normal display Drive
Display area Display area
These bits reset when
LCDC0
instruction
executed.
00FF12
contrast adjustment Contrast Dark Light
Constantly when being read
SVDSP auto-sampling control SVDON continuous sampling control/status 00FF20 00FF21 SVD3 SVD2 SVD1 SVD0 PK01 PK00 PSIF1 PSIF0 PSW1 PSW0 PTM1 PTM0 PPT1 PPT0 PK11 detection level
SVD3 SVD2 SVD1 SVD0 Detection level Level Level Level
These registers
reset when
Busy
Ready
10*1 instruction
K00-K07 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register Programmable timer interrupt priority register
PPT1 PPT0 PK11 PK10 Priority level Level Level Level Level PK01 PSIF1 PSW1 PTM1 PK00 PSIF0 PSW0 Priority PTM0 level Level Level Level Level
interrupt priority register PK10 00FF22 ESW100 Stopwatch timer interrupt enable register ESW10 Stopwatch timer interrupt enable register ESW1 ETM32 ETM8 ETM2 ETM1 Stopwatch timer interrupt enable register Clock timer interrupt enable register Clock timer interrupt enable register Clock timer interrupt enable register Clock timer interrupt enable register
executed.
Constantly when being read
when being read
Interrupt enable
Interrupt disable
After initial reset, this status until conclusion hardware first sampling. Initial values according supply voltage detected first sampling hardware. Until conclusion first sampling, SVD0-SVD3 data undefined.
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(c) Memory (00FF23H-00FF2CH)
Address Name Function Programmable timer interrupt enable register Programmable timer interrupt enable register interrupt enable register K04-K07 interrupt enable register K00-K03 interrupt enable register
Interrupt enable Interrupt disable
Comment
00FF23 EPT1 EPT0 EK0H EK0L
ESERR Serial (error) interrupt enable register ESREC Serial (receiving) interrupt enable register ESTRA Serial (transmitting) interrupt enable register 00FF24 FSW100 Stopwatch timer interrupt factor flag FSW10 Stopwatch timer interrupt factor flag FSW1 Stopwatch timer interrupt factor flag FTM32 FTM8 FTM2 FTM1 00FF25 00FF28 00FF2A FPT1 FPT0 FK0H FK0L FSERR FSREC FSTRA PADC1 PADC0 PMDY1 PMDY0 EMDY Clock timer interrupt factor flag Clock timer interrupt factor flag Clock timer interrupt factor flag Clock timer interrupt factor flag Programmable timer interrupt factor flag Programmable timer interrupt factor flag interrupt factor flag K04-K07 interrupt factor flag K00-K03 interrupt factor flag Serial (error) interrupt factor flag Serial (receiving) interrupt factor flag Serial (transmitting) interrupt factor flag converter interrupt priority register Melody interrupt priority register converter interrupt enable register Melody interrupt enable register converter interrupt factor flag Melody interrupt factor flag
Interrupt factor generated Reset Interrupt factor generated interrupt factor generated operation interrupt factor generated
when being read
Constantly when being read
Reset
operation Priority level Level Level Level Level Interrupt disable
PADC1 PADC0 PMDY1 PMDY0 Interrupt enable
Constantly when being read
00FF2C FMDY
Generated generated Reset operation
Constantly when being read
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(d) Memory (00FF30H-00FF34H)
Address 00FF30 Name Function
16-bit Timer fOSC3 fOSC3 Event counter Pulse width measurement
8-bit Timer fOSC1 fOSC1 Timer Normal mode Without
Comment
Constantly when being read
MODE16 8/16-bit mode selection CHSEL TOUT output channel selection PTOUT TOUT output control CKSEL1 Prescaler source clock selection CKSEL0 Prescaler source clock selection 00FF31 EVCNT Timer counter mode selection FCSEL Timer function selection timer mode event counter mode PLPOL Timer
With
noise rejector noise rejector
PSC01
Down count timing Rising edge event counter mode input High level pulse width measurement measurement mode input Timer prescaler dividing ratio selection pulse polarity selection PSC01 PSC00 Prescaler dividing ratio Source clock Source clock Source clock
Continuous Preset
Falling edge input level measurement input
PSC00
Source clock CONT0 Timer continuous/one-shot mode selection PSET0 Timer preset PRUN0 Timer Run/Stop control 00FF32 PSC11 Timer prescaler dividing ratio selection PSC11 PSC10 Prescaler dividing ratio Source clock 00FF33 00FF34 CONT1 PSET1 PRUN1 RLD07 RLD06 RLD05 RLD04 RLD03 RLD02 RLD01 RLD00 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 Source clock Source clock Source clock
One-shot operation Stop
when being read
Constantly when being read
PSC10
Timer continuous/one-shot mode selection Timer preset Timer Run/Stop control Timer reload data (MSB) Timer reload data Timer reload data Timer reload data Timer reload data Timer reload data Timer reload data Timer reload data (LSB) Timer reload data (MSB) Timer reload data Timer reload data Timer reload data Timer reload data Timer reload data Timer reload data Timer reload data (LSB)
Continuous Preset
One-shot operation Stop
when being read
High
High
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(e) Memory (00FF35H-00FF43H)
Address Name Function Timer counter data (MSB) Timer counter data Timer counter data Timer counter data Timer counter data Timer counter data Timer counter data Timer counter data (LSB) Timer counter data (MSB) Timer counter data Timer counter data Timer counter data Timer counter data Timer counter data Timer counter data Timer counter data (LSB) FOUT frequency selection
FOUT2 FOUT1 FOUT0 Frequency High
Comment
00FF35 PTD07 PTD06 PTD05 PTD04 00FF36 00FF40 PTD03 PTD02 PTD01 PTD00 PTD17 PTD16 PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 FOUT2
High
when being read
FOUT1
FOUT0
fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3
Reset Reset operation operation Stop
00FF41 00FF42 00FF43
FOUTON WDRST TMRST TMRUN TMD7 TMD6 TMD5 TMD4 TMD3 TMD2 TMD1 TMD0 SWRST SWRUN SWD7 SWD6 SWD5 SWD4 SWD3 SWD2 SWD1 SWD0
FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Stopwatch timer reset Stopwatch timer Run/Stop control Stopwatch timer data (1/10 sec) Stopwatch timer data (1/100 sec)
High
Reset
operation Stop
Constantly when being read
Constantly when being read
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(f) Memory (00FF44H-00FF47H)
Address Name Function One-shot buzzer forcibly stop One-shot buzzer trigger/status One-shot buzzer duration width selection Envelope attenuation time Envelope reset Envelope On/Off control Buzzer output control Buzzer signal duty ratio selection
DUTY2-0
Comment
Constantly when
00FF44 BZSTP BZSHT 00FF45 SHTPW ENRENRST ENON BZON DUTY2
Forcibly stop operation
Busy Trigger msec Reset
Ready operation 31.25 msec operation
being read when being read
when being read
DUTY1
Buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3
DUTY0
8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16
8/20 12/24 12/28 7/20 11/24 11/28 6/20 10/24 10/28 5/20 9/24 9/28 4/20 8/24 8/28 3/20 7/24 7/28 2/20 6/24 6/28 1/20 5/24 5/28
BZFQ2
Buzzer frequency selection
BZFQ2 BZFQ1 BZFQ0 Frequency (Hz)
when being read
BZFQ1
BZFQ0
4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3
00FF46 00FF47
MCAD7 MCAD6 MCAD5 MCAD4 MCAD3 MCAD2 MCAD1 MCAD0 MTT3
Note/scale address (MSB) Note/scale address Note/scale address Note/scale address Note/scale address Note/scale address Note/scale address Note/scale address (LSB) Tempo selection register
MTT3 MTT2 MTT1 MTT0 Tempo 68.6 53.3 43.6 36.9 34.3 shot MOUT Busy Play Level hold priority Ready Stop
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
MTT2
MTT1
MTT0
MLEV MOSEL MBUSY
Play mode selection Output selection Melody play status Melody output control
MOUTSEL
Reset during one-shot output.
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(g) Memory (00FF48H-00FF51H)
Address 00FF48 SCS1 Name Parity enable register Parity mode selection Clock source selection SCS1 SCS0 Clock source Programmable timer SMD1 fOSC3 fOSC3 fOSC3 Function
With parity
parity Even
Comment
when being read
Only asynchronous mode clock synchronous slave mode, external clock
SCS0
selected.
Serial mode selection SMD1 SMD0 Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master
Serial port error operation error operation error operation Stop operation Disable Stop operation Disable
SMD0
ESIF 00FF49
Serial enable register Framing error flag Parity error flag Overrun error flag
RXTRG Receive trigger/status RXEN Receive enable TXTRG Transmit trigger/status 00FF4A 00FF50 00FF51
Error Reset Error Reset Error Reset Trigger Enable Trigger Enable
when being read
Only asynchronous mode
TXEN TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 SIK07 SIK06 SIK05 SIK04 SIK03 SIK02 SIK01 SIK00 SIK11 SIK10
Transmit enable Transmit/Receive data (MSB) Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data (LSB) interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register General-purpose register interrupt selection register
High
Interrupt enable
Interrupt disable
Enable
Disable
Constantly when being read
Reserved register
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(h) Memory (00FF52H-00FF61H)
Address Name Function input comparison register input comparison register input comparison register input comparison register input comparison register input comparison register input comparison register input comparison register General-purpose register input comparison register input port data input port data input port data input port data input port data input port data input port data input port data input port data control register control register control register control register control register control register control register control register control register control register control register control register control register control register control register control register
Output Input Interrupt generated falling edge Interrupt generated rising edge
Comment
00FF52 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 00FF53 KCP11 KCP10 00FF54 00FF55 00FF60 K07D K06D K05D K04D K03D K02D K01D K00D K10D IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01
Constantly when being read
Falling edge Rising edge
Reserved register
High level input
level input
High level
level
Constantly when being read
when being read
Output
Input
IOC00 00FF61 IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(i) Memory (00FF62H-00FF75H)
Address Name port data port data port data port data port data port data port data port data port data port data port data port data port data port data port data port data high impedance control high impedance control General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register high impedance control high impedance control General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register high impedance control General-purpose register General-purpose register General-purpose register General-purpose register output port data output port data General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register
Hi-Z Output
Function
Comment
00FF62 P07D P06D P05D P04D P03D P02D P01D P00D 00FF63 P17D P16D P15D P14D P13D P12D P11D P10D 00FF70 00FF71 HZR51 HZR50 HZR4H HZR4L HZR1H HZR1L HZR0H HZR0L HZR27 HZR26 HZR25 HZR24 HZR23 HZR22 HZR21 HZR20
High
High
Reserved register Reserved register Reserved register Reserved register
Hi-Z
Output
00FF72 HZR37 HZR36 HZR35 HZR34 HZR33 HZR32 HZR31 HZR30
Hi-Z
Output
00FF75 R27D R26D R25D R24D R23D R22D R21D R20D
High
Reserved register
when TOUT output selected mask option.
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(j) Memory (00FF76H-00FF82H)
Address 00FF76 00FF78 00FF80 Name R37D R36D R35D R34D R33D R32D R31D R30D R51D R50D PRAD PSAD2 Function General-purpose register General-purpose register General-purpose register output port data General-purpose register General-purpose register General-purpose register General-purpose register output port data output port data converter clock control converter division ratio
PSAD2 PSAD1 PSAD0 Division ratio
Comment
High
Reserved register Reserved register
High
Constantly when being read
Constantly when being read
PSAD1
PSAD0
fOSC1 fOSC3 fOSC3 fOSC3 fOSC3 fOSC3 fOSC3 fOSC3
converter input Start Invalid port
00FF81 00FF82
PAD7 PAD6 PAD5 PAD4 ADRUN CHS1
CHS0
converter input control converter input control converter input control converter input control conversion start control register Analog input channel selection CHS1 CHS0 Input channel
Constantly when being read
Constantly when being read
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(k) Memory (00FF83H-00FF84H)
Address 00FF83 00FF84 Name ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Function conversion result (MSB) conversion result conversion result conversion result conversion result conversion result conversion result conversion result conversion result conversion result (LSB) Comment
Constantly when being read
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Watchdog Timer)
Watchdog Timer
5.2.1 Configuration watchdog timer
S1C88816 equipped with watchdog timer driven OSC1 source oscillation. watchdog timer must reset periodically software, reset more than seconds (when fOSC1 32.768 kHz) does take place, non-maskable interrupt signal generated output CPU. Figure 5.2.1.1 block diagram watchdog timer.
OSC1 oscillation circuit fOSC1 Divider
5.2.2 Interrupt function
cases where watchdog timer periodically reset software, watchdog timer outputs interrupt signal CPU's (level input. Unmaskable taking priority over other interrupts, this interrupt triggers generation exception processing. "S1C88 Core Manual" more details exception processing. This exception processing vector 000004H.
5.2.3 memory watchdog timer
Table 5.2.3.1 shows control bits watchdog timer.
Watchdog timer
Non-maskable interrupt (NMI)
WDRST
Watchdog timer reset signal
WDRST:
Resets watchdog timer. When written: Watchdog timer reset When written: operation Reading: Constantly writing WDRST, watchdog timer reset, after which immediately restarted. Writing will mean operation. Since WDRST writing only, constantly during readout.
Fig. 5.2.1.1 Block diagram watchdog timer running watchdog timer reset during main routine program, possible detect program runaway watchdog timer processing been applied. Normally, this routine integrated points that regularly being processed. watchdog timer continues operate during HALT when HALT state continuous longer than seconds, shifts exception processing. During SLEEP, watchdog timer stopped.
5.2.4 Programming notes
watchdog timer must reset within 3-second cycles software. execute instruction msec after interrupt occurred (when fOSC1 32.768 kHz).
Table 5.2.3.1 Watchdog timer control bits
Address Name Function FOUT frequency selection
FOUT2 FOUT1 FOUT0 Frequency
Comment
when being read
00FF40 FOUT2
FOUT1
FOUT0
fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3
Reset Reset operation operation Stop
FOUTON WDRST TMRST TMRUN
FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control
Constantly when being read
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Oscillation Circuits Operating Mode)
Oscillation Circuits Operating Mode
5.3.1 Configuration oscillation circuits
S1C88816 twin clock system with internal oscillation circuits (OSC1 OSC3). OSC1 oscillation circuit generates 32.768 (Typ.) main clock OSC3 oscillation circuit generates sub-clock when some peripheral circuits (output port, serial interface programmable timer) high speed operation. Figure 5.3.1.1 shows configuration oscillation circuit.
OSC1 oscillation circuit Clock switch OSC3 oscillation circuit SLEEP status
Oscillation circuit control signal peripheral circuit (fOSC1) (CLK) some peripheral circuit (fOSC3) clock selection signal
5.3.3 OSC1 oscillation circuit
OSC1 oscillation circuit generates 32.768 (Typ.) system clock which utilized during speed operation (low power mode) peripheral circuits. Furthermore, even when OSC3 utilized system clock, OSC1 continues generate source clock clock timer stopwatch timer. This oscillation circuit stops when instruction executed. However, case circuit runninging this time, oscillation stopped synchronization with completion sampling. terms oscillation circuit types, either crystal oscillation, oscillation, crystal oscillation (gate capacitor built-in) external clock input selected with mask option. Figure 5.3.3.1 shows configuration OSC1 oscillation circuit.
SLEEP status OSC1 X'tal1 fOSC1
OSCC
CLKCHG
OSC2
Fig. 5.3.1.1 Configuration oscillation circuits initial reset, OSC1 oscillation circuit selected operating clock OSC3 oscillation circuit stopped state. ON/OFF switching OSC3 oscillation circuit switching system clock between OSC1 OSC3 controlled software. OSC3 circuit utilized when high speed operation some peripheral circuits become necessary. Otherwise, OSC1 should used generate operating clock OSC3 circuit placed stopped state order reduce current consumption.
Crystal oscillation circuit
SLEEP status OSC1 fOSC1 External clock N.C. OSC2
External clock input
OSC1
5.3.2 Mask option
OSC1 oscillation circuit Crystal oscillation circuit External clock input oscillation circuit Crystal oscillation circuit (gate capacitor built-in) OSC3 oscillation circuit Crystal oscillation circuit Ceramic oscillation circuit oscillation circuit External clock input terms oscillation circuit types OSC1, either crystal oscillation, oscillation, crystal oscillation (gate capacitor built-in) external clock input selected with mask option. terms oscillation circuit types OSC3, either crystal oscillation, ceramic oscillation, oscillation external clock input selected with mask option, same OSC1.
RCR1
fOSC1
OSC2
SLEEP status
oscillation circuit
SLEEP status OSC1
fOSC1
X'tal1 OSC2
Crystal oscillation circuit (gate capacitor built-in) Fig. 5.3.3.1 OSC1 oscillation circuit
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Oscillation Circuits Operating Mode)
When crystal oscillation selected, crystal oscillation circuit easily formed connecting crystal oscillator X'tal1 (Typ. 32.768 kHz) between OSC1 OSC2 terminals along with trimmer capacitor (5-30 between OSC1 terminal VSS. addition, gate capacitor built into circuit mask option. When oscillation selected, connect resistor (RCR1) between OSC1 OSC2 terminals. When external input selected, release OSC2 terminal input rectangular wave clock into OSC1 terminal.
When oscillation selected, oscillation circuit formed merely connecting resistor (RCR3) between OSC3 OSC4 terminals. When external input selected, release OSC4 terminal input rectangular wave clock into OSC3 terminal.
5.3.5 Operating mode
select three types operating modes using software, obtain stable operation good characteristics (operating frequency current consumption) over broad operation voltage. Here below indicated features respective modes. Normal mode (VDD V-5.5 This mode following initial reset. permits OSC3 oscillation circuit (Max. MHz) used also permits relative power operation. power mode (VDD V-5.5 This lower power mode than normal mode. makes ultra-low power consumption possible operation OSC1 oscillation circuit, although OSC3 circuit cannot used. High speed mode (VDD V-5.5 This mode permits higher speed operation than normal mode. Since OSC3 oscillation circuit (Max. MHz) used, should this mode, when require operation more. However, current consumption will increase relative normal mode.
5.3.4 OSC3 oscillation circuit
OSC3 oscillation circuit generates system clock when some peripheral circuits (output port, serial interface programmable timer) high speed operation. This oscillation circuit stops when instruction executed, OSCC register "0". terms oscillation circuit types, crystal oscillation, ceramic oscillation, oscillation external clock input selected with mask option. Figure 5.3.4.1 shows configuration OSC3 oscillation circuit.
OSC3
X'tal2 Ceramic
fOSC3
OSC4
Oscillation circuit control signal SLEEP status
Crystal/Ceramic oscillation circuit
OSC3 fOSC3 RCR3 Oscillation circuit control signal SLEEP status
OSC4
Using software switch over among above three modes meet your actual usage circumstances will make possible power system. example, will able reduce current consumption switching over normal mode when using OSC3 clock and, conversely, changing over power mode when using OSC1 clock (OSC3 oscillation circuit OFF).
oscillation circuit
OSC3 External clock N.C. OSC4 fOSC3
Oscillation circuit control signal SLEEP status
External clock input Fig. 5.3.4.1 OSC3 oscillation circuit When crystal ceramic oscillation circuit selected, crystal ceramic oscillation circuit formed connecting either crystal oscillator (X'tal2) combination ceramic oscillator (Ceramic) feedback resistor (Rf) between OSC3 OSC4 terminals connecting capacitors (CG2, CD2) between OSC3 terminal VSS, between OSC4 terminal VSS, respectively.
S1C88816 TECHNICAL MANUAL
Note: turn OSC3 oscillation circuit power mode. switch over operating mode (normal mode high speed mode) OSC3 oscillation circuit status, this will cause faulty operation. modes, power mode high speed mode application, with respect operating voltages. When oscillation selected OSC1 oscillation circuit, operating mode fixed normal mode stabilize oscillation frequency. Consequently, settings mode setting registers VDC0 VDC1 become invalid.
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Oscillation Circuits Operating Mode)
5.3.6 Switching clocks
either OSC1 OSC3 system clock switch over means software. save power turning OSC3 oscillation circuit while operating OSC1. When must operate OSC3, change high speed operation turning OSC3 oscillation circuit switching over system clock. this case, since several msec several msec necessary oscillation stabilize after turning OSC3 oscillation circuit should switch over clock after stabilization time elapsed. (The oscillation start time will vary somewhat depending oscillator externally attached parts. Refer oscillation start time example indicated Chapter "ELECTRICAL CHARACTERISTICS".)
When switching over from OSC3 OSC1, turn OSC3 oscillation circuit immediately following clock changeover. basic clock switching procedure described above, however, must also combine with changeover operating mode permit current consumption high speed operation. Figure 5.3.6.1 indicates status transition diagram operation mode clock changeover.
Note: When turning OSC3 oscillation circuit after switching operating mode, should allow minimum waiting time msec.
Program Execution Status
High speed mode OSCC=1 OSC1 OSC3 clock OSC1 OSCC=0
VDC0= VDC1=1 VDC0=0 VDC1=0
High speed mode CLKCHG=1 High speed mode OSC1 OSC1 OSC3 OSC3 clock OSC1 CLKCHG=0 clock OSC3
RESET Normal mode OSCC=1 OSC1 OSC3 clock OSC1 OSCC=0
VDC0=0 VDC1=0 VDC0=1 VDC1=0
Normal mode Normal mode CLKCHG=1 OSC1 OSC1 OSC3 OSC3 clock OSC1 CLKCHG=0 clock OSC3
power mode OSC1 OSC3 clock OSC1
Interrupt
HALT instruction
Interrupt (Input interrupt)
instruction
HALT status OSC1 OSC3 clock STOP
SLEEP status OSC1 OSC3 clock STOP
Standby Status
return destination from standby status becomes program execution status prior shifting standby status
Fig. 5.3.6.1 Status transition diagram operation mode clock changeover
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Oscillation Circuits Operating Mode)
5.3.7 memory oscillation circuit
Table 5.3.7.1 shows control bits oscillation circuits operating modes. Table 5.3.7.1 Oscillation circuit operating mode control bits
Address Name 00FF02 Function General-purpose register General-purpose register General-purpose register General-purpose register Comment
Reserved register
CLKCHG operating clock switch OSCC OSC3 oscillation On/Off control VDC1 Operating mode selection VDC1 VDC0 Operating mode High speed (VD1=3.3V) power (VD1=1.3V) Normal (VD1=2.2V)
OSC3
OSC1
VDC0
VDC1, VDC0:
Selects operating mode according supply voltage operating frequency. Table 5.3.7.2 shows correspondence between register preset values operating modes. Table 5.3.7.2 Correspondence between register preset values operating modes
Operating mode Normal mode power mode High speed mode VDC1 VDC0 Power voltage Operating frequency
CLKCHG:
Selects operating clock CPU. When written: OSC3 clock When written: OSC1 clock Reading: Valid When operating clock switched OSC3, CLKCHG should when clock switched OSC1, CLKCHG should "0". initial reset, CLKCHG (OSC1 clock).
2.4-5.5 (Max.) 1.8-5.5 (Max.) 3.5-5.5 (Max.)
voltage value where been made standard (GND). initial reset, this register (normal mode).
OSCC:
Controls settings OSC3 oscillation circuit. When written: OSC3 oscillation When written: OSC3 oscillation Reading: Valid When some peripheral circuits (output port, serial interface programmable timer) operated high speed, OSCC "1". other times, should order reduce current consumption. initial reset, OSCC (OSC3 oscillation OFF).
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Oscillation Circuits Operating Mode)
5.3.8 Programming notes
When high speed operation necessary, should operate peripheral circuits according setting outline indicate below. operating clock OSC1 OSC3 oscillation circuit (When OSC3 clock necessary some peripheral circuits.) Operating mode power mode Normal mode turn OSC3 oscillation circuit power mode. switch over operating mode (normal mode high speed mode) OSC3 oscillation circuit status, this will cause faulty operation. When turning OSC3 oscillation circuit after switching operating mode, should allow minimum waiting time msec. Since several msec several msec necessary oscillation stabilize after turning OSC3 oscillation circuit Consequently, should switch operating clock (OSC1 OSC3) after allowing sufficient waiting time once OSC3 oscillation goes (The oscillation start time will vary somewhat depending oscillator externally attached parts. Refer oscillation start time example indicated Chapter "ELECTRICAL CHARACTERISTICS".) When switching clock from OSC3 OSC1, sure switch OSC3 oscillation with separate instructions. Using single instruction process simultaneously cause malfunction CPU.
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
Input Ports ports)
5.4.1 Configuration input ports
S1C88816 equipped with input port bits (K00-K07 K10) which usable general purpose input port terminals with interrupt function. terminal doubles external clock (EVIN) input terminal programmable timer (event counter) with input port functions sharing input signal (See "5.10 Programmable Timer") Each input port equipped with pull-up resistor. mask option used select either "With resistor" "Gate direct" each input port. Figure 5.4.1.1 shows structure input port.
Mask option Input interrupt circuit KxxD Data
5.4.2 Mask option
Input port pull-up resistors With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct
Gate direct
Input ports K00-K07 equipped with pull-up resistors. mask option used select 'With resistor' 'Gate direct' each port (bit). 'With resistor' option rendered suitable purposes such push switch matrix input. When changing input terminal from level HIGH with built-in pull-up resistor, delay waveform rise time will occur depending time constant pull-up resistor load capacitance terminal. necessary appropriate wait time introduction input port. particular, special attention should paid scan matrix formation. Make this wait time amount time more calculated following expression.
Wait time (CIN load capacitance board) [sec] RIN: Pull resistance Max. value CIN: Terminal capacitance Max. value
Address
Fig. 5.4.1.1 Structure input port Each input port terminal directly connected three-state buffer data bus. Furthermore, input signal state instant input port readout read that form data.
When 'Gate direct' selected, pull-up resistor detached port rendered suitable purposes such slide switch input interfacing with other LSIs. this case, take care that floating state does occur input. unused input ports, select default setting "With resistor".
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
5.4.3 Interrupt function input comparison register
Input port K00-K07 equipped with interrupt function. These input ports divided into three groupings: K00-K03 (K0L), K04-K07 (K0H) (K1). Furthermore, interrupt generation condition each series terminals software. When interrupt generation condition each series terminals met, interrupt factor flag FK0L, FK0H corresponding applicable series interrupt generated.
Input port K00D Input comparison register KCP00 Address Interrupt selection register SIK00 Address
Interrupt prohibited setting interrupt enable registers EK0L, EK0H corresponding interrupt factor flags. Furthermore, priority level input interrupt desired level (0-3) using interrupt priority registers PK00-PK01 PK10- PK11 corresponding each groups (K00-K07) K10. details interrupt control registers above operations subsequent interrupt generation, "5.16 Interrupt Standby Status". exception processing vectors each interrupt factor follows: input interrupt: 00000AH K04-K07 input interrupt: 00000CH K00-K03 input interrupt: 00000EH Figure 5.4.3.1 shows configuration input interrupt circuit.
Interrupt factor flag FK0L Address Interrupt enable register EK0L Address Interrupt priority register PK00, PK01
Input port K04D Input comparison register KCP04 Address Interrupt selection register SIK04 Address
Interrupt priority level judgement circuit
Interrupt request
Address
Data
Interrupt factor flag FK0H Address Interrupt enable register EK0H Address
Input port K10D Input comparison register KCP10 Address Interrupt selection register SIK10 Address Address Interrupt enable register Address Interrupt priority level judgement circuit Interrupt priority register PK10, PK11 Address Interrupt request
Interrupt factor flag
Fig. 5.4.3.1 Configuration input interrupt circuit
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
interrupt selection registers SIK00-SIK03, SIK04-SIK07 SIK10 input comparison registers KCP00-KCP03, KCP04-KCP07 KCP10 each port used interrupt generation condition described above. Input port interrupt permitted prohibited setting interrupt selection register SIK. contrast interrupt enable register which masks interrupt factor each series terminals, interrupt selection register masks units. input comparison register selects whether interrupt each input port will generated rising edge falling edge input. When data content input terminals which interrupt been permitted interrupt selection register data content input comparison register change from conformity state non-conformity state, interrupt factor flag should interrupt generated. Figure 5.4.3.2 shows example interrupt generation series terminals (K00-K03).
Because interrupt been prohibited interrupt selection register SIK00, with settings shown (2), interrupt will generated. Since next settings figure, non-conformity between input terminal data K01-K03 where interrupt permitted data from input comparison registers KCP01- KCP03 generates interrupt. line with explanation above, since change contents input data input comparison registers from conformity state nonconformity state introduces interrupt generation condition, switching from non-conformity state another, case figure, will generate interrupt. Consequently, order able generate second interrupt, either input terminal must returned state where content once again conformity with that input comparison register KCP, input comparison register must reset. Input terminals which interrupt prohibited will influence interrupt generation condition. Interrupt generated exactly same other series terminals (K04-K07) (K10).
Interrupt selection register SIK03 SIK02 SIK01 SIK00
Input comparison register KCP03 KCP02 KCP01 KCP00
With settings shown above, interrupt (K00-K03) generated under condition shown below. Input port
(Initial values)
Interrupt generation Because interrupt been prohibited K00, interrupt will generated when non-conformity occurs between contents three bits K01-K03 three bits input comparison register KCP01-KCP03.
Fig. 5.4.3.2 Interrupt generation example (K00-K03)
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
5.4.4 memory input ports
Table 5.4.4.1 shows input port control bits. Table 5.4.4.1(a) Input port control bits
Address Name Function interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register General-purpose register interrupt selection register input comparison register input comparison register input comparison register input comparison register input comparison register input comparison register input comparison register input comparison register General-purpose register input comparison register input port data input port data input port data input port data input port data input port data input port data input port data input port data
High level level High level input level input Enable Disable Interrupt enable Interrupt disable
Comment
00FF50 SIK07 SIK06 SIK05 SIK04 SIK03 SIK02 SIK01 SIK00 00FF51 00FF52 00FF53 SIK11 SIK10 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 KCP11 KCP10
Constantly when being read
Reserved register
Interrupt generated falling edge
Interrupt generated rising edge
Constantly when being read
Falling edge Rising edge
Reserved register
00FF54 K07D K06D K05D K04D K03D K02D K01D K00D 00FF55 K10D
Constantly when being read
when being read
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
Table 5.4.4.1(b) Input port control bits
Address Name Function K00-K07 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register Programmable timer interrupt priority register interrupt priority register Programmable timer interrupt enable register Programmable timer interrupt enable register interrupt enable register K04-K07 interrupt enable register
Interrupt enable Interrupt disable PPT1 PPT0 PK11 PK10 Priority level Level Level Level Level PK01 PSIF1 PSW1 PTM1 PK00 PSIF0 PSW0 Priority PTM0 level Level Level Level Level
Comment
00FF20 PK01 PK00 PSIF1 PSIF0 PSW1 PSW0 PTM1 PTM0 00FF21 PPT1 PPT0 PK11 PK10 00FF23 EPT1 EPT0 EK0H
Constantly when being read
EK0L K00-K03 interrupt enable register ESERR Serial (error) interrupt enable register ESREC Serial (receiving) interrupt enable register ESTRA Serial (transmitting) interrupt enable register 00FF25 FPT1 Programmable timer interrupt factor flag FPT0 Programmable timer interrupt factor flag FK0H interrupt factor flag K04-K07 interrupt factor flag
Interrupt factor generated
interrupt factor generated
FK0L K00-K03 interrupt factor flag FSERR Serial (error) interrupt factor flag FSREC Serial (receiving) interrupt factor flag FSTRA Serial (transmitting) interrupt factor flag
Reset
operation
K00D-K07D: 00FF54H K10D:
Input data input port terminal read out. When read: When read: Writing: HIGH level level Invalid
SIK00-SIK07: 00FF50H SIK10:
Sets interrupt generation condition (interrupt permission/prohibition) input port terminals K00-K07 K10. When written: Interrupt permitted When written: Interrupt prohibited Reading: Valid SIKxx interrupt selection register which correspond input port Kxx. setting permits interrupt that input port prohibits Changes state input terminal which interrupt prohibited, will influence interrupt generation. initial reset, this register (interrupt prohibited).
terminal voltage each input port K00- directly read either HIGH (VDD) level (VSS) level. This exclusively readout usable write operations.
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
KCP00-KCP07: 00FF52H KCP10:
Sets interrupt generation condition (interrupt generation timing) input port terminals K00- K10. When written: Falling edge When written: Rising edge Reading: Valid KCPxx input comparison register which correspond input port Kxx. Interrupt those ports which have been generated falling edge input those rising edge. initial reset, this register (falling edge).
FK0L, FK0H, FK1:
Indicates generation state input interrupt. When read: When read: Interrupt factor present Interrupt factor present
When written: Reset factor flag When written: Invalid interrupt factor flag FK0L corresponds K00- K03, FK0H K04-K07, they occurrence interrupt generation condition. When this manner, corresponding interrupt enable register corresponding interrupt priority register higher level than setting interrupt flags I1), interrupt will generated CPU. Regardless interrupt enable register interrupt priority register settings, interrupt factor flag will occurrence interrupt generation condition. accept subsequent interrupt after interrupt generation, re-setting interrupt flags (set interrupt flag lower level than level indicated interrupt priority registers, execute RETE instruction) interrupt factor flag reset necessary. interrupt factor flag reset writing "1". initial reset, this flag reset "0".
PK00, PK01: PK10, PK11:
Sets input interrupt priority level. bits PK00 PK01 interrupt priority registers corresponding interrupts K00-K07 (K0L K0H). Corresponding (K1), bits PK10 PK11 perform same function. Table 5.4.4.2 shows interrupt priority level which this register. Table 5.4.4.2 Interrupt priority level settings
PK11 PK01 PK10 PK00 Interrupt priority level Level (IRQ3) Level (IRQ2) Level (IRQ1) Level (None)
5.4.5 Programming note
When changing input terminal from level HIGH with built-in pull-up resistor, delay waveform rise time will occur depending time constant pull-up resistor load capacitance terminal. necessary appropriate wait time introduction input port. particular, special attention should paid scan matrix formation. Make this wait time amount time more calculated following expression.
Wait time (CIN load capacitance board) [sec] RIN: Pull resistance Max. value CIN: Terminal capacitance Max. value
initial reset, this register (level
EK0L, EK0H, EK1:
interrupt generation permitted prohibited. When written: Interrupt permitted When written: Interrupt prohibited Reading: Valid interrupt enable register EK0L corresponds K00-K03, EK0H K04-K07, K10. Interrupt permitted those series terminals prohibited those "0". initial reset, this register (interrupt prohibited).
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATIO (Output Ports)
Output Ports ports)
5.5.1 Configuration output ports
S1C88816 equipped with bits output ports (R26, R27, R34, R51). Furthermore, bits melody output ports MOUT MOUT available. Figure 5.5.1.1 shows basic structure (excluding special melody output circuits) output ports. output specification each port fixed complementary output.
Address High impedance control register
5.5.3 High impedance control
output port high impedance controlled software. high impedance control register each output port terminal shown below. Either complementary output high impedance state selected with this register. HZR26: high impedance control register HZR27: high impedance control register HZR34: high impedance control register HZR50: high impedance control register HZR51: high impedance control register When high impedance control register HZRxx "1", corresponding output port terminal becomes high impedance state when "0", becomes complementary output.
Data
Data register
5.5.4 output
Figure 5.5.1.1 shows, when written output port data register, output terminal switches HIGH (VDD) level when written switches (VSS) level. When output high impedance state, data written data register output from terminal instant when output switched complementary.
Address
Fig. 5.5.1.1 Structure output ports Each output port into high impedance state software. Besides normal output, output ports have special output functions. R27, functions selected software functions selected mask option. Figure 5.5.1.2 shows basic structure melody output port. output specification fixed complementary output. This circuit high-impedance control function data register, driven melody generator directly.
5.5.5 Special output
Besides normal output, each output port also assigned special output function software (R27, R34, R50) mask option (R26, R51) shown Table 5.5.5.1. Table 5.5.5.1 Special output ports
Output port Special output TOUT output (mask option) TOUT output (software selection) FOUT output (software selection) output (software selection) output (mask option)
Melody generator
MOUT
Fig. 5.5.1.2 Structure melody output port
5.5.2 Mask option
output port specifications output TOUT output output output mask option allows selection special outputs output ports well output. port TOUT output port (TOUT signal inverted output) port output port (buzzer signal inverted output).
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Output Ports)
TOUT output (R27), TOUT output (R26) order S1C88816 provide clock signal external device, output port terminal used output TOUT signal (clock output programmable timer). Furthermore, output port terminal used output TOUT signal (TOUT inverted signal). configuration output ports shown Figure 5.5.5.1.
Register R27D Register PTOUT TOUT signal Register R26D Mask option output output
FOUT output (R34) order S1C88816 provide clock signal external device, FOUT signal (divided clock oscillation clock fOSC1 fOSC3) output from output port terminal R34. Figure 5.5.5.3 shows configuration output port R34.
Register R34D Register FOUTON FOUT signal output
Fig. 5.5.5.3 Configuration output control FOUT signal done register FOUTON. When FOUTON, FOUT signal output from output port terminal R34, when set, HIGH (VDD) level output. this time, must always data register R34D. frequency FOUT signal selected software setting registers FOUT0-FOUT2. frequency selected from among eight settings shown Table 5.5.5.2. Table 5.5.5.2 FOUT frequency setting
FOUT2 FOUT1 FOUT0 FOUT frequency fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3
Fig. 5.5.5.1 Configuration output control TOUT (TOUT) signals done register PTOUT. When PTOUT, TOUT (TOUT) signal output from (R26) output port terminal. When set, goes HIGH (VDD) goes (VSS). output TOUT signal, must always data register R27D. data register R26D does affect TOUT output. TOUT signal generated from programmable timer underflow signal halving frequency. With respect frequency control, "5.10 Programmable Timer". Since TOUT (TOUT) signal generated asynchronously from register PTOUT, when signal turned setting register, hazard cycle less generated. Figure 5.5.5.2 shows output waveform TOUT (TOUT) signal.
PTOUT TOUT output (R27) TOUT output (R26)
when selected mask option
fOSC1: OSC1 oscillation frequency fOSC3: OSC3 oscillation frequency When FOUT frequency made "fOSC3/n", must turn OSC3 oscillation circuit before outputting FOUT. time interval several msec several msec, from turning OSC3 oscillation circuit until oscillation stabilizes, necessary, oscillation element that used. Consequently, abnormality occurs result unstable FOUT signal being output externally, should allow adequate waiting time after turning OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending oscillator externally attached parts. Refer oscillation start time example indicated Chapter "ELECTRICAL CHARACTERISTICS".) initial reset, OSC3 oscillation circuit state.
Fig. 5.5.5.2 TOUT (TOUT) output waveform
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATIO (Output Ports)
Since FOUT signal generated asynchronously from register FOUTON, when signal turned register settings, hazard cycle less generated. Figure 5.5.5.4 shows output waveform FOUT signal.
FOUTON FOUT output (R34)
MOUT MOUT outputs MOUT MOUT output ports dedicated direct driving external piezoelectric buzzer with melody signal. These ports fixed complementary output cannot into highimpedance state. Also data register available. initial reset, MOUT MOUT terminals HIGH. "5.13 Melody Generator" melody output.
Fig. 5.5.5.4 Output waveform FOUT signal output (R50), output (R51) order S1C88816 drive external buzzer, signal (sound generator output) output from output port terminal R50. Furthermore, output port terminal used output signal inverted signal). configuration output ports shown Figure 5.5.5.5.
Register R50D signal Register BZSHT Register BZSTP One-shot time Register BZON output
Register R51D Mask option
output
Fig. 5.5.5.5 Configuration output control (BZ) signal done registers BZON, BZSHT BZSTP. When BZON BZSHT, (BZ) signal output from output port terminal (R51). When BZON BZSTP, goes (VSS) goes HIGH (VDD). output signal, must always data register R50D. data register R51D does affect output. (BZ) signal generated sound generator. With respect control frequency envelope, "5.12 Sound Generator". Since (BZ) signal generated asynchronously from registers BZON, BZSHT BZSTP, when signal turned setting registers, hazard cycle less generated. Figure 5.5.5.6 shows output waveform (BZ) signal.
BZON/BZSHT output (R50) output (R51)
when selected mask option
Fig. 5.5.5.6 (BZ) output waveform
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Output Ports)
5.5.6 memory output ports
Table 5.5.6.1 shows output port control bits. Table 5.5.6.1(a) Output port control bits
Address Name Function high impedance control
Hi-Z
Output
Comment
00FF70 HZR51
HZR50 high impedance control HZR4H General-purpose register HZR4L General-purpose register HZR1H General-purpose register HZR1L General-purpose register HZR0H General-purpose register HZR0L 00FF71 HZR27 HZR26 HZR25 HZR24 HZR23 HZR22 HZR21 HZR20 00FF72 HZR37 HZR36 HZR35 HZR34 HZR33 HZR32 HZR31 HZR30 00FF75 R27D R26D R25D R24D R23D R22D R21D R20D 00FF76 00FF78 R37D R36D R35D R34D R33D R32D R31D R30D R51D R50D General-purpose register high impedance control high impedance control General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register high impedance control General-purpose register General-purpose register General-purpose register General-purpose register output port data output port data General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register General-purpose register output port data General-purpose register General-purpose register General-purpose register General-purpose register output port data output port data
Reserved register
Hi-Z
Output
Reserved register
Hi-Z
Output
Reserved register Reserved register
High
Reserved register Reserved register Reserved register
High
High
Constantly when being read
when TOUT output selected mask option.
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATIO (Output Ports)
Table 5.5.6.1(b) Output port control bits
Address 00FF30 Name Function
16-bit Timer fOSC3 fOSC3
8-bit Timer fOSC1 fOSC1
Comment
Constantly when being read
MODE16 8/16-bit mode selection CHSEL TOUT output channel selection PTOUT TOUT output control CKSEL1 Prescaler source clock selection CKSEL0 Prescaler source clock selection 00FF40 FOUT2 FOUT frequency selection
FOUT2 FOUT1 FOUT0 Frequency
when being read
FOUT1
FOUT0
fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3
Reset Reset operation operation Stop
FOUTON FOUT output control WDRST Watchdog timer reset TMRST Clock timer reset TMRUN Clock timer Run/Stop control 00FF44 BZSTP One-shot buzzer forcibly stop BZSHT One-shot buzzer trigger/status
Constantly when being read
Constantly when
Forcibly stop operation Busy Trigger msec Reset Ready operation 31.25 msec operation
being read
SHTPW One-shot buzzer duration width selection ENREnvelope attenuation time ENRST Envelope reset ENON BZON Envelope On/Off control Buzzer output control
when being read
Reset during one-shot output.
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Output Ports)
High impedance control
Special output control
HZR26: HZR27: HZR34: HZR50: HZR51:
Sets output terminals high impedance state. When written: High impedance When written: Complementary Reading: Valid HZRxx high impedance control register which correspond output port terminal. When HZRxx register, corresponding output port terminal becomes high impedance state when set, becomes complementary output. This control effective even port special output port. initial reset, this register (complementary). output control
PTOUT:
Controls TOUT (programmable timer output clock) output TOUT (TOUT inverted signal) output. When written: TOUT/TOUT output When written: HIGH (DC) output [R27] (DC) output [R26] Reading: Valid PTOUT output control register TOUT TOUT signals. When register, TOUT (TOUT) signal output from output port terminal (R26). When set, goes HIGH (VDD) goes (VSS). output TOUT signal, must always data register R27D. data register R26D does affect TOUT output. TOUT signal output from only when function selected mask option. initial reset, PTOUT output).
FOUTON:
Controls FOUT (fOSC1/fOSC3 dividing clock) signal output. When written: FOUT signal output When written: HIGH level (DC) output Reading: Valid FOUTON output control register FOUT signal. When set, FOUT signal output from output port terminal when set, HIGH (VDD) level output. this time, must always data register R34D. initial reset, FOUTON (HIGH level output).
R26D: R27D: R34D: R50D: R51D:
Sets data output from output port terminal Rxx. When written: HIGH level output When written: level output Reading: Valid RxxD data register output port. When register, corresponding output port terminal goes HIGH (VDD), when set, goes (VSS). initial reset, R50D (LOW level output). other registers (HIGH level output). When and/or special outputs mask option, R26D and/or R51D used general-purpose registers that affect output status.
FOUT0, FOUT1, FOUT2:
FOUT signal frequency shown Table 5.5.6.2. Table 5.5.6.2 FOUT frequency settings
FOUT2 FOUT1 FOUT0 FOUT frequency fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3
fOSC1: OSC1 oscillation frequency fOSC3: OSC3 oscillation frequency
initial reset, this register (fOSC1/1).
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATIO (Output Ports)
BZON:
Controls buzzer signal output. When written: Buzzer signal output When written: LOW(DC) output [R50] HIGH (DC) output [R51] Reading: Valid BZON output control register buzzer signal. When register, (BZ) signal output from output port terminal (R51). When set, goes (VSS) goes HIGH (VDD). output signal, must always data register R50D. data register R51D does affect output. initial reset, BZON output). signal output from only when function selected mask option.
BZSTP:
Forcibly stops one-shot buzzer output. When written: Forcibly stop When written: operation Reading: Constantly writing into BZSTP, one-shot buzzer output stopped prior elapsing time with SHTPW. Writing invalid writing except during one-shot output also invalid. When written BZSHT BZSTP simultaneously, BZSTP takes precedence one-shot output becomes stop status. Since BZSTP writing only, during readout constantly "0".
5.5.7 Programming notes
Since special output signals (TOUT/TOUT, FOUT, BZ/BZ) generated asynchronously from output control registers (PTOUT, FOUTON, BZON, BZSHT BZSTP), when signals turned output control register settings, hazard cycle less generated. instruction executed when special output signals (TOUT,/TOUT, FOUT, BZ/BZ) enable status, unstable clock output special output time return from SLEEP state. Consequently, when shifting SLEEP state, should special output signal disable status prior executing instruction. When FOUT frequency made "fOSC3/n", must turn OSC3 oscillation circuit before outputting FOUT. time interval several msec several msec, from turning OSC3 oscillation circuit until oscillation stabilizes, necessary, oscillation element that used. Consequently, abnormality occurs result unstable FOUT signal being output externally, should allow adequate waiting time after turning OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending oscillator externally attached parts. Refer oscillation start time example indicated Chapter "ELECTRICAL CHARACTERISTICS".) initial reset, OSC3 oscillation circuit state.
BZSHT:
Controls one-shot buzzer output. When written: Trigger When written: operation When read: When read: Busy Ready
Writing into BZSHT causes one-shot output circuit operate. (BZ) signal output from (R51) terminal. buzzer output automatically turned after time SHTPW elapsed. output signal, must always data register R50D. data register R51D does affect output. one-shot output only valid when normal buzzer output (BZON "0") state. trigger invalid during (BZON "1") state. When re-trigger assigned during one-shot output, one-shot output time with SHTPW measured again from that point. (time extension) operation status one-shot output circuit confirmed reading BZSHT, when oneshot output read from BZSHTand when output OFF, read. initial reset, BZSHT (ready). signal output from only when function selected mask option.
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Ports)
Ports ports)
5.6.1 Configuration ports
S1C88816 equipped with bits ports (P00-P07 P10-P17). Figure 5.6.1.1 shows structure port.
5.6.2 Mask option
port pull-up resistors
With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct
control register Data Data register
Mask option
Input control During output mode During input mode
Fig. 5.6.1.1 Structure port ports input output mode unit. These settings performed writing data control registers. port terminals P10-P13 shared with serial interface input/output terminals P14- shared with converter input terminals. function terminals switchable software. details serial interface converter, "5.7 Serial Interface" "5.15 Converter", respectively. data registers control registers ports serial interface outputs usable general purpose registers with read/write capabilities which affect activities terminal. same above, control registers ports serial interface converter inputs usable general purpose register.
ports P00-P07 P10-P17 equipped with pull-up resistor which goes input mode. Whether this resistor used selected each port (one unit). cases where 'With resistor' option selected, pull-up resistor goes when port input mode. When changing port terminal from level HIGH with built-in pull-up resistor, delay waveform rise time will occur depending time constant pull-up resistor load capacitance terminal. necessary appropriate wait time introduction port. Make this wait time amount time more calculated following expression.
Wait time (CIN load capacitance board) [sec] RIN: Pull resistance Max. value CIN: Terminal capacitance Max. value
When converter used, select "Gate direct" ports (P14-P17) which then become input terminals. unused ports, select default setting "With resistor".
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATIO (I/O Ports)
5.6.3 control registers mode
ports P00-P07 P10-P17 either input output modes writing data control registers IOC00-IOC07 IOC10-IOC17 which correspond each bit. port input mode, write control register. port which input mode will shift high impedance state functions input port. Readout input mode consists simply direct readout input terminal state: data being when input terminal HIGH level when (VSS) level. When "With resistor" option selected using mask option, resistor pulled onto port terminal input mode.
Even input mode, data written data registers without affecting terminal state. port output mode, write control register. port which output mode functions output port. When port output data "1", HIGH (VDD) level output when "0", (VSS) level output. Readout output mode consists contents data register. initial reset, control registers (I/O ports input mode).
5.6.4 memory ports
Table 5.6.4.1 shows port control bits.
Table 5.6.4.1 port control bits
Address Name Function control register control register control register control register control register control register control register control register control register control register control register control register control register control register control register control register port data port data port data port data port data port data port data port data port data port data port data port data port data port data port data port data
High
Comment
00FF60 IOC07 IOC06 IOC05 IOC04 IOC03 IOC02
Output
Input
IOC01 IOC00 00FF61 IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 00FF62 P07D P06D P05D 00FF63 P04D P03D P02D P01D P00D P17D P16D P15D P14D P13D P12D P11D P10D
Output
Input
High
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (I/O Ports)
P00D-P07D: 00FF62H P10D-P17D: 00FF63H
port terminal data readout output data settings performed.
When writing data:
5.6.5 Programming note
When changing port terminal from level HIGH with built-in pull-up resistor, delay waveform rise time will occur depending time constant pull-up resistor load capacitance terminal. necessary appropriate wait time introduction port. Make this wait time amount time more calculated following expression.
Wait time (CIN load capacitance board) [sec] RIN: Pull resistance Max. value CIN: Terminal capacitance Max. value
When written: HIGH level When written: level When port output mode, data written output port terminal. terms port data, when written, port terminal goes HIGH (VDD) level when written (VSS) level. Even when port input mode, data still written
When reading data:
When read: When read:
HIGH level ("1") level ("0")
When port input mode, voltage level being input port terminal read out. When terminal voltage HIGH (VDD), read "1", when (VSS), read "0". Furthermore, output mode, contents data register read out. initial reset, this register (HIGH level). data registers ports output terminal serial interface used general purpose registers with read/write capabilities which affect activities terminals.
IOC00-IOC07: 00FF60H IOC10-IOC17: 00FF61H
Sets ports input output mode. When written: Output mode When written: Input mode Reading: Valid control register which correspond each port unit. Writing register will switch corresponding port output mode, writing will switch input mode. initial reset, this register (input mode). data registers ports input terminals serial interface converter used general purpose registers with read/write capabilities which affect activities terminals.
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Serial Interface)
Serial Interface
5.7.1 Configuration serial interface
S1C88816 incorporates full duplex serial interface (when asynchronous system selected) that allows user select either clock synchronous system asynchronous system. data transfer method selected software. When clock synchronous system selected, 8bit data transfer possible. When asynchronous system selected, either 7bit 8-bit data transfer possible, parity check received data addition parity transmitting data automatically done selecting software. Figure 5.7.1.1 shows configuration serial interface. Serial interface input/output terminals, SIN, SOUT, SCLK SRDY shared with ports P10-P13. order utilize these terminals serial interface input/output terminals, proper settings have made with registers ESIF, SMD0 SMD1. initial reset, these terminals port terminals.) direction port terminals serial interface input/output terminals determined signal transfer mode each terminal. Furthermore, settings corresponding control registers ports become invalid.
Table 5.7.1.1 Configuration input/output terminals
Terminal When serial interface selected SOUT SCLK SRDY
terminals used vary depending transfer mode.
SOUT serial data input output terminals which function identically clock synchronous system asynchronous system. SCLK exclusively with clock synchronous system functions synchronous clock input/ output terminal. SRDY exclusively clock synchronous slave mode functions sendreceive ready signal output terminal. When asynchronous system selected, since SCLK SRDY superfluous, port terminals used ports. same way, when clock synchronous master mode selected, since SRDY superfluous, port terminal used port.
Data
Serial control status register
Received data buffer
Error detection circuit
Interrupt control circuit
Interrupt request
SIN(P10)
Serial input control circuit
Received data shift register
Transmitting data shift register
Serial output control circuit
SOUT(P11)
Start detection circuit
SCLK(P12)
Clock control circuit
READY output control circuit fOSC3 OSC3 oscillation circuit Programmable timer underflow signal
SRDY(P13)
Fig. 5.7.1.1 Configuration serial interface
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Serial Interface)
5.7.2 Mask option
Since serial interface input/output terminals shared with ports, serial interface terminal specifications have necessarily been selected with mask option ports. port pull-up resistors (SIN) With resistor Gate direct (SCLK) With resistor Gate direct Each port terminal equipped with pull-up resistor which goes input mode. selection made each port (one unit) whether resistor will used. Specifications (whether pull-up will used not) (SIN) (SCLK) which will become input terminals when using serial interface decided settings options port. When "Gate direct" selected serial mode, sure that input terminals into floating state.
synchronous clock also output from SCLK terminal which enables control external (slave side) serial device. Since SRDY terminal utilized this mode, used port. Figure 5.7.3.1(a) shows connection example input/output terminals clock synchronous master mode. Clock synchronous slave mode this mode, synchronous clock from external (master side) serial input/output device utilized clock synchronous 8-bit serial transfers performed with this serial interface slave. synchronous clock input SCLK terminal utilized this interface synchronous clock. Furthermore, SRDY signal indicating transmit-receive ready status output from SRDY terminal accordance with serial interface operating status. slave mode, settings registers SCS0 SCS1 used select clock source invalid. Figure 5.7.3.1(b) shows connection example input/output terminals clock synchronous slave mode. Asynchronous 7-bit mode this mode, asynchronous 7-bit transfer performed. Parity check during data reception addition parity (odd/even/none) during transmitting specified data processed bits with without parity. Since this mode employs internal clock, SCLK terminal used. Furthermore, since SRDY terminal utilized either, both these terminals used ports. Figure 5.7.3.1(c) shows connection example input/output terminals asynchronous mode. Asynchronous 8-bit mode this mode, asynchronous 8-bit transfer performed. Parity check during data reception addition parity (odd/even/none) during transmitting specified data processed bits with without parity. Since this mode employs internal clock, SCLK terminal used. Furthermore, since SRDY terminal utilized either, both these terminals used ports. Figure 5.7.3.1(c) shows connection example input/output terminals asynchronous mode.
5.7.3 Transfer modes
There four transfer modes serial interface mode selection made setting bits mode selection registers SMD0 SMD1 shown table below. Table 5.7.3.1 Transfer modes
SMD1 SMD0 Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master
Table 5.7.3.2 Terminal settings corresponding each transfer mode
Mode Asynchronous 8-bit Asynchronous 7-bit SOUT SCLK SRDY Input Output Input Output
Clock synchronous slave Input Output Input Output Clock synchronous master Input Output Output
initial reset, transfer mode clock synchronous master mode. Clock synchronous master mode this mode, internal clock utilized synchronous clock built-in shift registers, clock synchronous 8-bit serial transfers performed with this serial interface master.
EPSON
S1C88816 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Serial Interface)
S1C88816 SIN(P10) SOUT(P11) SCLK(P12) Input port(Kxx)
External serial device Data input Data output CLOCK input READY output
Clock synchronous master mode
S1C88816 SIN(P10) SOUT(P11) SCLK(P12) SRDY(P13) External serial device Data input Data output CLOCK output READY input
Clock synchronous slave mode
S1C88816 SIN(P10) SOUT(P11) External serial device Data input Data output
Asynchronous 7-bit/8-bit mode
Fig. 5.7.3.1 Connection examples serial interface terminals
5.7.4 Clock source
There four clock sources selection made setting bits clock source selection register SCS0 SCS1 shown table below. Table 5.7.4.1 Clock source
SCS1 SCS0 Clock source Programmable timer fOSC3 fOSC3 fOSC3
This register setting invalid clock synchronous slave mode external clock input from SCLK terminal used. When "programmable timer" selected, programmable timer underflow signal divided this signal used clock source. With respect transfer rate setting, "5.10 Programmable Timer". initial reset, synchronous clock "fOSC3/16". Whichever clock selected, signal further divided 1/16 then used synchronous clock. Furthermore, external clock input used SCLK clock synchronous slave mode. Table 5.7.4.2 shows examples transfer rates OSC3 oscillation frequencies when clock source programmable timer. When demultiplied signal OSC3 oscillation circuit made clock source, necessary turn OSC3 oscillation prior using serial interface. time interval several msec several msec, from turning OSC3 oscillation circuit until oscillation stabilizes, necessary, oscillation element that used. Consequently, should allow adequate waiting time after turning OSC3 oscillation, before starting transmitting/receiving serial interface. (The oscillation start time will vary somewhat depending oscillator externally attached parts. Refer oscillation start time example indicated Chapter "ELECTRICAL CHARACTERISTICS".) initial reset, OSC3 oscillation circuit status.
OSC3 fOSC3 oscillation Divider 1/16 circuit
Selector
1/16
Selector
Synchronous clock
Fig. 5.7.4.1 Programmable timer Division synchronous clock underflow signal
SCLK
(Clock synchronous slave mode)
Table 5.7.4.2 OSC3 oscillation frequencies transfer rates
OSC3 oscillation frequency Programmable timer settings Transfer rate fOSC3 3.072 fOSC3 4.608 fOSC3 4.9152 (bps) PSC1X RLD1X PSC1X RLD1X PSC1X RLD1X 9,600 (1/1) (1/1) (1/1) 4,800 (1/1) (1/1) (1/1) 2,400 (1/1) (1/1) (1/1) 1,200 (1/1) (1/1) (1/1) (1/1) (1/1) (1/1) (1/4) (1/4) (1/4) (1/4) (1/4) (1/4)
S1C88816 TECHNICAL MANUAL
EPSON
PERIPHERAL CIRCUITS THEIR OPERATION (Serial Interface)
5.7.5 Transmit-receive control
Below description registers which handle transmit-receive control. With respect transmitreceive control procedures operations, please refer following sections which these discussed mode mode basis. Shift register received data buffer Exclusive shift registers transmitting receiving installed this serial interface. Consequently, duplex communication simultaneous transmit receive possible when asynchronous system selected. Data being transmitted written TRXD0- TRXD7 converted serial through shift register output from SOUT terminal. reception section, received data buffer installed separate from shift register. Data being received input terminal converted parallel through shift register written received data buffer. Since received data buffer read even during serial input operation, continuous data received efficiently. However, since buffer functions used clock synchronous mode, sure read data before next data reception begins. Transmit enable register transmit control transmitting control, transmit enable register TXEN transmit control TXTRG. transmit enable register TXEN used transmitting enable/disable status. When written this register transmitting enable status, clock input shift register enabled system ready transmit data. clock synchronous mode, synchronous clock input/ output from SCLK terminal also enabled. transmit control TXTRG used trigger start transmitting data. Data transmitted written transmit data shift register, when transmitting preparations recomplete, written TXTRG whereupon data transmitting begins. When interrupt been enabled, interrupt generated when transmission completed. there subsequent data transmitted sent using this interrupt.
addition, TXTRG read status. When "1", indicates transmitting operation, indicates transmitting stop. details timing, timing chart which gives timing each mode. When transmitting, TXEN disable transmitting status. Receive enable register,
Other recent searches
TS27M4C - TS27M4C TS27M4C Datasheet
PD60143-N - PD60143-N PD60143-N Datasheet
IR2127 - IR2127 IR2127 Datasheet
IR2128 - IR2128 IR2128 Datasheet
IR21271 - IR21271 IR21271 Datasheet
PCA9685 - PCA9685 PCA9685 Datasheet
PCA9635 - PCA9635 PCA9635 Datasheet
HSMS-8101 - HSMS-8101 HSMS-8101 Datasheet
HSMS-8202 - HSMS-8202 HSMS-8202 Datasheet
HSMS-8205 - HSMS-8205 HSMS-8205 Datasheet
HSMS-8207 - HSMS-8207 HSMS-8207 Datasheet
FYS-5615AX - FYS-5615AX FYS-5615AX Datasheet
BX-XX - BX-XX BX-XX Datasheet
ECR-16 - ECR-16 ECR-16 Datasheet
E90482 - E90482 E90482 Datasheet
Bi10-G30-AP6X-B1141 - Bi10-G30-AP6X-B1141 Bi10-G30-AP6X-B1141 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
