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CMOS 8-BIT SINGLE CHIP MICROCOMPUTER
S1C88349
S1C88349 Technical Hardware
NOTICE
part this material reproduced duplicated form means without written permission Seiko Epson. Seiko Epson reserves right make changes this material without notice. Seiko Epson does assume liability kind arising inaccuracies contained this material application product circuit and, further, there representation that this material applicable products requiring high level reliability, such medical products. Moreover, license intellectual property rights granted implication otherwise, there representation warranty that anything made accordance with this material will free from patent copyright infringement third party. This material portions thereof contain technology subject relating strategic products under control Foreign Exchange Foreign Trade Japan require export license from Ministry International Trade Industry other approval from another government agency.
SEIKO EPSON CORPORATION 2004, rights reserved.
Revisions Additions this manual
Chapter Section 5.11.11 5.15.1 Page Item Fig. 1.2.1 S1C88349 block diagram Mask Option Peripheral circuit board option Programming notes Conversion time Recommended Operating Conditions Analog Circuit Characteristics converter circuit Characteristics External memory access Read cycle Characteristics Curves (reference value) Power current (During operation with OSC3) <Crystal/ceramic oscillation> oscillation> Table 10.2.1 coordinates S5U1C88000P1&S5U1C88816P2 Manual (Peripheral Circuit Board S1C88349) Contents figure revised. manual name revised. Explanation added. Item added. values were revised. table revised. table revised. note added. figures were revised.
Appendix
10.2
177-
table revised. section added.
Configuration product number
Devices 88104 0A01
Packing specifications Besides tape reel directions Tape reel BACK directions directions directions Tape reel FRONT directions directions directions directions Tape reel LEFT directions directions directions directions Tape reel RIGHT Specs fixed Specification Package form; Model number Model name microcomputer, digital products Product classification semiconductor
Development tools S5U1 88348
Packing specifications standard packing Version Version Tool type board Peripheral board Flash writer microcomputer writer peripheral board compiler package Assembler package Utility tool model Soft simulator Corresponding model number 88348: S1C88348 Tool classification microcomputer Product classification S5U1: development tool semiconductor products
CONTENTS
Contents
INTRODUCTION
Features Block Diagram Layout Diagram Description Mask Option
POWER SUPPLY
Operating Voltage Internal Power Supply Circuit
CONFIGURATION
Internal Memory
3.2.1 3.2.2 3.2.3 memory 3.2.4 Display memory
Exception Processing Vectors (Customized Condition Flag) Chip Mode
3.5.1 mode mode 3.5.2 mode
External
3.6.1 Data 3.6.2 Address 3.6.3 Read (RD)/write (WR) signals 3.6.4 Chip enable (CE) signal 3.6.5 WAIT control 3.6.6 authority release state
INITIAL RESET
Initial Reset Factors
4.1.1 RESET terminal 4.1.2 Simultaneous level input input port terminals K00-K03 4.1.3 Supply voltage detection (SVD) circuit 4.1.4 Initial reset sequence
Initial Settings After Initial Reset
PERIPHERAL CIRCUITS THEIR OPERATION
Memory System Controller Control
5.2.1 mode settings 5.2.2 Address decoder output) settings 5.2.3 WAIT state settings 5.2.4 Setting authority release request signal 5.2.5 Stack page setting 5.2.6 Control system controller 5.2.7 Programming notes
S1C88349 TECHNICAL MANUAL
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CONTENTS
Watchdog Timer
5.3.1 Configuration watchdog timer 5.3.2 Interrupt function 5.3.3 Control watchdog timer 5.3.4 Programming notes
Oscillation Circuits Operating Mode
5.4.1 Configuration oscillation circuits 5.4.2 Mask option 5.4.3 OSC1 oscillation circuit 5.4.4 OSC3 oscillation circuit 5.4.5 Operating mode 5.4.6 Switching clocks 5.4.7 Control oscillation circuit operating mode 5.4.8 Programming notes
Input Ports ports)
5.5.1 Configuration input ports 5.5.2 Mask option 5.5.3 Interrupt function input comparison register 5.5.4 Control input ports 5.5.5 Programming note
Output Ports ports)
5.6.1 Configuration output ports 5.6.2 Mask option 5.6.3 High impedance control 5.6.4 output 5.6.5 Special output 5.6.6 Control output ports 5.6.7 Programming notes
Ports ports)
5.7.1 Configuration ports 5.7.2 Mask option 5.7.3 control registers mode 5.7.4 Control ports 5.7.5 Programming notes
Serial Interface
5.8.1 Configuration serial interface 5.8.2 Mask option 5.8.3 Transfer modes 5.8.4 Clock source 5.8.5 Transmit-receive control 5.8.6 Operation clock synchronous transfer 5.8.7 Operation asynchronous transfer 5.8.8 Interrupt function 5.8.9 Control serial interface 5.8.10 Programming notes
Clock Timer
5.9.1 Configuration clock timer 5.9.2 Interrupt function 5.9.3 Control clock timer 5.9.4 Programming notes
5.10
Stopwatch Timer
5.10.1 Configuration stopwatch timer 5.10.2 Count pattern 5.10.3 Interrupt function 5.10.4 Control stopwatch timer 5.10.5 Programming notes
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S1C88349 TECHNICAL MANUAL
CONTENTS
5.11
Programmable Timer
5.11.1 Configuration programmable timer 5.11.2 Count operation setting basic mode 5.11.3 Setting input clock 5.11.4 Timer mode 5.11.5 Event counter mode 5.11.6 Pulse width measurement timer mode 5.11.7 Interrupt function 5.11.8 Setting TOUT output 5.11.9 Transmission rate setting serial interface 5.11.10 Control programmable timer 5.11.11 Programming notes
5.12
Controller .106
5.12.1 Configuration controller 5.12.2 Mask option 5.12.3 Switching drive duty 5.12.4 power supply 5.12.5 driver 5.12.6 Display memory 5.12.7 Display control 5.12.8 outputs 5.12.9 Control controller 5.12.10 Programming notes
5.13
Sound Generator .121
5.13.1 Configuration sound generator 5.13.2 Control buzzer output 5.13.3 Setting buzzer frequency sound level 5.13.4 Digital envelope 5.13.5 One-shot output 5.13.6 Control sound generator 5.13.7 Programming notes
5.14
Analog Comparator .127
5.14.1 Configuration analog comparator 5.14.2 Mask option 5.14.3 Analog comparator operation 5.14.4 Control analog comparator 5.14.5 Programming notes
5.15
Converter .129
5.15.1 Characteristics configuration converter 5.15.2 Terminal configuration converter 5.15.3 Mask option 5.15.4 conversion 5.15.5 Interrupt function 5.15.6 Control converter 5.15.7 Programming notes
5.16
Supply Voltage Detection (SVD) Circuit .136
5.16.1 Configuration circuit 5.16.2 Mask option 5.16.3 Operation circuit 5.16.4 Control circuit 5.16.5 Programming notes
5.17
Interrupt Standby Status .140
5.17.1 Interrupt generation conditions 5.17.2 Interrupt factor flag 5.17.3 Interrupt enable register 5.17.4 Interrupt priority register interrupt priority level 5.17.5 Exception processing vectors 5.17.6 Control interrupt 5.17.7 Programming notes
S1C88349 TECHNICAL MANUAL
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CONTENTS
SUMMARY NOTES
Notes Current Consumption .146 Precautions Mounting.147
BASIC EXTERNAL WIRING DIAGRAM ELECTRICAL CHARACTERISTICS
Absolute Maximum Rating .150 Recommended Operating Conditions .150 Characteristics .151 Analog Circuit Characteristics .152 Power Current Consumption .155 Characteristics .156 Oscillation Characteristics .164 Characteristics Curves (reference value) .165
PACKAGE
Plastic Package .172 Ceramic Package Test Samples .174
LAYOUT
10.1 10.2 Diagram Layout .175 Coordinates .176
APPENDIX S5U1C88000P1&S5U1C88816P2 MANUAL (Peripheral Circuit Board S1C88349)
Names Functions Each Part .177 Installation .179
A.2.1 Installing S5U1C88816P2 S5U1C88000P1 A2.2 Installing into (S5U1C88000H5)
Connecting Target System .180 Downloading Circuit Data S5U1C88000P1 .182 Precautions .183
A.5.1 Precaution operation A.5.2 Differences from actual
Product Specifications .185
A.6.1 S5U1C88000P1 specifications A.6.2 S5U1C88816P2 specifications
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S1C88349 TECHNICAL MANUAL
INTRODUCTION
INTRODUCTION
S1C88349 microcomputer features S1C88 (Model CMOS 8-bit core along with bytes ROM, bytes RAM, three different timers, serial interface with optional asynchronization clock synchronization, converter. S1C88349 fully operable over wide range voltages, perform high speed operations even voltage. Like equipment Family, these microcomputers have power consumption. 19-bit external address bits chip enable signals make possible this microcomputer control 512K bytes memory, making them ideal high performance data bank systems.
Features
Table 1.1.1 lists features S1C88349. Table 1.1.1 Main features
Core OSC1 oscillation circuit OSC3 oscillation circuit Instruction Min. instruction execution time Internal capacity Internal capacity line S1C88 (MODEL3) CMOS 8-bit core Crystal oscillation circuit/CR oscillation circuit/external clock input 32.768 (Typ.) Crystal oscillation circuit/ceramic oscillation circuit/CR oscillation circuit/external clock input (Max.) types (usable multiplication division instructions) 0.244 µsec/8.2 clock) bytes bytes/RAM 3,216 bits/display memory Address bus: bits (also usable general output port when used bus) bits (also usable general port when used bus) Data bus: bits signal: (also usable general output port when used bus) signal: signal: bits bits event counter external clock input request signal input terminal) bits bits buzzer output, control, FOUT, TOUT acknowledge signal output terminal) bits bits each serial interface input/output analog comparator/AD input) (optional clock synchronous system asynchronous system) Programmable timer bits): (1ch event counter bits programmable timer 1ch) Clock timer bits): Stopwatch timer bits): matrix type (supports5 fonts) segments commons (1/5 bias) segments commons (1/5 bias) Built-in power supply circuit (booster type, potentials) Envelope function, equipped with volume control Built-in built-in (not available converter used) Resolution: bits, input: 4ch, Maximum error: (not available analog comparator used) detect different voltage levels External interrupt: Input interrupt Internal interrupt: Timer interrupt Serial interface interrupt converter interrupt Normal mode: V-5.5 (Max. MHz) power mode: V-3.5 (Max. kHz) systems types)
Input port Output port port Serial interface Timer
driver
Sound generator Watchdog timer Analog comparator converter Supply voltage detection (SVD) circuit Interrupt
Supply voltage
Current consumption
Supply form
systems types) system types) system type) High speed mode: V-5.5 (Max. MHz) SLEEP mode: HALT mode: (Typ./normal mode) (Typ./normal mode) kHz): (Typ./normal mode) MHz): QFP18-176pin, QFP21-176pin chip
number bits cited output ports ports does include those shared with bus.
S1C88349 TECHNICAL MANUAL
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INTRODUCTION
Block Diagram
Core S1C88
OSC1,
Oscillator
OSC3, MCU/MPU BREQ (K11) BACK (R51) RESET
Interrupt Controller
K00-K07 (EVIN) (BREQ)
System Controller
Input Port
Reset/Test
TEST
Port
(SIN) (SOUT) (SCLK) (SRDY) (CMPP0/AD4) (CMPM0/AD5) (CMPP1/AD6) (CMPM1/AD7) P00-P07 (D0-D7) R00-R07, R10-R17, R20-R22 (A0-A7, A8-A15, A16-A18) R23, (RD, R30-R33 (CE0-CE3) R25, (CL, (TOUT) (FOUT) R35-R37 (BZ) (BACK) SEG0-SEG50 COM16-COM31 (SEG66-SEG51) COM0-COM15
Watchdog Timer
Serial Interface
EVIN (K10)
Programmable Timer /Event Counter
Analog Comparator Converter
Clock Timer
External Memory Interface
Stopwatch Timer Sound Generator
VOSC VC1-VC5 CA-CE VREF AVDD AVSS AVREF
Output Port Power Generator Driver
Supply Voltage Detector
byte
byte
Fig. 1.2.1 S1C88349 block diagram
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S1C88349 TECHNICAL MANUAL
INTRODUCTION
Layout Diagram
QFP18-176pin
QFP21-176pin
INDEX
INDEX
name SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45
name SEG46 SEG47 SEG48 SEG49 SEG50 COM31/SEG51 COM30/SEG52 COM29/SEG53 COM28/SEG54 COM27/SEG55 COM26/SEG56 COM25/SEG57 COM24/SEG58 COM23/SEG59 COM22/SEG60 COM21/SEG61 COM20/SEG62 COM19/SEG63 COM18/SEG64 COM17/SEG65 COM16/SEG66 N.C. N.C. N.C. N.C. N.C. N.C. VREF OSC3 OSC4 VOSC
name OSC1 OSC2 TEST RESET MCU/MPU K11/BREQ K10/EVIN P17/CMPM1/AD7 P16/CMPP1/AD6 P15/CMPM0/AD5 P14/CMPP0/AD4 P13/SRDY P12/SCLK P11/SOUT P10/SIN AVDD AVSS AVREF P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 R00/A0 R01/A1 R02/A2 R03/A3 R04/A4 R05/A5 R06/A6 R07/A7 R10/A8
name R11/A9 R12/A10 R13/A11 R14/A12 R15/A13 R16/A14 R17/A15 R20/A16 R21/A17 R22/A18 R23/RD R24/WR R25/CL R26/FR R27/TOUT R30/CE0 R31/CE1 R32/CE2 R33/CE3 R34/FOUT R50/BZ R51/BACK COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1
Fig. 1.3.1 S1C88349 layout
S1C88349 TECHNICAL MANUAL
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INTRODUCTION
Description
Table 1.4.1 S1C88349 description
name VOSC VC1-VC5 CA-CE VREF OSC1 OSC2 OSC3 OSC4 MCU/MPU K00-K07 K10/EVIN K11/BREQ R00-R07/A0-A7 R10-R17/A8-A15 R20-R22/A16-A18 R23/RD R24/WR R25/CL R26/FR R27/TOUT R30-R33/CE0-CE3 R34/FOUT R35-R37 R50/BZ R51/BACK P00-P07/D0-D7 P10/SIN P11/SOUT P12/SCLK P13/SRDY P14/CMPP0/AD4 P15/CMPM0/AD5 P16/CMPP1/AD6 P17/CMPM1/AD7 COM0-COM15 COM16-COM31 /SEG66-SEG51 SEG0-SEG50 RESET TEST AVDD AVSS AVREF 82-78 77-73 103-96 124-131 132-139 140-142 148-151 153-155 123-116 159-174 65-50 175-176, 1-49 In/Out Function Power supply terminal Power supply (GND) terminal Internal logic system voltage regulator output terminal Oscillation system voltage regulator output terminal drive voltage output terminals Booster capacitor connection terminals system power testing terminal OSC1 oscillation input terminal (select crystal oscillation/CR oscillation/external clock input mask option) OSC1 oscillation output terminal OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation/external clock input mask option) OSC3 oscillation output terminal Terminal setting modes Input terminals (K00-K07) Input terminal (K10) event counter external clock input terminal (EVIN) Input terminal (K11) request signal input terminal (BREQ) Output terminals (R00-R07) address (A0-A7) Output terminals (R10-R17) address (A8-A15) Output terminals (R20-R22) address (A16-A18) Output terminal (R23) read signal output terminal (RD) Output terminal (R24) write signal output terminal (WR) Output terminal (R25) synchronous signal output terminal (CL) Output terminal (R26) frame signal output terminal (FR) Output terminal (R27) programmable timer underflow signal output terminal (TOUT) Output terminals (R30-R33) chip enable output terminals (CE0-CE3) Output terminal (R34) clock output terminal (FOUT) Output terminals (R35-R37) Output terminal (R50) buzzer output terminal (BZ) Output terminal (R51) acknowledge signal output terminal (BACK) terminals (P00-P07) data (D0-D7) terminal (P10) serial data input terminal (SIN) terminal (P11) serial data output terminal (SOUT) terminal (P12) serial clock terminal (SCLK) terminal (P13) serial ready signal output terminal (SRDY) terminal (P14), analog comparator non-inverted input terminal converter input terminal terminal (P15), analog comparator inverted input terminal converter input terminal terminal (P16), analog comparator non-inverted input terminal converter input terminal terminal (P17), analog comparator inverted input terminal converter input terminal common output terminals common output terminals (when 1/32 duty selected) segment output terminal (when 1/16 duty selected) segment output terminals Initial reset input terminal Test input terminal Analog system power supply terminal Analog system power supply terminal Analog system reference voltage terminal
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S1C88349 TECHNICAL MANUAL
INTRODUCTION
Mask Option
Mask options shown below provided S1C88349. Several hardware specifications prepared each mask option, them selected according application. function option generator winfog, that been prepared development software tool S1C88349, used this selection. Mask pattern finally generated based data created winfog. Refer "S5U1C88000C Manual details winfog.
Option list
following options S1C88349 (S5U1C88000H5). Multiple specifications available each option item indicated Option List. Select specifications that meet target system check appropriate box. option selection done interactively screen during winfog execution, using this option list reference.
PERIPHERAL CIRCUIT BOARD option list
OSC1 SYSTEM CLOCK Internal Clock User Clock OSC3 SYSTEM CLOCK Internal Clock User Clock
S1C88349 mask option list
OSC1 SYSTEM CLOCK Crystal External Clock Crystal (with Gate Capacity) OSC3 SYSTEM CLOCK Crystal Ceramic External Clock MULTIPLE ENTRY RESET Combination K00, K00, K01, K00, K01, K02, MODE INITIAL 512K (MAX) 512K (MIN) RESET
S1C88349 TECHNICAL MANUAL
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INTRODUCTION
INPUT PORT PULL RESISTOR With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor MCU/MPU With Resistor RESET With Resistor PORT PULL RESISTOR With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor With Resistor OUTPUT PORT SPECIFICATION Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary Complementary POWER SUPPLY Internal External
Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct
Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Gate Direct Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain
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S1C88349 TECHNICAL MANUAL
INTRODUCTION
Outline mask options Peripheral circuit board option
These options configure Peripheral Circuit Board (S5U1C88000P1 with S5U1C88816P2) installed (S5U1C88000H5). selections affect IC's mask option. OSC1 system clock When User Clock selected, input clock OSC1 terminal. When Internal Clock selected, clock frequency changed according oscillation circuit selected IC's mask option. OSC3 system clock When User Clock selected, input clock OSC3 terminal. When Internal Clock selected, clock frequency changed according oscillation circuit selected IC's mask option.
Initial reset circuit circuit function that generates initial reset signal when supply voltage drops level less. mask option used select whether this function used not. Refer Section 5.16, "Supply Voltage Detection (SVD) Circuit", details.
Input port, MCU/MPU RESET terminal pull-up resistors This mask option select whether pull-up resistor input port terminal used not. possible select each input ports. Refer Section 5.5, "Input Ports ports)", details. Furthermore, pull-up option also provided MCU/MPU RESET terminals. port pull-up resistors This mask option select whether pull-up resistor port terminal works during input mode) used not. possible select each ports. Refer Section 5.7, "I/O Ports ports)", details. Since shared with serial interface terminals, selected terminal configuration applied serial input (SIN) terminal serial clock input terminal (SCLK clock synchronous mode) when serial interface used. Refer Section 5.8, "Serial Interface", details. Output port specifications Either complementary output open drain output selected output specification output ports R00-R07 R10-R17 units. Refer Section 5.6.2, "Mask option", details. power supply Either internal power supply (internal system voltage regulator voltage booster that generate VC5) external power supply selected system power source. Refer Section 5.12.2, "Mask option", details.
S1C88349 mask option
OSC1 oscillation circuit specification OSC1 oscillation circuit selected from among four types: "Crystal oscillation", oscillation", "Crystal oscillation (gate capacitor built-in)" "External clock input". Refer Section 5.4.3, "OSC1 oscillation circuit", details. OSC3 oscillation circuit specification OSC3 oscillation circuit selected from among four types: "Crystal oscillation", "Ceramic oscillation", oscillation" "External clock input". Refer Section 5.4.4, "OSC3 oscillation circuit", details. Multiple entry reset (K00-K03) This function resets when several keys pressed simultaneously. mask option used select whether this function used not. Further when function used, combination input ports (K00-K03), which connected keys pressed simultaneously, selected. Refer Section 4.1.2, "Simultaneous level input input port terminals K00-K03", details. Initial mode mode mode that initially mode selected from expanded 512K maximum mode, expanded 512K minimum mode expanded mode. Refer Section 5.2, "System controller Control", details.
S1C88349 TECHNICAL MANUAL
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POWER SUPPLY
POWER SUPPLY
this section, will explain operating voltage configuration internal power supply circuit S1C88349.
Operating Voltage
S1C88349 operating power voltage follows: Normal mode: power mode: High speed mode:
Note: Under circumstances should terminal output used drive external circuit.
oscillation system voltage regulator generates operating voltage <VOSC> OSC1 oscillation circuit. system power supply circuit generates drive voltage LCD. Drive voltage five potentials VC1-VC5 bias: generated voltage regulator, boosted generate VC3-VC5. These voltages output from terminals drive external driver (S1D15210 equivalent). Chapter "ELECTRICAL CHARACTERISTICS" voltage values. S1C88349, drive voltage supplied built-in driver which drives panel connected terminals.
Internal Power Supply Circuit
S1C88349 incorporates power supply circuit shown Figure 2.2.1. When voltage within range described above supplied (GND), voltages needed internal circuit generated internally Roughly speaking, power supply circuit divided into three sections. internal logic voltage regulator generates operating voltage <VD1> driving internal logic circuits OSC3 oscillation circuit. voltage selected from following three types: low-power mode, normal mode high-speed mode. should selected program switch according supply voltage oscillation frequency. Section 5.4, "Oscillation Circuits Operating Mode", switching operating mode.
AVDD External power supply Internal logic system voltage regulator Oscillation system VOSC voltage regulator system voltage regulator VC1,VC2
Notes: terminals VC1-VC5 except supply voltage expanded driver. Refer "S1D15000 Series Technical Manual" S1D15210 externaly expanded driver.
Internal voltage setting circuit OSC3 oscillation circuit Internal circuit OSC1 oscillation circuit OSC3, OSC4
VOSC VREF AVSS
OSC1, OSC2
system voltage booster
VC3-VC5
driver
COM0-COM15 COM16-COM31/SEG66-SEG51 SEG0-SEG50
converter
Fig. 2.2.1 Configuration power supply circuit
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S1C88349 TECHNICAL MANUAL
CONFIGURATION
CONFIGURATION
this section, will explain CPU, operating mode configuration.
S1C88349 utilize S1C88 8-bit core whose register configuration, command set, etc. virtually identical other units family processors incorporating S1C88. "S1C88 Core Manual" S1C88. Specifically, S1C88349 employ Model S1C88 which maximum address space 512K bytes
3.2.2
internal capacity bytes allocated 00F000H-00F7FFH. Even when external memory which overlaps internal area expanded, area released external memory. Access this area internal RAM.
3.2.3 memory
memory mapped method employed S1C88349 interfacing with internal peripheral circuit. Peripheral circuit control bits data register arranged data memory space. Control data exchange conducted normal memory access. memory arranged page 00FF00H-00FFFFH area. Section 5.1, "I/O Memory Map", details memory. Even when external memory which overlaps memory area expanded, memory area released external memory. Access this area memory.
Internal Memory
S1C88349 equipped with internal shown Figure 3.2.1. Small scale applications handled chip. also possible utilize internal memory combination with external memory. Furthermore, internal disconnected from resulting space released external applications.
00FFFFH memory 00FF00H 00FD42H Display memory 00F800H 00F7FFH bytes) 00F000H 00EFFFH Undefined area 00C000H 00BFFFH
3.2.4 Display memory
S1C88349 equipped with internal display memory which stores display data driver. Display memory arranged page 00Fx00H- 00Fx42H 8-DH) data memory area. Section 5.12, "LCD Controller", details display memory. Like memory, display memory cannot released external memory.
(48K bytes)
Exception Processing Vectors
000000H
Fig. 3.2.1 Internal memory
3.2.1
S1C88349 built-in 48K-byte ROM. allocated 000000H-00BFFFH. areas shown above released external memory depending setting MCU/MPU terminal. (See "3.5 Chip Mode".)
000000H-000025H program area S1C88349 assigned exception processing vectors. Furthermore, from 000028H 0000FFH, software interrupt vectors assignable bytes which begin with even address. Table 3.3.1 lists vector addresses exception processing factors which they correspond.
S1C88349 TECHNICAL MANUAL
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CONFIGURATION
Table 3.3.1 Exception processing vector table
Vector address Exception processing factor Priority High
Chip Mode
3.5.1 mode mode
chip operating mode settings using MCU/MPU terminal. mode.Set MCU/MPU terminal HIGH Switch this setting when using internal ROM. With respect areas other than internal memory, external memory even expanded. Section 3.5.2, "Bus mode", memory map. mode, during initial reset, only systems internal memory activated. Internal normally fixed portion program memory from common area (logical space 0000H-7FFFH). Exception processing vectors assigned internal ROM. Furthermore, application initialization routines that start with reset exception processing must likewise written internal ROM. Since other settings which correlate with external expanded memory executed software, this processing executed initialization routine written internal ROM. Once these mode settings made, external memory accessed. When accessing internal memory this mode, chip enable (CE) read (RD)/write (WR) signals output external memory, data (D0-D7) goes into high impedance status (pull-up status when "pull-up resistors P00-P07 enabled" have been selected mask option). Consequently, cases where addresses overlap external internal memory, areas external memory will unavailable. mode.Set MCU/MPU terminal Internal area released external device source. Internal then becomes unusable when this area accessed, chip enable (CE) read (RD)/write (WR) signals output external memory data (D0-D7) become active. These signals output external source when other areas internal memory accessed. mode, system activated external memory. this reason, order adjust settings conform configuration external memory during initial reset, user select applicable system configuration using mask option. (See "3.5.2 mode".)
000000H Reset 000002H Zero division 000004H Watchdog timer (NMI) 000006H Programmable timer interrupt 000008H Programmable timer interrupt 00000AH K10, input interrupt 00000CH K04-K07 input interrupt 00000EH K00-K03 input interrupt 000010H Serial error interrupt 000012H Serial receiving complete interrupt 000014H Serial transmitting complete interrupt 000016H Stopwatch timer interrupt 000018H Stopwatch timer interrupt 00001AH Stopwatch timer interrupt 00001CH Clock timer interrupt 00001EH Clock timer interrupt 000020H Clock timer interrupt 000022H Clock timer interrupt 000024H converter interrupt 000026H System reserved (cannot used) 000028H Software interrupt 0000FEH
priority rating
each vector address address after start address exception processing routine written into subordinate super ordinate sequence. When exception processing factor generated, exception processing routine executed starting from recorded address. When multiple exception processing factors generated same time, execution starts with highest priority item. priority sequence shown Table 3.3.1 assumes that interrupt priority levels same. interrupt priority levels software each system. (See Section 5.17 "Interrupt Standby Status".)
Note: exception processing other than reset, (system condition flag) (program counter) evacuated stack branches exception processing routines. Consequently, when returning main routine from exception processing routines, please RETE instruction.
"S1C88 Core Manual" information operations when exception processing factor generated.
(Customized Condition Flag)
S1C88349 does customized condition flag (CC) core CPU. Accordingly, cannot used branching condition conditional branching instruction (JRS, CARS).
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S1C88349 TECHNICAL MANUAL
CONFIGURATION
When employing this mode, exception processing vectors initialization routine must assigned within common area (000000H-007FFFH). select whether built-in pullup resistor MCU/MPU terminal mask option.
Expanded mode (MPU mode) expanded mode setting applies when S1C88349 used with bytes less external expanded memory. This mode only usable mode setting. Since internal area released mode, external memory this model assigned area from 000000H 00EFFFH. area from 00F000H 00FFFFH assigned internal memory (RAM, etc.) cannot used access external device. This mode setting suitable small- midscale systems. address range chip enable (CE) signal, adapted memory chips with capacity from bytes, selected software four settings. Section 3.6.4, "Chip enable (CE) signal", signal. operation this mode equivalent S1C88 core Model minimum mode. area within physical space 000000H 00FFFFH only effective target accessing.
mode 00FFFFH Internal memory 00F000H 00EFFFH
Note: Setting MCU/MPU terminal latched rising edge reset signal input from RESET terminal. Therefore, setting changed, RESET terminal must level once again.
3.5.2 mode
order specifications match configuration external expanded memory, four different modes described below selectable software. Single chip mode
mode 00FFFFH memory 00FF00H 00FD42H Display memory 00F800H 00F7FFH Internal 00F000H 00EFFFH Undefined area 00C000H 00BFFFH
Internal
External memory area
000000H
Fig. 3.5.2.1 Memory single chip mode single chip mode setting applies when S1C88349 used single chip microcomputer without external expanded memory. Since this mode employs internal ROM, system only operated mode discussed Section 3.5.1. mode, system cannot single chip mode. Since there need external line this mode, terminals normally used general purpose output ports ports. Accordingly, output ports 34-bit configuration S1C88349 ports 16-bit configuration. operation this mode equivalent S1C88 core Model minimum mode. Addresses assigned internal memory within physical space 000000H 00FFFFH only effective target accessing.
000000H
Figure 3.2.1 internal memory
Fig. 3.5.2.2 Memory expanded mode (MPU mode) Expanded 512K minimum mode expanded 512K minimum mode setting applies when S1C88349 used with over bytes less than 512K bytes external expanded memory. This mode usable regardless MCU/MPU mode setting. Because internal being used mode, external memory this model assigned area from 080000H 27FFFFH. Since internal area released mode, external memory this model assigned area from 000000H 1FFFFFH.
S1C88349 TECHNICAL MANUAL
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CONFIGURATION
However, area from 00F000H 00FFFFH assigned internal memory cannot used access external device. operation this mode equivalent S1C88 core Model3 minimum mode. area within physical space 000000H 1FFFFFH mode physical space 080000H 27FFFFH internal memory mode effective target accessing. Furthermore, since program memory expansion limited less than bytes configured with common area (000000H 007FFFH) optional bank area (internal mode), this mode suitable smallto mid-scale program memory large-scale data memory systems. address range chip enable (CE) signals this mode fixed 512K bytes.
mode 27FFFFH
mode 1FFFFFH
Because internal being used mode, external memory this model assigned area from 080000H 27FFFFH. Since internal area released mode, external memory this model assigned area from 000000H 1FFFFFH. area from 00F000H 00FFFFH assigned internal memory cannot used access external device. operation this mode equivalent S1C88 core Model maximum mode, area within physical space 000000H 1FFFFFH mode physical space 080000H 27FFFFH internal memory mode effective target accessing. above mentioned physical space, since program memory data memory secured with optional (maximum 512K bytes program data) size, this mode suitable systems with large-scale program data capacity. address range chip enable (CE) signals this mode fixed 512K bytes.
mode 27FFFFH
mode 1FFFFFH
External memory area
External memory area
080000H 07FFFFH
Unused area
010000H 00FFFFH Internal memory 00F000H 00EFFFH Unused area 00C000H 00BFFFH
External memory area
External memory area
Internal memory
080000H 07FFFFH
Unused area
010000H 00FFFFH Internal memory 00F000H 00EFFFH Unused area 00C000H 00BFFFH
Internal memory
Internal memory
External memory area
Internal memory
000000H
External memory area
Figure 3.2.1 internal memory
Fig. 3.5.2.3 Memory expanded 512K minimum mode Expanded 512K maximum mode expanded 512K maximum mode setting applies when S1C88349 used with over bytes less than 512K bytes external expanded memory. This mode usable regardless MCU/MPU mode setting.
000000H
Figure 3.2.1 internal memory
Fig. 3.5.2.4 Memory expanded 512K maximum mode There explanation these settings actually made "5.2 System Controller Control" this Manual.
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S1C88349 TECHNICAL MANUAL
CONFIGURATION
External
S1C88349 terminals that address maximum 512K bytes memory (and other) devices externally expanded according range each mode described previous section.
Address (A0-A18) Data (D0-D7)
3.6.2 Address
S1C88349 possesses 19-bit external address A0-A18. terminals output circuits address A0-A18 shared with output ports R00-R07 (=A0-A7), R10-R17 (=A8-A15) R20- (=A16-A18), switching between these functions being determined mode setting. single chip mode, 19-bit terminals output ports R00-R07, R10-R17 R20-R22. expanded mode, 19-bit terminals, A0-A15, address bus, while remaining bits, A16-A18, output ports R20-R22. expanded 512K minimum maximum modes, 19-bit terminals address (A0-A18). When address bus, data register high impedance control register each output port detached from output circuit used general purpose data register with read/write capabilities.
Output port Address
S1C88349
BREQ BACK
External device
External device
External device
External device
Fig. 3.6.1 External lines Below explanation external terminals. information control methods, Section 5.2, "System Controller Control".
3.6.1 Data
S1C88349 possesses 8-bit external data (D0-D7). terminals circuits data D0-D7 shared with ports P00-P07, switching between these functions being determined mode setting. single chip mode, 8-bit terminals ports P00-P07 other expanded modes, they data (D0-D7). When data bus, data register control register each port detached from circuits usable general purpose data register with read/write capabilities. With regard pull-up resistors that only input mode, mask option used select whether pull-up resistor each data line. (The same holds true when terminals used ports.)
port mode Data mode 512K (min.) 512K (max.)
mode
mode 512K (min.) 512K (max.)
Single chip
Fig. 3.6.2.1 Correspondence between address output ports
3.6.3 Read (RD)/write (WR) signals
output terminals output circuits read (RD)/write (WR) signals directed external devices shared respectively with output ports R24, switching between these functions being determined mode setting. single chip mode, both these terminals output port terminals other expanded modes, they read (RD)/write (WR) signal output terminals. When read (RD)/write (WR) signal output terminal, data register high impedance control register each output port (R23, R24) detached from output circuit usable general purpose data register with read/write capabilities.
EPSON
Single chip
Fig. 3.6.1.1 Correspondence between data ports
S1C88349 TECHNICAL MANUAL
CONFIGURATION
These signals only output when memory area external device being accessed. They output when internal memory accessed. Section 3.6.5, "WAIT control", output timing signal.
mode Output port Single chip RD/WR signal mode 512K (min.) 512K (max.)
single chip mode, these terminals output ports R30-R33.
mode Single chip Output port signal mode 512K (min.) 512K (max.)
Fig. 3.6.4.1 Correspondence between signals output ports address range assigned four chip enable (CE) signals determined mode setting. expanded mode, four different address ranges which match amount memory selected software. Table 3.6.4.1 shows address ranges which assigned chip enable (CE) signal each mode. When accessing internal memory area, signal output. Care should taken here because address range these portions memory involves irregular settings. arrangement memory space external devices does necessarily have continuous from subordinate address chip enable signals used assign areas memory. Each these signals only output when memory area external device being accessed. They output when internal memory accessed.
Fig. 3.6.3.1 Correspondence between read (RD)/write (WR) signal output ports
3.6.4 Chip enable (CE) signal
S1C88349 equipped with address decoders which output four different chip enable (CE) signals. Consequently, four devices equipped with chip enable (CE) chip select (CS) terminal directly connected without setting address decoder external device. four chip enable (CE0-CE3) signal output terminals output circuits shared with output ports R30-R33 modes other than single chip mode, selection chip enable (CE) output port software each four bits. When chip enable (CE) output, data register high impedance control register each output port detached from output circuit usable general purpose data register with read/write capabilities.
Note: signals will inactive status when chip enters standby mode (HALT mode SLEEP mode).
Section 3.6.5, "WAIT control", output timing signal.
Table 3.6.4.1 CE0-CE3 address settings Expanded mode (MPU mode only)
signal bytes 000000H-001FFFH 002000H-003FFFH 004000H-005FFFH 006000H-007FFFH Address range (selected software) bytes bytes 000000H-003FFFH 000000H-007FFFH 004000H-007FFFH 008000H-00EFFFH 008000H-00BFFFH 00C000H-00EFFFH bytes 000000H-00EFFFH
Expanded 512K minimum/maximum modes
signal Address range mode 200000H-27FFFFH 080000H-0FFFFFH 100000H-17FFFFH 180000H-1FFFFFH mode 000000H-00EFFFH, 010000H-07FFFFH 080000H-0FFFFFH 100000H-17FFFFH 180000H-1FFFFFH
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3.6.5 WAIT control
order insure accessing external speed devices during high speed operations, S1C88349 equipped with WAIT function which prolongs access time. (See "S1C88 Core Manual" details WAIT function.) WAIT state numbers inserted selected software from series shown Table 3.6.5.1. Table 3.6.5.1 Selectable WAIT state numbers
Selection Insert states
WAIT states software inserted between cycle states T3-T4. Note, however, that WAIT states cannot inserted when internal register internal memory being accessed when operating with OSC1 oscillation circuit (see "5.4 Oscillation Circuits Operating Mode"). Consequently, WAIT state settings meaningless single chip mode. Figure 3.6.5.1 shows memory read/write timing charts.
state cycle clock length.
A0-A18 D0-D7
Address
Address
Read data
Write data
Read cycle
Write cycle
WAIT
WAIT states inserted) WAIT states inserted)
A0-A18 D0-D7
Address
Address
Read data
Write data
Read cycle
Write cycle
WAIT state insertion Fig. 3.6.5.1 Memory read/write cycle
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3.6.6 authority release state
S1C88349 equipped with authority release function request from external device that (Direct Memory Access) transfer conducted between external devices. internal memory cannot accessed this function. There terminals used this function: authority release request signal (BREQ) input terminal authority release acknowledge signal (BACK) output terminal. BREQ input terminal shared with input port terminal BACK output terminal with output port terminal R51, with setting BREQ/BACK terminals done software. single chip mode, when using system which does require authority release, respective terminals input output ports.
Input port Output port
When authority release request (BREQ LOW) received from external device, S1C88349 switches address bus, data bus, signal, signal lines high impedance state, outputs level from BACK terminal releases authority. soon level output from BACK terminal, external device external bus. When completed, external device returns BREQ terminal HIGH releases authority. Figure 3.6.6.2 shows authority release sequence. During authority release state, internal memory cannot accessed from external device. cases where external memory areas which overlap areas internal memory, external memory areas accessed accordance with signal output external device.
BREQ input BACK output
Fig. 3.6.6.1 BREQ/BACK terminals
Note: careful with system, such that external device does become master, other than during release status. After setting BREQ terminal level, hold BREQ terminal level until BACK terminal becomes level. BREQ terminal returned HIGH level, before BACK terminal becomes level, shift authorization release status will become indefinite.
A0-A18 D0-D7 BREQ BACK Program execution status authority release status [HL],[IX] Program execution status (IX) (IX)
Fig. 3.6.6.2 authority release sequence
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S1C88349 TECHNICAL MANUAL
INITIAL RESET
INITIAL RESET
Initial reset S1C88349 required order initialize circuits. This section Manual contains description initial reset factors initial settings internal registers, etc.
Initial Reset Factors
There three initial reset factors S1C88349 shown below. RESET terminal Simultaneous level input input port terminals K00-K03 Supply voltage detection (SVD) circuit Figure 4.1.1 shows configuration initial reset circuit.
Input port Input port Input port Input port RESET Supply voltage detection (SVD) circuit Time authorize circuit Internal initial reset
peripheral circuits initialized means initial reset factors. When factor canceled, commences reset exception processing. (See "S1C88 Core Manual".) When this occurs, reset exception processing vectors, Bank 000000H-000001H from program memory read program (initialization routine) which begins readout address executed.
SLEEP status Oscillation stability waiting signal
Mask option
Fig. 4.1.1 Configuration initial reset circuit
4.1.1 RESET terminal
Initial reset done executed externally inputting level RESET terminal. sure maintain RESET terminal level regulation time after power assure initial reset. addition, sure RESET terminal first initial reset after power turned RESET terminal equipped with pull-up resistor. select whether mask option.
However, time authorize circuit bypassed during SLEEP (standby) status oscillation stabilization waiting period, initial reset executed immediately after simultaneous level input designated input ports. combination input ports (K00-K03) that selected mask option follows: Multiple entry reset instance, let's that mask option "K00 K03" selected. When input level input ports K00-K03 simultaneously LOW, initial reset will take place. When using this function, make sure that designated input ports simultaneously switch level while system normal operation.
4.1.2 Simultaneous level input input port terminals K00-K03
Another executing initial reset externally input level simultaneously input ports (K00-K03) selected mask option. Since there built-in time authorize circuit, sure maintain designated input port terminal level seconds (when oscillation frequency fOSC1 32.768 kHz) more perform initial reset means this function.
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INITIAL RESET
4.1.3 Supply voltage detection (SVD) circuit
When circuit detects that supply voltage dropped below level four successive times (see Chapter "ELECTRICAL CHARACTERISTICS"), outputs initial reset signal until supply voltage been restored level select whether this initial reset function mask option. more information, "5.16 Supply Voltage Detection (SVD) Circuit" this Manual.
4.1.4 Initial reset sequence
After cancellation level input RESET terminal, when power turned start-up held back until oscillation stabilization waiting time (8,192/fOSC1 sec.) initial sampling time (248/fOSC1 sec.) have elapsed. Figure 4.1.4.1 shows operating sequence following initial reset release. Also, when using initial reset simultaneous level input into input port, should careful following points. During SLEEP status, since time authorization circuit bypassed, initial reset triggered immediately after level simultaneous input value. this case, starts after waiting oscillation stabilization time circuit initial sampling time, following cancellation level simultaneous input. Other than during SLEEP status, initial reset will triggered seconds after level simultaneous input. this case, since reset differential pulse (64/fOSC1 sec.) generated within S1C88349, will start even level simultaneous input status canceled.
Note: supply voltage must least level first sampling circuit after initial reset regardless mask option selected. this time, power voltage level less than level circuit will continue sampling until supply voltage reaches level more.
fOSC1 RESET Internal initial reset Internal address Internal data Internal read signal
8192/fOSC1 [sec] Oscillation stable waiting time 248/fOSC1 [sec] First sampling time Dummy cycle Reset exception processing
00-0000
Dummy
Dummy
VECL
Fig. 4.1.4.1 Initial reset sequence
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S1C88349 TECHNICAL MANUAL
INITIAL RESET
Initial Settings After Initial Reset
internal registers initialized follows during initial reset. Table 4.2.1 Initial settings
Register name Data register Data register Index (data) register Index (data) register Index register Index register Program counter Stack pointer Base register Zero flag Carry flag Overflow flag Negative flag Decimal flag Unpack flag Interrupt flag Interrupt flag code bank register Code bank register Expand page register Expand page register Expand page register
Code length Setting value
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Reset exception processing loads preset values stored bank, 0000H-0001H into same time, initial value loaded into Initialize registers which initialized initial reset using software. Since internal display memory initialized initial reset, sure initialize using software. respectively stipulated initializations done internal peripheral circuits. necessary, initialization should done using software. initial value initial reset, sections memory peripheral circuit descriptions following chapter this Manual.
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PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
PERIPHERAL CIRCUITS THEIR OPERATION
peripheral circuits S1C88349 interfaced with means memory mapped method. this reason, just with other memory access operations, peripheral circuits controlled manipulating memory. Below description operation control method each individual peripheral circuit.
Memory
Table 5.1.1(a) Memory (00FF00H-00FF02H, mode)
Function Address Name 00FF00 BSMD1 mode (CPU mode) (MCU) BSMD1 BSMD0 Mode 512K (Maximum) BSMD0 512K (Minimum) Single chip CEMD1 register Comment
BSMD1-0 01B.
CEMD0 register
00FF01 00FF02
SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0
(R33) signal output Enable/Disable (R32) Enable: signal output (R31) Disable: (R3x) output (R30) Stack pointer page address page allocatable address Single chip mode: only page mode: only page 512K (min) mode: 0-27H page 512K (max) mode: 0-27H page (LSB) release enable register (K11 terminal specification) Wait control register Number state wait (MSB)
enable enable enable enable BREQ BACK
disable disable disable disable Input port Output port
Single chip mode, these setting fixed output.
CLKCHG operating clock switch OSCC OSC3 oscillation On/Off control Operating mode selection VDC1 VDC1 VDC0 Operating mode High speed (VD1=3.3V) power (VD1=1.2V) VDC0 Normal (VD1=2.2V)
OSC3
OSC1
Note:
interrupts including disabled, until write optional value into both "00FF00H" "00FF01H" addresses.
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Table 5.1.1(b) Memory (00FF00H-00FF02H, mode)
Address Name Function 00FF00 BSMD1 mode (CPU mode) (MPU) BSMD1 BSMD0 Mode 512K (Maximum) BSMD0 512K (Minimum) Option selection CEMD1 Chip enable mode CEMD1 CEMD0 Mode (CE0) CEMD0 (CE0, CE1) (CE0-CE3) (CE0-CE3) (R33) signal output Enable/Disable (R32) Enable: signal output (R31) Disable: (R3x) output (R30) 00FF01 SPP7 Stack pointer page address (MSB) SPP6 SPP5 page allocatable address SPP4 Single chip mode: only page SPP3 mode: only page SPP2 512K (min) mode: 0-27H page SPP1 512K (max) mode: 0-27H page SPP0 (LSB) 00FF02 release enable register (K11 terminal specification) Wait control register Number state wait CLKCHG operating clock switch OSCC OSC3 oscillation On/Off control Operating mode selection VDC1 VDC1 VDC0 Operating mode High speed (VD1=3.3V) power (VD1=1.2V) VDC0 Normal (VD1=2.2V) Comment Initial setting
selected among types (64K, 512K
512K max)
mask option setting.
Only
mode
enable enable enable enable BREQ BACK
disable disable disable disable Input port Output port
OSC3
OSC1
Note:
interrupts including disabled, until write optional value into both "00FF00H" "00FF01H" addresses.
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Table 5.1.1(c) Memory (00FF09H-00FF13H)
Address 00FF09 LCDB LCDAJ DUTY8 00FF10 LCCLK Name Reserved Power TYPE (4.5V)/B (5.5V) switch drive duty switch output control expanded driver Function
TYPE duty dots 1/16 duty
TYPE 1/16, 1/32 dots 1/32 duty
Comment
Constantly when being read
VCCHG Reserved
Constantly when being read
LCFRM output control expanded driver DTFNT font selection LDUTY drive duty selection SGOUT register 00FF11 DSPAR display memory area selection LCDC1 display control LCDC1 LCDC0 display LCDs LCDs Normal display Drive
Reserved register
when being read
Display area Display area
These bits reset when
LCDC0
instruction
executed.
00FF12
contrast adjustment Contrast Dark Light
Constantly when being read
SVDSP auto-sampling control SVDON continuous sampling control/status SVD3 00FF13 SVD2 SVD1 SVD0 CMP1ON CMP0ON CMP1DT CMP0DT detection level
SVD3 SVD2 SVD1 SVD0 Detection level Level Level Level
These registers
reset when
Busy
Ready
10*2 instruction
executed.
Comparator On/Off control Comparator On/Off control Comparator data Comparator data
+>+>-
+<+<-
Constantly when being read
Writing DUTY8 disables 1/16 1/32 duty selection using LDUTY After initial reset, this status until conclusion hardware first sampling. Initial value according supply voltage detected first hardware sampling after initial reset. Until conclusion first sampling, SVD0-SVD3 data undefined.
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PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(d) Memory (00FF20H-00FF25H)
Address 00FF20 00FF21 00FF22 00FF23 00FF24 00FF25 Name PK01 PK00 PSIF1 PSIF0 PSW1 PSW0 PTM1 PTM0 PPT1 PPT0 PK11 PK10 ESW100 ESW10 ESW1 ETM32 ETM8 ETM2 ETM1 EPT1 EPT0 EK0H EK0L ESERR ESREC ESTRA FSW100 FSW10 FSW1 FTM32 FTM8 FTM2 FTM1 FPT1 FPT0 FK0H FK0L FSERR FSREC FSTRA Function K00-K07 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register Programmable timer interrupt priority register interrupt priority register
PPT1 PPT0 PK11 PK10 Priority level Level Level Level Level PK01 PSIF1 PSW1 PTM1 PK00 PSIF0 PSW0 Priority PTM0 level Level Level Level Level
Comment
Constantly when being read
Stopwatch timer interrupt enable register Stopwatch timer interrupt enable register Stopwatch timer interrupt enable register Interrupt Clock timer interrupt enable register enable Clock timer interrupt enable register Clock timer interrupt enable register Clock timer interrupt enable register Programmable timer interrupt enable register Programmable timer interrupt enable register interrupt enable register K04-K07 interrupt enable register Interrupt K00-K03 interrupt enable register enable Serial (error) interrupt enable register Serial (receiving) interrupt enable register Serial (transmitting) interrupt enable register Stopwatch timer interrupt factor flag Stopwatch timer interrupt factor flag Interrupt Stopwatch timer interrupt factor flag factor Clock timer interrupt factor flag generated Clock timer interrupt factor flag Clock timer interrupt factor flag Reset Clock timer interrupt factor flag Programmable timer interrupt factor flag Programmable timer interrupt factor flag Interrupt interrupt factor flag factor K04-K07 interrupt factor flag generated K00-K03 interrupt factor flag Serial (error) interrupt factor flag Serial (receiving) interrupt factor flag Reset Serial (transmitting) interrupt factor flag
when being read
Interrupt disable
Interrupt disable
interrupt factor generated operation interrupt factor generated
when being read
operation
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PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(e) Memory (00FF28H-00FF31H)
Address Name Function
PADC1 PADC0 Prohibited Prohibited Enable
Priority Level Level Level Level Disable
Comment
00FF28 PADC1 converter interrupt priority register PADC0 00FF2A 00FF2C 00FF30 00FF31 MODE16 CHSEL PTOUT CKSEL1 CKSEL0 EVCNT FCSEL Reserved Reserved converter interrupt enable register Reserved converter interrupt factor flag
write "1".
Constantly when being read
Constantly when being read
Generated generated Reset operation 8-bit Timer fOSC1 fOSC1 Timer Normal mode Without
Reserved 8/16-bit mode selection 16-bit TOUT output channel selection Timer TOUT output control Prescaler source clock selection fOSC3 Prescaler source clock selection fOSC3 Timer counter mode selection Event counter Timer timer mode Pulse width function selection measurement event counter mode With Timer pulse polarity selection
Constantly when being read
Constantly when being read
noise rejector noise rejector
PLPOL
Down count timing event counter mode pulse width measurement mode PSC01 Timer prescaler dividing ratio selection PSC01 PSC00 Prescaler dividing ratio Source clock PSC00 Source clock Source clock Source clock CONT0 Timer continuous/one-shot mode selection PSET0 Timer preset PRUN0 Timer Run/Stop control
Rising edge Falling edge input input High level level measurement measurement input input
Continuous Preset
One-shot operation Stop
when being read
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Table 5.1.1(f) Memory (00FF32H-00FF36H)
Address 00FF32 Name PSC11 Function Comment
Constantly when being read
Timer prescaler dividing ratio selection PSC11 PSC10 Prescaler dividing ratio Source clock PSC10 Source clock Source clock Source clock CONT1 Timer continuous/one-shot mode selection Continuous One-shot PSET1 Timer preset Preset operation PRUN1 Timer Run/Stop control Stop 00FF33 RLD07 Timer reload data (MSB) RLD06 Timer reload data RLD05 Timer reload data RLD04 Timer reload data High RLD03 Timer reload data RLD02 Timer reload data RLD01 Timer reload data RLD00 Timer reload data (LSB) 00FF34 RLD17 Timer reload data (MSB) RLD16 Timer reload data RLD15 Timer reload data RLD14 Timer reload data High RLD13 Timer reload data RLD12 Timer reload data RLD11 Timer reload data RLD10 Timer reload data (LSB) 00FF35 PTD07 Timer counter data (MSB) PTD06 Timer counter data PTD05 Timer counter data PTD04 Timer counter data High PTD03 Timer counter data PTD02 Timer counter data PTD01 Timer counter data PTD00 Timer counter data (LSB) 00FF36 PTD17 Timer counter data (MSB) PTD16 Timer counter data PTD15 Timer counter data PTD14 Timer counter data High PTD13 Timer counter data PTD12 Timer counter data PTD11 Timer counter data PTD10 Timer counter data (LSB)
when being read
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Table 5.1.1(g) Memory (00FF40H-00FF44H)
Address Name FOUT frequency selection
FOUT2 FOUT1 FOUT0 Frequency
Function
Comment
when being read
00FF40 FOUT2
FOUT1
FOUT0
fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3
Reset Reset operation operation Stop
FOUTON FOUT output control WDRST Watchdog timer reset TMRST Clock timer reset TMRUN Clock timer Run/Stop control 00FF41 00FF42 00FF43 TMD7 TMD6 TMD5 TMD4 TMD3 TMD2 TMD1 TMD0 SWRST SWRUN SWD7 SWD6 SWD5 SWD4 SWD3 SWD2 SWD1 Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data
Constantly when being read
High
Stopwatch timer reset Stopwatch timer Run/Stop control Stopwatch timer data (1/10 sec) Stopwatch timer data (1/100 sec) One-shot buzzer forcibly stop One-shot buzzer trigger/status
Reset
operation Stop
Constantly when being read
SWD0 00FF44 BZSTP BZSHT
Forcibly stop operation Busy Trigger msec Reset Ready operation 31.25 msec operation
Constantly when
being read
SHTPW One-shot buzzer duration width selection ENREnvelope attenuation time ENRST Envelope reset ENON Envelope On/Off control BZON Buzzer output control Reset during one-shot output.
when being read
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Table 5.1.1(h) Memory (00FF45H-00FF49H)
Address Name Function Buzzer signal duty ratio selection
DUTY2-0
Comment
when being read
00FF45 DUTY2
DUTY1
Buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3
DUTY0
8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16
8/20 12/24 12/28 7/20 11/24 11/28 6/20 10/24 10/28 5/20 9/24 9/28 4/20 8/24 8/28 3/20 7/24 7/28 2/20 6/24 6/28 1/20 5/24 5/28
Frequency (Hz)
BZFQ2
Buzzer frequency selection
BZFQ2 BZFQ1 BZFQ0
when being read
BZFQ1
BZFQ0
4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3
parity Even
00FF48
Parity enable register With parity Parity mode selection Clock source selection SCS1 SCS0 Clock source Programmable timer SCS0 fOSC3 fOSC3 fOSC3 SMD1 Serial mode selection SMD1 SMD0 Mode Asynchronous 8-bit SMD0 Asynchronous 7-bit Clock synchronous slave Clock synchronous master ESIF Serial enable register Serial 00FF49 Framing error flag Error Reset Parity error flag Error Reset Overrun error flag Error Reset RXTRG Receive trigger/status Trigger RXEN Receive enable Enable TXTRG Transmit trigger/status Trigger TXEN Transmit enable Enable
SCS1
when being read
Only asynchronous mode
clock synchronous slave mode,
external clock
selected.
port error operation error operation error operation Stop operation Disable Stop operation Disable
when being read
Only asynchronous mode
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PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(i) Memory (00FF4AH-00FF54H)
Address 00FF4A 00FF50 00FF51 00FF52 00FF53 00FF54 Name TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 SIK07 SIK06 SIK05 SIK04 SIK03 SIK02 SIK01 SIK00 SIK11 SIK10 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 KCP11 KCP10 K07D K06D K05D K04D K03D K02D K01D K00D Function Transmit/Receive data (MSB) Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data Transmit/Receive data (LSB) interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register input port data input port data input port data input port data input port data input port data input port data input port data Comment
High
Interrupt enable
Interrupt disable
Interrupt enable
Interrupt disable
Constantly when being read
Interrupt generated falling edge
Interrupt generated rising edge
Falling edge
Rising edge
Constantly when being read
High level input
level input
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PERIPHERAL CIRCUITS THEIR OPERATION (I/O Memory Map)
Table 5.1.1(j) Memory (00FF55H-00FF70H)
Address 00FF55 00FF60 00FF61 00FF62 00FF63 00FF70 Name K11D K10D IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 P07D P06D P05D P04D P03D P02D P01D P00D P17D P16D P15D P14D P13D P12D P11D P10D HZR51 HZR50 HZR4H HZR4L HZR1H HZR1L HZR0H HZR0L Function input port data input port data control register control register control register control register control register control register control register control register control register control register control register control register control register control register control register control register port data port data port data port data port data port data port data port data port data port data port data port data port data port data port data port data high impedance control high impedance control register register R14-R17 high impedance control R10-R13 high impedance control R04-R07 high impedance control R00-R03 high impedance control
High level input
Comment
Constantly when being read
level input
Output
Input
Output
Input
High
High
High impedance
Complementary
Reserved register
High impedance
Complementary
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Table 5.1.1(k) Memory (00FF71H-00FF76H)
Address 00FF71 00FF72 00FF73 00FF74 00FF75 00FF76 Name HZR27 HZR26 HZR25 HZR24 HZR23 HZR22 HZR21 HZR20 HZR37 HZR36 HZR35 HZR34 HZR33 HZR32 HZR31 HZR30 R07D R06D R05D R04D R03D R02D R01D R00D R17D R16D R15D R14D R13D R12D R11D R10D R27D R26D R25D R24D R23D R22D R21D R20D R37D R36D R35D R34D R33D R32D R31D R30D Function high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control high impedance control output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data output port data Comment
High impedance
Complementary
High impedance
Complementary
High
High
High
High
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Table 5.1.1(l) Memory (00FF77H-00FF82H)
Address 00FF77 00FF78 00FF80 Name R47D R46D R45D R44D R43D R42D R41D R40D R51D R50D PRAD PSAD2 Function register register register register register register register register output port data output port data converter clock control converter division ratio
PSAD2 PSAD1 PSAD0 Division ratio
Comment
Reserved register
High High
Constantly when being read
Constantly when being read
PSAD1
PSAD0
fOSC1 fOSC3 fOSC3 fOSC3 fOSC3 fOSC3 fOSC3 fOSC3
converter input Start Invalid port
00FF81 00FF82
PAD7 PAD6 PAD5 PAD4 ADRUN CHS1
CHS0
converter input control converter input control converter input control converter input control conversion start control register Analog input channel selection CHS1 CHS0 Input channel
Constantly when being read
Constantly when being read
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Table 5.1.1(m) Memory (00FF83H-00FF84H)
Address 00FF83 00FF84 Name ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Function conversion result (MSB) conversion result conversion result conversion result conversion result conversion result conversion result conversion result conversion result conversion result (LSB) Comment
Constantly when being read
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System Controller Control
system controller management unit which sets such items mode accordance with memory system configuration factors. purposes controlling system, following settings performed software: mode (CPU mode) settings Chip enable (CE) signal output settings WAIT state settings external memory authority release request acknowledge signal (BREQ/BACK) settings Page address setting stack pointer
Below description these settings made.
5.2.1 mode settings
explained "3.5.2 mode", S1C88349 four modes. Settings modes must made software must match capacity external memory. shown Table 5.2.1.1, mode settings performed basis preset values each mode written registers BSMD0 BSMD1.
Table 5.2.1.1 mode settings
Setting value BSMD1 BSMD0
mode Expanded 512K maximum mode Expanded 512K minimum mode Expanded mode Single chip mode (MCU) Optional setting expanded modes (MPU)
Configuration external memory ROM+RAM>64K bytes (Program>64K bytes) ROM+RAM>64K bytes (Program64K bytes) ROM+RAM64K bytes None above
single chip mode setting only possible when this used mode. single chip mode setting incompatible with mode, since this mode does utilize internal ROM. When using mode, necessary select mode time initial resetting time <BSMD1 BSMD0 "0"> setting from among three types expanded modes (expanded mode, expanded 512K minimum mode expanded 512K maximum mode) mask option. Select expanded 512K maximum mode this option, when mode used all.
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function terminals shown Table 5.2.1.2 accordance with mode selection. Table 5.2.1.2 terminal settings mode Single chip Expanded mode Expanded 512K mode Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port Address Output port signal Output port signal port Data port Data port Data port Data port Data port Data port Data port Data
Terminal
initial reset, mode explained below. mode: initial reset, S1C88349 single chip mode. Accordingly, mode, even memory been externally expanded, system activated program written internal ROM. system with externally expanded memory, perform applicable mode settings during initialization routine originating internal ROM. mode: When mode used, expanded mode (expanded mode, expanded 512K minimum mode expanded 512K maximum mode) during initial reset must preselected mask option. should conform properly system configuration.
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5.2.2 Address decoder output) settings
explained Section 3.6.4, S1C88349 equipped with address decoders that output maximum four chip enable signals (CE0-CE3) external devices. output terminals output circuits CE0- shared with output ports R30-R33. initial reset, they output port terminals. this reason, when operating mode other than single chip mode, ports used signal output terminals must such. This setting performed through software which writes registers CE0-CE3 corresponding signals used. Table 5.2.2.1 shows address range assigned four chip enable (CE) signals.
arrangement memory space external devices does necessarily have continuous from subordinate address chip enable signals used assign areas memory. However, mode, program memory must assigned CE0. expanded 512K mode, address range each signals fixed. expanded mode, four address ranges, which match amount memory use, selected with registers CEMD0 CEMD1. These signals only output when appointed external memory area accessed output when internal memory accessed.
Table 5.2.2.1 Address settings CE0-CE3 Expanded mode (MPU mode only)
CEMD1 CEMD0 Chip size bytes bytes bytes bytes 000000H-00EFFFH 000000H-007FFFH 008000H-00EFFFH 000000H-003FFFH 004000H-007FFFH 008000H-00BFFFH 00C000H-00EFFFH 000000H-001FFFH 002000H-003FFFH 004000H-005FFFH 006000H-007FFFH
Expanded 512K minimum/maximum modes
signal Address range mode 200000H-27FFFFH 080000H-0FFFFFH 100000H-17FFFFH 180000H-1FFFFFH mode 000000H-00EFFFH, 010000H-07FFFFH 080000H-0FFFFFH 100000H-17FFFFH 180000H-1FFFFFH
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5.2.3 WAIT state settings
order insure accessing external speed devices during high speed operations, S1C88349 equipped with WAIT function which prolongs access time. number wait states inserted selected from choice eight shown Table 5.2.3.1 means registers WT0-WT2. Table 5.2.3.1 Setting number WAIT states
Number inserted states wait
5.2.5 Stack page setting
Although stack area used evacuate registers during subroutine calls arbitrarily moved area data using stack pointer page address registers SPP0-SPP7 memory. initial reset, SPP0-SPP7 "00H" (page Since internal arranged page (00F000H-00F7FFH), stack area single chip mode inevitably located page expanded mode where externally expanded, stack page likewise limited page order place stack area final address internal RAM, stack pointer placed initial setting "F800H". pre-decremented.) expanded 512K mode, place stack external expanded RAM, corresponding page SPP0-SPP7. page addresses which SPP0- SPP7 00H-27H must within area. page each recurrent division data memory beginning address zero.
state cycles clock length. WAIT states software inserted between cycle states T3-T4. Note, however, that WAIT states cannot inserted when internal register internal memory being accessed when operating with OSC1 oscillation circuit (see "5.4 Oscillation Circuits Operating Mode"). Consequently, WAIT state settings single chip mode meaningless. With regard WAIT insertion timing, Section 3.6.5, "WAIT control".
5.2.4 Setting authority release request signal
With systems performing transfer, authority release request signal (BREQ) input terminal acknowledge signal (BACK) output terminal have set. BREQ input terminal shared with input port terminal BACK output terminal with output port terminal R51. initial reset, these terminal facilities input port terminal output port terminal, respectively. terminals altered function BREQ/BACK terminals writing register EBR. details authority release, "3.6.6 authority release state" "S1C88 Core Manual".
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5.2.6 Control system controller
Table 5.2.6.1 shows control bits system controller. Table 5.2.6.1(a) System controller control bits (MCU mode)
Address Name Function 00FF00 BSMD1 mode (CPU mode) (MCU) BSMD1 BSMD0 Mode 512K (Maximum) BSMD0 512K (Minimum) Single chip CEMD1 register Comment
BSMD1-0 01B.
CEMD0 register
00FF01 00FF02
SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0
(R33) signal output Enable/Disable (R32) Enable: signal output (R31) Disable: (R3x) output (R30) Stack pointer page address (MSB) page allocatable address Single chip mode: only page mode: only page 512K (min) mode: 0-27H page 512K (max) mode: 0-27H page (LSB) release enable register (K11 terminal specification) Wait control register Number state wait
enable disable enable disable enable disable enable disable BREQ BACK Input port Output port
Single chip mode, these setting fixed output.
CLKCHG operating clock switch OSCC OSC3 oscillation On/Off control Operating mode selection VDC1 VDC1 VDC0 Operating mode High speed (VD1=3.3V) power (VD1=1.2V) VDC0 Normal (VD1=2.2V)
OSC3
OSC1
Note:
interrupts including disabled, until write optional value into both "00FF00H" "00FF01H" addresses.
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Table 5.2.6.1(b) System controller control bits (MPU mode)
Address Name Function 00FF00 BSMD1 mode (CPU mode) (MPU) BSMD1 BSMD0 Mode 512K (Maximum) BSMD0 512K (Minimum) Option selection CEMD1 Chip enable mode CEMD1 CEMD0 Mode (CE0) CEMD0 (CE0, CE1) (CE0-CE3) (CE0-CE3) (R33) signal output Enable/Disable (R32) Enable: signal output (R31) Disable: (R3x) output (R30) 00FF01 SPP7 Stack pointer page address (MSB) SPP6 SPP5 page allocatable address SPP4 Single chip mode: only page SPP3 mode: only page SPP2 512K (min) mode: 0-27H page SPP1 512K (max) mode: 0-27H page SPP0 (LSB) 00FF02 release enable register (K11 terminal specification) Wait control register Number state wait CLKCHG operating clock switch OSCC OSC3 oscillation On/Off control Operating mode selection VDC1 VDC1 VDC0 Operating mode High speed (VD1=3.3V) power (VD1=1.2V) VDC0 Normal (VD1=2.2V) Comment Initial setting
selected among types (64K, 512K
512K max)
mask option setting.
Only
mode
enable enable enable enable BREQ BACK
disable disable disable disable Input port Output port
OSC3
OSC1
Note:
interrupts including disabled, until write optional value into both "00FF00H" "00FF01H" addresses.
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BSMD0, BSMD1:
modes shown Table 5.2.6.2. Table 5.2.6.2 mode settings
Setting values BSMD1 BSMD0 mode Expanded 512K maximum mode Expanded 512K minimum mode Expanded mode Single chip mode (MCU) Optional setting expanded modes (MPU)
CE0-CE3:
Sets output terminals being used. When written: output enable When written: output disable Reading: Valid output enabled when written registers CE0-CE3 which correspond output being used. written registers disables signal output from that terminal reverts alternate function output port terminal (R30-R33). initial reset, register mode mode, register. Registers CE1-CE3 always regardless MCU/MPU mode setting.
single chip mode setting only possible when this used mode. single chip mode setting incompatible with mode, since this mode does utilize internal ROM. When using mode, necessary select mode time initial resetting time <BSMD1 BSMD0 "0"> setting from among three types expanded modes (expanded mode, expanded 512K minimum mode expanded 512K maximum mode) mask option. Select expanded 512K maximum mode this option, when mode used all. initial reset, mode unit single chip mode mode mask option used select applicable mode.
Note: avoid malfunction from interrupt generated before configuration initialized, interrupts including masked until write optional value into address "00FF00H".
SPP0-SPP7: 00FF01H
Sets page address stack area. single chip mode expanded mode, page address "00H". expanded 512K mode, value within range "00H"-"27H". Since carry borrow from/to stack pointer reflected register SPP, upper limit continuous stack area bytes. initial reset, this register "00H" (page
CEMD0, CEMD1:
Sets signal address range (valid only expanded mode). Settings made according external memory chip size shown Table 5.2.6.3. Table 5.2.6.3 signal settings
CEMD1 CEMD0 Address range Usable terminals bytes bytes bytes bytes CE0, CE0-CE3 CE0-CE3
Note: avoid malfunction from interrupt generated before configuration initialized, interrupts including disabled, until write optional value into "00FF01H" address. Furthermore, avoid generating interrupt while stack area being set, interrupts including disabled instruction execution period after writing address "00FF01H".
These settings invalid mode other than expanded mode. initial reset, each register (64K bytes). Settings these registers valid only mode. CEMD0 CEMD1 used general purpose registers with read/write capabilities mode.
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WT0-WT2:
WAIT state settings performed. number WAIT states inserted based register settings shown Table 5.2.6.4. Table 5.2.6.4 Setting WAIT states
Number inserted states wait
5.2.7 Programming notes
interrupts including masked, until write optional value into both "00FF00H" "00FF01H" addresses. Consequently, even change content this address (You initial value, is.), should still sure perform writing operation using initialization routine. When setting stack fields, including page addresses well, should write them order register ("00FF01H") stack pointer Example: When setting "178000H" address #00H #0FF01H During this period [HL], #17H interrupts (including #8000H NMI) masked.
state cycles clock length. initial reset, this register wait).
EBR:
Sets BREQ/BACK terminals function. When written: BREQ/BACK enabled When written: BREQ/BACK disabled Reading: Valid BREQ BACK terminal functions set. Writing enables BREQ/BACK input/ output. Writing sets BREQ terminal input port terminal BACK terminal output port terminal R51. initial reset, (BREQ/BACK disabled).
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Watchdog Timer
5.3.1 Configuration watchdog timer
S1C88349 equipped with watchdog timer driven OSC1 source oscillation. watchdog timer must reset periodically software, reset more than seconds (when fOSC1 32.768 kHz) does take place, non-maskable interrupt signal generated output CPU. Figure 5.3.1.1 block diagram watchdog timer.
fOSC1 OSC1 Divider oscillation circuit
5.3.2 Interrupt function
cases where watchdog timer periodically reset software, watchdog timer outputs interrupt signal CPU's (level input. Unmaskable taking priority over other interrupts, this interrupt triggers generation exception processing. "S1C88 Core Manual" more details exception processing. This exception processing vector 000004H.
5.3.3 Control watchdog timer
Table 5.3.3.1 shows control bits watchdog timer.
Watchdog timer
Non-maskable interrupt (NMI)
WDRST
Watchdog timer reset signal
WDRST:
Resets watchdog timer. When written: Watchdog timer reset When written: operation Reading: Constantly writing WDRST, watchdog timer reset, after which immediately restarted. Writing will mean operation. Since WDRST writing only, constantly during readout.
Fig. 5.3.1.1 Block diagram watchdog timer running watchdog timer reset during main routine program, possible detect program runaway watchdog timer processing been applied. Normally, this routine integrated points that regularly being processed. watchdog timer continues operate during HALT when HALT state continuous longer than seconds, shifts exception processing. During SLEEP, watchdog timer stopped.
5.3.4 Programming notes
watchdog timer must reset within 3-second cycles software. execute instruction msec after interrupt occurred (when fOSC1 32.768 kHz).
Table 5.3.3.1 Watchdog timer control bits
Address Name Function FOUT frequency selection
FOUT2 FOUT1 FOUT0 Frequency
Comment
when being read
00FF40 FOUT2
FOUT1
FOUT0
fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3
Reset Reset operation operation Stop
FOUTON WDRST TMRST TMRUN
FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control
Constantly when being read
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Oscillation Circuits Operating Mode
5.4.1 Configuration oscillation circuits
S1C88349 twin clock system with internal oscillation circuits (OSC1 OSC3). OSC1 oscillation circuit generates 32.768 (Typ.) main clock OSC3 oscillation circuit sub-clock when some peripheral circuits (output port, serial interface programmable timer) high speed operation. Figure 5.4.1.1 shows configuration oscillation circuit.
OSC1 oscillation circuit Clock switch OSC3 oscillation circuit SLEEP status
Oscillation circuit control signal peripheral circuit (fOSC1) (CLK) some peripheral circuit (fOSC3)
5.4.3 OSC1 oscillation circuit
OSC1 oscillation circuit generates 32.768 (Typ.) system clock which utilized during speed operation (low power mode) peripheral circuits. Furthermore, even when OSC3 utilized system clock, OSC1 continues generate source clock clock timer stopwatch timer. This oscillation circuit stops when instruction executed. However, case circuit executing instruction, oscillation stopped synchronization with completion sampling. terms oscillation circuit types, either crystal oscillation, oscillation, crystal oscillation (gate capacitor built-in) external clock input selected with mask option. Figure 5.4.3.1 shows configuration OSC1 oscillation circuit.
SLEEP status OSC1 fOSC1
clock selection signal
X'tal1 OSC2
OSCC
CLKCHG
Fig. 5.4.1.1 Configuration oscillation circuits initial reset, OSC1 oscillation circuit selected operating clock OSC3 oscillation circuit stopped state. ON/OFF switching OSC3 oscillation circuit switching system clock between OSC1 OSC3 controlled software. OSC3 circuit utilized when high speed operation some peripheral circuits become necessary. Otherwise, OSC1 should used generate operating clock OSC3 circuit placed stopped state order reduce current consumption.
Crystal oscillation circuit
SLEEP status OSC1 fOSC1 External clock N.C. OSC2
External clock input
OSC1
5.4.2 Mask option
OSC1 oscillation circuit Crystal oscillation circuit External clock input oscillation circuit Crystal oscillation circuit (gate capacitor built-in) OSC3 oscillation circuit Crystal oscillation circuit Ceramic oscillation circuit oscillation circuit External clock input terms oscillation circuit types OSC1, either crystal oscillation, oscillation, crystal oscillation (gate capacitor built-in) external clock input selected with mask option. terms oscillation circuit types OSC3, either crystal oscillation, ceramic oscillation, oscillation external clock input selected with mask option, same OSC1.
RCR1
fOSC1
OSC2
SLEEP status
oscillation circuit
SLEEP status OSC1
fOSC1
X'tal1 OSC2
Crystal oscillation circuit (gate capacitor built-in) Fig. 5.4.3.1 OSC1 oscillation circuit
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When crystal oscillation selected, crystal oscillation circuit easily formed connecting crystal oscillator X'tal1 (Typ. 32.768 kHz) between OSC1 OSC2 terminals along with trimmer capacitor (5-25 between OSC1 terminal VSS. addition, gate capacitor built into circuit mask option. When oscillation selected, connect resistor (RCR1) between OSC1 OSC2 terminals. When external input selected, release OSC2 terminal input rectangular wave clock into OSC1 terminal.
When crystal ceramic oscillation circuit selected, crystal ceramic oscillation circuit formed connecting either crystal oscillator (X'tal2) combination ceramic oscillator (Ceramic) feedback resistor (Rf) between OSC3 OSC4 terminals connecting capacitors (CG2, CD2) between OSC3 terminal VSS, between OSC4 terminal VSS, respectively. When oscillation selected, oscillation circuit formed merely connecting resistor (RCR3) between OSC3 OSC4 terminals. When external input selected, release OSC4 terminal input rectangular wave clock into OSC3 terminal.
5.4.4 OSC3 oscillation circuit
OSC3 oscillation circuit generates system clock when some peripheral circuits (output port, serial interface programmable timer) high speed operation. This oscillation circuit stops when instruction executed, OSCC register "0". terms oscillation circuit types, crystal oscillation, ceramic oscillation, oscillation external clock input selected with mask option. Figure 5.4.4.1 shows configuration OSC3 oscillation circuit.
OSC3
X'tal Ceramic
5.4.5 Operating mode
select three types operating modes using software, obtain stable operation good characteristics (operating frequency current consumption) over broad operation voltage. Here below indicated features respective modes. Normal mode (VDD V-5.5 This mode following initial reset. permits OSC3 oscillation circuit (Max. MHz) used also permits relative power operation. power mode (VDD V-3.5 This lower power mode than normal mode. makes ultra-low power consumption possible operation OSC1 oscillation circuit, although OSC3 circuit cannot used. High speed mode (VDD V-5.5 This mode permits higher speed operation than normal mode. Since OSC3 oscillation circuit (Max. MHz) used, should this mode, when require operation more. However, current consumption will increase relative normal mode.
fOSC3
OSC4
Oscillation circuit control signal SLEEP status
Crystal/Ceramic oscillation circuit
OSC3 fOSC3 RCR3 Oscillation circuit control signal SLEEP status
OSC4
oscillation circuit
OSC3 External clock N.C. OSC4 fOSC3
Oscillation circuit control signal SLEEP status
External clock input Fig. 5.4.4.1 OSC3 oscillation circuit
Using software switch over among above three modes meet your actual usage circumstances will make possible power system. example, will able reduce current consumption switching over normal mode when using OSC3 clock and, conversely, changing over power mode when using OSC1 clock (OSC3 oscillation circuit OFF).
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Note: turn OSC3 oscillation circuit power mode. switch over operating mode (normal mode high speed mode) OSC3 oscillation circuit status, this will cause faulty operation. modes, power mode high speed mode application, with respect operating voltages.
this case, since several msec several tens msec necessary oscillation stabilize after turning OSC3 oscillation circuit should switch over clock after stabilization time elapsed. (The oscillation start time will vary somewhat depending oscillator externally attached parts. Refer oscillation start time example indicated Chapter "ELECTRICAL CHARACTERISTICS".) When switching over from OSC3 OSC1, turn OSC3 oscillation circuit immediately following clock changeover. basic clock switching procedure described above, however, must also combine with changeover operating mode permit current consumption high speed operation. Figure 5.4.6.1 indicates status transition diagram operation mode clock changeover.
5.4.6 Switching clocks
either OSC1 OSC3 system clock switch over means software. save power turning OSC3 oscillation circuit while operating OSC1. When must operate OSC3, change high speed operation turning OSC3 oscillation circuit switching over system clock.
Program Execution Status
High speed mode OSCC=1 OSC1 OSC3 clock OSC1 OSCC=0
VDC0= VDC1=1 VDC0=0 VDC1=0
Note: When turning OSC3 oscillation circuit after switching operating mode, should allow minimum waiting time msec.
High speed mode CLKCHG=1 High speed mode OSC1 OSC1 OSC3 OSC3 clock OSC1 CLKCHG=0 clock OSC3
RESET Normal mode OSCC=1 OSC1 OSC3 clock OSC1 OSCC=0
VDC0=0 VDC1=0 VDC0=1 VDC1=0
Normal mode Normal mode CLKCHG=1 OSC1 OSC1 OSC3 OSC3 clock OSC1 CLKCHG=0 clock OSC3
power mode OSC1 OSC3 clock OSC1
Interrupt
HALT instruction
Interrupt (Input interrupt)
instruction
HALT status OSC1 OSC3 clock STOP
SLEEP status OSC1 OSC3 clock STOP
Standby Status
Fig. 5.4.6.1 Status transition diagram operation mode clock changeover
return destination from standby status becomes program execution status prior shifting standby status
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5.4.7 Control oscillation circuit operating mode
Table 5.4.7.1 shows control bits oscillation circuits operating modes. Table 5.4.7.1 Oscillation circuit operating mode control bits
Address Name 00FF02 Function release enable register (K11 terminal specification) Wait control register Number state wait
BREQ BACK
Input port Output port
Comment
CLKCHG operating clock switch OSCC OSC3 oscillation On/Off control Operating mode selection VDC1 VDC1 VDC0 Operating mode High speed (VD1=3.3V) power (VD1=1.2V) VDC0 Normal (VD1=2.2V)
OSC3
OSC1
VDC1, VDC0:
Selects operating mode according supply voltage operating frequency. Table 5.4.7.2 shows correspondence between register preset values operating modes. Table 5.4.7.2 Correspondence between register preset values operating modes
Operating mode Normal mode power mode High speed mode VDC1 VDC0 Power voltage Operating frequency
OSCC:
Controls settings OSC3 oscillation circuit. When written: OSC3 oscillation When written: OSC3 oscillation Reading: Valid When some peripheral circuits (output port, serial interface programmable timer) operated high speed, OSCC "1". other times, should order reduce current consumption. initial reset, OSCC (OSC3 oscillation OFF).
2.4-5.5 (Max.) 1.8-3.5 (Max.) 3.5-5.5 (Max.)
voltage value where been made standard (GND). initial reset, this register (normal mode).
CLKCHG:
Selects operating clock CPU. When written: OSC3 clock When written: OSC1 clock Reading: Valid When operating clock switched OSC3, CLKCHG should when clock switched OSC1, CLKCHG should "0". initial reset, CLKCHG (OSC1 clock).
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5.4.8 Programming notes
When high speed operation necessary, should operate peripheral circuits according setting outline indicate below. operating clock OSC1 OSC3 oscillation circuit (When OSC3 clock necessary some peripheral circuits.) Operating mode power mode (When VDD-VSS less) Normal mode (When VDD-VSS more) turn OSC3 oscillation circuit power mode. switch over operating mode (normal mode high speed mode) OSC3 oscillation circuit status, this will cause faulty operation. When turning OSC3 oscillation circuit after switching operating mode, should allow minimum waiting time msec. Since several msec several tens msec necessary oscillation stabilize after turning OSC3 oscillation circuit Consequently, should switch operating clock (OSC1 OSC3) after allowing sufficient waiting time once OSC3 oscillation goes (The oscillation start time will vary somewhat depending oscillator externally attached parts. Refer oscillation start time example indicated Chapter "ELECTRICAL CHARACTERISTICS".) When switching clock from OSC3 OSC1, sure switch OSC3 oscillation with separate instructions. Using single instruction process simultaneously cause malfunction CPU.
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Input Ports ports)
5.5.1 Configuration input ports
S1C88349 equipped with input port bits (K00-K07, K11) which usable general purpose input port terminals with interrupt function. terminal doubles external clock (EVIN) input terminal programmable timer (event counter) with input port functions sharing input signal (See "5.11 Programmable Timer") Furthermore, should noted, however, that terminal shared with authority release request signal (BREQ) input terminal. Function assignment this terminal selected software. When this terminal selected BREQ signal, cannot used input port. (See "5.2 System Controller Control") explanation below, assumed that input port. Each input port equipped with pull-up resistor. mask option used select either "With resistor" "Gate direct" each input port. Figure 5.5.1.1 shows structure input port.
Mask option Input interrupt circuit
5.5.2 Mask option
Input port pull-up resistors With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor With resistor Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct
Gate direct Gate direct
Input ports K00-K07, equipped with pull-up resistors. mask option used select 'With resistor' 'Gate direct' each port (bit). 'With resistor' option rendered suitable purposes such push switch matrix input. When changing input terminal from level HIGH with built-in pull-up resistor, delay waveform rise time will occur depending time constant pull-up resistor load capacitance terminal. necessary appropriate wait time introduction input port. particular, special attention should paid scan matrix formation. Make this wait time amount time more calculated following expression.
Wait time (CIN load capacitance board) [sec] RIN: Pull resistance Max. value CIN: Terminal capacitance Max. value
KxxD
Address
Data
Fig. 5.5.1.1 Structure input port Each input port terminal directly connected three-state buffer data bus. Furthermore, input signal state instant input port readout read that form data.
When 'Gate direct' selected, pull-up resistor detached port rendered suitable purposes such slide switch input interfacing with other LSIs. this case, take care that floating state does occur input. unused input ports, select default setting "With resistor".
S1C88349 TECHNICAL MANUAL
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PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
5.5.3 Interrupt function input comparison register
Input port K00-K07, equipped with interrupt function. These input ports divided into three groupings: K00-K03 (K0L), K04- (K0H) K10-K11 (K1). Furthermore, interrupt generation condition each series terminals software. When interrupt generation condition each series terminals met, interrupt factor flag FK0L, FK0H corresponding applicable series interrupt generated.
Interrupt prohibited setting interrupt enable registers EK0L, EK0H corresponding interrupt factor flags. Furthermore, priority level input interrupt desired level (0-3) using interrupt priority registers PK00-PK01 PK10- PK11 corresponding each groups (K00-K07) (K10-K11). details interrupt control registers above operations subsequent interrupt generation, "5.17 Interrupt Standby Status". exception processing vectors each interrupt factor follows: input interrupt: 00000AH K04-K07 input interrupt: 00000CH K00-K03 input interrupt: 00000EH Figure 5.5.3.1 shows configuration input interrupt circuit.
Interrupt factor flag FK0L Address Interrupt enable register EK0L Address Interrupt priority register PK00, PK01
Input port K00D Input comparison register KCP00 Address Interrupt selection register SIK00 Address
Input port K04D Input comparison register KCP04 Address Interrupt selection register SIK04 Address
Interrupt priority level judgement circuit
Interrupt request
Address
Data
Interrupt factor flag FK0H Address Interrupt enable register EK0H Address
Input port K10D Input comparison register KCP10 Address Interrupt selection register SIK10 Address Address Interrupt priority register PK10, PK11 Address
Interrupt factor flag Address Interrupt enable register Interrupt priority level judgement circuit Interrupt request
Fig. 5.5.3.1 Configuration input interrupt circuit
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S1C88349 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
interrupt selection registers SIK00-SIK03, SIK04-SIK07 SIK10-SIK11 input comparison registers KCP00-KCP03, KCP04-KCP07 KCP10-KCP11 each port used interrupt generation condition described above. Input port interrupt permitted prohibited setting interrupt selection register SIK. contrast interrupt enable register which masks interrupt factor each series terminals, interrupt selection register masks units. input comparison register selects whether interrupt each input port will generated rising edge falling edge input. When data content input terminals which interrupt been permitted interrupt selection register data content input comparison register change from conformity state non-conformity state, interrupt factor flag should interrupt generated. Figure 5.5.3.2 shows example interrupt generation series terminals (K00-K03).
Because interrupt been prohibited interrupt selection register SIK00, with settings shown (2), interrupt will generated. Since next settings figure, non-conformity between input terminal data K01-K03 where interrupt permitted data from input comparison registers KCP01- KCP03 generates interrupt. line with explanation above, since change contents input data input comparison registers from conformity state nonconformity state introduces interrupt generation condition, switching from non-conformity state another, case figure, will generate interrupt. Consequently, order able generate second interrupt, either input terminal must returned state where content once again conformity with that input comparison register KCP, input comparison register must reset. Input terminals which interrupt prohibited will influence interrupt generation condition. Interrupt generated exactly same other series terminals (K04-K07) (K10 K11).
Interrupt selection register SIK03 SIK02 SIK01 SIK00
Input comparison register KCP03 KCP02 KCP01 KCP00
With settings shown above, interrupt (K00-K03) generated under condition shown below. Input port
(Initial values)
Interrupt generation Because interrupt been prohibited K00, interrupt will generated when non-conformity occurs between contents three bits K01-K03 three bits input comparison register KCP01-KCP03.
Fig. 5.5.3.2 Interrupt generation example (K00-K03)
S1C88349 TECHNICAL MANUAL
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PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
5.5.4 Control input ports
Table 5.5.4.1 shows input port control bits. Table 5.5.4.1(a) Input port control bits
Address Name Function interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt selection register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register interrupt comparison register input port data input port data input port data input port data input port data input port data input port data input port data input port data input port data
Interrupt enable Interrupt disable Interrupt enable Interrupt disable
Comment
00FF50 SIK07 SIK06 SIK05 SIK04 SIK03 SIK02 SIK01 SIK00 00FF51 SIK11 SIK10 00FF52 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 00FF53 KCP01 KCP00
Constantly when being read
Interrupt generated falling edge
Interrupt generated rising edge
Falling edge
Rising edge
Constantly when being read
00FF54 00FF55 KCP11 KCP10 K07D K06D K05D K04D K03D K02D K01D K00D K11D K10D
High level input
level input
High level input
level input
Constantly when being read
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S1C88349 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
Table 5.5.4.1(b) Input port control bits
Address 00FF20 00FF21 00FF23 00FF25 Name PK01 PK00 PSIF1 PSIF0 PSW1 PSW0 PTM1 PTM0 PPT1 PPT0 PK11 PK10 EPT1 EPT0 EK0H EK0L ESERR ESREC ESTRA FPT1 FPT0 FK0H FK0L FSERR FSREC FSTRA Function K00-K07 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register Programmable timer interrupt priority register interrupt priority register Programmable timer interrupt enable register Programmable timer interrupt enable register interrupt enable register K04-K07 interrupt enable register K00-K03 interrupt enable register Serial (error) interrupt enable register Serial (receiving) interrupt enable register Serial (transmitting) interrupt enable register Programmable timer interrupt factor flag Programmable timer interrupt factor flag interrupt factor flag K04-K07 interrupt factor flag K00-K03 interrupt factor flag Serial (error) interrupt factor flag Serial (receiving) interrupt factor flag Serial (transmitting) interrupt factor flag
PPT1 PPT0 PK11 PK10 Priority level Level Level Level Level PK01 PSIF1 PSW1 PTM1 PK00 PSIF0 PSW0 Priority PTM0 level Level Level Level Level
Comment
Constantly when being read
Interrupt enable
Interrupt disable
Interrupt factor generated
interrupt factor generated
Reset
operation
K00D-K07D: 00FF54H K10D, K11D:
Input data input port terminal read out. When read: When read: Writing: HIGH level level Invalid
SIK00-SIK07: 00FF50H SIK10, SIK11:
Sets interrupt generation condition (interrupt permission/prohibition) input port terminals K00-K07, K11. When written: Interrupt permitted When written: Interrupt prohibited Reading: Valid SIKxx interrupt selection register which correspond input port Kxx. setting permits interrupt that input port prohibits Changes state input terminal which interrupt prohibited, will influence interrupt generation. initial reset, this register (interrupt prohibited).
terminal voltage each input port K00- K07, directly read either HIGH (VDD) level (VSS) level. This exclusively readout usable write operations.
S1C88349 TECHNICAL MANUAL
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PERIPHERAL CIRCUITS THEIR OPERATION (Input Ports)
KCP00-KCP07: 00FF52H KCP10, KCP11:
Sets interrupt generation condition (interrupt generation timing) input port terminals K00- K07, K11. When written: Falling edge When written: Rising edge Reading: Valid KCPxx input comparison register which correspond input port Kxx. Interrupt those ports which have been generated falling edge input those rising edge. initial reset, this register (falling edge).
FK0L, FK0H, FK1:
Indicates generation state input interrupt. When read: When read: Interrupt factor present Interrupt factor present
When written: Reset factor flag When written: Invalid interrupt factor flag FK0L corresponds K00- K03, FK0H K04-K07, K10-K11 they occurrence interrupt generation condition. When this manner, corresponding interrupt enable register corresponding interrupt priority register higher level than setting interrupt flags I1), interrupt will generated CPU. Regardless interrupt enable register interrupt priority register settings, interrupt factor flag will occurrence interrupt generation condition. accept subsequent interrupt after interrupt generation, re-setting interrupt flags (set interrupt flag lower level than level indicated interrupt priority registers, execute RETE instruction) interrupt factor flag reset necessary. interrupt factor flag reset writing "1". initial reset, this flag reset "0".
PK00, PK01: PK10, PK11:
Sets input interrupt priority level. bits PK00 PK01 interrupt priority registers corresponding interrupts K00-K07 (K0L K0H). Corresponding K10-K11 (K1), bits PK10 PK11 perform same function. Table 5.5.4.2 shows interrupt priority level which this register. Table 5.5.4.2 Interrupt priority level settings
PK11 PK01 PK10 PK00 Interrupt priority level Level (IRQ3) Level (IRQ2) Level (IRQ1) Level (None)
5.5.5 Programming note
When changing input terminal from level HIGH with built-in pull-up resistor, delay waveform rise time will occur depending time constant pull-up resistor load capacitance terminal. necessary appropriate wait time introduction input port. particular, special attention should paid scan matrix formation. Make this wait time amount time more calculated following expression.
Wait time (CIN load capacitance board) [sec] RIN: Pull resistance Max. value CIN: Terminal capacitance Max. value
initial reset, this register (level
EK0L, EK0H, EK1:
interrupt generation permitted prohibited. When written: Interrupt permitted When written: Interrupt prohibited Reading: Valid interrupt enable register EK0L corresponds K00-K03, EK0H K04-K07, K10-K11. Interrupt permitted those series terminals prohibited those "0". initial reset, this register (interrupt prohibited).
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S1C88349 TECHNICAL MANUAL
PERIPHERAL CIRCUITS THEIR OPERATION (Output Ports)
Output Ports ports)
5.6.1 Configuration output ports
S1C88349 equipped with bits output ports (R00-R07, R10-R17, R20-R27, R30-R37, R50, R51). Depending mode setting, configuration output ports vary shown table below. Table 5.6.1.1 Configuration output ports
Terminal Output port Output port Output port Output port mode
Single chip Expanded Expanded 512K
Only configuration output ports single chip mode will discussed here. With respect control, "5.2 System Controller Control". Figure 5.6.1.1 shows basic structure (excluding special output circuits) output ports.
Address High impedance control register
Data
Mask option
Data register
Address
Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port Output port
Data
Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address signal signal
open drain R00-R07 R10-R17 mask option.
Address High impedance control register Data register
Address
R20-R27, R30-R37, R50,
Fig. 5.6.1.1 Structure output ports modes other than single chip mode, data registers high impedance control registers output ports used function used general purpose registers with read/write capabilities. This will affect si
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