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MF1246-04
GATE ARRAY
S1L60000 Series
NOTICE part this material reproduced duplicated from means without written permission EPSON. EPSON reserves right make changes this material without notice. EPSON does assume liability kind arising inaccuracies contained this material application product circuit and, further, there representation that this material applicable products requiring high level reliability, such medical products. Moreover, license intellectual property rights granted implication otherwise, there representation warranty that anything made accordance with this marerial will free from patent copyright infringement third party. This material portions there contain techology subject relating strategic products under control Forign Exchange Foreign Trade Japan require export license from Ministry international Trade Industry other approval from another government agency.
MS-DOS Windows registered trademarks Microsoft Corporation, U.S.A. PC-DOS, PC/AT. VGA. registered trademarks International Business Machines Corporation, U.S.A. other product names mentioned herein trademarks and/or registered trademarks their respective owners.
©SEIKO EPSON CORPORATION 2003, rights reserved.
Configuration product number
DEVICES 60834 00A0
Packing specification Specifications Shape Model number Model name Product classification (S1:semiconductor)
Model name
Standard Cell Gate Array Embedded Array
Shape
Assembled board, COB, Plastic Bare Chip Plastic Ceramic Ceramic
Plastic TAB-QFP Tape Carrier (TAB) TSOP (Standard Bent) TSOP (Reverse Bent)
Packing Specifications
14th
15th
Packing Specifications Besides tape reel directions Tape reel BACK directions directions directions Tape reel FRONT directions directions directions directions Tape reel LEFT directions directions directions directions Tape reel RIGHT Space fixed
Contents
S1L60000 Series Table Contents
Chapter
3.10 3.11
Overview
Features. Master Structure Electrical Characteristics Specifications Overview Gate Array Development Flow.
Chapter
Estimating Gate Density Selecting Master
Dividing Logic Between Chips. Determining Gate Size. Estimating Number Input/Output Pins Selecting Master Estimating That Used Circuits Which Include
Chapter
Cautions Notes Regarding Circuit Design
Inserting Buffers. Differentiating Circuits Forbidden Wired Logic Forbidden Hazard Countermeasures. Limitations Logic Gate Output Load Circuits. Hold Circuits Schematic Capture Guidelines Clock Tree Synthesis. ATPG (Auto Test Pattern Generation). Restrictions Constraints VHDL/Verilog-HDL Netlist.
3.11.1 Common Restrictions Constraints 3.11.2 Restrictions Constraints Verilog Netlist 3.11.3 Restrictions Constraints VHDL Netlist
Chapter
4.1.1
Input/Out Cells Buffers Their
Selecting Buffer
Types Input/Output Buffer S1L60000 Series Buffer Configurations with Single Power Supply.
4.2.1 Buffer Configurations with Single Power Supply 4.2.1.1 Input Buffer Configurations with Single Power Supply 4.2.1.2 Output Buffer Configurations with Single Power Supply 4.2.1.3 Bi-directional Buffer Configurations with Single Power Supply
Oscillation Circuit
4.3.1 4.3.2 Oscillation Circuit Configurations. Oscillation Circuit Considerations. Overview Gated Cells. Feature Gated Cell Notes Using Gated Cell Overview Fail Safe Cell Feature Fail Safe Cell. Notes Using Fail Safe Cell.
Gated Cells
4.4.1 4.4.2 4.4.3
Fail Safe Cell
4.5.1 4.5.2 4.5.3
Chapter
RAM.
EPSON
Features.
GATE ARRAY S1L60000 SERIES
Contents
5.10
Configuration Simulation Model Selection Size.55 Investigating Placement Master Slice.56 Explanation Functions Delay Parameters Timing Charts Test Method.94 Estimating Current Consumption.94 Symbols They Used.95
Chapter
Circuit Design Taking Testability Into Account.
Considerations Regarding Circuit Initialization Considerations Regarding Compressing Test Patterns.96 Test Circuit Which Simplifies Testing
6.3.1 6.4.1 6.5.1 6.5.2 6.5.3 Test Circuit Structure Test Patterns Test Circuit Structures. Test Patterns Test Circuit Data
Test Circuit.104 Function Cell Test Circuits.107
Chapter
Propagation Delay Timing.
Notes relationship between .110 Simple Delay Models .110 Load Input Capacitance (Load .112 Load Interconnect Capacitance (Load B).113 Propagation Delay Calculations.113 Calculating Output Buffer Delay .115 Sequential Buffer Setup/Hold Time .115 Cells with Increased Speed .118 Chip Internal Skew.118
Chapter
Test Pattern Generation.
Testability Considerations.119 Waveform Types.119 Constraints Types Test Patterns .120
8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Test Period Input Delay Pulse Width Input Waveform Format Strobe.
Notes Regarding Testing.121 Notes Regarding Oscillation Circuits.124 Regarding Testing .125
8.6.1 8.6.2 8.6.3 8.6.4 Constraints Regarding Measurement Events Constraints Measurement Locations Testing. Constraints Regarding Path Delay Which Tested Other Constraints
Test Pattern Constraints Bi-directional Pins .126 Notes Devices High Impedance .126
EPSON
GATE ARRAY S1L60000 SERIES
Contents
Chapter
Estimating Power Consumption
Calculating Power Consumption. Constraints Power Consumption
Chapter Layout Considerations
10.1 Estimating Number Power Supply Pins 10.2 Number Simultaneous Operations Adding Power Supplies 10.3 Cautions Notes Regarding Layout pins
10.3.1 Fixed Power Supply Pins. 10.3.2 Cautions Notes Regarding Layout 10.3.3 Examples Recommended Connections
Chapter Dual Power Supplies Guidelines
11.1 11.2 11.3 11.4 Method Adapting Dual Power Supplies Power Supplies Dual Power Operation Turming ON/OFF Dual Power Supplies. Buffers Compatible with Dual Power Supplies.
11.4.1 Buffers LVDD System. 11.4.1.1 Input Buffers LVDD System 11.4.1.2 Output Buffers LVDD System. 11.4.1.3 Bi-directional Buffers LVDD System. 11.4.2 Buffers HVDD System 11.4.2.1 Input Buffers HVDD System. 11.4.2.2 Output Buffers HVDD System 11.4.2.3 Bi-directional Buffers HVDD System
11.5 Delay Calculation Dual Power Supplies 11.6 Cautions Notes Regarding Power Consumption Calculations When Using Dual Power Supplies 11.7 Estimating Number Power Supply Pins When Using Dual Power Supplies
Chapter (Clock Synchronous Type)
12.1 12.2 12.3 12.4 12.5 Features. Word/Bit Configurations Cell Names Number Basic Cells Synchronous Investigating Placement Master Slice. Functional Description
12.5.1 1-port (Clock Synchronous Type). 12.5.2 2-port (Clock Synchronous Type).
12.6 12.7 12.8 12.9 A1.1 A1.2 A1.3 A1.4
Timing Charts Delay Parameters Method Testing RAM. Estimating Current Consumption. 3.3V operation 2.5V operation 2.0V operation Estimated Wiring Load Table.
Appendix A1.Electrical Characteristica Data
Appendix A2.Release Note.
GATE ARRAY S1L60000 SERIES
EPSON
Contents
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Overview
Chapter Overview
S1L60000 Series family ultra high-speed VLSI CMOS gate arrays utilizing 0.25 "sea-of-gates" architecture.
Features
Integration Operating Speed maximum 2,519,604 gates input NAND gate equivalent) Internal gates: Input buffer: (2.5 Typ.), (2.0 Typ.) (2-input pair NAND, Typical wire load) (3.3 Typ.) Built-in level shifter used. (2.5 Typ.), (2.0 Typ.) (F/O Typical wire load) (3.3 Typ.) Built-in level shifter used. (2.5 Typ.), (2.0 Typ.)
Output buffer: Process Levels Input Modes
0.25 layer metalization CMOS process CMOS/LVTTL compatible CMOS, LVTTL, CMOS Schmitt, LVTTL Schmitt, PCI-3V, Gated Input, Fail-Safe Input Built-in pull-up pull-down resistors usable. types each resistor value) Normal, 3-state, bi-directional, PCI-3 Fail-Safe Input 0.1, selectable (Built-in level shifter used 0.1, selectable 0.05, 0.3, selectable
Output Modes Output Drive
Dual Power
Asynchronous 1-port, asynchronous 2-port Operation supported using level-shifter circuit Internal logic: operation supported voltage Buffer: built-in interfaces both high voltages possible
Operation possible
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Overview
Master Structure
S1L60000 Series comprises types masters, from which customer able select master most suitable.
Table Overview Columns Rows Master Total (Raw Gates) Number Pads Number Columns 1023 1213 1481 1747 2129 2413 2643 3043 Number Rows Cell utilization ratio (U)*1 3-layer metal 4-layer metal
S1L60093/60094 S1L60173/60174 S1L60283/60284 S1L60403/60404 S1L60593/60594 S1L60833/60834 S1L61233/61234 S1L61583/61584 S1L61903/61904 S1L62513/62514
99220 171720 284394 400290 595362 831572 1234820 1587754 1902960 2519604
NOTE: This value when there cells, such cells. cell effciency dependent only scope circuits, also number signals, number branches signal, operating frequency etc.; thus, values this table only estimate.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Overview
Electrical Characteristics Specifications
Table Absolute Maximum Ratings (For Single Power Supplies)
(VSS
Item Power Supply Voltage Input Voltage Output Voltage Output Current/Pin Storage Temperature
Symbol IOUT TSTG
Limits -0.3 -0.3 0.5*1 -0.3 0.5*1
Unit
Possibles from -0.3 channel open drain bi-directional buffers, input buffer Fail Safe cells.
Table Absolute Maximum Ratings (For Dual Power Supplies)
(VSS
Item Power Supply Voltage
Symbol HVDD*3 LVDD*3
Limits -0.3 -0.3 -0.3 HVDD 0.5*1 -0.3 LVDD 0.5*1 -0.3 HVDD 0.5*1 -0.3 LVDD 0.5*1 50*2)
Unit
Input Voltage Output Voltage Output Current/Pin Storage Temperature IOUT TSTG
Possibles from -0.3 channel open drain bi-directional buffers, input buffer Fail Safe cells. Possibles output buffer. HVDD LVDD
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Overview
Table 1-4-1 Recommended Operating Conditions (For Single Power Supplies) Item Power Supply Voltage Input Voltage Ambient Temperature Normal Input Rising Time*4 Normal Input Falling Time*4 Schmitt Input Rising Time*4 Schmitt Input Falling Time*4
Symbol
Min. 2.30
Typ. 2.50
Max. 2.70 VDD*1 70*2 85*3
Unit
Possibles channel open drain bi-directional buffers, input buffers, Fail Safe cells. ambient temperature range recommended 85°C. ambient temperature range recommended 125°C. These timing parameters indicate change time.
Table 1-4-2 Recommended Operating Conditions (For Single Power Supplies) Item Power Supply Voltage Input Voltage Ambient Temperature Normal Input Rising Time*4 Normal Input Falling Time*4 Schmitt Input Rising Time*4 Schmitt Input Falling Time*4
Symbol
Min. 1.80
Typ. 2.00
Max. 2.20 VDD*1 70*2 85*3
Unit
Possibles channel open drain bi-directional buffers, input buffers, Fail Safe cells. ambient temperature range recommended 85°C. ambient temperature range recommended 125°C. These timing parameters indicate change time.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Overview
Table 1-5-1 Recommended Operating Conditions (For Dual Power Supplies) Item Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage) Input Voltage Ambient Temperature Normal Input Rising Time*4 Normal Input Falling Time*4 Schmitt Input Rising Time*4 Schmitt Input Falling Time*4
Symbol HVDD LVDD
Min. 3.00 2.30
Typ. 3.30 2.50
Max. 3.60 2.70 HVDD*1
Unit
LVDD*1 70*2 85*3
Possibles channel open drain bi-directional buffers, input buffers, Fail Safe cells. ambient temperature range recommended 85°C. ambient temperature range recommended 125°C. These timing parameters indicate change time.
Table 1-5-2 Recommended Operating Conditions (For Dual Power Supplies) Item Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage) Input Voltage Ambient Temperature Htri Normal Input Rising Time*4 Ltri Htfa Normal Input Falling Time*4 Ltfa Htri Schmitt Input Rising Time*4 Ltri Htfa Schmitt Input Falling Time*4 Ltfa
Symbol HVDD LVDD
Min. 3.00 1.80
Typ. 3.30 2.00
Max. 3.60 2.20 HVDD*1
Unit
LVDD*1 70*2 85*3
Possibles channel open drain bi-directional buffers, input buffers, Fail Safe cells. ambient temperature range recommended 85°C. ambient temperature range recommended 125°C. These timing parameters indicate change time.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Overview
Table Electrical Characteristics S1L60000 Series
(HVDD common, 85°C) Item Input Leakage Current State Leakage Current Symbol Conditions -0.1 (Type (Type (Type (Type (Type (Type HVDD Min. (Type (Type (Type (Type (Type (Type HVDD Min. CMOS Level, HVDD Max. CMOS Level, HVDD Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt LVTTL Level, HVDD Max. LVTTL Level, HVDD Min. LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt Level, HVDD Max. Level, HVDD Min. Response 0.90 HVDD Min. 2.52 HVDD Max. Response 1.80 HVDD Min. 0.65 HVDD Max. Type Pull-up Resistance Type Type Pull-down Resistance HVDD Type High Level Maintenance Current Level Maintenance Current High Level Reversal Current Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance IBHH IBHL IBHHO IBHLO Hold Response, HVDD Min. Hold Response, HVDD Min. Hold Response, HVDD Max. Hold Response, HVDD Max. MHz, HVDD MHz, HVDD MHz, HVDD -350 Min. HVDD -0.4 Typ. Max. Unit
High Level Output Voltage
Level Output Voltage High Level Input Voltage Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage High Level Input Voltage Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage High Level Input Voltage*2 Level Input Voltage*2 High Level Output Current*2
VIH1 VIL1 VT1+ VT1VH1 VIH2 VIL2 VT2+ VT2VH2 VIH3 VIL3 IOH3
-115 (120)*1 (240)*1 (120)*1 (240)*1
Level Output Current*2
IOL3
values parenthesized means case 70°C. Compliance with Rev. Standard.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Overview
Table Electrical Characteristics
(VDD LVDD 85°C) Item Input Leakage Current State Leakage Current Symbol Conditions -0.1 (Type (Type (Type (Type (Type (Type Min. (Type (Type mA(Type (Type (Type (Type Min. CMOS Level, Max. CMOS Level, Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt Type Pull-up Resistance Type Type Pull-down Resistance Type High Level Maintenance Current Level Maintenance Current High Level Reversal Current Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance IBHH IBHL IBHHO IBHLO Hold Response, Min. Hold Response, Min. Hold Response, Max. Hold Response, Max. MHz, MHz, MHz, -280 Min. Typ. Max. Unit
High Level Output Voltage
-0.4
Level Output Voltage
High Level Input Voltage Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage
VIH1 VIL1 VT1+ VT1VH1
(100) (200) (100) (200)
values parenthesized means case 70°C.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Overview
Table Electrical Characteristics
(VDD LVDD 85°C) Item Input Leakage Current State Leakage Current Symbol Conditions -0.05 (Type -0.3 (Type (Type (Type (Type (Type Min. 0.05 (Type (Type mA(Type (Type (Type (Type Min. CMOS Level, Max. CMOS Level, Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt Type Pull-up Resistance Type Type Pull-down Resistance High Level Maintenance Current Level Maintenance Current High Level Reversal Current Type IBHH IBHL IBHHO IBHLO Hold Response, Min. Hold Response, Min. Hold Response, Max. Hold Response, Max. MHz, MHz, MHz, Min. Typ. Max. Unit
High Level Output Voltage
-0.2
Level Output Voltage
High Level Input Voltage Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage
VIH1 VIL1 VT1+ VT1VH1
-100
Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Overview
Table Quiescent Current (For Single Power Supplies)
85°C)
Master S1L60093/60094 S1L60173/60174 S1L60283/60284 S1L60403/60404 S1L60593/60594 S1L60833/60834 S1L61233/61234 S1L61583/61584 S1L61903/61904 S1L62513/62514
IDDS Max.
IDDS Max.
Unit
1000
Table 1-10 Quiescent Current (For Dual Power supplies)
85°C)
Master S1L60093/60094 S1L60173/60174 S1L60283/60284 S1L60403/60404 S1L60593/60594 S1L60833/60834 S1L61233/61234 S1L61583/61584 S1L61903/61904 S1L62513/62514
HIDDS Max.
LIDDS Max.
HIDDS Max.
LIDDS Max.
Unit
1000
HIDDS: quiescent current between HVDD LIDDS: quiescent current between LVDD
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Overview
value quiescent current, except when chip temperature 85°C, estimated from following formula: 85°C) (For 125°C, estimated quiescent current calculated from temperature coefficient 125°C, please consult Seiko Epson distributor.) IDDS (Tj) IDDS 85°C) Temperature coefficient IDDS 85°C)
(Example) value quiescent current S1L61583 50°C estimated. IDDS 50°C) IDDS 85°C) 0.261 164.43 (µA)
case dual power supplies, quiescent current both voltages used given total quiescent current (HIDDS LIDDS).
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Overview
Overview Gate Array Development Flow
Gate arrays developed jointly customer EPSON. System design, circuit design, test pattern design performed customer, based various reference materials, including cell libraries provided customer EPSON. When configuring interface, customers requested present required data documents Epson after confirming their validity against data release checklist provided Appendix Customers expected performs simulation, analysis other necessary work target project using available software EPITS (*1). When customer completed this work, Seiko Epson will undertake placement writing work that project.
Note: EPITS Seiko Epson's ASIC design support system that runs MS-Windows NT4.0 SUN-Solaris platforms. does include simulation synrhesis functions.
simulation currently supported following software: Verilog-XL (*1) ModelSim (*2)
Note: :Verilog-XL registered trademark Cadence Desgin Systems Corporation, USA. :ModelSim registered trademark Model Technology Corp., USA.
more information, contact sales office technical support.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Overview
process flow gate array development process shown below: Customer
Product Plan Functional Spec.
Distributor (Interface)
EPSON
Circuit Design Test Pattern Design Logical Check (Simulation) development request Simulation file *Schematic *Pin Assinment *Timing wave form *Marking diagram *P/O
Delay Analizing
Timing Check (Simulation)
Verification
Verification* Place Rout
Simulation list Verification Customer Spec (Sign off)
Delay Analizing
Post Simulation
Make Masks (Test Sample) fabrication
Check (Engineering Sample) fabrication
Check ES(TS) Prototype Approval Delivery Spec Setup Delivery Spec. publication
ES(TS) Approve Prototype Approve Delivery Spec
Delivery Spec Approval based customer's requirement.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Estimating Gate Density Selecting Master
Chapter Estimating Gate Density Selecting Master
Methods guidelines described below assist defining logic which will integrated into gate array, estimating array requirements, determining appropriate master given application.
Dividing Logic Between Chips
When extracting logic, which integrated into gate arrays from system being created user, logic should selected with following criteria mind. Integration Criteria Logic size integrated (Gate count) Number pins required (Pin count) Package used Power consumption Generally, larger gate size, more power consumed, more input output terminals required. Because this, better, from perspective total cost from perspective power consumption, etc., divide circuit into multiple chips, rather than forcing them into single chip.
Determining Gate Size
case gate arrays, scope array defined gates basic cells (BCs) used. number each cell listed Gate Array S1L60000 Series Cell Library. sure consult this library determine total number your circuit.
Estimating Number Input/Output Pins
After estimating number used, calculate number input/output pins actually used. sure include test pins power supply pins count. Estimate number power supply pins using method discussed Chapter
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Estimating Gate Density Selecting Master
Selecting Master
Select appropriate master from Table1-1, based estimated number BCs, number required input output pins (including power supply pins) package used. actual number (BCA) which used each device type estimated using following formula from gross number (BCG) loaded each master (shown Table previous chapter) cell utilization ratio (U). NOTE: When circuit included, this estimate should made after refering following section after refering Chapter Also when circuit used dual power, estimate should made after refering Chapter
Estimating That Used Circuits Which Include
blocks, comparison cells, extremely large have fixed shapes (defined vertical horizontal dimensions). Because this, some blocks which appear chip because calculations based number may, actuality, placable given master. Thus, first decision that whether configuration available given master. Please refer Chapter Once masters which accommodate have been selected, becomes possible estimate number (BCAWR) random logic (excluding RAM) available using formula below. BCAWR (BCG BCRAM) where BCAWR number available random logic total available mater (raw gates) BCRAM RAM(s) (See Chapter calculation) utilization ratio. NOTE: Actual available (BCAWR) design dependent. formula above estimation purposes only. Please consult EPSON design specific information.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
Chapter Cautions Notes Regarding Circuit Design
Inserting Buffers
external primary) input, output bi-directional signals must attached buffers. CMOS IC's extreme vulnerability electrical static discharge (ESD), protection circuitry been incorporated within buffers ensure device reliability quality.
Differentiating Circuits Forbidden
propagation delay (tpd) internal cells within gate array vary, depending process variance during mass production environment variance during device usage. Differentiating circuits such shown Figure should avoided difficulties associated with control resultant pulse width relative variances propagation delays through each logic element.
Figure Example Differentiating Circuit
Wired Logic Forbidden
Wired logic, available bipolar devices, allowable S1L60000 Series, CMOS technology. Consequently, cell output pins cannot wired together, such shown Figure 3-2, with exception internal 3-state elements.
Figure Examples Forbidden Wired Logic
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
Hazard Countermeasures
circuits such decoders multiplexors which structured from combinational functions such NAND gates gates, extremely short pulses produced differences gate delay times. These short pulses called hazards, when these hazards propagate clock, reset reset pins (Flip Flop), malfunctions occur. Because this, necessary caution when designing circuits which produce hazards, creating circuit structures which propagate hazards, having decoder circuits with "enable" terminals, etc.
Limitations Logic Gate Output Load
With CMOS circuits, signal propagation time (tpd) signal rise fall times (tslew) characteristically increase load capacitance output increases. Cell propagation delay determined, part, load capacitance output terminals. When load capacitance large, propagation delay increases, malfunctions result. Because this, there limitations number loads which connected output terminals each cell, these limitations referred "fan-out constraints". input terminal capacitance each gate differs from gate input gate input. input capacitance each gate input defined relative input capacitance inverter (IN1 which defined being equal called "fan-in". Circuits should designed that fan-ins connected output terminals each gate does exceed fan-out constraints that output terminal. Also, high speed clock lines more), should designed that output terminal load associated logic gates about half fan-out constraints ensure high performance. actual circuit layout, both input capacitance next-stage gate wiring capacitance signal applied load capacitance. Because accurate wiring capacitance determined placement routing circuit, placement routing result application large load capacitance specific node. conditions loads each circuit node determined output results tslew. Please note that output tslew exceeds standard value, request circuit modification order keep within specified limit. control increases load capacitance following placement routing circuit, number circuit branches within single node should kept possible and, branches exist, buffers with higher number fanouts should used.
Circuits
Internal 3-state circuits constructed, using 3-state logic gates. 3-state logic gates output terminals wired together times one, only 3-state logic gate active given time (while remaining 3-state logic gate outputs high impedance state). This circuit allows multiple signal sources share given different time intervals during circuit operation.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
Please keep following recommendations mind when circuits used: Notes Regarding Circuits: cells cannot used except circuits. (Please refer Table regarding S1L60000 Series cells.) When cells used, please attach (and only one) cell (bus latch) each 3state net. maximum cells attached single bus. (Fan-out One, only one, 3-state cell active (output terminal driving logic state logic state) time. other 3-state cells connected that must inactive (output terminal high impedance state). 3-state cells inactive (output terminals high impedance state) given net, (bus latch) will maintain last valid state (either logic state logic state). function merely avoid floating, therefore, processing internal 3-state latch data must performed while 3-state drivers active rather than processing data while BLTs control data. order improve testability, design 3-state such that initialized easily quickly during device testing. This done utilizing separate test control 3-state bus, instantiating default 3-sate drivers. 3-state cell control terminals must change only once during single test vector event (cycle) allow test vector usage during device testing. High speed 3-state operation inhibited large fan-out loading 3-state drivers.
Table shows table cells which used S1L60000 Series.
Table S1L60000 Series Cells Cell Name Cell Type latches driver Inverting driver Transparent latches with reset 3-state output D-flip flops with rest 3-state output 1-bit TSB, TSB4, TSB8, TSBP TSV, TSV4, TSV8, TSVP T244H T240H T373H T374H T244 T240 T373 T374
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
BLT1
Figure Example Cell Circuit Structure
Hold Circuits
S1L60000 Series, buffers with added hold function maintain output signal data) have been provided, that output signal bi-directional signal pin) does enter high-impedance state. However, prevent these circuits from affecting normal operation, latching capability hold circuit weak; thus, stored data output should used valid data. This state overriden easily externally supplied signal. Please refer Tables regarding output maintenance current hold circuit.
Input signal Output signal Enable Test TB1HT Output buffer Output Test Output signal Enable BC1HT Bi-directional buffer Bi-directional
Figure Examples Structures Hold Circuits
Schematic Capture Guidelines
Please adhere following conventions when designing ASIC manual schematic entry: logic cells found Gate Array S1L60000 Series Cell Library. orthogonal (not oblique) connections when wiring logic cells another. Primary uni-directional bi-directional signal names must characters length, must begin with alphabetic character.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
Clock Tree Synthesis
Overview Clock Tree Synthesis support that automatically inserts ClockTree into buffer group that optimizes skew delay time "ClockLine". customer program insert ClockTree adjust Fan-out "ClockLine", clock skew large, tool started placing routing designing gate array executed voluntarily. Also, propagation delay time longer than estimated because there many cases difficult maintain good balance between wire interconnecting load intrinsic cell delay. Clock Tree Synthesis used solve this problem. Also, circuits that contain Gating Cells (simple gates) Clock Lines, optimize Clock Line skew delay values. (The synthesis method applied Clock Lines that include Gating Cells known Gated Clock Tree Synthesis.) insert Clock Tree Synthesis, customer must insert special buffer Clock Line following three purposes. Judging place insert Clock Tree Synthesis. Estimating delay time Clock Tree inserted execute simulation virtual wire interconnecting level (pre-simulation). Back annotate delay time inserted Clock Tree accurately estimate post-simulation. Examine Clock Tree Synthesis Select special buffer Clock Tree Synthesis Table special Gating Cell Gated Clock Tree Synthesis Table 3-4. Then insert special buffer selected from table into Clock Line taking into consideration restriction notes mentioned later same placing normal cells (Refer Figures 3-6). Otherwise, logic designed HDL, special buffer insert automatically Clock Line, assign directly content using script language. Note that another buffer combined clock Line inserted special buffer, execute following command: set_don't_touch_net net_name
Table Guidance Skew Values Guidance number fan-outs 0-500 500-3000 3000-10000 10000- Without Gating Cells [ps] ±200 ±250 ±300 ±350 With Gating Cells [ps] ±300 ±400 ±500 ±600
Note: cases with Gating Cells, skew value varies significantly depending number Gating Cells other factors. number Gating Cells high, contact EPSON skew values.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
[The special buffer] Select special buffer from table below corresponding estimated number fanouts.
Table Special Buffers S1L60000 Cell Name CRBF2 CRBF3 CRBF4 CRBF5 CRBF6 CRBF7 CRBF8 (ns) 2.00 3.00 4.00 5.00 6.00 7.00 Estimated number fan-out 3000 3000 10000 Over 10000
Note value (load delay fan-out) these cells pre-simulation. Note number fan-outs these cells infinity. Note Please consider that load delay number fan-outs accurately only estimated.
Table Special Gating Cell Names Function Selector NAND Selector INVERTER Cell Name CAD2V COR2V CAO24AV CNA2V CNO2V CAN24A CGIN4
Note load delay value (To) these cells pre-simulation. Note value (load delay fan-out) these cells pre-simulation. Note number fan-outs these cells infinity.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
[Restriction Notes] special buffer used purpose other than Clock Tree Synthesis. Clock Tree Synthesis also used data line other control signals. However, when nets used synthesis increased, skew propagation delay also became larger. Therefore, number nets used synthesis less than which critical large fan-out should used. which small fan-out used Clock Tree Synthesis, propagation delay skew larger. target with fan-out should used more than scores. there cases corresponding skew adjustment between multiple Clock lines, contact EPSON handing detail schematic (the clock line configuration described very clearly) checked. Clock group separated into multiple Clock Lines with same Root Clock gates, contact EPSON obtain materials "Gated Clock Tree Synthesis Explanations".
[Necessary Information from Customer] Send following information until data released, because Clock Tree Synthesis used efficiently.
Instance name CRBF
Target skew value (Max.) (SIM Condition: Max.)
Target propagation delay (Min./Max.) (SIM Condition: Max.)
Note target values table needed estimate Synthesis. target values always satisfied.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
number Clock Lines fewer? Does Clock include dedicated Gating Cell?. answered question above, answer questions through below. number dedicated Gating Cells included each Clock fewer? number dedicated gated cell stages fewer? Does Clock include cell other than Gating Cells?
Note: Clock contains cell other than Gating Cells, Clock Tree Synthesis requires special procedure. Please consult Epson have cell other than Gating Cells your Clock Nets.
Clock Tree Synthesis applied cells other than DFFs latches? Yes, write cell names below. there circuit configuration similar Figure 3-7? there circuit configuration similar Figure 3-8?
Note: Make corrections referring processing examples problem circuits below (Figures 3-8).
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
[Additional information] Concept implementation Clock Tree Synthesis (Case which Gating Cells inserted)
(Before Clock Tree Syntheis)
Clock Root
CRBF
Clock Root
CRBF
(After Clock Tree Syntheis)
Figure Conceptual Diagram Implementation Clock Tree Synthesis
When Clock Tree Synthesis used shown circuit above, buffers will inserted within dotted circles. During post-simulation, delay each buffer inserted within dotted circles delay added wiring will added delay information wiring original circuit.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
Concept implementation Clock Tree Synthesis (Case which Gating Cells inserted)
(Before Clock Tree Syntheis)
Clock Root
CRBF
CAD2V
Clock Root
CRBF
CAD2V
(After Clock Tree Syntheis)
Figure Conceptual Diagram Implementation Clock Tree Synthesis
When Clock Tree Synthesis used shown circuit above, buffers will inserted within dotted circles. During post-simulation, delay each buffer inserted within dotted circles delay added wiring will added delay information wiring original circuit.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
Example handling problem circuit (Original Schematic)
(Clock Root
CRBF
(Clock Root
CRBF CAO24AV
(Modified Schematic)
(Clock Root
Dummy Cell
CRBF CAO24AV
(Clock Root
CRBF CAO24AV
Figure Example Handling Problem Circuit
case original circuit, DFFs within dotted circle driven both clock root clock root circuits this type, Clock Tree Synthesis cannot used. example circuit this type, insert dummy CAO24A, shown, into circuit following modification. Moreover, Clock Tree Synthesis thick-solid-line section.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
Example handling problem circuit
(Clock Root
CRBF
(Clock Root
CRBF CAO24AV
Please Delete
Figure Example Handling Problem Circuit
DFFs dotted circles above diagram driven both clock root clock root circuits this type, Clock Tree Synthesis cannot used. such case, remove CRBF cell from clock root
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
3.10 ATPG (Auto Test Pattern Generation)
Introduction so-called "ATPG" means tools automatically generate test patterns that released tool-producing vendors. "TestGen" tool executed "ATPG" supplied Synopsys Inc. Sunrise Inc. used ASIC design EPSON. using "TestGen", scanning circuit inserted original circuit test patterns generated automatically. word "control" described this chapter used specify free level target without passing sequential circuit. This "control" meaning should noted because used dividing clocks needed some cycles state. example, when using "control" where clock each flip-flop circuit controlled externally, circuit means that external input clock original signal) reach each flip-flop circuit. Outline When scanning circuit inserted into design ruled circuit "ATPG" support, some faults detected circuit when using "ATPG" tool. However, internal nodes forced move from external pins through scanning circuit observed. Therefore, test patterns outputted from "ATPG" tool used check operations user's circuit. Users need create test patterns check standard operations their circuit. test patterns outputted from "ATPG" tool only used reach level fault detecting rate circuit. When using "ATPG" tool, test patterns 100% fault detecting generated, except that nodes tested faults tested logically. "ATPG" method adapted full scanning using "MUXSCAN type (Flip-flop)". Fault Detecting Definition single stuck-at fault mode used. SA0: stack-at-zero fault (shorted) SA1: stack-at-one fault (shorted) following test pattern circuit created using TestGen ATPG tool. circuit SA0, respective nodes created observe detection faults. other words, test pattern circuit should created that causes malfunctions when each node "1".
S-a-0
S-a-1 S-a-0/1
Figure Example Untestable
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
Design Flow
Customer
ATPG Rule Check APTG Check Sheet
Seiko Epson
APTG Application Note
Temporary Schematic Assignment
Dummy Netlist
Circuit Block Diagrams
ATPG Rule Check Verification Logical check
Design Creation Creation
Expected Values Input Patters
Netlist
Circuit Data Assignment
Schematic
ATPG Rule Check Logic Synthesis Pre-Simulation Insert Scanning Fault Detection Verilog-XL Netlist
Verification after ATPG
Verification Fault Detection Rate
ATPG ATPG Rule Check
Circuit Data
Clock Tree Synthesys Post-Simulation
Post-Simulation Verification
Post-Simulation Result List
Sign
Figure 3-10 ATPG flow when designing logic synthesis
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
Test pattern composition created ATPG There test patters generated ATPG, their modes must exchanged scanning enable input (SCANEN). SCANEN needs used dedicated input because connected when circuit scanned. Scanning shift mode This mode used when memory element (scan circuit composed shift register inputted outputted data. Scanning test mode This mode used when data inputted memory element scanning shift mode used operate circuit clock input. Pins ATPG pins SCANEN ATPGEN used, ATPG execute very efficiently. result, delivery time shortened fault detection rate goes following explanation describes pins needed execute ATPG. Scan Enable Input Terminal (SCANEN) This used exchange scan shift mode with scan test mode. also used when resetting setting (Flip Flop) bi-directional exchange signals while shifting each scan. This must ready dedicated because definitely needed scan Test input ATPG (ATPGEN) This used make circuit suitable ATPG. example, asynchronous part circuit should fixed using test input clock line cannot controlled externally, controlled using exchange. original circuit adequate rule ATPG, needed ATPG dedicated used. Scan data input This scan data input used data shift register generated scanning case multi-scan number scan data input pins increased. These pins shared with others. However, they used share with control reset scan data clock other pins scan scan data input pins used share with bi-directional pins, they should designed always used input utilizing ATPGEN pin. Scan data output This scan data output used read data from shift register generated scanning case multi-scan number scan data output pins increased. These pins shared with other pins. scan data output pins used share with bi-directional pins, they should designed always used output considering utilizing ATPGEN pin. Scan clock input This clock input test pattern generated ATPG. This usually utilizes system clock normal operation.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
Logic circuit design rule ATPG (DFT) operate ATPG, logic circuits should scanned. According following rules, original circuits that observed check very well should designed. following contents show concrete example, please contact EPSON Sales division logic circuit design difficulty handling ATPG design. Only needed dedicated used scan enable (SCANEN). Please send trial data EPSON about week before sending formal data. EPSON will check trial data logic circuit before getting formal data. process after obtaining formal logic circuit data should highly efficient fault detection rate logic circuit must clock, setting resetting scan data scanned must controlled directly external pin. they cannot controlled, ATPG test (ATPGEN) separated from SCANEN design logic circuit that controlled. When logic circuit configured input multiple clocks from external pin, ATPGEN should designed operated again active state inputting only clock scanned. However, there only circuit, please contact EPSON sales division about multiple circuits this case.
LOGIC
CRBF AO24A ATPGEN IBCD1
Figure 3-11 Example Clock Line Process
forbidden design circuit used scan original circuit. Cope with clock skew clock nets using Clock Tree Synthesis. Allocate cells hierarchical design.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
internal 3-state bus. internal 3-state should composed multiplexer However, circuit design needs internal 3-state means, ATPGEN circuit must designed never cause contention. When circuit designed using internal 3-state bus, fault detection rate circuit does always Please contact EPSON sales division high fault detection rate desired (Refer Figure 3-13).
BLT1
ATPGEN IBCD1
Figure 3-12 Process Example Internal 3-state
When using macro cells, example RAM, ROM, Mega cell design circuit inserted scanned before after ports macro cells. circuit design impossible, faults often detected before after macro cells. Keep away using macro cells included Flip Flop, example T175, A161 cells scan. them high fault detection rate desired. asynchronous circuit circuit that causes racing latch, differentiating circuit these circuits used, their output using ATPGEN pin. Furthermore, fault detection rate always circuit high fault detection rate desired. latch cell using ATPGEN that always through. fault detection rate always circuit high fault detection rate desired. Design bi-directional state input scan shifting mode. bi-directional must assigned scan data input output pins, state each condition (Refer Figure 3-14).
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
SCANIN
SCANOUT
ATPGEN IBCD1 SCANEN IBCD1
Figure 3-13 Process Example bi-directional pins
that scanned T-FF, macro cells include output from scanned causes malfunction ATPG test patterns. Also, fault detection circuit often executed, possible they should fixed ATPGEN. Others number gates goes about compared original circuit, depends number scanned FFs. fault detection rate scanned depends circuit configuration scale gates. least three working days needed ATPG EPSON. unusual case, about working days needed depending circuit configuration. Please refer this book circuit configuration before designing it.) Please send papers "ATPG check sheet" "External information" EPSON before sending logic circuit data. there problems with logic circuit, EPSON change design. Please define external pins (ATPGEN, SCANEN added scan test patterns interfaced EPSON. Please send "CTS Application/On Notes" attached sheet same time, because when placing cells routing interconnections, they requested cope with (Clock Tree Synthesis).
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
ATPG check sheet Never delay sending this sheet week before sending logic circuit data. Please mark "Yes" "No" each item.
Which netlist format (gate level) interfaced EPSON? scanned used original circuit? (Note macro cells, cells interval oscillator cells? answer "Yes" question above, write cell name. internal 3-state bus? Does your logic circuit have latch, differential circuit asynchronous circuit? latch cells? there bi-directional pin? there clocks that directly controlled externally? Verilog EDIF
there reset pins latch cells that directly controlled externally? answers "Yes" question Nos.3 does circuit design correspond rule? (Note cells arranged hierarchy? clocknets cope with skew CTS?
Note1: answered "Yes", please design logic circuit again, because circuit scan. Note2: answered "No", please insert DFT, because circuit scan. Also, insert EPSON, please contact EPSON sales division, because circuit information addition that this sheet required.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
qInformation External Pins Please fill each name corresponding arrangement table follows. Clock input pins name name name name name Operation edge Operation edge Operation edge Operation edge Operation edge Rise Rise Rise Rise Rise Fall Fall Fall Fall Fall
Scan enable input (Note Exist Nonexist name Active level High ATPG test input Exist Nonexist name Active level High Clear/Preset input Exist Nonexist name Active level High Other ATPG mode control pins Exist Nonexist name What controlled? Operation levels name What controlled? Operation levels name What controlled? Operation levels name What controlled? Operation levels Input impossible assign scan data input (Note
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
Output impossible assign scan data output (Note
Explanatory column
<Others> Number gates before inserting scanning cells (BC) Total number D-FFs JK-FFs Expected date send trial data Year Month (Trial data: check sheet, virtual netlist, tentative arrangement table, circuit blocks) Expected fault detection rate Please send materials checking circuit blocks, hierarchy (module names instance name), clock lines data paths between blocks with this sheet same time.
Note scan enable inserted into original circuit, please write what expect Note there special indication about pin, EPSON will design assigned.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Cautions Notes Regarding Circuit Design
3.11 Restrictions Constraints VHDL/Verilog-HDL Netlist
VHDL/Verilog-HDL list interfaced EPSON shall pure gate-level list (not containing description operation). restrictions constraints developing EPSON ASIC using VHDL/Verilog follows.
3.11.1 Common Restrictions Constraints
Names External Terminal (I/O Terminal) only upper-case letters. Number characters: Usable characters: Alphanumeric characters "_." alphabetical letter head. Examples prohibited character strings INPUT \2INPUT InputA _INPUTA TNA[3:0] INA[3] digit head. head. Lower-case letters included. head. used name external terminal. used name external terminal.
Names Internal Terminal (including names) Upper-and lower-case letters used combination, except following. Combinations same words expressed upper-and lower-case letters, such "_RESET_" "_Reset_." Number characters:2 Usable characters:Alphanumeric characters, "_," (Verilog blanket), "_()_" (VHDL blanket) with alphabetical letter head. description prohibited most significant place module. Examples: DATA [0:3], DATA [3], DATA prohibited. DATA0, DATA1, DATA2 allowed. cells same library series, cannot combine those different series. possible describe operations behaviors language. Such descriptions existing list invalid. Precision time scale library each series
3.11.2 Restrictions Constraints Verilog Netlist
Descriptions using functions "assign" "tran" prohibited gate-level Verilog list.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Cautions Notes Regarding Circuit Design
Descriptions connection with cell names recommended Verilog list. Example:Connection with names: inst_1 (.A(inst_2),.X(inst_3)); Recommended Connection with names: inst_1(net1, net2): cannot Verilog command "force" description flip-flop operation. (Example: force logic .singal (10)The time scale description added head gate-level list generated Synopsys design compiler. value described EPSON Verilog library. time scale each series. Example:'timescale 1ps/1ps (11)EPSON prohibits combination single port name name that includes "_\_", such following, same module. input [0]; wire [0]; (12)The following letter strings reserved Verilog, which cannot used userdefined name. always, and, assign, begin, buf, bufif0, bufif1, case, design,default, defparam, disable, else, end, endcase, endfunction, endmodule, endtask, event, for, force, forever, fork, function, highz0, highz1, initial, inout, input, integer, join, large, medium, module, nand, negedge, nor, not, notif0, notif1, output, parameter, posedge, pull0, pull1, reg, release, repeat, scalared, small, specify, strong0, strong1, supply0, supply1, task, time, tri, tri0, tri1, trinand, trior, trireg, vectored, wait, wand, weak0, weak1, while, wire, wor, xor, xnor
3.11.3 Restrictions Constraints VHDL Netlist
(13)In addition constraints (1), following letter strings also prohibited. INPUTA_:"_" used end. INPUT_ _A:"_" used twice more succession. read:Used system. write:Used system. (14)The following letter strings reserved VHDL, which cannot used userdefined name. abs, access, after, alias, all, and, architecture, array, assert, attribute, begin, block, body, buffer, bus, case, component, configuration, constant, disconnect, downto, else, elsif, end, entity, exit, file, for, function, generate, generic, guarded, inout, label, library, linkage, loop, map, mod, nand, new, next, nor, not, null, open, others, out, package, port, procedure, process, range, record, register, rem, report, return, select, severity, signal, subtype, then, transport, type, units, until, use, variable, wait, when, while, with, (15)To EPSON utilities tools, necessary change VHDL format into Verilog format. Therefore, letter strings reserved Verilog (12) also prohibited.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Chapter Input/Out Cells Buffers Their
This chapter describes detail configure input buffer, output buffer, bidirectional buffer single power supply. information configuring input output buffers compliant with dual power supplies, Chapter
Types Input/Output Buffer S1L60000 Series
Various buffers types S1L60000 Series available according input interface level, schmitt trigger input not, output drive capacity, pull pull down resistors, pull-up pull down resistors. select ones appropriate your needs. buffers, keep mind that these ways use, which used single power system (2.5 other used dual power system (3.3 V/2.5 V/2.0
4.1.1 Selecting Buffer
Selecting Input Buffer required interface level CMOS level LVTTL level? schmitt trigger input necessary? (Are hysteresis characteristics necessary?) necessary pull-up/pull-down resistors? Selecting Output Buffer much output current must driven? (IOL/IOH) noise countermeasures necessary? hold circuit necessary? Selecting Bi-directional Buffer Select bi-directional buffer examining both sets criteria selecting input buffer selecting output buffer. Interface Level system Input level: LVTTL Level, CMOS Level, LVTTL Schmitt, CMOS Schmitt, PCI-3V* Output level: CMOS Level, PCI-3V* system Input level: CMOS Level, CMOS Schmit Output level: CMOS Level
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
system Input levell: CMOS Level, CMOS Schmit Output levell: CMOS Level
NOTE When single power supply used, LVTTL level input cannot used. interface, contact EPSON sales office.
Output Drive Capability electrical characteristics (Tables 1-8). Pull-up/Pull-down Resistor electrical characteristics (Tables 1-8).
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Buffer Configurations with Single Power Supply
When using single power supply, power supply voltage (VDD) used only
4.2.1 Buffer Configurations with Single Power Supply
4.2.1.1 Input Buffer Configurations with Single Power Supply
Table Input Buffer List
(VDD
Cell Name IBCP IBCD IBHP IBHD
Input Level CMOS CMOS CMOS CMOS Schmitt CMOS Schmitt CMOS Schmitt
Pull-up/Pull-down Resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor
NOTE: When value pull-up/pull-down resistance values correspond 1:50k, 2:100k respectively.
Table Input Buffer List
(VDD
Cell Name IBCP IBCD IBHP IBHD
Input Level CMOS CMOS CMOS CMOS Schmitt CMOS Schmitt CMOS Schmitt
Pull-up/Pull-down Resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor
NOTE: When value pull-up/pull-down resistance values correspond 1:70k, 2:140k respectively.
4.2.1.2 Output Buffer Configurations with Single Power Supply
Figure connectivity reference Tables 4-3, 4-4, 4-5, below regarding list output buffers S1L60000.
Output signal Test
OB1T Output
Output signal Enable Test
TB1T Output
Normal output buffer
3-state output buffer
Figure Examples Output Buffer Symbols
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
Table Output Buffers
(VDD
Function
IOL*/IOH** mA/-0.1 mA/-1 mA/-3 mA/-6 mA/-9 mA/-18 mA/-9 mA/-18 mA/-9 mA/-18 mA/-0.1 mA/-1 mA/-3 mA/-6 mA/-9 mA/-18 mA/-9 mA/-18 mA/-9 mA/-18 mA/-1 mA/-3 mA/-6 mA/-9 mA/-18 mA/-9 mA/-18 mA/-9 mA/-18
Cell Name*** OBST OBMT OB1T OB2T OB3T OB4T OB3AT OB4AT OB3BT OB4BT TBST TBMT TB1T TB2T TB3T TB4T TB3AT TB4AT TB3BT TB4BT TBMHT TB1HT TB2HT TB3HT TB4HT TB3AHT TB4AHT TB3BHT TB4BHT
Normal output
Normal output high speed Normal output noise
3-state output
3-state output high speed 3-state output noise
3-state output (Bus hold circuit)
3-state output high speed (Bus hold circuit) 3-state output noise (Bus hold circuit)
NOTES: (VDD (VDD addition configurations Table 4-3, output buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Table Output Buffers
(VDD
Function
IOL*/IOH** 0.05 mA/-0.05 mA/-0.3 mA/-1 mA/-2 mA/-3 mA/-6 mA/-3 mA/-6 mA/-3 mA/-6 0.05 mA/-0.05 mA/-0.3 mA/-1 mA/-2 mA/-3 mA/-6 mA/-3 mA/-6 mA/-3 mA/-6 mA/-0.3 mA/-1 mA/-2 mA/-3 mA/-6 mA/-3 mA/-6 mA/-3 mA/-6
Cell Name*** OBST OBMT OB1T OB2T OB3T OB4T OB3AT OB4AT OB3BT OB4BT TBST TBMT TB1T TB2T TB3T TB4T TB3AT TB4AT TB3BT TB4BT TBMHT TB1HT TB2HT TB3HT TB4HT TB3AHT TB4AHT TB3BHT TB4BHT
Normal output
Normal output high speed Normal output noise
3-state output
3-state output high speed 3-state output noise
3-state output (Bus hold circuit)
3-state output high speed (Bus hold circuit) 3-state output noise (Bus hold circuit)
NOTES: (VDD (VDD addition configurations Table 4-4, output buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
Output signal Test
OD1T
Output
Figure Example Channel Open Drain Output Buffer Symbols
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
Table channel Open Drain Output Buffers
(VDD
Function
IOL*/IOH
Cell Name** OD1T OD2T OD3T OD4T
Normal output
NOTES: (VDD addition configurations Table 4-5, channel open drain output buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
Table channel Open Drain Output Buffers
(VDD
Function
IOL*/IOH
Cell Name** OD1T OD2T OD3T OD4T
Normal output
NOTES:
(VDD addition configurations Table 4-6, channel open drain output buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
4.2.1.3 Bi-directional Buffer Configurations with Single Power Supply
bi-directional buffers list S1L60000 shown Tables 4-7, 4-8, 4-10.
Input signal Output signal Enable Test BC1T Bi-directional
Figure Example Bi-directional Buffer Symbols
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Table Bi-directional Buffers
(VDD
Input Level
Function
IOL*/IOH** mA/-0.1 mA/-1 mA/-3 mA/-6 mA/-9 mA/-18 mA/-9 mA/-18 mA/-9 mA/-18 mA/-0.1 mA/-1 mA/-3 mA/-6 mA/-9 mA/-18 mA/-9 mA/-18 mA/-9 mA/-18 mA/-1 mA/-3 mA/-6 mA/-9 mA/-18 mA/-9 mA/-18 mA/-9 mA/-18 mA/-1 mA/-3 mA/-6 mA/-9 mA/-18 mA/-9 mA/-18 mA/-9 mA/-18
Cell Name*** BCST BCMT BC1T BC2T BC3T BC4T BC3AT BC4AT BC3BT BC4BT BHST BHMT BH1T BH2T BH3T BH4T BH3AT BH4AT BH3BT BH4BT BCMHT BC1HT BC2HT BC3HT BC4HT BC3AHT BC4AHT BC3BHT BC4BHT BHMHT BH1HT BH2HT BH3HT BH4HT BH3AHT BH4AHT BH3BHT BH4BHT
Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise
Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise
Bi-directional output (Bus hold circuit) CMOS Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit) Bi-directional output (Bus hold circuit) CMOS Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
NOTES: (VDD (VDD addition configurations Table 4-7, bi-directional buffers configured with pull-up pull-down resistors which have test pins. Customers desiring such structures should direct inquiries EPSON.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
Table Bi-directional Buffers
(VDD
Input Level
Function
IOL*/IOH** 0.05 mA/-0.05 mA/-0.3 mA/-1 mA/-2 mA/-3 mA/-6 mA/-3 mA/-6 mA/-3 mA/-6 0.05 mA/-0.05 mA/-0.3 mA/-1 mA/-2 mA/-3 mA/-6 mA/-3 mA/-6 mA/-3 mA/-6 mA/-0.3 mA/-1 mA/-2 mA/-3 mA/-6 mA/-3 mA/-6 mA/-3 mA/-6 mA/-0.3 mA/-1 mA/-2 mA/-3 mA/-6 mA/-3 mA/-6 mA/-3 mA/-6
Cell Name*** BCST BCMT BC1T BC2T BC3T BC4T BC3AT BC4AT BC3BT BC4BT BHST BHMT BH1T BH2T BH3T BH4T BH3AT BH4AT BH3BT BH4BT BCMHT BC1HT BC2HT BC3HT BC4HT BC3AHT BC4AHT BC3BHT BC4BHT BHMHT BH1HT BH2HT BH3HT BH4HT BH3AHT BH4AHT BH3BHT BH4BHT
Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise
Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise
Bi-directional output (Bus hold circuit) CMOS Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
Bi-directional output (Bus hold circuit) CMOS Schmitt
Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
NOTES: (VDD (VDD addition configurations Table 4-8, bi-directional buffers configured with pull-up pull-down resistors which have test pins. Customers desiring such structures should direct inquiries EPSON.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Input signal Output signal Enable Test BDC1T Bi-directional
Figure Example Channel Open Drain Bi-directional Buffer Symbols
Table Channel Open Drain Bi-directional Buffers
(VDD
Input Level
Function
IOL*
Cell Name** BDC1T BDC2T BDC3T BDC4T BDH1T BDH2T BDH3T BDH4T
CMOS
Bi-directional output
CMOS Schmitt
Bi-directional output
NOTES: (VDD addition configurations Table 4-9, channel open drain bi-directional buffers configured with pull-down resistors which have test pins. Customers desiring such structures should direct inquiries EPSON.
Table 4-10 Channel Open Drain Bi-directional Buffers
(VDD
Input Level
Function
IOL*
Cell Name** BDC1T BDC2T BDC3T BDC4T BDH1T BDH2T BDH3T BDH4T
CMOS
Bi-directional output
CMOS Schmitt
NOTES:
Bi-directional output
(VDD addition configurations Table 4-10, channel open drain bi-directional buffers configured with pull-down resistors which have test pins. Customers desiring such structures should direct inquiries EPSON.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
Oscillation Circuit
4.3.1 Oscillation Circuit Configurations
Oscillation circuits should configured, shown Figure 4-5. Both standard gated oscillation circuit configurations supported shown.
Inside Enable Oscillation Inside Oscillation
X'tal
X'tal
Oscillation circuit without Enable
Oscillation circuit with
Figure Method Structuring Oscillator
4.3.2 Oscillation Circuit Considerations
Layout package, follow rules layout described below. other packages, please contact sales office necessary information layout. inputs outputs oscillation circuits should positioned adjacent pins, should located between power supply pins (VDD, VSS). locate high drive output pins near input/output pins oscillation circuit. especially careful locate outputs having same phase opposite phase oscillating wave form possible from oscillation circuit input/output pins. Whenever possible, locate input/output pins oscillation circuit near center edge package. Oscillation Cell Selection Criteria frequency which oscillation possible approximately several mega hertz(MHz). details, please direct inquiries EPSON.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Selecting Values Resistors Capacitors Attached characteristics oscillation depends capacitive resistive biasing elements (IC, X'tal, boards). Because this, capacitive resistive values must adjusted, depending crystal which will used actual board. Consequently, optimal values should chosen through spending adequate time evaluating available engineering samples. Assurance Levels EPSON unable guarantee function characteristics oscillation. EPSON warrantee only oscillation cell. Because this, necessary customer spend adequate time evaluating engineering samples terms their oscillation characteristics. Structuring Oscillation Circuits Dual Power Supplies structure oscillation circuits dual power supplies essentially different than structure single power supplies. oscillation circuit operates LVDD system. Moreover, input/output cells LOT, LLIN LLOT, which each have prefix denote operation using LVDD.
Gated Cells
4.4.1 Overview Gated Cells
Gated cells input pins floated Hi-Z state, other words, without using pull down resistor that impossible usual. Also, they used, power source high voltage side (HVDD) designed dual power sources circuit off. There types; High level control signal other level control signal, selectable depending circuit design.
4.4.2 Feature Gated Cell
There limitation many Gated cells used arranged, they used correspond need design logic circuit. power source high voltage side (HVDD) designed dual power source off. Before power high-voltage side (HVDD), first contact EPSON's marketing division, special procedure required this case. gated cells input cells floated Hi-Z state, other words without using pull down resistor. input levels dual power source circuit gated cells correspond CMOS (LVDD). There types; High level control signal other level control signal. gated cells S1L60000 series composed complete CMOS structure, they operate power.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
4.4.3 Notes Using Gated Cell
When input cells Hi-Z state using gated cells, power source must operated using control gated cells before input cells Hi-Z state. this operation executed input cells state, large current flows input cell same manner normal cells elements destroyed. Otherwise, when input cells Hi-Z state connecting operation executed using control gated cell, large current flows input cell same manner normal cells elements destroyed. this case, EPSON does guarantee logic levels internal device. When power source high voltage side (HVDD) using gated cells, same process needs carried out. Also, this case, EPSON does guarantee logic levels internal device. Before power highvoltage side (HVDD), first contact EPSON's marketing division, special procedure also required this case.
Table 4-11 Gated Input Cell List
(VDD
Drain Type Normal
Input Level CMOS
Without Resistor
Pull Down IBAD1 IBOD1
Pull IBAP1 IBOP1 IBAP2 IBOP2
IBAD2 IBOD2
*1:The value
Table 4-12 Gated Input Cell List
(HVDD
Drain Type Normal
Input Level CMOS
Without Resistor HIBA HIBO
Pull Down HIBAD1 HIBOD1 HIBAD2 HIBOD2
Pull HIBAP1 HIBOP1 HIBAP2 HIBOP2
value HVDD
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Table 4-13 Gated Bi-directional Cell List
(AND Type,
Input Level
Drain Type
Test Function*2
Output Latch Function
Speed
Output Current (mA)*1
-3/3 -6/6 -9/9 -18/18
Without Resistor
BA1T BA2T BA3T BA4T BA3AT BA4AT BA3BT BA4BT
Pull Down
BA1D1T BA2D1T BA3D1T BA4D1T
Pull
BA1P1T BA2P1T BA3P1T BA4P1T
BA1D2T BA2D2T BA3D2T BA4D2T
BA1P2T BA2P2T BA3P2T BA4P2T
Normal Nonexist
CMOS
Normal
Exist
High Speed Noise
-9/9 -18/18 -9/9 -18/18
BA3AD1T BA4AD1T BA3BD1T BA4BD1T
BA3AD2T BA4AD2T BA3BD2T BA4BD2T
BA3AP1T BA4AP1T BA3BP1T BA4BP1T
BA3AP2T BA4AP2T BA3BP2T BA4BP2T
value addition configurations Table 4-13, gated bi-directional buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
Table 4-14 Gated Bi-directional Cell List
Type,
Input Level
Drain Type
Test Function*2
Output Latch Function
Speed
Output Current (mA)*1
-3/3 -6/6 -9/9 -18/18
Without Resistor
BO1T BO2T BO3T BO4T BO3AT BO4AT BO3BT BO4BT
Pull Down
BO1D1T BO2D1T BO3D1T BO4D1T
BO3AD1T BO4AD1T BO3BD1T BO4BD1T
Pull
BO1P1T BO2P1T BO3P1T BO4P1T
BO1D2T BO2D2T BO3D2T BO4D2T
BO3AD2T BO4AD2T BO3BD2T BO4BD2T
BO1P2T BO2P2T BO3P2T BO4P2T
Normal Nonexist
CMOS
Normal
Exist
High Speed Noise
-9/9 -18/18 -9/9 -18/18
BO3AP1T BO4AP1T BO3BP1T BO4BP1T
BO3AP2T BO4AP2T BO3BP2T BO4BP2T
value addition configurations Table 4-14, gated bi-directional buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
Table 4-15 Gated Bi-directional Cell List
(AND Type, HVDD
Input Level
Drain Type
Test Function*2
Output Latch Function
Speed
Output Current (mA)*1
-3/3 -6/6 -12/12 -24/24
Without Resistor
HBA1T HBA2T HBA3T HBA4T HBA3AT HBA4AT HBA3BT HBA4BT
Pull Down
HBA1D1T HBA2D1T HBA3D1T HBA4D1T
HBA3AD1T HBA4AD1T HBA3BD1T HBA4BD1T
Pull
HBA1P1T HBA2P1T HBA3P1T HBA4P1T
HBA3AP1T HBA4AP1T HBA3BP1T HBA4BP1T
HBA1D2T HBA2D2T HBA3D2T HBA4D2T
HBA3AD2T HBA4AD2T HBA3BD2T HBA4BD2T
HBA1P2T HBA2P2T HBA3P2T HBA4P2T
HBA3AP2T HBA4AP2T HBA3BP2T HBA4BP2T
Normal Nonexist
CMOS
Normal
Exist
High Speed Noise
-12/12 -24/24 -12/12 -24/24
value HVDD addition configurations Table 4-15, gated bi-directional buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
Table 4-16 Gated Bi-directional Cell List
(AND Type, HVDD
Input Level
Test Drain Type Function*2
Output Output Latch Speed Current Function (mA)*1
-3/3 Normal Nonexist -6/6 -12/12 -24/24 High Speed Noise -12/12 -24/24 -12/12 -24/24
Without Resistor
HBO1T HBO2T HBO3T HBO4T
Pull Down
HBO1D1T HBO2D1T HBO3D1T HBO4D1T HBO3AD1T HBO4AD1T HBO3BD1T HBO4BD1T
Pull
HBO1P1T HBO2P1T HBO3P1T HBO4P1T HBO3AP1T HBO4AP1T HBO3BP1T HBO4BP1T
HBO1D2T HBO2D2T HBO3D2T HBO4D2T HBO3AD2T HBO4AD2T HBO3BD2T HBO4BD2T
HBO1P2T HBO2P2T HBO3P2T HBO4P2T HBO3AP2T HBO4AP2T HBO3BP2T HBO4BP2T
CMOS
Normal
Exist
HBO3AT HBO4AT HBO3BT HBO4BT
value HVDD addition configurations Table 4-16, gated bi-directional buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter Input/Out Cells Buffers Their
Fail Safe Cell
4.5.1 Overview Fail Safe Cell
Fail Safe cell S1L60000 series interface signal that more power voltage than bi-directional designed single power source without setting special power source interface. Therefore, does need power sources, which used operation other interface. Furthermore, same level signal power source operation interfaced without changing circuit, logic circuit designed more freely.
4.5.2 Feature Fail Safe Cell
There limitation many Fail Safe cells used arranged, they used correspond need design logic circuit. Fail Safe cells S1L60000 series interface external signal that more power voltage than that designed single power source without setting special power source interface. input levels S1L60000 series Fail Safe cells correspond CMOS CMOS Schmitt. Fail Safe cells S1L60000 series composed complete CMOS structure, they operate power.
4.5.3 Notes Using Fail Safe Cell
Fail Safe cells released output pins High-Z such that current never flows input mode, even though they inputted higher power voltage signal than designed power voltage. However, when they output High level output mode inputted higher power voltage signal than designed power voltage, current flow usual. example, when Fail Safe cells produced EPSON output High level (2.5 another device indicates output High level (3.3 same time. Also, this other device includes pull resistor. Note that Fail Safe cell impressed only signal voltage that less than absolute maximum ratings, although they receive signal voltage that higher than operation voltage.
Table 4-17 Fail Safe Input Buffer List
(VDD
Drain Type Fail Safe
Input Level CMOS CMOS-Schmitt
Without Resistor
Pull Down*1
Pull Up*1 IBBP1 IBGP1 IBBP2 IBGP2
value
EPSON
GATE ARRAY S1L60000 SERIES
Chapter Input/Out Cells Buffers Their
Table 4-18 Fail Safe Output Buffer List
(VDD
Drain Type
Test Function*2
Output Latch Function
Speed Normal
Output Current (mA)*1
-3/3 -6/6 -9/9 -18/18 -9/9 -18/18
Output state Output 3-state TBF1T TBF2T TBF3AT TBF4AT TBF3BT TBF4BT
Fail Safe
Exist
Nonexist
High Speed Noise
value addition configurations Table 4-19, Fail Safe output buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
Table 4-19 Fail Safe Bi-directional Buffer List
(VDD
Input Level
Drain Type
Test Function*2
Output Latch Function
Speed
Output Current (mA)*1
-9/9 -18/18 -9/9 -18/18 -9/9 -18/18 -9/9 -18/18
Without Resistor
BB1T BB2T BB3AT BB4AT BB3BT BB4BT BG1T BG2T BG3AT BG4AT BG3BT BG4BT
Pull Down
BB1D1T BB2D1T
Pull
BB1P1T BB2P1T
BB1D2T BB2D2T
BB1P2T BB2P2T
Normal Fail Safe Nonexist High Speed Noise Normal CMOS Schmitt Fail Safe Nonexist High Speed Noise
CMOS
Exist
BB3AD1T BB4AD1T BB3BD1T BB4BD1T BG1D1T BG2D1T
BG3AD1T BG4AD1T BG3BD1T BG4BD1T
BB3AD2T BB4AD2T BB3BD2T BB4BD2T BG1D2T BG2D2T
BG3AD2T BG4AD2T BG3BD2T BG4BD2T
BB3AP1T BB4AP1T BB3BP1T BB4BP1T BG1P1T BG2P1T BG3AP1T BG4AP1T BG3BP1T BG4BP1T
BB3AP2T BB4AP2T BB3BP2T BB4BP2T
BG1P2T BG2P2T
Exist
BG3AP2T BG4AP2T BG3BP2T BG4BP2T
value addition configurations Table 4-21, Fail Safe output buffers configured which have test pins. Customers desiring such structures should direct inquiries EPSON.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Chapter
S1L60000 Series supports port port RAM.
Features
1-Port Asynchronous Static operation read/write address port, input data port, output data port configurations supported:Word Depth (incremental words) Width (incremental bit) Maximum size: bits/module 2-Port Asynchronous Static operation read address port, write address port, input data port, output data port configurations supported:Word Depth (incremental words) Width (incremental bit) Maximum size: bits/module
Configuration Simulation Model Selection
delay parameters change depending word/bit structure. Simulation models have been prepared using performance characteristics indicative word/bit configuration. 1-port 2-port word/bit structure simulation models shown Tables respectively. with word/bit structures exceeding limitations tables below, combinations multiple RAMs.
Table Simulation Model Selection Chart (1-Port Word/Bit Structure) Word depth width
RAM1P1 RAM1P2 RAM1P3 RAM1P4
RAM1P5 RAM1P6 RAM1P7 RAM1P8 RAM1P9 RAM1P10 RAM1P11 RAM1P12
RAM1P13 RAM1P14 RAM1P15 RAM1P16
RAM1P17 RAM1P18 RAM1P19 RAM1P20
RAM1P21 RAM1P22 RAM1P23 RAM1P24
RAM1P25 RAM1P26 RAM1P27 RAM1P28
RAM1P29 RAM1P30 RAM1P31 RAM1P32
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Table Simulation Model Selection Chart (2-Port Word/Bit Structure) Word depth width
RAM2P1 RAM2P2 RAM2P3 RAM2P4
RAM2P5 RAM2P6 RAM2P7 RAM2P8 RAM2P9 RAM2P10 RAM2P11 RAM2P12
RAM2P13 RAM2P14 RAM2P15 RAM2P16
RAM2P17 RAM2P18 RAM2P19 RAM2P20
RAM2P21 RAM2P22 RAM2P23 RAM2P24
RAM2P25 RAM2P26 RAM2P27 RAM2P28
RAM2P29 RAM2P30 RAM2P31 RAM2P32
Size
X-direction size, Y-direction size, number used calculated using formulas below. formulas below include interconnect region contained RAM. 1-Port Size direction:RX Word/2 Size direction:RY word 256) (256 word 512) Number BCs: RAMBCS
Table Example Structure 1-Port Number width Word depth
3248 (116 5936 (212 11312 (404 22852 (788
5104 (116 9328 (212 17776 (404 35460 (788
8816 (116 16112 (212 30704 (404 60676 (788
16240 (116 140) 29680 (212 140) 56560 (404 140) 111108 (788 141)
2-Port Size direction:RX Word/2 Size direction:RY word 256) (256 word 512) Number BCs: RAMBCS
Table Example Structure 2-Port Number width Word depth
3596 (116 6572 (212 12524 (404 26004 (788
5452 (116 9964 (212 18988 (404 38612 (788
9164 (116 16748 (212 31916 (404 63828 (788
16588 (116 143) 30316 (212 143) 57772 (404 143) 114260 (788 145)
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Investigating Placement Master Slice
When investigating placement master slice, please insure that sufficient area available both direction (column) direction (row). When loading onto chip, necessary insure that capacity master exceeds required area both directions. When multiple RAMs used, blocks placed adjacent each other either horizontally vertically. wiring areas around included equation shown previous section. therefore possible determine advantages disadvantages placing master slice based values obtained simply adding RXSIZE RYSIZE sizes directions, respectively. shown Figure 5-1, interconnecting area Bit/2 (round nearest whole number) direction every upper lower direction, then regarding master slice selection should decided mount not. Please Table Chapter regarding number columns (X-direction) number rows (Y-direction). example, four word 1-port RAMs required. shown Figure 5-1, total layout area would direction: direction: Because this, S1L60093/60094 (605, 164) impossible area constraints, however, S1L60173/60174 (795, 216) possible. Section Chapter pertaining estimating number gates, which used random logic.
256W
Figure Example Layout
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Explanation Functions
1-Port
Table 5-5-1 1-Port Signals Signal Name A(m-1) D(n-1) Y(n-1) Function Chip select signal, active Read/write signal, Read, Write Read/write address port, Data input port, Data output port,
Table 5-5-2 1-Port
28.9LU 28.9LU 28.9LU 28.9LU
corresponds "IN4"
Table 1-Port Truth Table A(m-1) Stable Stable Y(n-1) Unknown Unknown Read Data Mode Wait Write Read
High Data Read data read holding High High setting address. Data Write data written either following ways: Holding High, setting address, sending negative pulse Holding Low, setting address, sending positive pulse When either method used, data latched trailing edge pulse. Wait State When Low, port enters wait state only maintains data. current consumed merely leakage current, almost zero.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
2-Port
Table 5-7-1 2-Port Signals Signal Name RA0, RA(m-1) WA0, WA(m-1) D(n-1) Y(n-1) Function Chip select signal, active Read signal, Read enable Write signal, Write enable Read address port, RA0: Write address port, WA0: Data input port, Data output port,
Table 5-7-2 2-Port RA0/ RA1/ RA2/ RA3/ RA4/ RA5/ RA6/ RA7/ RA8/
28.9LU 28.9LU 28.9LU 28.9LU
corresponds "IN4"
Table 2-Port Truth Table RA0, RA(n-1) Stable Stable WA0, WA(m-1) Stable Stable Y(n-1) Unknown Unknown Unknown Read Data Read Data Mode Wait Wait Write Read Read Write
High Data Read data read holding High High setting read address. Data Write data written either following ways: Holding High, setting write address, sending positive pulse Holding High, setting write address, sending positive pulse
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Data Read/Write When reading done same time writing, possible performing respective methods simultaneously. However, these operations cannot performed simultaneously same address. read cycle access time described Section applies data which writing already been completed. Wait State port enters wait state either situations below, does nothing maintain data. current consumed merely leakage current, almost Low. High, Low, Low.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Delay Parameters
Specifications (VDD 85°C)
Table 1-Port/2-Port Read Cycle (1/8)
RAM1P1/RAM2P1 RAM1P2/RAM2P2 RAM1P3/RAM2P3 RAM1P4/RAM2P4
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 4.605 4.605 0.093 0.093 0.093
Unit Max.
4.605 4.605 4.605
Min.
5.239 5.239 0.153 0.153 0.153
Max.
5.239 5.239 5.239
Min.
5.519 5.519 0.212 0.212 0.212
Max.
5.519 5.519 5.519
Min.
6.203 6.203 0.272 0.272 0.272
Max.
6.203 6.203 6.203
Table 1-Port/2-Port Read Cycle (2/8)
RAM1P5/RAM2P5 RAM1P6/RAM2P6 RAM1P7/RAM2P7 RAM1P8/RAM2P8
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 5.668 5.668 0.093 0.093 0.093
Unit Max.
5.668 5.668 5.668
Min.
6.302 6.302 0.153 0.153 0.153
Max.
6.302 6.302 6.302
Min.
6.581 6.581 0.212 0.212 0.212
Max.
6.581 6.581 6.581
Min.
7.266 7.266 0.272 0.272 0.272
Max.
7.266 7.266 7.266
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 1-Port/2-Port Read Cycle (3/8)
RAM1P9/RAM2P9 RAM1P10/RAM2P10 RAM1P11/RAM2P11 RAM1P12/RAM2P12
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 6.731 6.731 0.093 0.093 0.093
Unit Max.
6.731 6.731 6.731
Min.
7.365 7.365 0.153 0.153 0.153
Max.
7.365 7.365 7.365
Min.
7.644 7.644 0.212 0.212 0.212
Max.
7.644 7.644 7.644
Min.
8.328 8.328 0.272 0.272 0.272
Max.
8.328 8.328 8.328
Table 1-Port/2-Port Read Cycle (4/8) RAM1P13/RAM2P13 RAM1P14/RAM2P14 RAM1P15/RAM2P15 RAM1P16/RAM2P16 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 7.794 7.794 0.093 0.093 0.093
Unit Max.
7.794 7.794 7.794
Min.
8.428 8.428 0.153 0.153 0.153
Max.
8.428 8.428 8.428
Min.
8.707 8.707 0.212 0.212 0.212
Max.
8.707 8.707 8.707
Min.
9.391 9.391 0.272 0.272 0.272
Max.
9.391 9.391 9.391
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 85°C)
Table 1-Port/2-Port Read Cycle (5/8) RAM1P17/RAM2P17 RAM1P18/RAM2P18 RAM1P19/RAM2P19 RAM1P20/RAM2P20 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 8.856 8.856 0.093 0.093 0.093
Unit Max.
8.856 8.856 8.856
Min.
9.490 9.490 0.153 0.153 0.153
Max.
9.490 9.490 9.490
Min.
9.770 9.770 0.212 0.212 0.212
Max.
9.770 9.770 9.770
Min.
10.454 10.454 0.272 0.272 0.272
Max.
10.454 10.454 10.454
Table 1-Port/2-Port Read Cycle (6/8) RAM1P21/RAM2P21 RAM1P22/RAM2P22 RAM1P23/RAM2P23 RAM1P24/RAM2P24 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 9.919 9.919 0.093 0.093 0.093
Unit Max.
9.919 9.919 9.919
Min.
10.553 10.553 0.153 0.153 0.153
Max.
10.553 10.553 10.553
Min.
10.832 10.832 0.212 0.212 0.212
Max.
10.832 10.832 10.832
Min.
11.517 11.517 0.272 0.272 0.272
Max.
11.517 11.517 11.517
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 1-Port/2-Port Read Cycle (7/8) RAM1P25/RAM2P25 RAM1P26/RAM2P26 RAM1P27/RAM2P27 RAM1P28/RAM2P28 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 10.982 10.982 0.093 0.093 0.093
Unit Max.
10.982 10.982 10.982
Min.
11.616 11.616 0.153 0.153 0.153
Max.
11.616 11.616 11.616
Min.
11.895 11.895 0.212 0.212 0.212
Max.
11.895 11.895 11.895
Min.
12.579 12.579 0.272 0.272 0.272
Max.
12.579 12.579 12.579
Table 1-Port/2-Port Read Cycle (8/8) RAM1P29/RAM2P29 RAM1P30/RAM2P30 RAM1P31/RAM2P31 RAM1P32/RAM2P32 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 12.045 12.045 0.093 0.093 0.093
Unit Max.
12.045 12.045 12.045
Min.
12.679 12.679 0.153 0.153 0.153
Max.
12.679 12.679 12.679
Min.
12.958 12.958 0.212 0.212 0.212
Max.
12.958 12.958 12.958
Min.
13.642 13.642 0.272 0.272 0.272
Max.
13.642 13.642 13.642
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 85°C)
Table 5-10 1-Port/2-Port Write Cycle (1/8)
RAM1P1/RAM2P1 RAM1P2/RAM2P2 RAM1P3/RAM2P3 RAM1P4/RAM2P4
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 2.776 1.347 1.347 0.481 0.938 0.000 1.671
Unit Max.
Min.
3.624 2.223 2.223 0.481 0.938 0.000 2.374
Max.
Min.
4.520 3.101 3.101 0.481 0.938 0.000 3.078
Max.
Min.
5.396 3.977 3.977 0.481 0.938 0.000 3.781
Max.
Table 5-10 1-Port/2-Port Write Cycle (2/8)
RAM1P5/RAM2P5 RAM1P6/RAM2P6 RAM1P7/RAM2P7 RAM1P8/RAM2P8
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 2.924 1.425 1.425 0.561 0.938 0.000 1.731
Unit Max.
Min.
3.799 2.300 2.300 0.561 0.938 0.000 2.434
Max.
Min.
4.677 3.178 3.178 0.561 0.938 0.000 3.138
Max.
Min.
5.553 4.054 4.054 0.561 0.938 0.000 3.841
Max.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 5-10 1-Port/2-Port Write Cycle (3/8)
RAM1P9/RAM2P9 RAM1P10/RAM2P10 RAM1P11/RAM2P11 RAM1P12/RAM2P12
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.092 1.513 1.513 0.641 0.938 0.000 1.791
Unit Max.
Min.
3.968 2.389 2.389 0.641 0.938 0.000 2.495
Max.
Min.
4.846 3.267 3.267 0.641 0.938 0.000 3.198
Max.
Min.
5.722 4.143 4.143 0.641 0.938 0.000 3.901
Max.
Table 5-10 1-Port/2-Port Write Cycle (4/8) RAM1P13/RAM2P13 RAM1P14/RAM2P14 RAM1P15/RAM2P15 RAM1P16/RAM2P16 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.273 1.614 1.614 0.721 0.938 0.000 1.851
Unit Max.
Min.
4.148 2.489 2.489 0.721 0.938 0.000 2.555
Max.
Min.
5.026 3.367 3.367 0.721 0.938 0.000 3.258
Max.
Min.
5.902 4.243 4.243 0.721 0.938 0.000 3.961
Max.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 85°C)
Table 5-10 1-Port/2-Port Write Cycle (5/8) RAM1P17/RAM2P17 RAM1P18/RAM2P18 RAM1P19/RAM2P19 RAM1P20/RAM2P20 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.397 1.679 1.679 0.780 0.938 0.000 1.895
Unit Max.
Min.
4.272 2.554 2.554 0.780 0.938 0.000 2.593
Max.
Min.
5.150 3.432 3.432 0.780 0.938 0.000 3.296
Max.
Min.
6.026 4.308 4.308 0.780 0.938 0.000 4.000
Max.
Table 5-10 1-Port/2-Port Write Cycle (6/8) RAM1P21/RAM2P21 RAM1P22/RAM2P22 RAM1P23/RAM2P23 RAM1P24/RAM2P24 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.558 1.764 1.764 0.856 0.938 0.000 1.952
Unit Max.
Min.
4.443 2.639 2.639 0.856 0.938 0.000 2.650
Max.
Min.
5.311 3.517 3.517 0.856 0.938 0.000 3.353
Max.
Min.
6.188 4.394 4.394 0.856 0.938 0.000 4.057
Max.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 5-10 1-Port/2-Port Write Cycle (7/8) RAM1P25/RAM2P25 RAM1P26/RAM2P26 RAM1P27/RAM2P27 RAM1P28/RAM2P28 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.720 1.850 1.850 0.932 0.938 0.000 2.009
Unit Max.
Min.
4.595 2.725 2.725 0.932 0.938 0.000 2.707
Max.
Min.
5.473 3.603 3.603 0.932 0.938 0.000 3.410
Max.
Min.
6.349 4.479 4.479 0.932 0.938 0.000 4.113
Max.
Table 5-10 1-Port/2-Port Write Cycle (8/8) RAM1P29/RAM2P29 RAM1P30/RAM2P30 RAM1P31/RAM2P31 RAM1P32/RAM2P32 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.880 1.935 1.935 1.007 0.938 0.000 2.066
Unit Max.
Min.
4.755 2.810 2.810 1.007 0.938 0.000 2.764
Max.
Min.
5.633 3.688 3.688 1.007 0.938 0.000 3.467
Max.
Min.
6.509 4.564 4.564 1.007 0.938 0.000 4.170
Max.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 70°C)
Table 5-11 1-Port/2-Port Read Cycle (1/8)
RAM1P1/RAM2P1 RAM1P2/RAM2P2 RAM1P3/RAM2P3 RAM1P4/RAM2P4
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 4.356 4.356 0.099 0.099 0.099
Unit Max.
4.356 4.356 4.356
Min.
4.956 4.956 0.163 0.163 0.163
Max.
4.956 4.956 4.956
Min.
5.220 5.220 0.226 0.226 0.226
Max.
5.220 5.220 5.220
Min.
5.868 5.868 0.289 0.289 0.289
Max.
5.868 5.868 5.868
Table 5-11 1-Port/2-Port Read Cycle (2/8)
RAM1P5/RAM2P5 RAM1P6/RAM2P6 RAM1P7/RAM2P7 RAM1P8/RAM2P8
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 5.362 5.362 0.099 0.099 0.099
Unit Max.
5.362 5.362 5.362
Min.
5.961 5.961 0.163 0.163 0.163
Max.
5.961 5.961 5.961
Min.
6.226 6.226 0.226 0.226 0.226
Max.
6.226 6.226 6.226
Min.
6.873 6.873 0.289 0.289 0.289
Max.
6.873 6.873 6.873
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 70°C)
Table 5-11 1-Port/2-Port Read Cycle (3/8)
RAM1P9/RAM2P9 RAM1P10/RAM2P10 RAM1P11/RAM2P11 RAM1P12/RAM2P12
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 6.367 6.367 0.099 0.099 0.099
Unit Max.
6.367 6.367 6.367
Min.
6.967 6.967 0.163 0.163 0.163
Max.
6.967 6.967 6.967
Min.
7.231 7.231 0.226 0.226 0.226
Max.
7.231 7.231 7.231
Min.
7.878 7.878 0.289 0.289 0.289
Max.
7.878 7.878 7.878
Table 5-11 1-Port/2-Port Read Cycle (4/8) RAM1P13/RAM2P13 RAM1P14/RAM2P14 RAM1P15/RAM2P15 RAM1P16/RAM2P16 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 7.372 7.372 0.099 0.099 0.099
Unit Max.
7.372 7.372 7.372
Min.
7.972 7.972 0.163 0.163 0.163
Max.
7.972 7.972 7.972
Min.
8.236 8.236 0.226 0.226 0.226
Max.
8.236 8.236 8.236
Min.
8.884 8.884 0.289 0.289 0.289
Max.
8.884 8.884 8.884
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 70°C)
Table 5-11 1-Port/2-Port Read Cycle (5/8) RAM1P17/RAM2P17 RAM1P18/RAM2P18 RAM1P19/RAM2P19 RAM1P20/RAM2P20 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 8.378 8.378 0.099 0.099 0.099
Unit Max.
8.378 8.378 8.378
Min.
8.977 8.977 0.163 0.163 0.163
Max.
8.977 8.977 8.977
Min.
9.242 9.242 0.226 0.226 0.226
Max.
9.242 9.242 9.242
Min.
9.889 9.889 0.289 0.289 0.289
Max.
9.889 9.889 9.889
Table 5-11 1-Port/2-Port Read Cycle (6/8) RAM1P21/RAM2P21 RAM1P22/RAM2P22 RAM1P23/RAM2P23 RAM1P24/RAM2P24 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 9.383 9.383 0.099 0.099 0.099
Unit Max.
9.383 9.383 9.383
Min.
9.983 9.983 0.163 0.163 0.163
Max.
9.983 9.983 9.983
Min.
10.247 10.247 0.226 0.226 0.226
Max.
10.247 10.247 10.247
Min.
10.894 10.894 0.289 0.289 0.289
Max.
10.894 10.894 10.894
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 70°C)
Table 5-11 1-Port/2-Port Read Cycle (7/8) RAM1P25/RAM2P25 RAM1P26/RAM2P26 RAM1P27/RAM2P27 RAM1P28/RAM2P28 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 10.388 10.388 0.099 0.099 0.099
Unit Max.
10.388 10.388 10.388
Min.
10.988 10.988 0.163 0.163 0.163
Max.
10.988 10.988 10.988
Min.
11.252 11.252 0.226 0.226 0.226
Max.
11.252 11.252 11.252
Min.
11.900 11.900 0.289 0.289 0.289
Max.
11.900 11.900 11.900
Table 5-11 1-Port/2-Port Read Cycle (8/8) RAM1P29/RAM2P29 RAM1P30/RAM2P30 RAM1P31/RAM2P31 RAM1P32/RAM2P32 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 11.394 11.394 0.099 0.099 0.099
Unit Max.
11.394 11.394 11.394
Min.
11.993 11.993 0.163 0.163 0.163
Max.
11.993 11.993 11.993
Min.
12.257 12.257 0.226 0.226 0.226
Max.
12.257 12.257 12.257
Min.
12.905 12.905 0.289 0.289 0.289
Max.
12.905 12.905 12.905
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 70°C)
Table 5-12 1-Port/2-Port Write Cycle (1/8)
RAM1P1/RAM2P1 RAM1P2/RAM2P2 RAM1P3/RAM2P3 RAM1P4/RAM2P4
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 2.617 1.275 1.275 0.455 0.887 0.000 1.581
Unit Max.
Min.
3.444 2.102 2.102 0.455 0.887 0.000 2.246
Max.
Min.
4.275 2.933 2.933 0.455 0.887 0.000 2.911
Max.
Min.
5.104 3.762 3.762 0.455 0.887 0.000 3.577
Max.
Table 5-12 1-Port/2-Port Write Cycle (2/8)
RAM1P5/RAM2P5 RAM1P6/RAM2P6 RAM1P7/RAM2P7 RAM1P8/RAM2P8
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 2.766 1.348 1.348 0.531 0.887 0.000 1.638
Unit Max.
Min.
3.594 2.176 2.176 0.531 0.887 0.000 2.303
Max.
Min.
4.424 3.006 3.006 0.531 0.887 0.000 2.968
Max.
Min.
5.253 3.835 3.835 0.531 0.887 0.000 3.633
Max.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 70°C)
Table 5-12 1-Port/2-Port Write Cycle (3/8)
RAM1P9/RAM2P9 RAM1P10/RAM2P10 RAM1P11/RAM2P11 RAM1P12/RAM2P12
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 2.926 1.432 1.432 0.607 0.887 0.000 1.694
Unit Max.
Min.
3.754 2.260 2.260 0.607 0.887 0.000 2.360
Max.
Min.
4.584 3.090 3.090 0.607 0.887 0.000 3.025
Max.
Min.
5.413 3.919 3.919 0.607 0.887 0.000 3.690
Max.
Table 5-12 1-Port/2-Port Write Cycle (4/8) RAM1P13/RAM2P13 RAM1P14/RAM2P14 RAM1P15/RAM2P15 RAM1P16/RAM2P16 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.096 1.527 1.527 0.682 0.887 0.000 1.751
Unit Max.
Min.
3.923 2.354 2.354 0.682 0.887 0.000 2.416
Max.
Min.
4.754 3.185 3.185 0.682 0.887 0.000 3.082
Max.
Min.
5.583 4.014 4.014 0.682 0.887 0.000 3.747
Max.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 70°C)
Table 5-12 1-Port/2-Port Write Cycle (5/8) RAM1P17/RAM2P17 RAM1P18/RAM2P18 RAM1P19/RAM2P19 RAM1P20/RAM2P20 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.213 1.588 1.588 0.738 0.887 0.000 1.793
Unit Max.
Min.
4.041 2.416 2.416 0.738 0.887 0.000 2.453
Max.
Min.
4.872 3.247 3.247 0.738 0.887 0.000 3.118
Max.
Min.
5.701 4.076 4.076 0.738 0.887 0.000 3.784
Max.
Table 5-12 1-Port/2-Port Write Cycle (6/8) RAM1P21/RAM2P21 RAM1P22/RAM2P22 RAM1P23/RAM2P23 RAM1P24/RAM2P24 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.366 1.669 1.669 0.810 0.887 0.000 1.847
Unit Max.
Min.
4.194 2.497 2.497 0.810 0.887 0.000 2.507
Max.
Min.
5.024 3.327 3.327 0.810 0.887 0.000 3.172
Max.
Min.
5.853 4.156 4.156 0.810 0.887 0.000 3.837
Max.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 70°C)
Table 5-12 1-Port/2-Port Write Cycle (7/8) RAM1P25/RAM2P25 RAM1P26/RAM2P26 RAM1P27/RAM2P27 RAM1P28/RAM2P28 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.518 1.750 1.750 0.881 0.887 0.000 1.900
Unit Max.
Min.
4.345 2.577 2.577 0.881 0.887 0.000 2.560
Max.
Min.
5.176 3.408 3.408 0.881 0.887 0.000 3.226
Max.
Min.
6.005 4.237 4.237 0.881 0.887 0.000 3.891
Max.
Table 5-12 1-Port/2-Port Write Cycle (8/8) RAM1P29/RAM2P29 RAM1P30/RAM2P30 RAM1P31/RAM2P31 RAM1P32/RAM2P32 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 3.670 1.830 1.830 0.953 0.887 0.000 1.954
Unit Max.
Min.
4.498 2.658 2.658 0.953 0.887 0.000 2.614
Max.
Min.
5.329 3.489 3.489 0.953 0.887 0.000 3.280
Max.
Min.
6.157 4.317 4.317 0.953 0.887 0.000 3.945
Max.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 85°C)
Table 5-13 1-Port/2-Port Read Cycle (1/8)
RAM1P1/RAM2P1 RAM1P2/RAM2P2 RAM1P3/RAM2P3 RAM1P4/RAM2P4
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 6.804 6.804 0.182 0.182 0.182
Unit Max.
6.804 6.804 6.804
Min.
7.736 7.736 0.257 0.257 0.257
Max.
7.736 7.736 7.736
Min.
8.134 8.134 0.332 0.332 0.332
Max.
8.134 8.134 8.134
Min.
9.109 9.109 0.407 0.407 0.407
Max.
9.109 9.109 9.109
Table 5-13 1-Port/2-Port Read Cycle (2/8)
RAM1P5/RAM2P5 RAM1P6/RAM2P6 RAM1P7/RAM2P7 RAM1P8/RAM2P8
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 8.450 8.450 0.182 0.182 0.182
Unit Max.
8.450 8.450 8.450
Min.
9.382 9.382 0.257 0.257 0.257
Max.
9.382 9.382 9.382
Min.
9.781 9.781 0.332 0.332 0.332
Max.
9.781 9.781 9.781
Min.
10.755 10.755 0.407 0.407 0.407
Max.
10.755 10.755 10.755
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 5-13 1-Port/2-Port Read Cycle (3/8)
RAM1P9/RAM2P9 RAM1P10/RAM2P10 RAM1P11/RAM2P11 RAM1P12/RAM2P12
Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 10.096 10.096 0.182 0.182 0.182
Unit Max.
10.096 10.096 10.096
Min.
11.028 11.028 0.257 0.257 0.257
Max.
11.028 11.028 11.028
Min.
11.427 11.427 0.332 0.332 0.332
Max.
11.427 11.427 11.427
Min.
12.402 12.402 0.407 0.407 0.407
Max.
12.402 12.402 12.402
Table 5-13 1-Port/2-Port Read Cycle (4/8) RAM1P13/RAM2P13 RAM1P14/RAM2P14 RAM1P15/RAM2P15 RAM1P16/RAM2P16 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 11.743 11.743 0.182 0.182 0.182
Unit Max.
11.743 11.743 11.743
Min.
12.675 12.675 0.257 0.257 0.257
Max.
12.675 12.675 12.675
Min.
13.074 13.074 0.332 0.332 0.332
Max.
13.074 13.074 13.074
Min.
14.048 14.048 0.407 0.407 0.407
Max.
14.048 14.048 14.048
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 85°C)
Table 5-13 1-Port/2-Port Read Cycle (5/8) RAM1P17/RAM2P17 RAM1P18/RAM2P18 RAM1P19/RAM2P19 RAM1P20/RAM2P20 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 13.389 13.389 0.182 0.182 0.182
Unit Max.
13.389 13.389 13.389
Min.
14.321 14.321 0.257 0.257 0.257
Max.
14.321 14.321 14.321
Min.
14.720 14.720 0.332 0.332 0.332
Max.
14.720 14.720 14.720
Min.
15.694 15.694 0.407 0.407 0.407
Max.
15.694 15.694 15.694
Table 5-13 1-Port/2-Port Read Cycle (6/8) RAM1P21/RAM2P21 RAM1P22/RAM2P22 RAM1P23/RAM2P23 RAM1P24/RAM2P24 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 15.036 15.036 0.182 0.182 0.182
Unit Max.
15.036 15.036 15.036
Min.
15.967 15.967 0.257 0.257 0.257
Max.
15.967 15.967 15.967
Min.
16.366 16.366 0.332 0.332 0.332
Max.
16.366 16.366 16.366
Min.
17.341 17.341 0.407 0.407 0.407
Max.
17.341 17.341 17.341
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 5-13 1-Port/2-Port Read Cycle (7/8) RAM1P25/RAM2P25 RAM1P26/RAM2P26 RAM1P27/RAM2P27 RAM1P28/RAM2P28 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 16.682 16.682 0.182 0.182 0.182
Unit Max.
16.682 16.682 16.682
Min.
17.614 17.614 0.257 0.257 0.257
Max.
17.614 17.614 17.614
Min.
18.013 18.013 0.332 0.332 0.332
Max.
18.013 18.013 18.013
Min.
18.987 18.987 0.407 0.407 0.407
Max.
18.987 18.987 18.987
Table 5-13 1-Port/2-Port Read Cycle (8/8) RAM1P29/RAM2P29 RAM1P30/RAM2P30 RAM1P31/RAM2P31 RAM1P32/RAM2P32 Parameter
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
Signal Min.
tACC tACS tARW tRCS tOHCS tOHRW 18.328 18.328 0.182 0.182 0.182
Unit Max.
18.328 18.328 18.328
Min.
19.260 19.260 0.257 0.257 0.257
Max.
19.260 19.260 19.260
Min.
19.659 19.659 0.332 0.332 0.332
Max.
19.659 19.659 19.659
Min.
20.633 20.633 0.407 0.407 0.407
Max.
20.633 20.633 20.633
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 85°C)
Table 5-14 1-Port/2-Port Write Cycle (1/8)
RAM1P1/RAM2P1 RAM1P2/RAM2P2 RAM1P3/RAM2P3 RAM1P4/RAM2P4
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 4.807 2.720 2.720 0.696 1.391 0.000 2.652
Unit Max.
Min.
6.341 4.254 4.254 0.696 1.391 0.000 3.712
Max.
Min.
7.878 5.791 5.791 0.696 1.391 0.000 4.773
Max.
Min.
9.413 7.326 7.326 0.696 1.391 0.000 5.834
Max.
Table 5-14 1-Port/2-Port Write Cycle (2/8)
RAM1P5/RAM2P5 RAM1P6/RAM2P6 RAM1P7/RAM2P7 RAM1P8/RAM2P8
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 5.008 2.822 2.822 0.795 1.391 0.000 2.744
Unit Max.
Min.
6.542 4.356 4.356 0.795 1.391 0.000 3.804
Max.
Min.
8.079 5.893 5.893 0.795 1.391 0.000 4.866
Max.
Min.
9.614 7.428 7.428 0.795 1.391 0.000 5.926
Max.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 5-14 1-Port/2-Port Write Cycle (3/8)
RAM1P9/RAM2P9 RAM1P10/RAM2P10 RAM1P11/RAM2P11 RAM1P12/RAM2P12
Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 5.238 2.953 2.953 0.894 1.391 0.000 2.836
Unit Max.
Min.
6.772 4.487 4.487 0.894 1.391 0.000 3.897
Max.
Min.
8.309 6.024 6.024 0.894 1.391 0.000 4.958
Max.
Min.
9.844 7.559 7.559 0.894 1.391 0.000 6.019
Max.
Table 5-14 1-Port/2-Port Write Cycle (4/8) RAM1P13/RAM2P13 RAM1P14/RAM2P14 RAM1P15/RAM2P15 RAM1P16/RAM2P16 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 5.497 3.113 3.113 0.993 1.391 0.000 2.928
Unit Max.
Min.
7.031 4.647 4.647 0.993 1.391 0.000 3.989
Max.
Min.
8.568 6.184 6.184 0.993 1.391 0.000 5.050
Max.
Min.
10.103 7.719 7.719 0.993 1.391 0.000 6.111
Max.
GATE ARRAY S1L60000 SERIES
EPSON
Chapter
Specifications (VDD 85°C)
Table 5-14 1-Port/2-Port Write Cycle (5/8) RAM1P17/RAM2P17 RAM1P18/RAM2P18 RAM1P19/RAM2P19 RAM1P20/RAM2P20 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 5.711 3.223 3.223 1.097 1.391 0.000 3.009
Unit Max.
Min.
7.245 4.757 4.757 1.097 1.391 0.000 4.069
Max.
Min.
8.752 6.294 6.294 1.097 1.391 0.000 5.131
Max.
Min.
10.317 7.829 7.829 1.097 1.391 0.000 6.191
Max.
Table 5-14 1-Port/2-Port Write Cycle (6/8) RAM1P21/RAM2P21 RAM1P22/RAM2P22 RAM1P23/RAM2P23 RAM1P24/RAM2P24 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 5.941 3.353 3.353 1.197 1.391 0.000 3.098
Unit Max.
Min.
7.475 4.887 4.887 1.197 1.391 0.000 4.159
Max.
Min.
9.012 6.424 6.424 1.197 1.391 0.000 5.220
Max.
Min.
10.547 7.959 7.959 1.197 1.391 0.000 6.281
Max.
EPSON
GATE ARRAY S1L60000 SERIES
Chapter
Specifications (VDD 85°C)
Table 5-14 1-Port/2-Port Write Cycle (7/8) RAM1P25/RAM2P25 RAM1P26/RAM2P26 RAM1P27/RAM2P27 RAM1P28/RAM2P28 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 6.171 3.483 3.483 1.297 1.391 0.000 3.188
Unit Max.
Min.
7.705 5.017 5.017 1.297 1.391 0.000 4.249
Max.
Min.
9.242 6.554 6.554 1.297 1.391 0.000 5.310
Max.
Min.
10.777 8.089 8.089 1.297 1.391 0.000 6.371
Max.
Table 5-14 1-Port/2-Port Write Cycle (8/8) RAM1P29/RAM2P29 RAM1P30/RAM2P30 RAM1P31/RAM2P31 RAM1P32/RAM2P32 Parameter
Write cycle Write pulse width active time Address setup time Address hold time Data setup time Data hold time
Signal Min.
tWCS 6.400 3.613 3.613 1.396 1.391 0.000 3.278
Unit Max.
Min.
7.934 5.147 5.147 1.396 1.391 0.000 4.339
Max.
Min.
9.471 6.684 6.684 1.396 1.391 0.000 5.400
Max.
Min.
11.006 8.219 8.219 1.396 1.391 0.000 6.461
M
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