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EMBEDDED ARRAY
S1X60000 Series
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©SEIKO EPSON CORPORATION 2004, rights reserved.
Configuration product number
DEVICES 65013 00A0
Packing specifications (*3) Specifications Shape (*2) Model number Model name (*1) Product classification (S1:semiconductors) Model name
Standard Cell Gate Array Embedded Array
Shape
Assembled board, COB, Plastic Bare Chip Plastic Ceramic Ceramic
Packing Specifications 14th 15th Packing Specifications Besides tape reel directions Tape reel Back directions directions directions Tape reel FRONT directions directions directions directions Tape reel LEFT directions directions directions directions Tape reel RIGHT Specs fixed
Plastic TAB-QFP Tape Carrier (TAB) TSOP (Standard Bent) TSOP (Reverse Bent)
Table Contents
S1X60000 Series
Table Contents
Chapter Overview
Features. 1.1.1 Outline S1X60000 Series 1.1.2 Internal Structure S1X60000 Series 1.1.3 Structure Types MSIs.3 1.1.4 Structure Tolerant Fail-Safe Cells 1.1.5 Structure Types Input/Output Buffers.3 Electrical Characteristics Specifications 1.2.1 When Using Standard type Input/Output Buffers Type) 1.2.2 When Using Tolerant Fail-Safe Input/Output Buffers Type) Estimating Quiescent Current 1.3.1 Quiescent Current Random Logic Part (IQBC) 1.3.2 Quiescent Current Basic Cell Type (IQBM) 1.3.3 Quiescent Current Input/Output Buffers (IQIO) 1.3.4 Temperature Characteristics Quiescent Current Embedded Array Development Flow. Dividing Logic Between Chips. Estimating Gate Counts Used. Estimating Number Input/Output Pins Bulk List. Cell Types. Types Input/Output Buffers. 4.1.1 Selecting input/output buffers.27 4.1.2 Hold Circuit.28 Input/Output Buffers Single Power Supply 4.2.1 Input Buffers 4.2.2 Output Buffers 4.2.3 Bi-directional Buffers.32 4.2.4 Fail-Safe Cells 4.2.5 Gated Cells Dual Power Supply Input/Output Buffers 4.3.1 Input Buffers 4.3.2 Output Buffers 4.3.3 Bi-directional Buffers.44 4.3.4 Fail-Safe Cells 4.3.5 Gated Cells Dual Power Supplies Guidelines 4.4.1 Method Adapting Dual Power Supplies 4.4.2 Power Supplies Dual Power Operation.52 4.4.3 Turning On/Off Dual Power Supplies.52
Chapter Estimating Gate Density.
Chapter Cells. Chapter Types Input/Output Buffers Their Type).
Chapter Types Input/Output Buffers Their Type).
Types Input/Output Buffers. 5.1.1 Selecting input/output buffers.53 5.1.2 Hold Circuit.54
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Dual Power Supply Input/Output Buffers 5.2.1 Input Buffers 5.2.2 Output Buffers. 5.2.3 Bi-directional Buffers 5.2.4 Fail-Safe Cells. 5.2.5 Gated Cells. 5.2.6 Tolerant Fail-Safe Cells Dual Power Supplies Guidelines. 5.3.1 Method Adapting Dual Power Supplies. 5.3.2 Power Supplies Dual Power Operation 5.3.3 Turning On/Off Dual Power Supplies 5.3.4 Interface with external devices Basic Cell Type (Asynchronous) 6.1.1 Features 6.1.2 Word/Bit Configuration Simulation Model Selection. 6.1.3 Size. 6.1.4 Investigating Placement Master Slice. 6.1.5 Explanation Functions 6.1.6 Delay Parameters 6.1.7 Timing Charts. Basic Cell Type (Synchronous Type). 6.2.1 Features 6.2.2 Word/Bit Configurations Cell Names 6.2.3 Sizes 6.2.4 Investigating Placement Master Slice. 6.2.5 Functional Description. 6.2.6 Timing Charts. 6.2.7 Delay Parameters Standard Type port 6.3.1 Features 6.3.2 Sizes 6.3.3 Input Signals Block Diagrams 6.3.4 Truth Table Device Operation 6.3.5 Timing Charts. 6.3.6 Electrical Characteristics. Standard Type Dual Port RAM. 6.4.1 Features 6.4.2 Sizes 6.4.3 Input Signals Block Diagrams 6.4.4 Truth Table Device Operation 6.4.5 Timing Charts. 6.4.6 Electrical Characteristics. High Density Type port RAM. 6.5.1 Features 6.5.2 Sizes 6.5.3 Input/Output Signals Block Diagrams 6.5.4 Truth Table Device Operation 6.5.5 Timing Charts. 6.5.6 Electrical Characteristics. Mask ROM. 6.6.1 Features 6.6.2 Sizes. 6.6.3 Input/Output Signals Block Diagrams 6.6.4 Truth Table Device Operation 6.6.5 Timing Charts. 6.6.6 Electrical Characteristics.
Chapter Memory Blocks.
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Access Nonexistent Addresses Inhibited Accuracy Propagation Delay Time Calculating Propagation Delay Time. Virtual Wiring Capacitance Fluctuations Propagation Delay Time Setup Hold Times Flip-Flop (FF) Calculation Power Consumption 8.1.1 Internal Cells (Pint).175 8.1.2 Input Buffers (Pi).176 8.1.3 Output Buffers (Po) .176 Limitations Power Consumption Basic Circuit Configuration 9.1.1 Inserting Input/Output Buffers.179 9.1.2 Limitations Logic Gate Output Load .179 9.1.3 Wired Logic Forbidden.179 9.1.4 Synchronized Design Recommended .180 Differentiating Circuits Forbidden Clock Tree Synthesis 9.3.1 Overview .182 9.3.2 Design Flow .183 9.3.3 Applying Clock Tree Synthesis .184 9.3.4 Limitations Notes .186 9.3.5 Clock Tree Synthesis Checksheet .187 9.3.6 Attached Materials.188 Designing Fast Operating Circuits. Metastable State. Configuration Internal Preventing Contention with External Buses Hazard Protection. Oscillation Circuits 9.9.1 Configuration Oscillation Circuits .198 9.9.2 Notes Regarding Oscillation Circuits .200 Restrictions Constraints VHDL/Verilog-HDL Netlist 9.10.1 Common Restrictions Constraints.201 9.10.2 Restrictions Constraints Verilog Netlist .202 9.10.3 Restrictions Constraints VHDL Netlist .203 9.10.4 Description Oscillation Cell AC/DC Test Circuit Cell L1TCIR2 .203 9.10.5 Clock Buffer Description.204 Layout Simultaneous Operation. 9.11.1 Estimating Number Power Supply Pins .206 9.11.2 Simultaneous Operation Adding Power Supplies.208 9.11.3 Cautions Notes Regarding Layout .213 9.11.4 Example Recommended Layout.219 About Power Supply Cutoff Type) 9.12.1 Single Power Supply Systems .220 9.12.2 Dual Power Supply Systems.220 About Power Supply Cutoff Type) 9.13.1 Cell Types Usable during Cut-off.222
Chapter Propagation Delay Timing
Chapter Estimating Power Consumption
Chapter Circuit Design.
9.10
9.11
9.12 9.13
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Chapter Circuit Design that Takes Testability into Account
10.1 Consideration Regarding Circuit Initialization 10.2 Consideration Regarding Compressing Test Patterns. 10.3 Test Circuit Which Simplifies Testing 10.3.1 Configuration Test Circuits. 10.4 Memory Block Test Circuits 10.4.1 Basic Cell Type RAM. 10.4.2 Standard Type port RAM. 10.4.3 Standard Type Dual port 10.4.4 High Density Type 10.4.5 Mask 10.5 Memory BIST Design. 10.5.1 Outline Memory BIST Circuit Block 10.5.2 Outline Memory BIST Circuit Test Sequence. 10.5.3 Types Memory Suitable Memory BIST 10.5.4 Estimating Memory BIST Circuit Size. 10.5.5 About Memory BIST Circuit Design 10.5.6 Other 10.6 Function Cell Test Circuits 10.6.1 Test Circuit Structures 10.6.2 Test Patterns 10.6.3 Test Circuit Data 10.7 Scan Design 10.7.1 About Scan Circuit. 10.7.2 Scan Design Flow 10.7.3 Design Rules 10.8 Boundary Scan Design. 10.8.1 Boundary Scan Design Flow. 10.8.2 Instructions. 10.8.3 Estimating Number Gates 10.8.4 Design Rules
Chapter Test Pattern Generation.
11.1 Testability Consideration 11.2 Usable Input Waveforms 11.3 Constraints Test Patterns 11.3.1 Test Rate Event Counts. 11.3.2 Input Delay 11.3.3 Pulse Width. 11.3.4 Input Waveform Format 11.3.5 Strobes. 11.4 Notes Regarding Testing. 11.5 Notes Regarding Oscillation Circuits 11.6 Regarding Testing. 11.6.1 Constraints Regarding Measurement Events 11.6.2 Constraints Measurement Location Testing. 11.6.3 Constraints Regarding Path Delay Which Tested 11.6.4 Other Constraints. 11.7 Test Patterns Constraints Bi-directional Pins 11.8 Notes Device High Impedance State A1.1 Characteristics Input/Output Buffers (3.3 operation). A1.1.1 Input Buffer Characteristics (3.3 A1.1.2 Input Through Current (3.3 A1.1.3 Output Buffer Characteristics (3.3
Appendix Electrical Characteristics Data Type).
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A1.2 Characteristics Input/Output Buffers (2.5 operation) A1.2.1 Input Buffer Characteristics (2.5 V).290 A1.2.2 Input Through Current (2.5 .291 A1.2.3 Output Buffer Characteristics (2.5 V).292 A1.3 Characteristics Input/Output Buffers (2.0 operation) A1.3.1 Input Buffer Characteristics (2.0 V).299 A1.3.2 Input Through Current (2.0 .300 A1.3.3 Output Buffer Characteristics (2.0 V).301
Appendix Electrical Characteristics Data Type)
A2.1 Characteristics Input/Output Buffers (3.3 operation) A2.1.1 Input Buffer Characteristics (3.3 V).308 A2.1.2 Input Through Current (3.3 .309 A2.1.3 Output Buffer Characteristics (3.3 V).312 A2.2 Characteristics Input/Output Buffers (2.5 operation) A2.2.1 Input Buffer Characteristics (2.5 V).320 A2.2.2 Input Through Current (2.5 .321 A2.2.3 Output Buffer Characteristics (2.5 V).322 A2.3 Characteristics Input/Output Buffers (2.0 operation) A2.3.1 Input Buffer Characteristics (2.0 V).329 A2.3.2 Input Through Current (2.0 .330 A2.3.3 Output Buffer Characteristics (2.0 V).331 A2.4 Characteristics Input/Output Buffers Tolerant Fail-Safe Cell). A2.4.1 Input Buffer Characteristics (3.3 V).338 A2.4.2 Input Through Current (3.3 .338 A2.4.3 Output Buffer Characteristics (3.3 V).339
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Chapter Overview
Chapter Overview
Epson's S1X60000 series consists ultra high speed, super integrated CMOS type embedded arrays manufactured 0.25 process.
1.1.1
Features
Outline S1X60000 Series
27.4k gates/mm2 Internal gates (2.5 Typ.), (2.0 Typ.) input NAND, Standard Wiring Load) Input buffers Standard Wiring Load, Typ. Condition
Operating Speed TYPE Voltage Input Buffer (XHIBC) Input Buffer (XFHIBC) TYPE Tolerant Fail-Safe Input Buffer (XFHIBB) Unit
Integration Operating Speed
V/2.5
Operating Speed TYPE Voltage V/2.0 Input Buffer (XIBC) V/2.0 Input Buffer (XFLIBC) TYPE Tolerant Fail-Safe Input Buffer Unit
Output buffers 15pF, Typ.Condition
Operating Speed TYPE Voltage Output Buffer Output Buffer (XHOB3AT) (XFHOB3AT) TYPE Torelant Fail-Safe Output Buffer (XFHOBF3AT) Unit
V/2.5
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Chapter Overview
Operating Speed TYPE Voltage V/2.0 V/2.0 Output Buffer Output Buffer (XOB3AT) (XFLOB3AT) TYPE Torelant Fail-Safe Output Buffer Unit
Process Levels Input Modes
0.25 3/4/5 layered metalization CMOS LVTTL compatible CMOS, LVTTL, CMOS Schmitt, LVTTL Schmitt, PCI-3 Gated input, Fail-Safe input Tolerant Fail-Safe Input Type only) provided with internal pull-up pull-down resistors resistance values each) Normal, 3-state, Bi-directional, Fail-Safe outputs, PCI-3 Tolerant Fail-Safe output Type only) 0.1, selectable (HVDD (VDD LVDD 0.1, selectable 0.05, 0.3, selectable (VDD LVDD Basic Cell type Asynchronous, port; Asynchronous, ports Synchronous, port; Synchronous, ports Standard type Synchronous, port; Synchronous, dual ports High Density type Synchronous, port Synchronous
Output Modes Drive Output
Memory
Built-in level shifter operation with dual supply voltages Internal logic: Operates with voltage Input/output buffers: interfaced with high voltages
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Chapter Overview
1.1.2
Internal Structure S1X60000 Series
S1X60000 series constructed with cell area input/output buffer circuit area, shown Figure 1-1.
High Density Type
cell area Input/Output buffer circuit area
Figure Outline Structure S1X60000 Series Various cells memory blocks located cell area, depending desired circuit. These cells interconnected order implement desired circuit. input/output buffer area contains input buffers, output buffers, bi-directional buffers, power supply cells. this area, signals exchanged between external circuits units S1X60000 series.
1.1.3
Structure Types MSIs
S1X60000 series available Basic Cell type embedded arrays. Memory also available various types addition Basic Cell type RAM. These include highly integrated Cell Based type (with port, dual ports, high density port) ROM. most suitable memory type selected accordance with customer needs. details cell types, refer Chapter "MSI Cells." details memory, refer Chapter "Memory Block."
1.1.4
Structure Tolerant Fail-Safe Cells
tolerant Fail-Safe cells S1X60000 series allow interfacing without requiring dedicated power supply.
1.1.5
Structure Types Input/Output Buffers
S1X60000 series available types input/output buffers: standard type input/output buffers type) tolerant Fail-Safe input/output buffers type). Therefore, customers choose type that best suits their system specifications. (Note that combined types allowed.) details about input/output buffers, Chapter "Types Input/Output Buffers Their Type)," Chapter "Types Input/Output Buffers Their Type)."
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Chapter Overview
1.2.1
Electrical Characteristics Specifications
When Using Standard type Input/Output Buffers Type)
Table Absolute Maximum Ratings (for Single Power Supply)
(VSS [V]) Parameter Symbol Limits Unit
Power Supply Voltage Input Voltage Output Voltage Output Current/Pin Storage Temperature Notes
IOUT Tstg
-0.3 +3.0 -0.3 -0.3 +150
Possible -0.3 +4.0 channel open drain bi-directional buffers, input buffers, Fail-Safe cells.
Table Absolute Maximum Ratings (for Dual Power Supplies)
(VSS [V]) Parameter Power Supply Voltage Symbol Limits Unit
HVDD LVDD
-0.3 +4.0 -0.3 +3.0 -0.3 HVDD -0.3 LVDD -0.3 LVDD +150 -0.3 HVDD
Input Voltage
Output Voltage Output Current/Pin Storage Temperature Notes
IOUT Tstg
Possible -0.3 +4.0 channel open drain bi-directional buffers input buffers. Possible -0.3 +4.0 channel open drain bi-directional buffers, input buffers, Fail-Safe cells. HVDD LVDD
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Chapter Overview
Table Recommended Operating Conditions (for Single Power Supply
(VSS [V])
Parameter Power Supply Voltage Input Voltage Ambient Temperature Normal Input Rising Time Normal Input Falling Time Schmitt Input Rising Time Schmitt Input Falling Time
Notes
Symbol
Min. 2.30 -0.3
Typ. 2.50
Max. 2.70
Unit
Possible channel open drain bi-directional buffers, input buffers, Fail-Safe cells. ambient temperature range recommended [°C]. ambient temperature range recommended +125 [°C]. This finite time during which power supply voltage changes from vice versa.
Table Recommended Operating Conditions (for Single Power Supply
(VSS [V])
Parameter Power Supply Voltage Input Voltage Ambient Temperature Normal Input Rising Time Normal Input Falling Time Schmitt Input Rising Time Schmitt Input Falling Time
Notes
Symbol
Min. 1.80 -0.3
Typ. 2.00
Max. 2.20
Unit
Possible channel open drain bi-directional buffers, input buffers, Fail-Safe cells. ambient temperature range recommended [°C]. ambient temperature range recommended +125 [°C]. This finite time during which power supply voltage changes from vice versa.
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Chapter Overview
Table Recommended Operating Conditions (for Dual Power Supplies)
(VSS [V])
Parameter
Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage)
Symbol HVDD LVDD
Min. 3.00 2.30 -0.3 -0.3
Typ. 3.30 2.50
Max. 3.60 2.70 HVDD LVDD
Unit
Input Voltage Ambient Temperature
Normal Input Rising Time Normal Input Falling Time Schmitt Input Rising Time
Schmitt Input Falling Time Notes
Possible channel open drain bi-directional buffers input buffers. Possible channel open drain bi-directional buffers, input buffers, Fail-Safe cells. ambient temperature range recommended +85[°C]. ambient temperature range recommended +125[°C]. This finite time during which power supply voltage changes from vice versa.
Table Recommended Operating Conditions (for Dual Power Supplies)
(VSS [V])
Parameter
Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage)
Symbol HVDD LVDD Htri Htra Htri Htra Htri Htra Htri Htra
Min. 3.00 1.80 -0.3 -0.3
Typ. 3.30 2.00
Max. 3.60 2.20 HVDD LVDD
Unit
Input Voltage Ambient Temperature
Normal Input Rising Time
Normal Input Falling Time
Schmitt Input Rising Time
Schmitt Input Falling Time Notes
Possible channel open drain bi-directional buffers input buffers. Possible channel open drain bi-directional buffers, input buffers, Fail-Safe cells. ambient temperature range recommended +85[°C]. ambient temperature range recommended +125[°C]. This finite time during which power supply voltage changes from vice versa.
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Chapter Overview
Table Electrical Characteristics
(HVDD +85°C) Parameter Input Leakage Current State Leakage Current High Level Output Voltage Symbol Conditions -0.1 (Type (Type (Type (Type (Type HVDD Min. (Type (Type (Type (Type (Type HVDD Min. CMOS Level, HVDD Max. CMOS Level, HVDD Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt LVTTL Level, HVDD LVTTL Level, HVDD LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt Level, HVDD Max. Level, HVDD Min. Type Pull-up Resistance Type Type Pull-down Resistance HVDD Type Min. HVDD -0.4 Typ. Max. Unit
Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage High Level Input Voltage Level Input Voltage
VIH1 VIL1 VT1+ VT1VH1 VIH2 VIL2 VT2+ VT2VH2 VIH3 VIL3
(120)*1 (240)*1 (120)*1 (240)*1 -115
0.90 HVDD Min. High Level Output IOH3 Current Response 2.52 HVDD Max. 1.80 HVDD Min. Level Output IOL3 Current Response 0.65 HVDD Max. Hold High Level Maintenance IBHH Current Response HVDD Min. Hold Level Maintenance IBHL Current Response HVDD Min. Hold High Level Reversal -350 IBHHO Current Response HVDD Max. Hold Level Reversal IBHLO Current Response HVDD Max. Input Terminal MHz, HVDD Capacitance Output Terminal MHz, HVDD Capacitance Input/Output Terminal MHz, HVDD Capacitance Notes value enclosed indicates resistance value when +70°C. Compliant with Standard Rev.
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Chapter Overview
Table Electrical Characteristics
(VDD LVDD +85°C) Parameter Input Leakage Current State Leakage Current High Level Output Voltage Symbol Conditions -0.1 (Type (Type (Type (Type (Type Min. (Type (Type (Type (Type (Type Min. CMOS Level, Max. CMOS Level, Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt Type Pull-up Resistance Type Type Pull-down Resistance HVDD Type High Level Maintenance Current Level Maintenance Current High Level Reversal Current Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance Note IBHH IBHL IBHHO IBHLO Hold Response Hold Response Hold Response Hold Response MHz, MHz, MHz, Min. Min. Max. Max. -280 Min. -0.4 Typ. Max. Unit
Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage
VIH1 VIL1 VT1+ VT1VH1
(100) (200)*1 (100)*1 (200)*1
value enclosed indicates resistance value when +70°C.
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Chapter Overview
Table Electrical Characteristics
(VDD LVDD +85°C) Parameter Input Leakage Current State Leakage Current High Level Output Voltage Symbol Conditions -0.05 (Type -0.3 (Type (Type (Type (Type Min. 0.05 (Type (Type (Type (Type (Type Min. CMOS Level, Max. CMOS Level, Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt Type Type Type Type Min. Min. Max. Max. Min. -0.2 Typ. Max. Unit
Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage Pull-up Resistance
VIH1 VIL1 VT1+ VT1VH1
-100
Pull-down Resistance High Level Maintenance Current Level Maintenance Current High Level Reversal Current Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance
IBHH IBHL IBHHO IBHLO
Hold Response Hold Response Hold Response Hold Response
MHz, MHz, MHz,
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Chapter Overview
1.2.2
When Using Tolerant Fail-Safe Input/Output Buffers Type)
Table 1-10 Absolute Maximum Ratings (for Dual Power Supplies)
(VSS [V])
Parameter Power Supply Voltage
Symbol HVDD*3 LVDD*3 Iout Tstg
Limits -0.3 +4.0 -0.3 +2.5 -0.3 HVDD -0.3 HVDD -0.3 LVDD
Unit
Input Voltage
-0.3 LVDD 0.5*2
Output Voltage Output Current/Pin Storage Temperature Notes
+150
Possible -0.3 +4.0 channel open drain bi-directional buffers input buffers, -0.3 Tolerant Fail-Safe cells. Possible -0.3 +4.0 channel open drain bi-directional buffers, input buffers, Fail-Safe cells. HVDD LVDD
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Table 1-11 Recommended Operating Conditions (for Dual Power Supplies)
(VSS [V]) Parameter Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage) Input Voltage Ambient Temperature Normal Input Rising Time Normal Input Falling Time Schmitt Input Rising Time Schmitt Input Falling Time Notes
Symbol HVDD LVDD
Min. 3.00 2.30 -0.3 -0.3
Typ. 3.30 2.50
Max. 3.60 2.70 HVDD LVDD
Unit
Possible channel open drain bi-directional buffers input buffers Tolerant Fail-Safe cells. Possible channel open drain bi-directional buffers, input buffers, Fail-Safe cells. ambient temperature range recommended +85[°C]. ambient temperature range recommended +125[°C]. This finite time during which power supply voltage changes from vice versa.
Table 1-12 Recommended Operating Conditions (for Dual Power Supplies)
(VSS [V]) Parameter Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage) Input Voltage Symbol HVDD LVDD Min. 3.00 1.80 -0.3 -0.3 Typ. 3.30 2.00 Max. 3.60 2.20 HVDD LVDD
Unit
Ambient Temperature Normal Input Rising Time Normal Input Falling Time Schmitt Input Rising Time Schmitt Input Falling Time Notes
Possible channel open drain bi-directional buffers input buffers Tolerant Fail-Safe cells. Possible channel open drain bi-directional buffers, input buffers, Fail-Safe cells. ambient temperature range recommended +85[°C]. ambient temperature range recommended +125[°C]. This finite time during which power supply voltage changes from vice versa.
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Chapter Overview
Table 1-13 Electrical Characteristics (1/2)
(HVDD +85°C) Parameter Input Leakage Current State Leakage Current Input Leakage Current Tolerant Fail-Safe Cell) State Leakage Current Tolerant Fail-Safe Cell) High Level Output Voltage (Ordinary Cell) High Level Output Voltage Tolerant Fail-Safe Cell) Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage High Level Input Voltage*2 Level Input Voltage*2 Pull-up Resistance Symbol ILIF Conditions Min. Typ. Max. Unit
IOZF
-0.1 (Type (Type (Type (Type (Type HVDD Min. (Type (Type (Type HVDD Min. -0.1 (Type (Type (Type (Type (Type HVDD Min. CMOS Level, HVDD Max. CMOS Level, HVDD Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt LVTTL Level, HVDD Max. LVTTL Level, HVDD Min. LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt Level, HVDD Max. Level, HVDD Min. TYPE
VOH1
HVDD -0.4 HVDD -1.0
VOH2
VOL1 VIH1 VIL1 VT1+ VT1VH1 VIH2 VIL2 VT2+ VT2VH2 VIH3 VIL3
(120) (240)*1 (120)*1 (240)*1
TYPE TYPE
Pull-down Resistance
HVDD TYPE
Note
value enclosed indicates resistance value when +70°C. Compliant with Standard Rev.
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Table 1-13 Electrical Characteristics (2/2)
(HVDD +85°C) Parameter High Level Output Voltage Level Output Voltage High Level Maintenance Current Level Maintenance Current High Level Reversal Current Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance Note Symbol IOH3 IOL3 IBHH IBHL IBHHO IBHLO Hold Response Hold Response Hold Response Hold Response Conditions 0.90 HVDD Min. 1.80 HVDD Min. HVDD Min. HVDD Min. HVDD Max. HVDD Max. Response 2.52 HVDD Max. Response 0.65 HVDD Max. Min. -350 Typ. Max. -115 -137 Unit
MHz, HVDD MHz, HVDD MHz, HVDD
Compliant with Standard Rev.
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Chapter Overview
Table 1-14 Electrical Characteristics
(LVDD +85°C) Parameter Input Leakage Current State Leakage Current High Level Output Voltage Symbol Conditions -0.1 (Type (Type (Type (Type (Type LVDD Min. (Type (Type (Type (Type (Type Min. CMOS Level, Max. CMOS Level, Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt TYPE Pull-up Resistance TYPE TYPE Pull-down Resistance High Level Maintenance Current Level Maintenance Current High Level Reversal Current Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance LVDD TYPE IBHH IBHL IBHHO IBHLO Hold Response Hold Response Hold Response Hold Response Min. Min. Max. Max. -280 Min. LVDD -0.4 Typ. Max. Unit
VOH1
Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage
VOL1 VIH1 VIL1 VT1+ VT1VH1
(100) (200)*1 (100)*1 (200)*1
MHz, LVDD MHz, LVDD MHz, LVDD
Note value enclosed indicates resistance value when +70°C.
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Table 1-15 Electrical Characteristics
(LVDD +85°C) Parameter Input Leakage Current State Leakage Current High Level Output Voltage Symbol Conditions Min. Typ. Max. Unit
VOH1
-0.05 (Type -0.3 (Type LVDD (Type (Type (Type -0.2 LVDD Min. 0.05 (Type (Type (Type (Type (Type LVDD Min. CMOS Level, Max. CMOS Level, Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt TYPE TYPE TYPE TYPE LVDD Min. LVDD Min. LVDD Max. LVDD Max. -100
Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage Pull-up Resistance
VOL1 VIH1 VIL1 VT1+ VT1VH1
Pull-down Resistance High Level Maintenance Current Level Maintenance Current High Level Reversal Current Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance
IBHH IBHL IBHHO IBHLO
LVDD Hold Response Hold Response Hold Response Hold Response
MHz, LVDD MHz, LVDD MHz, LVDD
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Chapter Overview
Estimating Quiescent Current
quiescent current cells S1X60000 series roughly estimated using equation shown below. When calculating quiescent current, please assume ambient temperature (Ta) chip temperature (Tj). quiescent current depends current each transistor. Because quiescent current entire chip cannot easily calculated simultaneously, divide chip into several blocks calculation quiescent current, total blocks chip's quiescent current.
IDDS 85°C) IQBC IQBM IQIO
1.3.1
Quiescent Current Random Logic Part (IQBC)
Table 1-16 lists quiescent current gate S1X60000 series. Table 1-16 Quiescent Current Gate 85°C)
2.70 2.20 6.35
Unit
IQBC
7.94
1.3.2
Quiescent Current Basic Cell Type (IQBM)
quiescent current values primary Basic Cell type RAMs S1X60000 series listed Table 1-17. find quiescent current when 2.20 85°C, multiply values shown below 0.8.) (For quiescent current values RAMs listed here, quiescent current value that closest structure those RAMs. more detailed information quiescent current values required, please contact sales division Epson.) Table 1-17 Quiescent Current Values Basic Cell Type (Common port port RAM, 2.70 85°C)
Asynchronous Word 2.19
Word 3.73
Word 6.82
Word 12.99
Unit
3.08 10-6 4.87
5.24 10-6 8.25
9.54 10-6 14.99
18.16 10-6 28.48
8.46 10-6
14.27 10-6
25.89 10-6
49.14 10-6
Synchronous Word 2.19 10-6 3.08 3.98 4.87
Word 3.73 10-6 5.24 6.74 8.25
Word 5.27 10-6 7.39 9.51
Word 6.82 10-6 9.54
Unit
12.27 14.99
11.62
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Chapter Overview
1.3.3
Quiescent Current Input/Output Buffers (IQIO)
quiescent current values flowing input/output buffers roughly estimated using values listed Table 1-18 calculation formula shown next page. (Make sure input signals input bi-directional buffers fixed (LVDD HVDD). buffers with pull-up pull-down resistors have been selected, leave pins open.) systems with dual power supplies, calculate quiescent current L-voltage buffers separately. Note: When connecting (LVDD HVDD) pin, sure number pins power supply cells) number input/output cells. Table 1-18 Quiescent Current Value Input/Output Buffer
Quiescent Current Value 3.60V 2.70V 2.20V 10-9
Unit
10-9
Quiescent current value input output buffer (values Table 1-18) (number output cells number bi-directional cells number (HVDD LVDD) power supply cells)
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Chapter Overview
Calculation example: Find quiescent current value following case. Power supply voltage: cells HVDD LVDD VSS: HVDD: LVDD: H-voltage input cells: H-voltage output cells: H-voltage bi-directional cells: L-voltage input cells: L-voltage output cells: L-voltage bi-directional cells: words bits, pcs. (Synchronous RAM) words bits, pcs. (Synchronous RAM) 1240k gates
Basic Cell type port RAM: Cell Based Logic:
Because this dual power supply system, first find quiescent current system. From Table 1-16, quiescent current value Cell-Based Logic IQBC 7.94 10-7 1240 984.56 10-6 (VDD 85°C) Next, find quiescent current value Basic Cell type RAMs. From Table 1-17, quiescent current value piece Word 9.54 10-6 Word 3.73 10-6 Therefore, quiescent current value Basic Cell type RAMs IQBM (9.54 10-6 (3.73 10-6 38.16 10-6 22.38 10-6 60.54 10-6 (VDD 85°C) Next, find quiescent current value input/output buffers using equation quiescent current values shown above. IQIO 10-9 3.60 10-6 From quiescent current values obtained thus far, find quiescent current value LVDD system. (LVDD) IQBC IQBM IQIO 984.56 10-6 60.54 10-6 10-6 1048.7 10-6 Next, find quiescent current value HVDD system. find quiescent current value HVDD system, simply calculate quiescent current flowing input/output buffers. (HVDD) 10-9 22.40 10-6
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Chapter Overview
From above calculation results, quiescent current values obtained this example (LVDD) 1048.7 10-6 (HVDD) 22.40 10-6
1.3.4
Temperature Characteristics Quiescent Current
quiescent current values temperatures other than 85[°C] approximately calculated using equation shown below. (However, this only applies when [°C]. When 125°C, temperature coefficient calculate equation below. When [°C], please contact nearest Epson office distributor.
IDDS IDDS 85°C) temperature coefficient IDDS 85°C)
(However, 125°C) Calculation example: chip whose quiescent current [µA] when [°C], calculate approximate value quiescent current when [°C] follows: IDDS 50°C) IDDS 85°C) 1060 0.261 164.43 [µA] dual-power supply systems, quiescent currents voltages used constitutes total amount quiescent current. (HIDDS LIDDS)
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Chapter Overview
Embedded Array Development Flow
embedded arrays developed jointly customers Epson. Customers perform work based cell libraries various design materials supplied Epson. This work includes system design, circuit design, pattern design. Before these designs interfaced Epson, customers requested check them based data release checklist included herein. After completion that check, necessary data documentation presented Epson. Customers conduct simulations said designs using software EPITS* available hand, Epson undertakes subsequent work following placement routing. Note EPITS Epson's ASIC library that runs MS-Windows NT4.0 SUN-Solaris platforms.
EPITS currently supports following types software: Verilog-XL (*1) Design Compiler (*2)
Note Verilog-XL registered trademark Cadence Design Systems Corporation, USA. Design Compiler registered trademark Synopsys, Inc., USA.
more information, please contact sales division Epson.
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Chapter Overview
process flow embedded array development process shown below.
Customer Product Plan Functional Spec.
Circuit Design Test Pattern Design Logic Check (Simulation) Standard-cell Development Request Simulation File Delay Time Analysis Timing Check (Simulation) Verification* Automatic Place Rout Delay Time Analysis Simulation List Verification (Post Simulation)
Distributor (Interface)
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Verification
Schematic Assignment Timing Wave Form Marking-diagram
Customer Spec. Sign Make Masks (Test Sample) Fabrication
Functional Evaluation
Overall Evaluation
(Engineering Sample) Fabrication
(TS) Prototype-Evaluation Approval Notification
(TS) Approval Notification
Setup
Delivery Spec. Delivery Spec. Approval
Delivery Spec. Approval Notification
Delivery Spec. Publication
Operations enclosed performed only when requested customers.
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Chapter Estimating Gate Density
Chapter Estimating Gate Density
This chapter describes procedure estimating circuit size after cutting circuits from customer's system, then estimating approximate bulk size. precautions taken when performing this work also described.
Dividing Logic Between Chips
When cutting circuits from customer's system, care must taken with respect following points. Precautions taken Logic size integrated (Gate count) Number pins required (Pin count) Package used Power consumption Generally speaking, circuit size increases, does power consumption circuit number input/output pins circuit size significantly large, circuit divided into multiple chips rather than being integrated into single chip. This helps reduce total cost power consumption circuit.
Estimating Gate Counts Used
circuit size estimated counting total number basic cells each cell counts). "Embedded Array S1X60000 Series Cell Library" lists counts each cell. Refer this manual obtain total counts circuit.
Estimating Number Input/Output Pins
After number gates used cells been estimated, calculate number actually used input/output pins. When performing this calculation, make sure test pins power supply pins Basic Cell type Cell Based-type included counts. estimate number power supply pins, method described Section 9.11, "Pin Layout Simultaneous Operation."
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Chapter Estimating Gate Density
Bulk List
optimum master (Bulk) determined from gate counts used, RAM, functional cells, number input/output pins (including power supply pins), package used. Table lists primary Bulks S1X60000 series. Table List Representative Bulks
Bulk Counts 99,220 171,720 284,394 400,290 595,362 831,572 1,234,820 1,587,754 1,902,960 2,519,604 Counts Basic Cell Arrays direction 1,023 1,213 1,481 1,747 2,129 2,413 2,643 3,043 direction Cell Usage Efficiency layers layers layers
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Chapter Cells
Chapter Cells
Cell Types
Below list functions cell types S1X60000 series. more information, please contact sales division Epson. List cell functions S1X60000 series BUFFER INVERTER DELAY LINE GATE INPUT (2/3/4) INPUT (5/6/8) NAND GATE INPUT (2/3/4) INPUT (5/6/8) GATE INPUT (2/3/4) INPUT (5/6/8) GATE INPUT (2/3/4) INPUT (5/6/8) /INPUT (2/3/4) with Inverted Input (1/2/3)
/INPUT (2/3/4) with Inverted Input (1/2/3)
/INPUT (2/3/4) with Inverted Input (1/2/3)
/INPUT (2/3/4) with Inverted Input (1/2/3)
EXCLUSIVE OR/NOR INPUT (2/3) AND-NOR GATES 2-AND-NOR INPUT (3/4/6/8) 3-AND-NOR INPUT (4/6) AND-OR GATES 2-AND-OR INPUT (3/4/5/6/8) 3-AND-OR INPUT (4/5/6) 4-AND-OR INPUT OR-AND GATES 2-OR-AND INPUT (3/4/5/6/8) 3-OR-AND INPUT (4/5/6) 4-OR-AND INPUT OR-NAND GATES 2-AND-OR INPUT (3/4/8) 3-AND-OR INPUT (4/6)
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Chapter Cells
MULTI-FUNCTION GATES 2-OR 2-AND 4-INPUT GATE 2-AND 2-OR 4-INPUT GATE 2-OR 2-NAND 4-INPUT GATE 2-AND 2-NOR 4-INPUT GATE MAJORITY GATES 3/Inverted TEST Function Special Delay Cell Testing Test Mode Control Circuit CLOCK Tree ROOT BUFFER BUFFER/INVERTER GATED CLOCK 2-INPUT GATE 2-INPUT GATE 2-INPUT NAND GATE 2-INPUT GATE INVERTER SELECTOR/MULTIPLEXER FLIP FLOPS D-FLIP FLOP SET/RESET SYNCHRONOUS Enabled OUTPUT NEGATIVE CLOCK SCAN QUADRUPLE (Reset/Reset Output Only) OCTAL (Reset/Reset Output Only) JK-FLIP FLOP SET/RESET OUTPUT SCAN RS-FLIP FLOP NAND-TYPE/NOR-TYPE LATCHES PRESET/RESET OUTPUT NEGATIVE CLOCK QUADRUPLE (Reset/Reset Output Only) OCTAL with Enable ADDER 1-Bit Full Adder/Power (2/4) 4-Bit Full Adder 4-Bit Full Adder with Fast Carry
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Chapter Cells
COMPARATORS 4-Bit Magnitude Comparator with Enable 8-Bit Magnitude Comparator with Enable COUNTERS 4Bit Binary Counter with Reset, Load Enable 4Bit Binary Counter with Reset Enable 4Bit Binary Up/Down Counter with Load Enable 4Bit Binary Up/Down Counter with Reset, Load Enable DECODERS 3-LINE 8-LINE 2-LINE 4-LINE ENABLE SELECTORS/MULTIPLEXERS 2-LINE 1-LINE 4-LINE 1-LINE ENABLE QUADRUPLE 2-LINE 1-LINE ENABLE NEGATIVE OUTPUT SHIFT REGISTERS 8-Bit SI/PO Shift Register with Reset 8-Bit SI/PO PI/SO Shift Register with Reset, Load Enable 4-Bit SI/PO PI/SO Shift Register with Reset, Load Enable 4-Bit Bi-Directional Universal Shift Register with Reset CELLS LATCH (QUADRUPLE/OCTAL) 1Bit 3-STATE BUFFER -Low ENABLE/High ENABLE Driver
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Chapter Types Input/Output Buffers Their Type)
Chapter Types Input/Output Buffers Their Type)
This chapter describes detail input buffers, output buffers, bi-directional buffers SIX60000 series Type) constructed.
Types Input/Output Buffers
S1X60000 series type) offers wide selection cells choose from depending input interface level, whether Schmitt trigger input needed pull-up/pull-down resistors included, output drive capability, whether noise reduction measures incorporated. Choose input/output buffers that best suit your system considering items described below. Note that there methods using input/output buffers: when operating buffers with single power supply (2.5 operating buffers with dual power supplies (3.3 V/2.5 V/2.0
4.1.1
Selecting input/output buffers
Selecting input buffer Whether necessary interface level CMOS level LVTTL level Whether Schmitt trigger input needed (i.e., whether hysteresis characteristics required) Whether internal pull-up/pull-down resistors needed
Selecting output buffer Necessary amounts output drive currents (IOL/IOH) Whether noise reduction measures needed Whether hold circuit needed
Selecting bi-directional buffer Consider items above select bi-directional buffer.
Input interface level
When HVDD Input level LVTTL level, CMOS level, LVTTL Schmitt, CMOS Schmitt, PCI-3V* Output level CMOS level, PCI-3V* When LVDD Input level CMOS level, CMOS Schmitt Output level CMOS level
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Chapter Types Input/Output Buffers Their Type)
When LVDD Input level CMOS level, CMOS Schmitt Output level CMOS level Note: LVTTL level input cannot used single-power supply systems. interface, please contact sales division Epson.
Output drive capability
Tables 1-7, 1-8, electrical characteristics.
Pull-up/pull-down resistors
Tables 1-7, 1-8, electrical characteristics.
4.1.2
Hold Circuit
ensure that output pins bi-directional pins will enter high-impedance state, S1X60000 Type) series available input/output buffer that comes equipped with hold facility hold data output pins. However, because hold circuit's retention capability suppressed adversely affect ordinary operation cell, output data held circuit valid data. retained data easily change state when data supplied from external circuit. hold circuit's output retention current, refer Table through 1-9.
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Chapter Types Input/Output Buffers Their Type)
Input/Output Buffers Single Power Supply
When input/output buffers used with single power supply, useful power supply voltage only.
4.2.1
Input Buffers
Table Rated Pull-up/Pull-down Resistance Values Each Voltage
Type Pull-up/Pull-down Resistor Type Type
Resistance Value
Unit
Table Input Buffers List
Cell Name*1 XIBC XIBCP# XIBCD# XIBH XIBHP# XIBHD# Notes Input Level CMOS CMOS CMOS CMOS Schmitt CMOS Schmitt CMOS Schmitt Whether Pull-up/Pull-down Resistors Included None Pull-up resistor included Pull-down resistor included None Pull-up resistor included Pull-down resistor included
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 4-1).
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Chapter Types Input/Output Buffers Their Type)
4.2.2
Output Buffers
Tables list output buffers. Table Rated Values Each Voltage
Type Output Current Type Type Type Type Type Notes -0.1/0.1 -1/1 -3/3 -6/6 -9/9 (VDD (VDD (VDD (VDD IOH*1/IOL*2 -0.05/0.05 -0.3/0.3 -1/1 -2/2 -3/3 Unit
Table Output Buffers List
Function IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1,
Normal output
XOB#T
Normal output high speed Normal output noise
XOB3AT XOB3BT
3-state output
XTB#T
3-state output high speed 3-state output noise
XTB3AT XTB3BT
3-state output (Bus hold circuit)
XTB$HT
3-state output high speed (Bus hold circuit) 3-state output noise (Bus hold circuit) Notes
XTB3AHT XTB3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 4-3). addition configurations shown Table 4-4, output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Chapter Types Input/Output Buffers Their Type)
Table Rated Values Each Voltage
Type Output Current Type Type Type Note (VDD (VDD IOL*1 Unit
Table channel Open drain Output Buffers List
Function Normal output Notes Type Type Type Cell Name*1, XOD#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 4-5). addition configurations Table 4-6, channel open drain output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Chapter Types Input/Output Buffers Their Type)
4.2.3
Bi-directional Buffers
Tables list bi-directional buffers. Table Bi-directional Buffers List
Input Level Function IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1,
Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise
XBC#T
XBC3AT XBC3BT
Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise
XBH#T
XBH3AT XBH3BT
Bi-directional output (Bus hold circuit) CMOS Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XBC$HT
XBC3AHT XBC3BHT
Bi-directional output (Bus hold circuit) CMOS Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit) Notes
XBH$HT
XBH3AHT XBH3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 4-3). addition configurations shown Table 4-7, bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Chapter Types Input/Output Buffers Their Type)
Table channel Open drain Bi-directional Buffers List
Input Level CMOS Bi-directional output Function Type Type Type Type Type Type Cell Name*1, XBDC#T
CMOS Schmitt Notes
Bi-directional output
XBDH#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 4-5). addition configurations shown Table 4-8, channel open drain bi-directional buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Chapter Types Input/Output Buffers Their Type)
4.2.4
4.2.4.1
Fail-Safe Cells
Overview
S1X60000 series type) Fail-Safe cells allow signals above power supply voltage interfaced, even while power supplied. Furthermore, leakage current flows those cells, despite fact that signals interfaced while power off. Therefore, they provide greater freedom design than ever before. dual-power supply systems, these used LVDD system cells.)
4.2.4.2
Features
Fail-Safe cells positioned desired customers. Even when input signals above power supply voltage applied while power supplied, input leakage current flows. (For input buffers bi-directional buffers with pull-up resistors, however, small input leakage current approximately flow their circuit configuration.) Even when input signals applied from outside while power off, input leakage current flows. Fail-Safe cells with different input levels, CMOS level CMOS Schmitt level, available. Because Fail-Safe cells completely CMOS structured, power consumption suppressed minimum.
4.2.4.3
Usage Precautions
About input cells input buffers without resistors with pull-down resistors, ordinary input buffers used directly Fail-Safe cells. input buffers with pull-up resistors needed, always sure Fail-Safe cells (however, small input leakage current approximately flow their circuit configuration).
About output cells Provided that output buffers placed High-Z state bi-directional buffers placed input mode, input leakage current flow even when input signals above power supply voltage applied while power supplied. signals above power supply voltage applied while bi-directional buffers placed output mode, input leakage current flows ordinary input/output buffers. same applies when pull-up resistors above power supply voltage exist outside chip. High logic level above power supply voltage needed, open drain type input/output buffers, with pull-up resistors added external chip order pull-up logic level High.)
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Chapter Types Input/Output Buffers Their Type)
Although Fail-Safe cells receive high voltage signals above LSI's operating voltage, aware that signal voltages applied Fail-Safe cells must never exceed their rated maximum voltage.
4.2.4.4
List Cells
Table Fail-Safe Input Buffers List
Cell Name*1, XIBBP# XIBGP# Notes
Input Level CMOS CMOS Schmitt
Whether Pull-up Resistors Included Pull-up resistor included Pull-up resistor included
denotes with pull-up resistance values corresponding Type Type respectively (for details, refer Table 4-1).
Table 4-10 Fail-Safe Output Buffers List
Function 3-state output 3-state output high speed 3-state output noise Notes IOH/IOL Type Type Type Type Cell Name*1, XTBF#T XTBF3AT XTBF3BT
denotes with IOH/IOL values corresponding Type Type respectively (for details, refer Table 4-3). addition configurations shown Table 4-10, Fail-Safe output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
Table 4-11 Fail-Safe Bi-directional Buffers List
Input Level Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise Notes Function IOH/IOL Type Type Type Type Type Type Type Type Cell Name*1, XBB#T XBB3AT XBB3BT XBG#T XBG3AT XBG3BT
denotes with IOH/IOL values corresponding Type Type respectively (for details, refer Table 4-3). addition configurations shown Table 4-11, Fail-Safe bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Chapter Types Input/Output Buffers Their Type)
4.2.5
4.2.5.1
Gated Cells
Overview
S1X60000 series type) Gated cell first product that allows inputs pins placed floating, High-Z, state without pull-up pull-down circuits. Moreover, power supply high voltage side (HVDD) dual power supply design off. There types cells choose from depending whether High level control signal level control signal shuts power supply. Therefore, customers choose desired type cell according their circuit design.
4.2.5.2
Features
Gated cells positioned desired customers. There limitations number cells used locations which they placed. result, freedom design increased. power supply high voltage side (HVDD) dual power supply design off. However, because special measures must taken this off, please contact sales division Epson. Inputs placed High-Z state without pull-up pull-down circuits. circuit structure, input level Gated cell dual power supply system HVDD system LVDD system CMOS level. There types cells choose from depending whether High level control signal level control signal shuts power supply. Because Gated cells completely CMOS structured, power consumption suppressed minimum.
4.2.5.3
Usage Precautions
place inputs High-Z state through Gated cells, inputs pins must shut using Gated cell control signals before they enter High-Z state. inputs placed High-Z state without performing this control, large current flow into cell ordinary cells, causing break down. Conversely, same problem occur when using Gated cell control connect inputs High-Z state) pins. such case, logic level latched into device's internal circuit cannot guaranteed. When power supply high voltage side (HVDD) using Gated cell, same processing described required. This processing must performed; otherwise, logic level latched device's internal circuit cannot guaranteed. Moreover, because special measures must taken cut-off, please contact sales division Epson.
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Chapter Types Input/Output Buffers Their Type)
4.2.5.4
List Cells
Table 4-12 Gated Input Buffers List
Cell Name*1 XIBA XIBAP# XIBAD# XIBO XIBOP# XIBOD# Notes
Input Level CMOS (AND Type)
Whether Pull-up/Pull-down Resistors Included None Pull-up resistor included Pull-down resistor included None Pull-up resistor included Pull-down resistor included
CMOS Type)
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 4-1).
Table 4-13 Gated Bi-directional Buffers List
Input Level Function Bi-directional output Type Bi-directional output high speed CMOS Bi-directional output noise Bi-directional output Type Bi-directional output high speed Bi-directional output noise Notes IOH/IOL Type Type Type Type Type Type Type Type Type Type Cell Name*1, XBA#T XBA3AT XBA3BT XBO#T XBO3AT XBO3BT
denotes with IOH/IOL values corresponding Type Type Type respectively (for details, refer Table 4-3). addition configurations shown Table 4-13, Gated bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Chapter Types Input/Output Buffers Their Type)
Dual Power Supply Input/Output Buffers
your system uses dual power supplies, input/output buffers designed exclusively operation with dual power supplies. this case, careful input/output buffers designed operation with single power supply.) Moreover, input/output buffers single power supply system those dual power supply system cannot used combination. However, test buffer (XITST1) used both single power supply dual power supply systems. (Combined with type input/output buffers also allowed.) HVDD input/output buffers HVDD input/output buffers available several types. These include input buffers that accept input signals, output buffers that output amplitude signals, bi-directional buffers that accept input signals output amplitude signals. LVDD input/output buffers LVDD input/output buffers available several types. These include input buffers that accept input signals, output buffers that output amplitude signals, bi-directional buffers that accept input signals output amplitude signals. LVDD bi-directional buffers, apply voltages above LVDD. This fact that, HVDD signals supplied those buffers, excessive current flows their internal protective diode, causing their quality degrade such case, Fail-Safe cells described Section 4.3.4, "Fail-Safe Cells").
4.3.1
Input Buffers
HVDD input buffers input buffers configured using only input cells. HVDD input buffers consist first input stage configured with HVDD input circuit next stage configured with LVDD circuit, that HVDD signals converted into LVDD signals before being into cell. Table 4-15 lists HVDD input buffers. Table 4-14 Rated Pull-up/Pull-down Resistance Values Each Voltage
Type Pull-up/Pull-down Resistor Type Type
Resistance Value (HVDD
Unit
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Table 4-15 HVDD Input Buffers List
Cell Name*1 XHIBC XHIBCP# XHIBCD# XHIBT XHIBTP# XHIBTD# XHIBH XHIBHP# XHIBHD# XHIBS XHIBSP# XHIBSD# XHIBPB XHIBPBP# XHIBPBD# Notes Input Level CMOS CMOS CMOS LVTTL LVTTL LVTTL CMOS Schmitt CMOS Schmitt CMOS Schmitt LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt PCI-3V PCI-3V PCI-3V Whether Pull-up/Pull-down Resistors Included None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 4-14).
LVDD input buffers input buffers configured using only input cells. Table 4-17 lists LVDD input buffers. Table 4-16 Rated Pull-up/Pull-down Resistance Values Each Voltage
Type Pull-up/Pull-down Resistor Type Type
Resistance Value LVDD LVDD
Unit
Table 4-17 LVDD Input Buffers List
Cell Name*1 XLIBC XLIBCP# XLIBCD# XLIBH XLIBHP# XLIBHD# Notes Input Level CMOS CMOS CMOS CMOS Schmitt CMOS Schmitt CMOS Schmitt Whether Pull-up/Pull-down Resistors Included None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 4-16).
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4.3.2
Output Buffers
HVDD output buffers Tables 4-19 4-21 list HVDD output buffers. Table 4-18 Rated Values Each Voltage
Type Output Current IOH*1/IOL*2 (HVDD 3.3V) -0.1/0.1 -1/1 -3/3 -6/6 -12/12 HVDD Unit
Type Type Type Type Type Note
Table 4-19 HVDD Output Buffers List
Function IOL/IOH Type Type Type Type Type Type Type PCI-3V Type Type Type Type Type Type Type PCI-3V Type Type Type Type Type Type Cell Name*1,
Normal output
XHOB#T
Normal output high speed Normal output noise Normal output
XHOB3AT XHOB3BT XHOBPBT
3-state output
XHTB#T
3-state output high speed 3-state output noise 3-state output
XHTB3AT XHTB3BT XHTBPBT
3-state output (Bus hold circuit)
XHTB$HT
3-state output high speed (Bus hold circuit) 3-state output noise (Bus hold circuit) Notes
XHTB3AHT XHTB3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 4-18). addition configurations shown Table 4-19, output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 4-20 Rated Values Each Voltage
Type Output Current Type Type Type Note IOL*1 (HVDD 3.3V) Unit
Table 4-21 HVDD channel Open drain Output Buffers List
Function Normal output Notes Type Type Type Cell Name*1, XHOD#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 4-20). addition configurations shown Table 4-21, HVDD channel open drain output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Chapter Types Input/Output Buffers Their Type)
LVDD output buffers Tables 4-23 4-25 list LVDD output buffers. Table 4-22 Rated Values Each Voltage
Type Output Current IOH*1/IOL*2 LVDD LVDD -0.05/0.05 -0.3/0.3 -1/1 -2/2 -3/3 Unit
Type Type Type Type Type Notes
-0.1/0.1 -1/1 -3/3 -6/6 -9/9
LVDD (LVDD LVDD (LVDD (LVDD (LVDD
Table 4-23 LVDD Output Buffers List
Function IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1,
Normal output
XLOB#T
Normal output high speed Normal output noise
XLOB3AT XLOB3BT
3-state output
XLTB#T
3-state output high speed 3-state output noise
XLTB3AT XLTB3BT
3-state output (Bus hold circuit)
XLTB$HT
3-state output high speed (Bus hold circuit) 3-state output noise (Bus hold circuit) Notes
XLTB3AHT XLTB3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 4-22). addition configurations shown Table 4-23, output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 4-24 Rated Values Each Voltage
Type Output Current LVDD Type Type Type Note (LVDD (LVDD IOL*1 LVDD Unit
Table 4-25 LVDD channel Open drain Output Buffers List
Function Normal output Notes Type Type Type Cell Name*1, XLOD#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 4-24). addition configurations shown Table 4-25, channel open drain output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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4.3.3
Bi-directional Buffers
HVDD bi-directional buffers Tables 4-26 4-27 list HVDD bi-directional buffers. Table 4-26 HVDD Bi-directional Buffers List (1/2)
Input Level
Function
IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type PCI-3V Type Type Type Type Type Type Type Type Type Type Type Type Type Type
Cell Name*1,
Bi-directional output LVTTL Bi-directional output high speed Bi-directional output noise
XHBT#T
XHBT3AT XHBT3BT
Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise Bi-directional output
XHBC#T
XHBC3AT XHBC3BT XHBPBT
Bi-directional LVTTL Schmitt Bi-directional output high speed Bi-directional output noise
XHBS#T
XHBS3AT XHBS3BT
Bi-directional CMOS Schmitt Bi-directional output high speed Bi-directional output noise Notes
XHBH#T
XHBH3AT XHBH3BT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 4-18). addition configurations shown Table 4-26, HVDD bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 4-26 List HVDD Bi-directional Buffers List (2/2)
Input Level Function IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1,
Bi-directional output (Bus hold circuit) LVTTL Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XHBT#HT
XHBT3AHT XHBT3BHT
Bi-directional output (Bus hold circuit) CMOS Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XHBC#HT
XHBC3AHT XHBC3BHT
Bi-directional output (Bus hold circuit) LVTTL Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XHBS#HT
XHBS3AHT XHBS3BHT
Bi-directional output (Bus hold circuit) CMOS Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit) Notes
XHBH#HT
XHBH3AHT XHBH3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 4-18). addition configurations shown Table 4-26, HVDD bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 4-27 HVDD channel Open drain Bi-directional Buffers List
Input Level LVTTL Bi-directional output Function Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1, XHBDT#T
CMOS
Bi-directional output
XHBDC#T
LVTTL Schmitt CMOS Schmitt Notes
Bi-directional output
XHBDS#T
Bi-directional output
XHBDH#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 4-20). addition configurations shown Table 4-27, HVDD channel open drain bi-directional buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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LVDD bi-directional buffers Tables 4-28 4-29 list LVDD bi-directional buffers. Table 4-28 LVDD Bi-directional Buffers List
Input Level
Function
IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type
Cell Name*1,
Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise
XLBC#T
XLBC3AT XLBC3BT
Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise
XLBH#T
XLBH3AT XLBH3BT
Bi-directional output (Bus hold circuit) CMOS Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XLBC$HT
XLBC3AHT XLBC3BHT
Bi-directional output (Bus hold circuit) CMOS Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit) Notes
XLBH$HT
XLBH3AHT XLBH3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 4-22). addition configurations shown Table 4-28, bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 4-29 LVDD channel Open drain Bi-directional Buffers List
Input Level CMOS Bi-directional output Function Type Type Type Type Type Type Cell Name*1, XLBDC#T
CMOS Schmitt Notes
Bi-directional output
XLBDH#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 4-24). addition configurations shown Table 4-29, channel open drain bi-directional buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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4.3.4
4.3.4.1
Fail-Safe Cells
Overview
dual power supply Fail-Safe cells outlined Section 4.2.4.1, "Overview" (the Fail-Safe cells used dual power supply specification LVDD cells).
4.3.4.2
Features
features dual power supply Fail-Safe cells, refer Section 4.2.4.2, "Features."
4.3.4.3
Usage Precautions
precautions taken when dual power supply Fail-Safe cells used, refer Section 4.2.4.3, "Usage Precautions."
4.3.4.4
List Cells
Table 4-30 Fail-Safe Input Buffers List
Cell Name*1 XLIBBP# XLIBGP# Notes
Input Level CMOS CMOS Schmitt
Whether Pull-up Resistors Included Pull-up Resistors Pull-up Resistors
denotes with pull-up resistance values corresponding Type Type respectively (for details, refer Table 4-16).
Table 4-31 Fail-Safe Output Buffers List
Function 3-state output 3-state output high speed 3-state output noise Notes IOH/IOL Type Type Type Type Cell Name*1, XLTBF#T XLTBF3AT XLTBF3BT
denotes with IOH/IOL values corresponding Type Type respectively (for details, refer Table 4-22). addition configurations shown Table 4-31, Fail-Safe output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 4-32 Fail-Safe Bi-directional Buffers List
Input Level Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise Notes Function IOH/IOL Type Type Type Type Type Type Type Type Cell Name*1, XLBB#T XLBB3AT XLBB3BT XLBG#T XLBG3AT XLBG3BT
denotes with IOH/IOL values corresponding Type Type respectively (for details, refer Table 4-22). addition configurations shown Table 4-32, Fail-Safe bi-directional buffers configures with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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4.3.5
4.3.5.1
Gated Cells
Overview
dual power supply Gated cells outlined Section 4.2.5.1, "Overview." (The Gated cells dual power supply specification HVDD cells.)
4.3.5.2
Features
features dual power supply Gated cells, refer Section 4.2.5.2, "Features."
4.3.5.3
Usage Precautions
precautions taken when dual power supply Gated cells used, refer Section 4.2.5.3, "Usage Precautions."
4.3.5.4
List Cells
Table 4-33 Gated Cell Input Buffers List
Cell Name*1, XHIBA XHIBAP# XHIBAD# XHIBO XHIBOP# XHIBOD# Notes
Input Level CMOS (AND Type)
Whether Pull-up/Pull-down Resistors None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor
CMOS Type)
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 4-14).
Table 4-34 Gated Cell Bi-directional Buffers List
Input Level Function Bi-directional output Type Bi-directional output high speed CMOS Bi-directional output noise Bi-directional output Type Bi-directional output high speed Bi-directional output noise Notes IOH/IOL Type Type Type Type Type Type Type Type Type Type Cell Name*1, XHBA#T XHBA3AT XHBA3BT XHBO#T XHBO3AT XHBO3BT
denotes with IOH/IOL values corresponding Type Type Type respectively (for details, refer Table 4-18). addition configurations shown Table 4-34, Gated bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Dual Power Supplies Guidelines
S1X60000 series allows each input/output buffer interfaced with signals desired, using dual power supply system. internal cell area operates using single power supply.
4.4.1
Method Adapting Dual Power Supplies
S1X60000 series allows input/output buffers interfaced with signals voltages that differ from internal operating voltage. There methods interfacing with different power supply voltages. single power supply single power supply system, possible apply input signals voltages higher than power supply voltage, using channel open drain type buffers Fail-Safe cells. However, high voltage signals above power supply voltage cannot output. This problem solved through combined channel open drain type buffers external pull-up resistors. dual power supplies using input buffers designed exclusively operation with dual power supplies, possible apply input signals voltages higher than internal operating voltage. Similarly, high voltage signals above internal operating voltage output using dual power supply output buffers.
4.4.2
Power Supplies Dual Power Operation
your circuit operated using different power supplies, power supply cells: HVDD LVDD. Specifically, HVDD used HVDD input/output buffers, LVDD used LVDD input/output buffers internal cells. power supply voltages must always satisfy equation below. HVDD LVDD HVDD LVDD, operation internal circuit cannot guaranteed. operating conditions specified below recommended. HVDD LVDD HVDD LVDD
4.4.3
Turning On/Off Dual Power Supplies
chips designed dual power supply specifications, make sure power turned order specified below.
When turning LVDD (internal) HVDD (I/O section) input signals applied When turning off: Input signals HVDD (I/O section) LVDD (internal)
Note Avoid keeping only HVDD turned (for more) while LVDD turned off, degrade chip's reliability. Note When turning HVDD back after off, always sure initialize circuit following power This necessary ensure internal circuit state event power supply noise like.
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Chapter Types Input/Output Buffers Their Type)
This chapter describes detail input buffers, output buffers, bi-directional buffers SIX6000 series Type) constructed.
Types Input/Output Buffers
S1X60000 series type) offers wide selection cells choose from depending input interface level, whether Schmitt trigger input needed pull-up/pull-down resistors included, output drive capability, whether noise reduction measures incorporated. Choose input/output buffers that best suit your system considering items described below. Note that input/output buffers this type only used with dual power supplies (3.3 V/2.5 V/2.0
5.1.1
Selecting input/output buffers
Selecting input buffer Whether interfacing needed Whether necessary interface level CMOS level LVTTL level Whether Schmitt trigger input needed (i.e., whether hysteresis characteristics required)
Whether internal pull-up/pull-down resistors needed Selecting output buffer Whether pull-up resisters external chip needed Necessary amounts output drive currents (IOL/IOH) Whether noise reduction measures needed
Whether hold circuit needed Selecting bi-directional buffer Consider items above select bi-directional buffer.
Input interface level
When HVDD Input level LVTTL level, CMOS level, LVTTL Schmitt, CMOS Schmitt, PCI-3V* Output level CMOS level, PCI-3V*
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When LVDD Input level CMOS level, CMOS Schmitt Output level CMOS level When LVDD Input level CMOS level, CMOS Schmitt Output level CMOS level Note: interface, please contact sales division Epson.
Output drive capability
Tables 1-13, 1-14, 1-15 electrical characteristics.
Pull-up/pull-down resistors
Tables 1-13, 1-14, 1-15 electrical characteristics.
5.1.2
Hold Circuit
ensure that output pins bi-directional pins will enter high-impedance state, S1X60000 series Type) available input/output buffer that comes equipped with hold facility hold data output pins. However, because hold circuit's retention capability suppressed adversely affect ordinary operation cell, output data held circuit valid data. retained data easily change state when data supplied from external circuit. hold circuit's output retention current, refer Table 1-13 through 1-15.
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Dual Power Supply Input/Output Buffers
input/output buffers S1X60000 series type) only used dual power supply system. (These buffers cannot used combination with type input/output buffers.) HVDD input/output buffers HVDD input/output buffers available several types. These include input buffers that accept input signals, output buffers that output amplitude signals, bi-directional buffers that accept input signals output amplitude signals. Moreover, tolerant Fail-Safe cells available, which allow amplitude signals applied. LVDD input/output buffers LVDD input/output buffers available several types. These include input buffers that accept input signals, output buffers that output amplitude signals, bi-directional buffers that accept input signals output amplitude signals. LVDD bi-directional buffers, apply voltages above LVDD. This fact that, HVDD signals supplied those buffers, excessive current flows their internal protective diode, causing their quality degrade such case, Fail-Safe cells described Section 5.2.4, "Fail-Safe Cells").
5.2.1
Input Buffers
HVDD input buffers input buffers configured using only input cells. HVDD input buffers consist first input stage configured with HVDD input circuit next stage configured with LVDD circuit, that HVDD signals converted into LVDD signals before being into cell (internal cell area). Table lists HVDD input buffers. Table Rated Pull-up/Pull-down-Resistance Values Each Voltage
Type Pull-up/Pull-down Resistor Type Type
Resistance Value (HVDD
Unit
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Table HVDD Input Buffers List
Cell Name*1 XFHIBC XFHIBCP# XFHIBCD# XFHIBT XFHIBTP# XFHIBTD# XFHIBH XFHIBHP# XFHIBHD# XFHIBS XFHIBSP# XFHIBSD# XFHIBPB XFHIBPBP# XFHIBPBD# Notes Input Level CMOS CMOS CMOS LVTTL LVTTL LVTTL CMOS Schmitt CMOS Schmitt CMOS Schmitt LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt PCI-3V PCI-3V PCI-3V Whether Pull-up/Pull-down Resistors Included None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 5-1).
LVDD input buffers input buffers configured using only input cells. Table lists LVDD input buffers. Table Rated Pull-up/Pull-down Resistance Values Each Voltage
Type Pull-up/Pull-down Resistor Type Type
Resistance Value LVDD LVDD
Unit
Table LVDD Input Buffers List
Cell Name*1 XFLIBC XFLIBCP# XFLIBCD# XFLIBH XFLIBHP# XFLIBHD# Notes Input Level CMOS CMOS CMOS CMOS Schmitt CMOS Schmitt CMOS Schmitt Whether Pull-up/Pull-down Resistors Included None Pull-up resistor Pull-down resistor None Pull-up resistor Pull-down resistor
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 5-3).
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5.2.2
Output Buffers
HVDD output buffers Tables list HVDD output buffers. Table Rated Values Each Voltage
Type Output Current IOH*1/IOL*2 (HVDD 3.3V) -0.1/0.1 -1/1 -3/3 -6/6 -12/12 HVDD Unit
Type Type Type Type Type Note
Table HVDD Output Buffers List
Function IOL/IOH Type Type Type Type Type Type Type PCI-3V Type Type Type Type Type Type Type PCI-3V Type Type Type Type Type Type Cell Name*1,
Normal output
XFHOB#T
Normal output high speed Normal output noise Normal output
XFHOB3AT XFHOB3BT XFHOBPBT
3-state output
XFHTB#T
3-state output high speed 3-state output noise 3-state output
XFHTB3AT XFHTB3BT XFHTBPBT
3-state output (Bus hold circuit)
XFHTB$HT
3-state output high speed (Bus hold circuit) 3-state output noise (Bus hold circuit) Notes
XFHTB3AHT XFHTB3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 5-5). addition configurations shown Table 5-6, HVDD output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table Rated Values Each Voltage
Type Output Current Type Type Type Note IOL*1 (HVDD 3.3V) Unit
Table HVDD channel Open drain Output Buffers List
Function Normal output Notes Type Type Type Cell Name*1, XFHOD#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 5-7). addition configurations shown Table 5-8, HVDD channel open drain output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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LVDD output buffers Tables 5-10 5-12 list LVDD output buffers. Table Rated Values Each Voltage
Type Output Current IOH*1/IOL*2 LVDD LVDD -0.05/0.05 -0.3/0.3 -1/1 -2/2 -3/3 Unit
Type Type Type Type Type Notes
-0.1/0.1 -1/1 -3/3 -6/6 -9/9
LVDD (LVDD LVDD (LVDD (LVDD (LVDD
Table 5-10 LVDD Output Buffers List
Function IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1,
Normal output
XFLOB#T
Normal output high speed Normal output noise
XFLOB3AT XFLOB3BT
3-state output
XFLTB#T
3-state output high speed 3-state output noise
XFLTB3AT XFLTB3BT
3-state output (Bus hold circuit)
XFLTB$HT
3-state output high speed (Bus hold circuit) 3-state output noise (Bus hold circuit) Notes
XFLTB3AHT XFLTB3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 5-9). addition configurations shown Table 5-10, output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 5-11 Rated Values Each Voltage
Type Output Current LVDD Type Type Type Note (LVDD (LVDD IOL*1 LVDD Unit
Table 5-12 LVDD channel Open drain Output Buffers List
Function Normal output Notes Type Type Type Cell Name*1, XFLOD#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 5-11). addition configurations shown Table 5-12, LVDD channel open drain output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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5.2.3
Bi-directional Buffers
HVDD bi-directional buffers Tables 5-13 5-14 list HVDD bi-directional buffers. Table 5-13 HVDD Bi-directional Buffers List (1/2)
Input Level
Function
IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type PCI-3V Type Type Type Type Type Type Type Type Type Type Type Type Type Type
Cell Name*1,
Bi-directional output LVTTL Bi-directional output high speed Bi-directional output noise
XFHBT#T
XFHBT3AT XFHBT3BT
Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise Bi-directional output
XFHBC#T
XFHBC3AT XFHBC3BT XFHBPBT
Bi-directional LVTTL Schmitt Bi-directional output high speed Bi-directional output noise
XFHBS#T
XFHBS3AT XFHBS3BT
Bi-directional CMOS Schmitt Bi-directional output high speed Bi-directional output noise Notes
XFHBH#T
XFHBH3AT XFHBH3BT
denotes with IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 5-5). addition configurations shown Table 5-13, HVDD bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 5-13 List HVDD Bi-directional Buffers List (2/2)
Input Level Function IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1,
Bi-directional output (Bus hold circuit) LVTTL Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XFHBT#HT
XFHBT3AHT XFHBT3BHT
Bi-directional output (Bus hold circuit) CMOS Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XFHBC#HT
XFHBC3AHT XFHBC3BHT
Bi-directional output (Bus hold circuit) LVTTL Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XFHBS#HT
XFHBS3AHT XFHBS3BHT
Bi-directional output (Bus hold circuit) CMOS Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit) Notes
XFHBH#HT
XFHBH3AHT XFHBH3BHT
denotes with IOH/IOL values corresponding Type Type Type Type respectively (for details, refer Table 5-5). addition configurations shown Table 5-13, HVDD bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 5-14 HVDD channel Open drain Bi-directional Buffers List
Input Level LVTTL Bi-directional output Function Type Type Type Type Type Type Type Type Type Type Type Type Cell Name*1, XFHBDT#T
CMOS
Bi-directional output
XFHBDC#T
LVTTL Schmitt CMOS Schmitt Notes
Bi-directional output
XFHBDS#T
Bi-directional output
XFHBDH#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 5-7). addition configurations shown Table 5-14, HVDD channel open drain bi-directional buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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LVDD bi-directional buffers Tables 5-15 5-16 list LVDD bi-directional buffers. Table 5-15 LVDD Bi-directional Buffers List
Input Level
Function
IOH/IOL Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type Type
Cell Name*1,
Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise
XFLBC#T
XFLBC3AT XFLBC3BT
Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise
XFLBH#T
XFLBH3AT XFLBH3BT
Bi-directional output (Bus hold circuit) CMOS Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit)
XFLBC$HT
XFLBC3AHT XFLBC3BHT
Bi-directional output (Bus hold circuit) CMOS Schmitt Bi-directional output high speed (Bus hold circuit) Bi-directional output noise (Bus hold circuit) Notes
XFLBH$HT
XFLBH3AHT XFLBH3BHT
Note that denotes denotes with their IOH/IOL values corresponding Type Type Type Type Type respectively (for details, refer Table 5-9). addition configurations shown Table 5-15, LVDD bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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Table 5-16 LVDD channel Open drain Bi-directional Buffers List
Input Level CMOS Bi-directional output Function Type Type Type Type Type Type Cell Name*1, XFLBDC#T
CMOS Schmitt Notes
Bi-directional output
XFLBDH#T
denotes with values corresponding Type Type Type respectively (for details, refer Table 5-11). addition configurations shown Table 5-16, LVDD channel open drain bi-directional buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
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5.2.4
5.2.4.1
Fail-Safe Cells
Overview
S1X60000 series Type) Fail-Safe cells allow signals above power supply voltage interfaced, even while power supplied. Furthermore, leakage current flows those cells, despite fact that signals interfaced while power off. Therefore, they provide greater freedom design than ever before. (These cells used LVDD system cells.)
5.2.4.2
Features
Fail-Safe cells positioned desired customers. There limitations number cells that used locations which they placed. Even when input signals above power supply voltage applied while power supplied, input leakage current flows. (For input buffers bi-directional buffers with pull-up resistors, however, small input leakage current approximately flow their circuit configuration.) Even when input signals applied from outside while power off, input leakage current flows. Fail-Safe cells with different input levels, CMOS level CMOS Schmitt level, available. Because Fail-Safe cells completely CMOS structured, power consumption suppressed minimum.
5.2.4.3
Usage Precautions
About input cells input buffers without resistors with pull-down resistors, ordinary input buffers used directly Fail-Safe cells. input buffers with pull-up resistors needed, always sure Fail-Safe cells (however, small input leakage current approximately flow their circuit configuration).
About output cells Provided that output buffers placed High-Z state bi-directional buffers placed input mode, input leakage current flow even when input signals above power supply voltage applied while power supplied. signals above power supply voltage applied while bi-directional buffers placed output mode, input leakage current flows ordinary input/output buffers. same applies when pull-up resistors above power supply voltage exist outside chip. High logic level above power supply voltage needed, open drain type input/output buffers, with pull-up resistors added external chip order pull logic level High.)
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Although Fail-Safe cells receive high voltage signals above LSI's operating voltage, aware that signal voltages applied Fail-Safe cells must never exceed their rated maximum voltage.
5.2.4.4
List Cells
Table 5-17 Fail-Safe Input Buffers List
Cell Name*1 XFLIBBP# XFLIBGP# Notes
Input Level CMOS CMOS Schmitt
Whether Pull-up Resistors Included Pull-up resistor included Pull-up resistor included
denotes with pull-up resistance values corresponding Type Type respectively (for details, refer Table 5-3).
Table 5-18 Fail-Safe Output Buffers List
Function 3-state output 3-state output high speed 3-state output noise Notes IOH/IOL Type Type Type Type Cell Name*1, XFLTBF#T XFLTBF3AT XFLTBF3BT
denotes with IOH/IOL values corresponding Type Type Type Type respectively (for details, refer Table 5-9). addition configurations shown Table 5-18, Fail-Safe output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
Table 5-19 Fail-Safe Bi-directional Buffers List
Input Level Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise Notes Function IOH/IOL Type Type Type Type Type Type Type Type Cell Name*1, XFLBB#T XFLBB3AT XFLBB3BT XFLBG#T XFLBG3AT XFLBG3BT
denotes with IOH/IOL values corresponding Type Type respectively (for details, refer Table 5-9). addition configurations shown Table 5-19, Fail-Safe bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
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EPSON
Chapter Types Input/Output Buffers Their Type)
5.2.5
5.2.5.1
Gated Cells
Overview
S1X60000 series Type) Gated cell first product that allows inputs pins placed floating, High-Z, state without pull-up pull-down circuits. Moreover, power supply high voltage side (HVDD) off. There types cells choose from depending whether High-level control signal Low-level control signal shuts power supply. Therefore, customers choose desired type cell according their circuit design. (These cells used HVDD system cells.)
5.2.5.2
Features
Gated cells positioned desired customers. There limitations number cells used locations which they placed. result, freedom design increased. also possible power supply high- voltage side (HVDD). However, because special measures must taken cut-off, please contact sales division Epson. Inputs placed High-Z state without pull-up pull-down circuits. circuit structure, input level Gated cell HVDD system LVDD system CMOS level. There types cells choose from depending whether High-level control signal Low-level control signal shuts power supply. Because Gated cells completely CMOS structured, power consumption suppressed minimum.
5.2.5.3
Usage Precautions
place inputs High-Z state through Gated cells, inputs pins must shut using Gated cell control signals before they enter High-Z state. inputs placed High-Z state without performing this control, large current flow into cell ordinary cells, causing break down. Conversely, same problem occur when using Gated cell control connect inputs High-Z state) pins. such case, logic level latched into device's internal circuit cannot guaranteed. When power supply high voltage side (HVDD) using Gated cell, same processing described required. This processing must performed; otherwise, logic level latched device's internal circuit cannot guaranteed. Moreover, because special measures must taken off, please contact sales division Epson.
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Types Input/Output Buffers Their Type)
5.2.5.4
List Cells
Table 5-20 Gated Input Buffers List
Cell Name*1, XFHIBA XFHIBAP# XFHIBAD# XFHIBO XFHIBOP# XFHIBOD# Notes
Input Level CMOS (AND Type)
Whether Pull-up/Pull-down Resistors Included None Pull-up resistor Pull-up included None Pull-up resistor Pull-up included
CMOS Type)
denotes with pull-up/pull-down resistance values corresponding Type Type respectively (for details, refer Table 5-1).
Table 5-21 Gated Bi-directional Buffers List
Input Level Function Bi-directional output Type Bi-directional output high speed CMOS Bi-directional output noise Bi-directional output Type Bi-directional output high speed Bi-directional output noise Notes IOH/IOL Type Type Type Type Type Type Type Type Type Type Cell Name*1, XFHBA#T XFHBA3AT XFHBA3BT XFHBO#T XFHBO3AT XFHBO3BT
denotes with IOH/IOL values corresponding Type Type Type respectively (for details, refer Table 5-5). addition configurations shown Table 5-21, Gated bi-directional buffers configured with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
EMBEDDED ARRAY S1X60000 SERIES
EPSON
Chapter Types Input/Output Buffers Their Type)
5.2.6
5.2.6.1
Tolerant Fail-Safe Cells
Overview
tolerant Fail-Safe cells S1X60000 series type) allow interfacing without requiring dedicated power supply. Moreover, input signals received even while HVDD power supply off, allowing greater freedom design than ever. (However, LVDD power supply must have voltage applied it.)
5.2.6.2
Features
There restrictions number cells used their placement, thus allowing customers place cells required. Without having install dedicated power supply, signals from external sources interfaced. input leakage current flows even when signals applied from external sources while cell output mode High level signal output. Input leakage current does occur even input buffers that include pull-up resistors. input leakage current occurs even when input signals applied while HVDD power supply off. (However, LVDD power supply must have voltage applied it.) types cells (one CMOS level CMOS Schmitt level) have been released. Because Fail-Safe cells completely CMOS-structured, power consumption minimized.
5.2.6.3
Usage Precautions
apply input signals while HVDD power supply off, always make sure LVDD power supply voltage applied This necessary circuit structure cell. About input cells When input signals applied while HVDD power supply off, control must always pulled before input signals applied. other than mode, control signal must always held high. level input applied cell terminal while control signal remains levels, current flow continuously into input buffer.
About output cells High level signals output from cell circuit structure. Therefore, outputs needed, pull-up resistors external chip.
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Types Input/Output Buffers Their Type)
5.2.6.4
List Cells
Table 5-22 Tolerant Fail-Safe Input Buffers List
Cell Name*1 XFHIBB XFHIBBP# XFHIBBD# XFHIBG XFHIBGP# XFHIBGD# Notes
Input Level CMOS CMOS CMOS CMOS Schmitt CMOS Schmitt CMOS Schmitt
Whether Pull-up/Pull-down Resistors Included None Pull-up resistors Pull-down resistors None Pull-up resistors Pull-down resistors
denotes with pull-up resistance values corresponding Type Type respectively (for details, refer Table 5-1).
Table 5-23 Rated Values Each Voltage
Type Output Current Type Type Type Notes HVDD IOH*1/IOL*2 (HVDD -3/3 -6/6 -12/12 Unit
Table 5-24 Tolerant Fail-Safe Output Buffers List
Function Normal output Normal output high speed Normal output noise 3-state output 3-state output high speed 3-state output noise Notes IOH/IOL Type Type Type Type Type Type Type Type Cell Name*1, XFHOBF#T XFHOBF3AT XFHOBF3BT XFHTBF#T XFHTBF3AT XFHTBF3BT
denotes with IOH/IOL values corresponding Type Type respectively (for details, refer Table 5-23). addition configurations shown Table 5-24, Tolerant Fail-Safe output buffers configured without test pins. Customers desiring such configurations should direct inquiries Epson.
EMBEDDED ARRAY S1X60000 SERIES
EPSON
Chapter Types Input/Output Buffers Their Type)
Table 5-25 Tolerant Fail-Safe Bi-directional Buffers List
Input Level Function Bi-directional output CMOS Bi-directional output high speed Bi-directional output noise Bi-directional output CMOS Schmitt Bi-directional output high speed Bi-directional output noise Notes IOH/IOL Type Type Type Type Type Type Type Type Cell Name*1, XFHBB#T XFHBB3AT XFHBB3BT XFHBG#T XFHBG3AT XFHBG3BT
denotes with IOH/IOL values corresponding Type Type respectively (for details, refer Table 5-23). addition configurations shown Table 5-25, Tolerant Fail-Safe bi-directional buffers configures with pull-up/pull-down resistors without test pins. Customers desiring such configurations should direct inquiries Epson.
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Types Input/Output Buffers Their Type)
Dual Power Supplies Guidelines
S1X60000 series Type) allows each input/output buffer interfaced with signals desired, using dual power supply system. internal cell area operates using single power supply.
5.3.1
Method Adapting Dual Power Supplies
S1X60000 series Type), possible apply input signals voltages higher internal operating voltage using HVDD input buffers. Similarly, high voltage signals above internal operating voltage output using dual power supply output buffers.
5.3.2
Power Supplies Dual Power Operation
your circuit operated using different power supplies, power supply cells: HVDD LVDD. Specifically, HVDD used HVDD input/output buffers, LVDD used LVDD input/output buffers internal cells. power supply voltages must always satisfy equation below. HVDD LVDD HVDD LVDD, operation internal circuit cannot guaranteed. operating conditions specified below recommended. HVDD LVDD HVDD LVDD
5.3.3
Turning On/Off Dual Power Supplies
chips designed dual power supply specifications, make sure power turned order specified below.
When turning LVDD (internal) HVDD (I/O section) input signals applied When turning off: Input signals HVDD (I/O section) LVDD (internal)
Note Avoid keeping only HVDD turned (for more) while LVDD turned off, degrade chip's reliability. Note When turning HVDD back after off, always sure initialize circuit following power This necessary ensure internal circuit state event power supply noise like.
EMBEDDED ARRAY S1X60000 SERIES
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Chapter Types Input/Output Buffers Their Type)
5.3.4
Interface with external devices
tables shown below when connecting input/output buffers external LSIs.
5.3.4.1
When power supplied HVDD
Table 5-26 Example Connection System LSIs
LSIs which connected
S1X60000 series input buffer
Whether connectable
Remarks pull-up resistor necessary. pull-up resistor necessary.
system output buffer
tolerant Fail-Safe input buffer output buffer
system input buffer
tolerant Fail-Safe output buffer bi-directional buffer tolerant Fail-Safe bi-directional buffer
system bi-directional buffer
Table 5-27 Example Connection System LSIs
LSIs which connected S1X60000 series input buffer system output buffer tolerant Fail-Safe input buffer output buffer system input buffer tolerant Fail-Safe output buffer bi-directional buffer tolerant Fail-Safe bi-directional buffer Whether connectable Remarks
However, connection cells possible. external pull-up resistor required. (Not required cells)
system bi-directional buffer
external pull-up resistor required.
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Types Input/Output Buffers Their Type)
5.3.4.2
When power supplied HVDD (LVDD
Note that following description assumes case where signals supplied from external LSIs buffer, even while HVDD power supply off. Table 5-28 Example Connection System LSIs
LSIs which connected S1X60000 series Whether connectable Remarks sure Gated cells. However, input buffers with pull-up resistors cannot used. input buffers with pull-up resistors, note that input leakage current about will flow.
input buffer
system output buffer LVDD Fail-Safe input buffer
tolerant Fail-Safe input buffer system bi-directional buffer bi-directional buffer tolerant Fail-Safe bi-directional buffer
pull-up resistor necessary.
Table 5-29 Example Connection System LSIs
LSIs which connected S1X60000 series input buffer system output buffer LVDD Fail-Safe input buffer tolerant Fail-Safe input buffer system bi-directional buffer bi-directional buffer tolerant Fail-Safe bi-directional buffer Whether connectable Remarks
external pull-up resistor required.
EMBEDDED ARRAY S1X60000 SERIES
EPSON
Chapter Memory Blocks
Chapter Memory Blocks
60000 Series supports memory blocks.This memory block comes following types classified memory capacity function: Basic Cell type port port), asynchronous type Basic Cell type port port), synchronous type Standard type port RAM, synchronous type Standard type dual port RAM, synchronous type High density type port RAM, synchronous type Mask ROM, synchronous type
6.1.1
Basic Cell Type (Asynchronous)
Features
port Asynchronous clock Fully static operation read/write address port, input data port, output data port configurations supported:Word Depth (incremental words) Width (incremental bit) Maximum size: bits/module
S1X60000 Series supports port port RAM.
port Asynchronous clock Fully static operation read address port, write address port, input data port, output data port configurations supported: Word Depth (incremental words) Width (incremental bit) Maximum size: bits/module
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Memory Blocks
6.1.2
Word/Bit Configuration Simulation Model Selection
delay parameters change depending word/bit structure. Simulation models have been prepared using performance characteristics indicative word/bit configuration. port port word/bit structure simulation models shown Tables respectively. with word/bit structures exceeding limitations tables below, combinations multiple RAMs. Table Simulation Model Selection Chart port Word/Bit Structure)
Word depth width RAM1P1 RAM1P2 RAM1P3 RAM1P4 RAM1P5 RAM1P6 RAM1P7 RAM1P8 RAM1P9 RAM1P10 RAM1P11 RAM1P12 RAM1P13 RAM1P14 RAM1P15 RAM1P16 RAM1P17 RAM1P18 RAM1P19 RAM1P20 RAM1P21 RAM1P22 RAM1P23 RAM1P24 RAM1P25 RAM1P26 RAM1P27 RAM1P28 RAM1P29 RAM1P30 RAM1P31 RAM1P32
Table Simulation Model Selection Chart port Word/Bit Structure)
Word depth width RAM2P1 RAM2P2 RAM2P3 RAM2P4 RAM2P5 RAM2P6 RAM2P7 RAM2P8 RAM2P9 RAM2P10 RAM2P11 RAM2P12 RAM2P13 RAM2P14 RAM2P15 RAM2P16 RAM2P17 RAM2P18 RAM2P19 RAM2P20 RAM2P21 RAM2P22 RAM2P23 RAM2P24 RAM2P25 RAM2P26 RAM2P27 RAM2P28 RAM2P29 RAM2P30 RAM2P31 RAM2P32
6.1.3
Size
direction size, direction size, number used calculated using formulas below. formulas below include interconnect region contained RAM. port Size direction: Word/2 Size direction: word 256) (256 word 512) Number BCs: RAMBCS
Table Example Structure port Number
width Word depth 3,248 (116 5,936 (212 11,312 (404 22,852 (788 5,104 (116 9,328 (212 17,776 (404 35,460 (788 8,816 (116 16,112 (212 30,704 (404 60,676 (788 16,240 (116 140) 29,680 (212 140) 56,560 (404 140) 111,108 (788 141)
EMBEDDED ARRAY S1X60000 SERIES
EPSON
Chapter Memory Blocks
port Size direction: Word/2 Size direction: word 256) (256 word 512) Number BCs: RAMBCS
Table Example Structure port Number
width Word depth 3,596 (116 6,572 (212 12,524 (404 26,004 (788 5,452 (116 9,964 (212 18,988 (404 38,612 (788 9,164 (116 16,748 (212 31,916 (404 63,828 (788 16,588 (116 143) 30,316 (212 143) 57,772 (404 143) 114,260 (788 145)
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Memory Blocks
6.1.4
Investigating Placement Master Slice
When investigating placement master slice, please insure that sufficient area available both direction (column) direction (row). When loading onto chip, necessary insure that capacity master exceeds required area both directions. When multiple RAMs used, blocks placed adjacent each other either horizontally vertically. wiring areas around included equation shown previous section. therefore possible determine advantages disadvantages placing master slice based values obtained simply adding RXSIZE RYSIZE sizes directions, respectively. shown Figure 6-1, interconnecting area Bit/2 (round nearest whole number) direction every upper lower direction, then regarding master slice selection should decided mount not.
256W
Figure Example Layout
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EPSON
Chapter Memory Blocks
6.1.5
Explanation Functions
port Table 6-5-1 port Signals
Signal Name (m-1) (n-1) (n-1) FUNCTION Chip select signal, active Read/write signal, Read, Write Read/write address port, Data input port, Data output port,
Table 6-5-2 port
28.9LU 28.9LU 28.9LU 28.9LU
corresponds "IN4"
Table port Truth Table
(m-1) Stable Stable (n-1) Unknown Unknown Read Data Mode Wait Write Read High
Data Read data read holding High High setting address.
Data Write data written either following ways: Holding High, setting address, sending negative pulse Holding Low, setting address, sending positive pulse
When either method used, data latched trailing edge pulse.
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Memory Blocks
Wait State When Low, port enters wait state only maintains data. current consumed merely leakage current, almost zero. port Table 6-7-1 port Signals
Signal Name RA0, (m-1) WA0, (m-1) (n-1) (n-1) Function Chip select signal, active Read signal, Read enable Write signal, Write enable Read address port, RA0: Write address port, WA0: Data input port, Data output port,
Table 6-7-2 port
RA0/ RA1/ RA2/ RA3/ RA4/ RA5/ RA6/ RA7/ RA8/ 2.1LU
28.9LU 28.9LU 28.9LU 28.9LU
corresponds "IN4"
Table port Truth Table
RA0, (n-1) Stable Stable WA0, (m-1) Stable Stable (n-1) Unknown Unknown Unknown Read Data Read Data Mode Wait Wait Write Read Read Write High
EMBEDDED ARRAY S1X60000 SERIES
EPSON
Chapter Memory Blocks
Data Read data read holding High High setting read address.
Data Write data written either following ways: Holding High, setting write address, sending positive pulse Holding High, setting write address, sending positive pulse
Data Read/Write When reading done same time writing, possible performing respective methods simultaneously. However, these operations cannot performed simultaneously same address. read cycle access time described Section 6.1.6 applies data which writing already been completed.
Wait State port enters wait state either situations below, does nothing maintain data. current consumed merely leakage current, almost Low. High, Low, Low.
EPSON
EMBEDDED ARRAY S1X60000 SERIES
Chapter Memory Blocks
6.1.6
Delay Parameters
Specifications (VDD +85°C) Table port/2 port Read Cycle (1/8)
Parameter Signal RAM1P1/ RAM2P1 Min. Max.
4.605 4.605 4.605
RAM1P2/ RAM2P2 Min.
5.239 5.239 0.153 0.153 0.153
RAM1P3/ RAM2P3 Min.
5.519 5.519 0.212 0.212 0.212
RAM1P4/ RAM2P4 Min.
6.203 6.203 0.272 0.272 0.272
Unit
Max.
5.239 5.239 5.239
Max.
5.519 5.519 5.519
Max.
6.203 6.203 6.203
Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
tACC tACS tARW tRCS tOHCS tOHRW
4.605 4.605 0.093 0.093 0.093
Table port/2 port Read Cycle (2/8)
Parameter Signal RAM1P5/ RAM2P5 Min. Read cycle Address access time access time access time active time Output hold time after address change Output hold time after disable Output hold time after disable
tACC tACS tARW tRCS tO
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