5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) D

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5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) D

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PDU1032H
5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H)
Digitally programmable delay steps Monotonic delay-versus-address variation Precise stable delays Input outputs fully 10KH-ECL interfaced buffered Fits 32-pin socket
PACKAGES
PDU1032H-xx PDU1032H-xxM
PDU1032H-xxC5 PDU1032H-xxMC5
FUNCTIONAL DESCRIPTION
PDU1032H-series device 5-bit digitally programmable delay line. delay, TDA, from input (IN) output (OUT) depends address code (A4-A0) according following formula: TINC
DESCRIPTIONS
A0-A4 Signal Input Signal Output Address Bits Output Enable Volts Ground
where address code, TINC incremental delay device, inherent delay device. incremental delay specified dash number device range from 0.5ns through 20ns, inclusively. enable (ENB) held during normal operation. When this signal brought HIGH, forced into state. address latched must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance: 2ns, whichever greater Inherent delay (TD0): 5.5ns typical dash numbers greater larger Setup time propagation delay: Address input setup (TAIS): 3.6ns Disable output delay (TDISO): 1.7ns typical Operating temperature: Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VEE: -5VDC Power Dissipation: 615mw typical load) Minimum pulse width: total delay
DASH NUMBER SPECIFICATIONS
Part Number PDU1032H-.5 PDU1032H-1 PDU1032H-2 PDU1032H-3 PDU1032H-4 PDU1032H-5 PDU1032H-6 PDU1032H-8 PDU1032H-10 PDU1032H-12 PDU1032H-15 PDU1032H-20 Incremental Delay Step (ns) 10.0 12.0 15.0 20.0 Total Delay (ns) 15.5 12.4 15.5 18.6 23.2 31.0
2009 Data Delay Devices
NOTE: dash number between shown also available.
#97045
2/25/03
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU1032H
APPLICATION NOTES
ADDRESS UPDATE
PDU1032H memory device. such, special precautions must taken when changing delay address order prevent spurious output signals. timing restrictions shown Figure After last signal edge delayed appeared pin, minimum time, TOAX, required before address lines change. This time given following relation: TOAX i-1) TINC where address codes, respectively. Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TOAX elapsed. similar situation occurs when using signal disable output while active. this case, unit must held disabled state until device able "clear" itself. This achieved holding signal high signal time given TDISH TINC Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TDISH elapsed.
INPUT RESTRICTIONS
There three types restrictions input pulse width period listed Characteristics table. recommended conditions those which delay tolerance specifications monotonicity guaranteed. suggested conditions those which signals will propagate through unit without significant distortion. absolute conditions those which unit will produce some type output given input. When operating unit between recommended absolute conditions, delays deviate from their values frequency. However, these deviations will remain constant from pulse pulse input pulse width period remain fixed. other words, delay unit exhibits frequency pulse width dependence when operated beyond recommended conditions. Please consult technical staff Data Delay Devices your application specific high-frequency requirements. Please note that increment tolerances listed represent design goal. Although most delay increments will fall within tolerance, they guaranteed throughout address range unit. Monotonicity however, guaranteed over addresses.
A4-A0 TAENS TENIS
TOAX TDISO TAIS
TDISH
Figure Timing Diagram
#97045
2/25/03
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU1032H
DEVICE SPECIFICATIONS
TABLE CHARACTERISTICS
PARAMETER SYMBOL Total Programmable Delay Inherent Delay Disable Output Delay TDISO Address Enable Setup Time TAENS Address Input Setup Time TAIS Enable Input Setup Time TENIS Output Address Change TOAX Text Disable Hold Time TDISH Text Absolute PERIN Input Period Suggested PERIN Recommended PERIN Absolute PWIN Input Pulse Width Suggested PWIN Recommended PWIN Greater dash numbers larger than UNITS TINC
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -7.0 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
75C) PARAMETER High Level Output Voltage Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current SYMBOL -1.020 -1.950 -1.480 -0.735 -1.600 -1.070 UNITS NOTES MAX,50 MIN,
#97045
2/25/03
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU1032H
PACKAGE DIMENSIONS
.400 TYP.
1.650 TYP.
.020 .320 TYP. MAX. .150 ±.030 .100 .600 .700 .800 1.000 1.400 1.500 .018 TYP.
.012 TYP. .300 TYP.
.075
PDU1032H-xx (Commercial DIP) PDU1032H-xxM (Military DIP)
.020 TYP.
.040 TYP.
.010±.002
.710 .590 ±.00 MAX.
.882 ±.00 .007 ±.00
.090 1.100 2.080±.020
.100
.320 MAX.
.050 ±.01
PDU1032H-xxC5 (Commercial SMD) PDU1032H-xxMC5 (Military SMD)
#97045
2/09/09
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU1032H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): -5.0V 0.1V Input Pulse: Standard 10KH levels Source Impedance: Max. Rise/Fall Time: Max. (measured between 80%) Pulse Width: PWIN Total Delay Period: PERIN Total Delay OUTPUT: Load: Cload: Threshold: (VOH VOL) (Rising Falling)
NOTE: above conditions test only restrict operation device.
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG OSCILLOSCOPE
ADDRESS SELECT
Test Setup
PERIN TRISE INPUT SIGNAL
TFALL
DFALL
DRISE OUTPUT SIGNAL
Timing Diagram Testing
#97045
2/25/03
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013

5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) D

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