8-BIT 12-BIT PROGRAMMABLE PULSE GENERATORS (SERIES 3D3608 3D3612: PARA
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3D3608 3D3612
8-BIT 12-BIT PROGRAMMABLE PULSE GENERATORS (SERIES 3D3608 3D3612: PARALLEL INTERFACE)
All-silicon, low-power CMOS technology 3.3V operation Vapor phase, wave solderable Programmable latched parallel interface Increment range: 0.25ns through 800us Pulse width tolerance: (See Table Supply current: typical Temperature stability: ±1.5% (-40C 85C) stability: ±1.0% (3.0V 3.6V)
TRIG
data delay devices, inc.
OUTB
TRIG
PACKAGES PINOUTS
OUTB
3D3608R-xx SOIC
3D3612W-xx
mechanical dimensions, click here. package marking details, click here.
FUNCTIONAL DESCRIPTION
3D3608 3D3612 devices versatile 12-bit programmable monolithic pulse generators. rising-edge trigger input (TRIG) initiates pulse, which presented output pins (OUT,OUTB). pulse width, programmed parallel interface, varied over (3D3608) 4095 (3D3612) equal steps according formula: tinh addr tinc where addr programmed address, tinc pulse width increment (equal device dash number), tinh inherent (address zero) pulse width. device also offers reset input (RES), which used terminate pulse before programmed time expired.
DESCRIPTIONS
Trigger Input Reset Input Pulse Output Complementary Pulse Output Address Enable Input P0-P11 Address Inputs +3.3 Volts Ground connect externally TRIG OUTB
all-CMOS 3D3608 3D3612 integrated circuits have been designed reliable, economic alternatives hybrid pulse generators. 3D3608 offered standard 16-pin SOIC, 3D3612 offered standard 20-pin SOL.
TABLE PART NUMBER SPECIFICATIONS
PART (8-BIT) 3D3608R-0.25 3D3608R-0.5 3D3608R-1 3D3608R-2 3D3608R-5 3D3608R-10 3D3608R-20 3D3608R-50 3D3608R-100 3D3608R-200 3D3608R-500 3D3608R-1K 3D3608R-2K 3D3608R-5K 3D3608R-10K 3D3608R-20K 3D3608R-50K PART (12-BIT) 3D3612W-0.25 3D3612W-0.5 3D3612W-1 3D3612W-2 3D3612W-5 3D3612W-10 3D3612W-20 3D3612W-50 3D3612W-100 3D3612W-200 3D3612W-500 3D3612W-1K 3D3612W-2K 3D3612W-5K 3D3612W-10K 3D3612W-20K 3D3612W-50K Pulse Width Increment 0.25ns 0.12ns 0.50ns 0.25ns 1.0ns 0.5ns 2.0ns 1.0ns 5.0ns 2.5ns 10ns 5.0ns 20ns 10ns 50ns 25ns 100ns 50ns 200ns 100ns 500ns 250ns 1.0us 0.5us 2.0us 1.0us 5.0us 2.5us 10us 5.0us 20us 10us 50us 25us Maximum P.W. (8-Bit) 78.25ns 142.5ns 270ns 525ns 1.28us 13ns 2.56us 26ns 5.11us 52ns 12.8us 128ns 25.5us 255ns 51.0us 510ns 128us 1.3us 255us 2.6us 510us 5.2us 1.28ms 13us 2.55ms 26us 5.10ms 52us 12.8ms 128us Maximum P.W. (12-Bit) 1.04us 10ns 2.06us 21ns 4.11us 41ns 8.19us 82ns 20.5us 205ns 41.0us 410ns 81.9us 819ns 205us 2.1us 410us 4.1us 819us 8.2us 2.05ms 21us 4.10ms 41us 8.19ms 82us 20.5ms 205us 41.0ms 410us 81.9ms 819us 205ms PART (8-BIT) 3D3608R-100K 3D3608R-200K 3D3608R-500K 3D3608R-750K Pulse Width Increment 100us 50us 200us 100us 500us 250us 750us 375us Maximum P.W. (8-Bit) 25.5ms 260us 51.0ms 510us 128ms 1.3ms 191ms 1.9ms
NOTE: increment between 0.25ns 800us (50us 12-bit generator) shown also available standard device.
2008 Data Delay Devices
#06010
7/28/2008
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D3608 3D3612
APPLICATION NOTES
GENERAL INFORMATION
Figure illustrates main functional blocks 3D3608 3D3612. Since these devices CMOS designs, unused input pins must returned well-defined logic levels, Ground. pulse generator architecture comprised number delay cells (for fine control) oscillator counter (for coarse control). Each device individually trimmed maximum accuracy linearity throughout address range. change pulse width from address setting next called increment, LSB. nominally equal device dash number. minimum pulse width, achieved setting address zero, called inherent pulse width. best performance, essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred. Also, signal traces should kept short possible. absolute error defined follows: eabs (tinh addr tinc) where tinh nominal inherent delay. absolute error limited whichever greater, every address. inherent pulse width error deviation inherent width from nominal value. limited from nominal inherent pulse width
PULSE WIDTH STABILITY
characteristics CMOS integrated circuits strongly dependent power supply temperature. 3D3608 3D3612 utilize novel compensation circuitry minimize performance variations induced fluctuations power supply and/or temperature. With regard stability, output pulse width 3D3608 3D3612 given address, addr, split into components: inherent pulse width (tinh) relative pulse width (tPW tinh). These components exhibit very different stability coefficients, both which must considered very critical applications. thermal coefficient relative pulse width limited ±250 PPM/C (except -0.25), which equivalent variation, over -40C operating range, ±1.5% (±9% dash 0.25) from room-temperature pulse width. This holds dash numbers. thermal coefficient inherent pulse width nominally +20ps/C dash numbers less than +30ps/C other dash numbers. power supply sensitivity relative pulse width ±1.0% (±3.0% dash 0.25) over 3.0V 3.6V operating range, with respect pulse width nominal 3.3V power supply. This holds dash numbers. sensitivity inherent pulse width nominally -5ps/mV dash numbers. should also noted that also adversely affected thermal supply variations, particularly MSL/LSB crossovers (ie, 128, etc).
PULSE WIDTH ACCURACY
There number ways characterizing pulse width accuracy programmable pulse generator. first differential nonlinearity (DNL), also referred increment error. defined deviation increment given address from nominal value. most dash numbers, within every address (see Table Pulse Width Step). integrated nonlinearity (INL) determined first constructing least-squares best straight line through pulse-width-versusaddress data. then deviation given width from this line. dash numbers, within every address. relative error defined follows: erel (tPW tinh) addr tinc where addr address, measured width this address, tinh measured inherent width, tinc nominal increment. very similar INL, simpler calculate. most dash numbers, relative error less than every address (see Table
#06010
7/28/2008
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D3608 3D3612
APPLICATION NOTES (CONT'D)
TRIGGER RESET TIMING
Figure shows timing diagram device when reset input (RES) used. this case, pulse triggered rising edge TRIG signal ends time determined address loaded into device. While pulse active, additional triggers occurring ignored. Once pulse ended, after short recovery time, next trigger recognized. Figure shows timing case where reset issued before pulse ended. Again, there short recovery time required before next trigger occur.
ADDRESS UPDATE
3D3608/3D3612 operate addressing modes. transparent mode held high), parallel address inputs must persist duration output pulse, accordance with Figure latched mode, address data stored internally, which allows parallel inputs connected multi-purpose data bus. Timing this mode also shown Figure
TRIGGER RESET
INPUT LOGIC
DELAY LINE
OSCILLATOR/ COUNTER
OUTPUT LOGIC
OUTB PULSE
BIT-SHIFT LOGIC
ADDR ENABLE
12-BIT LATCH
Figure Functional block diagram
TRIG
OUTB
tRTO
Figure Timing Diagram (RES=0)
TRIG
tRTR
OUTB
Figure Timing Diagram (with reset)
#06010
7/28/2008
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D3608 3D3612
APPLICATION NOTES (CONT'D)
Addr TRIG
VALID
VALID
tAT1
Transparent Mode (AE=1)
Addr
VALID
tAT1
TRIG
tAT2
Latched Mode
Figure Address Update
#06010
7/28/2008
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D3608 3D3612
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 3.0V 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 12.0 UNITS NOTES
-35.0 15.0
3.0V 2.4V 3.0V 0.4V
*IDD(Dynamic) where: Average capacitance load/output (pf) Trigger frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 3.0V 3.6V) PARAMETER Trigger Width Trigger Inherent Delay Output Pulse Width Re-trigger Time Reset Width Reset Output Reset Next Trigger Width Data Setup Data Hold from Output High Data Valid Trigger High Trigger SYMBOL tRTO tRTR tAT1 tAT2 UNITS REFER Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
#06010
7/28/2008
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D3608 3D3612
TYPICAL APPLICATIONS
TRIG OUTB
FOUT
Addr
Addr
3D3608 3D3612
FOUT (tPW tNOR)
tNOR
FOUT
Figure Programmable Oscillator
TRIG Addr
OUTB
SETB RESB
D-FF
3D3608/12 R-Edge Delay
TRIG
OUTB
SETB RESB
Addr
Addr
3D3608/12 F-Edge Delay
D-FF
tPWR
tPWF
Figure Programmable Delay Line
#06010
7/28/2008
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D3608 3D3612
SILICON DEVICE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 20ns Period: PERIN Prog'd Pulse Width OUTPUT: Rload: Cload: Threshold: 1.5V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG TRIG DEVICE UNDER TEST (DUT) TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER
Figure Test Setup
PERIN tRISE INPUT SIGNAL
tFALL
OUTPUT SIGNAL
Figure Timing Diagram
#06010
7/28/2008
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
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