BH62UV1601 Wide operation voltage 1.65V 3.6V Ultra power consumpt

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

BH62UV1601 Wide operation voltage 1.65V 3.6V Ultra power consumpt

Datasheet Thumbnail

Top Searches for this datasheet

Ultra Power/High Speed CMOS SRAM
BH62UV1601
Wide operation voltage 1.65V 3.6V Ultra power consumption Operation current 12mA (Max.)at 55ns 3.6V (Max.) 1MHz Standby current 30uA (Max.) 3.6V/85 Data retention current 15uA (Max.) 1.2V High speed access time 55ns (Max.) VCC=3.0V 70ns (Max.) VCC=1.8V Automatic power down when chip deselected Easy expansion with CE1, options Three state outputs compatible Fully static operation, clock, refresh Data retention supply voltage 1.0V
DESCRIPTION
BH62UV1601 high performance, ultra power CMOS Static Random Access Memory organized 2,048K bits operates wide range 1.65V 3.6V supply voltage. Advanced CMOS technology circuit techniques provide both high speed power features with maximum standby current 30uA Vcc=3.6V maximum access time 55/70ns Vcc=3.0V/1.8V. Easy memory expansion provided active chip enable (CE1), active HIGH chip enable (CE2) active output enable (OE) three-state output drivers. BH62UV1601 automatic power down feature, reducing power consumption significantly when chip deselected. BH62UV1601 made with chips 8Mbit SRAM stacked multi-chip-package. BH62UV1601 available 48-ball package.
POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
TYPE
VCC=1.8V 10MHz fMax.
VCC=3.6V
VCC=1.8V
1MHz
VCC=3.6V 10MHz
fMax.
1MHz
BH62UV1601AI
Industrial
30uA
25uA
12mA
1.5mA
BGA-48-0608
CONFIGURATIONS
BLOCK DIAGRAM
Address Input Buffer
Decoder
1024
Memory Array
1024 16384
16384 Data Output Buffer 2048 Column Decoder Control Address Input Buffer Data Input Buffer Column Write Driver Sense
48-ball view
Brilliance Semiconductor, Inc. reserves right change products specifications without notice.
Detailed product characteristic test report available upon request being accepted.
R0201-BH62UV1601
Revision Oct. 2008
BH62UV1601
DESCRIPTIONS
Name
A0-A20 Address Input Chip Enable Input Chip Enable Input Write Enable Input
Function
These address inputs select 2,048K active active HIGH. Both chip enables must active when data read from write device. either chip enable active, device deselected standby power mode. pins will high impedance state when device deselected. write enable input active controls read write operations. With chip selected, when HIGH LOW, output data will present pins; when LOW, data present pins will written into selected memory location.
Output Enable Input
output enable input active LOW. output enable active while chip selected write enable inactive, data will present pins they will enabled. pins will high impendence state when inactive.
DQ0-DQ7 Data Input/Output Ports
bi-directional ports used read data from write data into RAM. Power Supply Ground
TRUTH TABLE MODE
Chip De-selected (Power Down) Output Disabled Read Write
OPERATION
High High DOUT
CURRENT
ICCSB, ICCSB1
NOTES: means VIH; means VIL; means don't care (Must state)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG IOUT
OPERATING RANGE
UNITS
PARAMETER
Terminal Voltage with Respect Temperature Under Bias Storage Temperature Power Dissipation Output Current
RATING
-0.5
RANG
Industrial
AMBIENT TEMPERATURE
1.65V 3.6V
4.6V
+125 +150
CAPACITANCE 25OC, 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input Capacitance Input/Output Capacitance VI/O
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. -2.0V case pulse width less than R0201-BH62UV1601
This parameter guaranteed 100% tested.
Revision Oct., 2008
BH62UV1601
ELECTRICAL CHARACTERISTICS -40OC +85OC)
PARAMETER NAME ICC1 ICCSB ICCSB1 PARAMETER
Power Supply Input Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current Standby Current CMOS
TEST CONDITIONS
MIN.
1.65
VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V
TYP.(1)
-5.0
MAX.
VCC+0.3
UNITS
-0.3
VCC, VI/O VCC, Max, 0.1mA Max, 2.0mA Min, -0.1mA Min, -1.0mA VIL, VIH, 0mA, FMAX
VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V
-VCC-0.2
VIH, 0mA, 1MHz VIH, VIL, CE1VCC-0.2V CE20.2V, VCC-0.2V 0.2V
Typical characteristics TA=25 100% tested. Undershoot: -1.0V case pulse width less than Overshoot: VCC+1.0V case pulse width less than FMAX=1/tRC. VCC=3.0V TA=25
DATA RETENTION CHARACTERISTICS -40OC +85OC)
SYMBOL ICCDR tCDR PARAMETER
Data Retention Data Retention Current Chip Deselect Data Retention Time Operation Recovery Time
TEST CONDITIONS
CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V
VCC=1.2V
MIN.
TYP.
-2.5
MAX.
UNITS
Retention Waveform
Typical characteristics TA=25 100% tested. Read Cycle Time.
DATA RETENTION WAVEFORM (CE1 Controlled)
Data Retention Mode VDR1.0V
tCDR
CE1VCC 0.2V
R0201-BH62UV1601
Revision Oct., 2008
BH62UV1601
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode VDR1.0V
tCDR
CE20.2V
TEST CONDITIONS
(Test Load Input/Output Reference) Input Pulse Levels Input Rise Fall Times Input Output Timing Reference Level tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tWHZ, Output Load Others 1V/ns 0.5Vcc 5pF+1TTL 30pF+1TTL INPUT PULSES Output
SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST STEADY CHANGE FROM CHANGE FROM DON'T CARE CHANGE PERMITTED DOES APPLY OUTPUTS MUST STEADY WILL CHANGE FROM WILL CHANGE FROM CHANGE STATE UNKNOW CENTER LINE HIGH INPEDANCE "OFF" STATE
Rise Time: 1V/ns
Fall Time: 1V/ns
Including scope capacitance.
ELECTRICAL CHARACTERISTICS -40OC +85OC) READ CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable Output Valid Chip Select Output Chip Select Output Output Enable Output Chip Select Output High Chip Select Output High Output Enable Output High Data Hold from Address Change (CE1) (CE2) (CE1) (CE2) (CE1) (CE2) CYCLE TIME 55ns (VCC 3.0V) MIN. TYP. MAX. -CYCLE TIME 70ns (VCC 1.8V) MIN. TYP. MAX. -UNITS
tAVAX tAVQX tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tE1HQZ tE2LQZ tGHQZ tAVQX
tACS1 tACS2 tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ
R0201-BH62UV1601
Revision Oct., 2008
BH62UV1601
SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE (1,2,4) ADDRESS DOUT READ CYCLE (1,3,4) tACS1 tCLZ
tACS2 tCHZ1, tCHZ2(5)
DOUT
READ CYCLE ADDRESS tCLZ1(5) tCLZ2(5) DOUT tOLZ tACS1 tCHZ1(1,5) tOHZ(5)
tACS2
tCHZ2(2,5)
NOTES: high read Cycle. Device continuously selected when CE2= VIH. Address valid prior coincident with transition and/or transition high. VIL. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested.
R0201-BH62UV1601
Revision Oct., 2008
BH62UV1601
ELECTRICAL CHARACTERISTICS -40OC +85OC) WRITE CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Write Cycle Time Chip Select Write Address Time Address Valid Write Write Pulse Width Write Recovery Time Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Disable Output High Write Output Active (CE1, (CE2) CYCLE TIME 55ns (VCC 3.0V) MIN. TYP. MAX. -CYCLE TIME 70ns (VCC 1.8V) MIN. TYP. MAX. -UNITS
tAVAX tAVWL tAVWH tE1LWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWR1 tWR2 tWHZ tOHZ
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE ADDRESS tWR1(3) tCW(11)
tOHZ(4,10) DOUT
tCW(11) tWP(2)
tWR2(3)
R0201-BH62UV1601
Revision Oct., 2008
BH62UV1601
WRITE CYCLE (1,6) ADDRESS tCW(11)
tCW(11) tWP(2)
tWR2(3)
tWHZ(4,10)
DOUT
(8,9)
NOTES: must high during address transitions. internal write time memory defined overlap active low. signals must active initiate write signal terminate write going inactive. data input setup hold timing should referenced second transition edge signal that terminates write. measured from earlier going high going write cycle. During this period, pins output state that input signals opposite phase outputs must applied. transition high transition occurs simultaneously with transitions after transition, output remain high impedance state. continuously VIL). DOUT same phase write data this write cycle. DOUT read data next address. high during this period, pins output state. Then data input signals opposite phase outputs must applied them. 10.Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested. 11.tCW measured from later going going high write.
R0201-BH62UV1601
Revision Oct., 2008
BH62UV1601
ORDERING INFORMATION
BH62UV1601
SPEED 55ns
MATERIAL Green, RoHS Compliant
GRADE
PACKAGE BGA-48-0608
Note: Brilliance Semiconductor Inc. (BSI) assumes responsibility application product circuit described herein. does authorize products critical components application which failure product expected result significant injury death, including life-support systems critical medical instruments.
PACKAGE DIMENSIONS
NOTES: CONTROLLING DIMENSIONS MILLIMETERS. PIN#1 MARKING LASER PRINT. SYMBOL NUMBER SOLDER BALLS.
Max.
BALL PITCH 0.75 5.25 3.75
VIEW
mini-BGA
R0201-BH62UV1601
Revision Oct., 2008
BH62UV1601
Revision History Revision History Initial Production Version Change I-grade operation temperature range from -25OC -40OC Change 55ns(Max.) VCC=1.65~3.6V 55ns(Max.) VCC=3.0V 70ns(Max.) VCC=1.8V Typical value standby current replaced maximum value Featues Description section Remove Normal" (Leaded) Material ordering information Draft Date 10,2006 May. 2006 Oct. 2008 Remark Initial
R0201-BH62UV1601
Revision Oct., 2008

BH62UV1601 Wide operation voltage 1.65V 3.6V Ultra power consumpt

Top Searches for this datasheet

Other recent searches