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Ultra Low Power / High Speed CMOS SRAM 2M X 8 bit

BH62UV1601

Ultra Low Power / High Speed CMOS SRAM 2M X 8 bit
Green package materials are compliant to RoHS
BH62UV1601
FEATURES
DESCRIPTION
POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PKG TYPE
fMax.
BH62UV1601AI
Industrial O O -40 C to +85 C
1.5mA
BGA-48-0608
PIN CONFIGURATIONS
1 A B C D E F G H NC NC DQ0 VSS VCC DQ3 NC A18 2 OE NC NC DQ1 DQ2 NC A20 A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 NC DQ5 DQ6 NC WE A11 6 CE2 NC DQ4 VCC VSS DQ7 NC A19
BLOCK DIAGRAM
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3
Address Input Buffer
10 Row Decoder
Memory Array
1024 x 16384
16384 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 CE2 WE OE VCC GND 8 Data Output Buffer 8 2048 Column Decoder 11 Control Address Input Buffer 8 Data Input Buffer 8 Column I / O Write Driver Sense Amp
A20 A19 A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH62UV1601
Revision 1.2 Oct. 2008
BH62UV1601
PIN DESCRIPTIONS
A0-A20 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input
Function
These 21 address inputs select one of the 2, 048K x 8 bit in the RAM CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input / Output Ports VCC VSS
8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE MODE
Chip De-selected (Power Down) Output Disabled Read Write
I / O OPERATION
High Z High Z DOUT DIN
VCC CURRENT
ICCSB, ICCSB1 ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM TBIAS TSTG PT IOUT
OPERATING RANGE
UNITS
PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
RATING
Industrial
AMBIENT TEMPERATURE
1.65V ~ 3.6V
to 4.6V
-40 to +125 -60 to +150 1.0 20
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. -2.0V in case of AC pulse width less than 30 ns R0201-BH62UV1601
Revision 1.2 Oct., 2008
BH62UV1601
PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC ICC1 ICCSB ICCSB1 PARAMETER
Power Supply Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current - TTL Standby Current - CMOS
TEST CONDITIONS
TYP.(1)
3.6 0.4 0.8 VCC+0.3 1 1 0.2 0.4 -8 12 1.5 2.0 0.5 1.0 25 30
UNITS
-VCC-0.2 2.4 ---
SYMBOL VDR ICCDR tCDR tR PARAMETER
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
TEST CONDITIONS
CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V
TYP. (1)
UNITS
See Retention Waveform tRC
LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode VDR1.0V
VIH CE1VCC - 0.2V
R0201-BH62UV1601
Revision 1.2 Oct., 2008
BH62UV1601
LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode VDR1.0V
CE20.2V
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
VCC GND
Rise Time: 1V / ns
Fall Time: 1V / ns
1. Including jig and scope capacitance.
tAVAX tAVQX tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tE1HQZ tE2LQZ tGHQZ tAVQX
tRC tAA tACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH
R0201-BH62UV1601
Revision 1.2 Oct., 2008
BH62UV1601
SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1, 2, 4) tRC ADDRESS tOH DOUT READ CYCLE 2 (1, 3, 4) CE1 tACS1 CE2 tCLZ
tACS2 tCHZ1, tCHZ2(5)
READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE CE1 tCLZ1(5) CE2 tCLZ2(5) DOUT tOLZ tACS1 tCHZ1(1, 5) tOHZ(5) tOH
tACS2
tCHZ2(2, 5)
R0201-BH62UV1601
Revision 1.2 Oct., 2008
BH62UV1601
tAVAX tAVWL tAVWH tE1LWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWC tAS tAW tCW tWP tWR1 tWR2 tWHZ tDW tDH tOHZ tOW
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1(3) OE tCW(11)
tAW WE tAS tOHZ(4, 10) DOUT
tCW(11) tWP(2)
tWR2(3)
tDH tDW DIN
R0201-BH62UV1601
Revision 1.2 Oct., 2008
BH62UV1601
WRITE CYCLE 2 (1, 6) tWC ADDRESS tCW(11)
tAW WE tAS
tCW(11) tWP(2)
tWR2(3)
tWHZ(4, 10) tDW
DOUT tDH DIN
R0201-BH62UV1601
Revision 1.2 Oct., 2008
BH62UV1601
ORDERING INFORMATION
BH62UV1601
SPEED 55: 55ns
PKG MATERIAL G: Green, RoHS Compliant
PACKAGE A: BGA-48-0608
Note: Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
VIEW A
48 mini-BGA (6 x 8)
R0201-BH62UV1601
Revision 1.2 Oct., 2008
BH62UV1601
R0201-BH62UV1601
Revision 1.2 Oct., 2008