Features Precision single-phase, current input energy measurement
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AS8218 AS8228 Highly Integrated Single Phase 2-Current Energy Metering Integrated Circuits with Microcontroller, RTC, Programmable Multi-Purpose I/Os Driver
Features
Precision single-phase, current input energy measurement front-end including SigmaDelta modulators A/D-conversion digital signal processor (DSP). current consumption 5mA, depending activity. Digital phase correction selectable gain both current channels with current transformers (CT) shunt. Power-supply monitor (PSM) power-on reset reset when supply voltage falls below defined threshold. Customer programmable 8-bit 8051 compatible microcontroller (MCU). Programmable clock with optional power operating conditions. Universal Asynchronous Receiver Transmitters (UART) external communications such programme download debugging. Programmable watchdog timer (WDT) external system reset pin. Real-time clock/calendar (RTC) with on-chip digital calibration separate battery supply pin. On-chip voltage reference (VREF) with small temperature coefficient. power 4.0MHz crystal oscillator. compatible interface external EEPROM memory. Standard on-chip driver (LCDD) interface. Programmable multi-purpose I/Os (MPIO) with selectable data direction, pull-up pull-down resistors drive strength. Mains current lead/lag status indication reactive energy measurement. power battery operating mode meter reading when Mains voltage present.
AS8218 AS8228 offer following options: AS8218: segment LCDD multi-purpose (MPIO) AS8228: segment LCDD multi-purpose (MPIO)
General Description
AS8218 AS8228 highly integrated CMOS single-phase energy metering devices fully electronic meter systems. AS8218 AS8228 have been designed ensure meters full compliance with international Standards IEC62052 ANSI. AS8218 AS8228 include functions required conventional current 2-current anti-tamper meters. functions include precision energy measurement, 8-bit microcontroller unit (MCU), on-chip Liquid Crystal Display driver (LCDD), programmable multi-purpose Inputs/Outputs (MPIO), real time clock/calendar (RTC) complex tariff functions such time-ofuse maximum demand billing Serial Peripheral Interface (SPI) reading data from writing data external non-volatile memory (EEPROM). AS8218 AS8228 have dedicated energy measurement front-end, which includes analog front-end programmable Digital Signal Processor (DSP) from which active energy, mains voltage mains current provided. Reactive apparent energy also calculated. on-chip 8-bit 8051 compatible microcontroller freely programmable provides user access various functional blocks. dedicated Universal Asynchronous Receiver Transmitter (UART1) System Control block provides access various system functions blocks. second UART (UART2) also provided, which example used debugging. on-chip memory includes 24kByte program memory 1kByte data memory. meter system designer select size external EEPROM memory from 1kByte 32kByte binary steps).
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Data Sheet AS8218 AS8228
on-chip programmable watchdog timer (WDT) available automatically initiate system reset regular `hold-off' signal detected. system timing real time clock (RTC) dedicated external battery supply (VDD_BAT), enabling oscillator continue during `power-down'. digitally calibrated oscillator frequency accuracy. Driver (LCDD) block enables display information provided microcontroller, directly LCD. dedicated data register banks provided simplify programming, particularly case where display data needs scrolled. programmable multi-purpose pins (MPIO) independently configured inputs outputs. pins programmable data direction, pull-up/pull-down resistors drive
strength (4mA/8mA). Typical functions include energy consumption pulse output, energy direction fault condition indication depending current current being active energy calculation, push button display scrolling, mains isolation relay control prepayment meters, optical interface etc. on-chip analog ground buffer (ABUF) voltage reference (VREF) ensures that external circuitry required. power-supply monitor (PSM) provides reset, when falls below safe operating threshold. reset (RES_N) available external system reset. AS8218 AS8228 available LQFP64 plastic packages.
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Data Sheet AS8218 AS8228
Typical Application Circuit
3.3V 3.3V
3.3V XOUT Power Oscillator VDDA Power Divider VDDD LBP0 LBP1 LBP2 LBP3
Vrms Irms
LSD0 LSD1 LSD2 LSD3 LSD4 LSD5 LSD6 LSD7 LSD8 LSD9 LSD10 LSD11 LSD12 LSD13 LSD14 LSD15 LSD16 LSD17 LSD18 LSD19 LSD20 LSD21 LSD22 LSD23 IO10 IO11 DIRO FAULT
VDD_BAT
System Timing
LOAD
Analog Front
Driver
I/Os
Examples only
RES_N
Multipurpose I/Os
Push-Button Reference pulses calibration
AS8228 only System Control UART1
VSSA VSSD VSSD
EEPROM
3.3V
3.3V HOLD 3.3V
3.3V
Figure
Typical application circuit AS8218 AS8228
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AS8228 only
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Data Sheet AS8218 AS8228
LSD19 LSD18 LSD17 LSD16 LSD15 LSD14 LSD13 LSD12 LSD11 LSD10 LSD23 LSD22 LSD21 LSD20 LSD19 LSD18 LSD17 LSD16 LSD15 LSD14 LSD13 LSD12 LSD11 LSD10
LSD9
LSD8
LSD9
VDDA VSSA VDDD VSSD
LSD7 LSD6 LSD5 LSD4 LSD3 LSD2 LSD1 LSD0 LBP3 LBP2 LBP1 LBP0 n.c. n.c. RES_N XOUT
VDDA VSSA VDDD VSSD
LSD8
n.c.
n.c.
n.c.
n.c.
LSD7 LSD6 LSD5 LSD4 LSD3 LSD2 LSD1 LSD0 LBP3 LBP2 LBP1 LBP0 n.c. n.c. RES_N XOUT
AS8218 LQFP64
AS8228 LQFP64
VDD_BAT
VSSD
VDDD
n.c.
IO10
IO11
VDD_BAT
VSSD
Description
Name AS8218 Name AS8228 Positive input voltage channel. differential input with typical differential voltage ±100mV peak. Negative input voltage channel. differential input with Positive input first current channel. differential input with I1N. input gain programmable depending desired current sensor. typical differential voltage ±150mV peak (Gain Negative input first current channel. differential input with I1P. input gain programmable depending desired current sensor. typical differential voltage ±150mV peak (Gain Positive input second current channel. differential input with I2N. input gain programmable depending desired current sensor. typical differential voltage ±150mV peak (Gain Negative input second current channel. differential input with I2P. input gain programmable depending desired current sensor. typical differential voltage ±150mV peak (Gain Positive analog supply. VDDA provides positive supply voltage analog circuitry. required supply voltage 3.3V ±10%. Negative analog supply. VSSA ground reference analog circuitry. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Type Description
VDDA VSSA
VDDA VSSA
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VDDD
n.c.
n.c.
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Data Sheet AS8218 AS8228
Name AS8218 VDDD
Name AS8228 VDDD
Type Description Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Positive digital supply. VDDD provides positive supply voltage digital circuitry internally connected required supply voltage 3.3V ±10%. Negative digital supply. VSSD ground reference digital circuitry. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength.
VSSD VSSD VDDD
VSSD VSSD VDDD
DIPD Serial peripheral interface (SPI) external EEPROM: Serial data input. digital input with on-chip pull-down resistor. Negative digital supply. VSSD ground reference digital circuitry. Positive digital supply. VDDD provides positive supply voltage digital circuitry internally connected required supply voltage 3.3V ±10%. Serial peripheral interface (SPI) external EEPROM: Chip select (active low). Serial peripheral interface (SPI) external EEPROM: Serial data output Serial peripheral interface (SPI) external EEPROM: Serial clock Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up pull-down resistors selectable drive strength. Universal Asynchronous Receiver/Transmitter (UART1) serial transmit data output.
n.c. n.c. n.c. VDD_BAT
IO10 IO11 VDD_BAT
DIPU Universal Asynchronous Receiver/Transmitter (UART1) serial receive data input. digital input with on-chip pull-up resistor. Battery backup supply voltage input system timing real time clock (RTC). 4.0MHz crystal connected across XOUT without requirement external load capacitors. Alternatively, external clock signal applied XIN.
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Data Sheet AS8218 AS8228
Name AS8218 XOUT RES_N n.c. n.c. LBP0 LBP1 LBP2 LBP3 LSD0 LSD1 LSD2 LSD3 LSD4 LSD5 LSD6 LSD7 LSD8 LSD9 LSD10 LSD11 LSD12 LSD13 LSD14 LSD15 LSD16 LSD17 LSD18 LSD19 n.c. n.c. n.c. n.c.
Name AS8228 XOUT RES_N n.c. n.c. LBP0 LBP1 LBP2 LBP3 LSD0 LSD1 LSD2 LSD3 LSD4 LSD5 LSD6 LSD7 LSD8 LSD9 LSD10 LSD11 LSD12 LSD13 LSD14 LSD15 LSD16 LSD17 LSD18 LSD19 LSD20 LSD21 LSD22 LSD23
Type Description above, connection crystal. When external clock applied XIN, XOUT connected. System reset active low. connected connected back-plane driver output signal. back-plane driver output signal. back-plane driver output signal. back-plane driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal. segment driver output signal.
Note: Shaded pins above only available with AS8228
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Data Sheet AS8218 AS8228
Types:
DIPD DIPU
Supply Analog Input Analog Output Digital Input with pull-down resistor Digital Input with pull-up resistor Digital Output Programmable Digital Input Output
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Data Sheet AS8218 AS8228
Table Contents
Features General Description Typical Application Circuit Out.4 Description Electrical Characteristics.9 Absolute Maximum Ratings (Non-Operating) Operating Conditions DC/AC Characteristics Digital Inputs Outputs. Electrical System Specification Performance Graphs Detailed Functional Description Energy Measurement Front (Including DSP) Driver (LCDD) Programmable Multi-Purpose I/Os (MPIO) Serial Peripheral Interface (SPI) External EEPROM Requirements 8051 Microcontroller (MCU) System Control (SCT) Serial Interface UART1. Circuit Diagram.
Parts List. Packaging Product Ordering Guide Collection Formulae Terminology Revision Copyright Disclaimer Contact
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Data Sheet AS8218 AS8228
Electrical Characteristics
Absolute Maximum Ratings (Non-Operating)
Stresses beyond `Absolute Maximum Ratings' cause permanent damage AS8218 AS8228 ICs. These stress ratings only. Functional operation device these other conditions beyond those indicated under `Operating Conditions' implied. Caution: Exposure absolute maximum rating conditions extended periods affect device reliability. Parameter supply voltage Input voltage Electrostatic discharge Storage temperature Lead temperature profile Humidity non-condensing Symbol Tstrg Tlead -0.3 -0.3 +5.0 VDD+0.3 1000 Unit Notes Norm: IPC/JEDEC-020C Norm: method 3015
Operating Conditions
Symbol VDDA VSSA VDDD VSSD VDD_BAT Tamb Isupp fosc -0.1 3.579545 Unit Depending activity VDDA VDDD VSSA VSSD Referring VSSD, typical Notes
Parameter Positive analog supply voltage Negative analog supply voltage Difference supplies Positive digital supply voltage Negative digital supply voltage Battery supply voltage Ambient temperature Supply current System clock frequency
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Data Sheet AS8218 AS8228
DC/AC Characteristics Digital Inputs Outputs
CMOS Input with Schmitt Trigger Pull-up Resistor (RXD)
Parameter High level input voltage level input voltage level input current Symbol -100 Unit Tested VDD=3.6V Vin=0V Notes
CMOS Input (SI)
Parameter High level input voltage level input voltage High level input current Symbol Unit Tested VDD=3.6V Vin=3.6V Notes
CMOS Outputs (TXD, S_N)
Parameter High level output voltage level output voltage High level output current level output current Symbol Unit Notes Tested VDD=3.0V Tested VDD=3.0V Tested VDD=3.0V Vout=VOH Tested VDD=3.0V Vout=VOL
MPIO Inputs with Schmitt Trigger Selectable Pull-up/Pull-down
Parameter High level input voltage level input voltage High level input current level input current Symbol -100 Unit Tested VDD=3.6V Vin=3.6V; `pull-down' Tested VDD=3.6V Vin=0V; `pull-up' Notes
MPIO Outputs with Programmable Drive Strength
Parameter High level output current level output current High level output current level output current Symbol Unit Notes Tested VDD=3.0V Tested VDD=3.0V `4mA' selected. Tested VDD=3.0V Vout=VOH `4mA' selected. Tested VDD=3.0V Vout=VOL
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Data Sheet AS8218 AS8228
Parameter High level output current level output current
Symbol
Unit
Notes `8mA' selected. Tested VDD=3.0V Vout=VOH `8mA' selected. Tested VDD=3.0V Vout=VOL
LCDD Outputs
Liquid Crystal display driver (LCDD) outputs specified Driver section this data sheet.
Electrical System Specification
Symbol |VVP| |VI1P|, |VI2P| |VI1P|, |VI2P| |VI1P|, |VI2P| fmains DR(I) DR(P) 600:1 2000:1 err(dr) err(temp) err(cosphi) err(VDD) Vmains Imax 1.75 V(rms) A(rms) Reading Within operating temperature range, From 0.5, 240V 10%, Unit Notes Referenced VSSA Referenced VSSA Referenced VSSA Referenced VSSA
Parameter Input Signals Voltage channel input voltage Current channel input voltage (Gain=4) Current channel input voltage (Gain=16) Current channel input voltage (Gain=20) Mains frequency Dynamic range current Dynamic range power Accuracy Error variation over dyn. range Error variation over temperature Error variation over cos(phi) Error variation with Output pulse jitter Mains voltage Measured current Measurement bandwidth
Notes: Errors determined during energy measurement using demoboard reference meter with high accuracy (0.05%), which calculates actual error. Difference between largest smallest error successive error samples; maximum meter constant: 1,600i/kWh; reference meter: 10,000 DUT-meter-constant; measured What used system considerations/calculations.
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Data Sheet AS8218 AS8228
Performance Graphs
PF=0.5
Error
Error
PF=0.8
-0,1 -0,2 -0,3 -0,4 -0,5 0,01
-0,1 -0,2 -0,3 -0,4 -0,5
PF=1.0
0,01
Graph
Error reading gain setting 25°C
Graph
Error reading PF=1, PF=0.8, PF=0.5 25°C
Error
Error
-0,1 -0,2 -0,3 -0,4 -0,5 0,01
-0,1 -0,2 -0,3 -0,4 -0,5 0,01
PF=0.5 PF=0.8
PF=1.0
Graph
Error reading gain setting 25°C
Graph
Error reading PF=1, PF=0.8, PF=0.5 -40°C
PF=0.5
Error
PF=0.8
-0,1 -0,2 -0,3 -0,4 -0,5 0,01
-0,1 -0,2 -0,3 -0,4 -0,5 0,01
PF=1.0
Graph
Error reading gain setting 25°C
Graph
Error reading PF=1, PF=0.8, PF=0.5 85°C
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Data Sheet AS8218 AS8228
Error
-0,1 -0,2 -0,3 -0,4 -0,5
-0,1 -0,2 -0,3 -0,4 -0,5 0,01
[Hz]
Graph
Error reading with variation
Graph
Error reading with mains frequency variation
Gain
290V 230V 170V
Error
Error
-0,1 -0,2 -0,3 -0,4 -0,5 0,01
Gain
-0,5 -1,5 0,01
Gain16
Graph
Error reading with mains voltage variation
Graph Error reading using vconst mains voltage value
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Data Sheet AS8218 AS8228
Detailed Functional Description
AS8218 AS8228 integrated circuits have dedicated measurement front end, which capable measuring active reactive energy, mains voltage, mains current well power factor. There completely separate differential current channel inputs, measurement both Live Neutral currents. current inputs connected shunt resistor (I1) current transformer (I2); which secondary winding terminated with burden resistor. Both current channels have programmable gains; thus possible connect shunt resistor differential current inputs. option current transformers also available. AS8218 AS8228 programmed accept either measured currents energy calculation, programmed accept larger currents energy calculation. AS8218 AS8228 also used conventional 1-phase single current measurement applications, where only Live current measured. this case, pins left unconnected second current channel modulator powered down. voltage channel input measurement line voltage also differential connected resistive divider line voltage. resistive divider accommodate line voltage standard mains including 100V, 110V, 220V, 230V 240V. 4.0MHz power oscillator generates system clock AS8218 AS8228 ICs. absolute clock frequency calibrated on-chip. power divider used generate clock on-chip real time clock/calendar (RTC). supply voltage power oscillator, power divider buffered with external battery case mains power dips failures, which results AS8218 AS8228 power supply being interrupted. driver (LCDD) signals LSD0 LSD23 LBP0 LBP3 directly connected liquid crystal display (LCD), which used display various measured parameters. total segments driven AS8218 segments driven AS8228 measurement data display annunciators fully programmable. meter system designer should define annunciators that customer's specific meter system requirements met. maximum twelve programmable multi-purpose input/output (MPIO) pins available various meter functions, example light-emitting diodes (LED) signal energy consumption, energy direction, fault condition, etc. These pins also programmed bi-directional communication channels such optical interface additional Universal Asynchronous Receiver/Transmitter (UART2) Interface, should required. AS8218 MPIO pins, while AS8228 MPIO pins. dedicated Serial Peripheral Interface (SPI) also provided direct connection external EEPROM memory with compatible serial peripheral interface. Depending meter system requirements, external EEPROM memory capacity selected from 32kB, binary steps. on-chip 8051 compatible microcontroller performs required calculations enables user customize input output configuration meter. microcontroller 24kB program memory, data memory, square root calculation facility second UART (UART2) debugging purposes. programmable watchdog timer provided automatically initiate system reset when regular hold-off signal detected watchdog timer. watchdog timer optional function which software enabled.
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Data Sheet AS8218 AS8228
dedicated serial Universal Asynchronous Receiver/Transmitter (UART1) Interface within System Control provided communicate with AS8218 AS8228 perform required programming reading data, especially during meter production process. AS8218 AS8228 supply voltages VDDD VDDA) typically Volts. These supply voltages should derived from mains with standard voltage regulated power supply circuit. typical Volt power supply circuit described later. on-chip power supply monitor (PSM) ensures that reset generated independently supply voltage rise fall times. Monitoring mains provided ensure early power-down detection. reset (RES_N) also available external system reset, which active low. RES_N left unconnected required. individual functional elements AS8218 AS8228 ICs, well relationships between various functional blocks shown following block diagram. detailed description AS8218 AS8228 system flexibility available meter designer, through system programmability also described below:
XOUT
VDD_BAT
System Timing Real Time Clock
LBP3
Driver
LSD23
Energy Measurement Front Analog Front
8051 MicroController
Multi-purpose I/Os
IO11
UART1
System Control
RES_N
Figure
AS8218 AS8228 block diagram
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Data Sheet AS8218 AS8228
Energy Measurement Front (Including DSP)
Energy Measurement Front made analog front digital signal processing block (DSP), which performs active energy measurement calculations microcontroller. analog front comprises three Sigma-Delta modulators sampling mains voltage, Line current second current channel, optional measurement Neutral current. Also included analog front voltage reference, which provides temperature stability Sigma-Delta modulators. Setting optimum input conditions voltage current channels also described this section. digital signal processing block (DSP) provides filtering processing output data from sigma-delta modulators ensures that specified measurement accuracy provided AS8218 AS8228. offers programming flexibility provides fast efficient meter production calibration procedures. power supply monitor (PSM) also described this section. ensures that reset generated independently rise fall times supply voltage (VDD).
Analog Front
analog front comprises three identical Sigma-Delta modulators, which convert differentially connected analog voltage current inputs into digital signals. current inputs gain adjustable accommodate both directly connected galvanically isolated current sensors. on-chip voltage reference (VREF) most important contributor accuracy AS8218 AS8228 providing temperature stability circuit. Considering that voltage current signals multiplied derive energy value, errors introduced prior multiplication function results errors being multiplied. Thus introduction errors into voltage current channel inputs will result doubling percentage error after multiplication energy output. temperature coefficient VREF specified ppm/K typical. Voltage Reference Specifications Parameter Output voltage Temperature coefficient Symbol Vref 1.217 1.219 1.221 Unit ppm/K Notes
Current Inputs Energy Calculation
AS8218 AS8228 have identical mains current inputs, I1P/I1N I2P/I2N, measurement both Live Neutral currents. Either current inputs selected calculating energy value. These differential current inputs second order Sigma-Delta modulators, with each inputs being provided with selectable gains selectable gains provided that AS8218 AS8228 easily adapted with either current transformers alternatively shunt resistor current transformer current sensing. AS8218 AS8228 also used conventional single current configuration with either current transformer shunt resistor being used current sensing.
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Data Sheet AS8218 AS8228
current input signal levels programmed means on-chip programmable gain settings. required gain setting selected follows:
Current Input Gain Settings Gain Input Voltage -30mVV 30mV -38mVV 38mV -150mVV 150mV -30mVV 30mV -38mVV 38mV -150mVV 150mV Comments Shunt mode; default setting mode shunt mode mode Shunt mode mode shunt mode mode; default setting
Current Inputs I1P,
Current Inputs I2P,
Notes: connected VSSA. Refer Settings Register (SREG) section programming Gain Settings. optimum operating conditions, input signal Maximum Current condition should ±30mVp, when Gain ±150mVp, when Gain default Gain, AS8218 AS8228 current input gain settings without programming required, Gain input Gain input. value ideal shunt resistor, calculated follows: Assuming rating (rms) 84.85A (peak), then shunt value 350µ would suitable.
Rshunt
30mVp 84.85
thus standard 300µ shunt resistor selected.
mains currents sampled 3.4956kHz, assuming that recommended crystal oscillator frequency 3.5795MHz, used. current transformer(s) must terminated with voltage setting resistor ensure optimum voltage input level current input(s) AS8218 AS8228 ICs. value calculated follows:
secondary current rated conditions ains where in(p) peak input voltage rated conditions mains example, Gain in(p) should 150mVpeak.
Example: current transformer specified 60A/24mA Gain
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Data Sheet AS8218 AS8228
150mV 24mA
4.42
Voltage Input Energy Calculation
voltage channel input consisting inputs differential, with connected resistor divider circuit line voltage connected VSSA. optimum operating conditions, input signal should 100mVp rated voltage condition. resistor values ideal voltage divider calculated follows: Assuming mains 230V (rms) 325V (peak) (according voltage divider shown below), value R1A+R1B calculated follows:
Vmains R1A+R1B
Vmains Vin(P) Vin(P)
100mV 1.53M 100mV
thus 820k 750k resistors selected. mains voltage also sampled 3.4956kHz, assuming that recommended crystal oscillator frequency 3.5795MHz used.
Digital Signal Processing Block (DSP)
digital signal processing (DSP) block provides signal processing required ensure that specified measured accuracy performed that microcontroller (MCU) provided with appropriate data protocol perform required meter functions. description below, please refer following block diagram (Figure makes allowance phase correction current channels within Sinc decimation filters phase correction block. applicable phase correction setting (pcorr_i1 pcorr_i2) selected (sel_i), depending upon which current being used power calculation. equalization filters voltage current channels which by-passed (sel_equ), correct attenuation introduced decimation filters edge input frequency band, while high pass filters, which also by-passed (sel_hp), eliminate offsets introduced into input channels.
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Data Sheet AS8218 AS8228
Independent calibration voltage (cal_v) current signals (cal_i1 cal_i2) done after voltage current signals provided power calculation. This ensures that calibration voltage (sos_v), current channel (sos_i1), current channel (sos_i2) influence power (np) calibration. iMux (current multiplexer) allows selection applicable current power calculation (sel_i), while vMux (voltage multiplexer) allows selection either mains voltage data, constant voltage value, vconst (sel_v). multiplication appropriately selected voltage current signals then performed. After multiplication, next multiplexer (sel_p) enables selection either instantaneous power real power, which filtered through pass filter, PLP. direction indicator output (diro) derived from output power pass filter (PLP). following multiplexer (creep) allows selection power signal, blocks power signal, depending required anti-creep starting current thresholds, which microcontroller. Only when constant voltage value (vconst) selected vMux (voltage multiplexer) when diro=1, necessary derive absolute power value, measurement (Abs). first pulse generator (Fast Pulse Gen) produces fast internal pulses, with number pulses being proportional measured energy. multiplexer enables selection appropriate pulse level (pulselev_i1 pulselev_i2) depending current being used energy measurement (sel_i). output Fast Pulse always directly proportional pulse output, generated Pulse Gen. output pulse rate selectable (mconst). polarity output pulses also selectable (ledpol). ensure that power data transferred microcontroller (MCU) identical that pulses, power accumulator (P_ACCU) counts pulses generated Fast Pulse Gen. After defined number sampling periods (nsamp), interrupt sent MCU, collect accumulated energy data.
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Data Sheet AS8218 AS8228
pddeton
Registers
PD_DET
alarm
Phase Correction
Filter
Filter
Square
Accu
sos_v
cal_v
Filter
Filter
Square
Accu
sos_i1
cal_i1
Filter
sel_equ
Filter
sel_hp sel_i
Square
Accu
sos_i2
cal_i2 vconst
sel_i
iMux
vMux
sel_v
pcorr_i1 pcorr_i2
sel_p diro
creep
sel_v
nsamp
pulselev_i1 pulselev_i2
sel_i
Fast Pulse
P_ACCU
Pulse mconst ledpol
Figure
block diagram
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Data Sheet AS8218 AS8228
Phase Correction
provides phase correction current channels means Sinc decimation filters phase correction block. Only phase correction settings (pcorr_i1 pcorr_i2) valid time, depending which current been selected power calculation (sel_i). phase correction step size dependent upon main oscillator frequency selected mains frequency mains Assuming 3.579545MHz crystal oscillator frequency 50Hz mains frequency, phase corrected steps 2.41' 0.04 degrees, which equal oversampling sample, `unit' table below: pcorr Phase Correction [unit(s)] -127 -128 -255 -256
`unit' equals certain phase shift related mains frequency:
unit 360°
360° mains 360° mains mains
Phase unit 360°
mains fosc
where fmains mains frequency fOSC oscillator frequency.
Example: unit 360° mains
units 2.41' 10.26°
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Data Sheet AS8218 AS8228
Calculating Phase Correction Factors
measured phase_error percentage defined following formula
phase error
cos( phase shift cos( 60°) cos( 60°)
while phase_shift degrees, calculated follows:
phase error phase shift arccos cos( 60°)
phase correction -phase shift
required phase correction factor determined from error measurements with power factor (PF) less than Assuming that meter been calibrated error approximately (calibration current), reduced effect phase differences results increased error (`phase_error'). Example: phase_error 60°) measured related phase shift calculated using following formula:
phase error phase shift where phase_error measured error percentage phase angle.
phase_error 9.2[%] phase_shift -3.0° phase correction 3.0°. 3.579545MHz mains 50Hz, phase correction unit represents 2.41', which 0.04023°. Thus phase correction factor must
74.57 units 0.04023 units. pcorr register 4bh.
Equalization Filters
equalization filters voltage current channels correct attenuation effects introduced decimation filters around frequency band limit. resulting transfer curve after equalization filter approximately attenuation over entire frequency band. equalization filters by-passed (sel_equ), required.
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Data Sheet AS8218 AS8228
High-Pass Filters
high pass filters voltage current channels, with corner frequencies <10Hz, correct offsets introduced into input channels. Each voltage current channels separate high pass filter order avoid phase shift being introduced between voltage current channels. high pass filters also by-passed (sel_hp), desired. Corner frequency: <10Hz
Calculations
provides voltage current channel data `sum-of-squares' format. calculate values from voltage (sos_v) current (sos_i1 sos_i2), following formula should applied voltage current respectively:
Vrms
nsamp nsamp nsamp nsamp
nsamp
where
sos_v value
Irms
nsamp
where
sos_i value
nsamp should selected order achieve coherent sampling close possible: e.g. 3.4956kHz 3.579545MHz) nsamp 3496 should selected interrupted every second. When mains 50Hz, mains periods monitored. Refer Squareroot Block (SQRT) detailed description programming sequence squareroot input operand.
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Data Sheet AS8218 AS8228
Calibration Channels
single channel data corrected with 16-bit calibration value. calibration range LSB; LSB], step size LSB): 3.052
Calibration Register Setting
0000h 0001h 2000h 4000h 8000h FFFFh
Value
0.00003052 LSB) 0.25 1.99996948 1LSB)
channel calculation calibration described below channel identical, thus only channel shown): ideal values after calculations voltage current are: RMS_V(ideal) 479(rms) RMS_I(ideal) 292,110(rms) These values assume ideal input conditions with 100mVp rated conditions 30mVp (Gain rated conditions. e.g: 292,110 I(ideal)
292,110 48,685
non-ideal components different value calculated: RMS_I(actual). From this, required calibration factor calculated using following formula:
I(ideal) I(actual)
following formula calculates actual value programmed into calibration registers (cal_v; cal_i1; cal_i2):
i(reg) hex(round(cal 32,768
Constant Voltage Register (vconst)
vconst registers (9334h 9335h) provide predefined voltage value that used calculating energy when mains available.
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default value vconst 2877 (0B3Dh) which translates into equivalent mains value 311V. energy calculated using vconst selected current when sel_v SREG/Select register `1'. vconst value calculated according formula:
vconst
Example: RMS_V vconst 2,128 Note: When vconst used calculation energy, sel_p must `0'. (Once voltage channel been calibrated, typical value when mains 230V)
Pass Filter Real Power (PLP)
When instantaneous power pass filtered result practically value power, which termed real power. generally preferred real power generate pulses calibration, duration between pulses more constant (pulse jitter). Corner frequency: 18.6Hz
pass filter ensures that power output pulse jitter minimised.
Direction Indicator (DIRO)
direction indicator (DIRO) situated Status Register (Bit defines direction measured power. direction determined phase relationship between Mains voltage selected Mains current i2). When Status Register `0', Mains voltage selected Mains current phase, thus indicating positive energy flow. When Status Register `1', Mains voltage selected Mains current have phase reversal, indicating negative energy flow. energy calculation (np) generated from positive energy, thus when DIRO negative energy converted positive energy `Abs' block shown Figure block diagram. Should meter application require unidirectional energy measurement, separately derive both positive negative energy values, depending status DIRO bit.
Accumulator Real Power (P_ACCU)
ensure that power information transferred identical that pulses, P_ACCU counts pulses generated Fast Pulse Gen. After `nsamp' (nyquist) sampling periods interrupt sent requesting fetch energy information. (Interrupt line `IE.0' goes high `data available interrupt' (dai) flag SREG/Status register set). `ack' SREG/Status register also takes energy information, reset `ack' signalling that energy information
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been taken. `ack' reset P_ACCU will `old' energy information `new' energy information accumulated following cycle. event, must reset flag order clear interrupt.
Wait fast pulse
fast pulse?
Increment P_ACCU
nsamp reached?
P_ACCU (old) P_ACCU IE.0
Note: above flow chart assumes that flag always reset time before next interrupt generated.
Pulse Generation
pulse generators provided ensure that virtually pulse rate output programmed display calibration purposes. first pulse generator (Fast Pulse Gen) produces fast internal pulses. These fast pulses accumulated power accumulator (P_ACCU) energy data transfer MCU. second pulse generator (LED Pulse Gen) produces output pulses (meter constant) from fast internal pulses. This type data interface ensures that receives exactly same energy information displayed pulses. case `creep', power samples added will This advantage that previously recorded energy lost remains exactly same. following flow chart shows basic flow diagram pulse generation:
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Wait next power samples
power sample accu
Accu> threshold defined pulse_lev?
Generate pulse
Fast Pulse output pulse rate always same relationship with pulse rate defined mconst. Only calibrated meter constant different from those provided mconst table, will fast internal pulse rate different. Formula fast internal pulse rate
PRint 204,800
Pulse Rate mconst
where mconst meter constant.
1,000 3,600 PRint
when impulse representing energy equivalent.
Active Power Calibration (Pulse_lev)
This paragraph describes active power measurement within AS8218 AS8228 calibrated. parameter Pulse_lev main parameter which determines output frequency Fast Pulse Gen. This frequency relates measured power basis from which output pulse rate derived. Prior system calibration, appropriate value parameter Pulse_lev must calculated produce required output pulse rate. calibration exercise must accommodate non-idealities that present meter system. Pulse_lev specified such that typical pulse rate 204,800i/kWh achieved. During energy pulse calibration correct Pulse_lev determined order desired pulse rate. default value Pulse_lev defined =40A mains =230V. Default Pulse_lev: 570,950 Example Pulse_lev calculations:
Pulse lev(ideal)
Pulse lev( default Vmains Imax
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mains
Pulse_lev (ideal)
228,380 285,475 380,633 570,950 1,141,900 2,283,800 218,864 273,580 364,774 547,160 1,094,321 2,188,642
Notes
Default setting
Pulse_lev(ideal) 230/V mains 40/I 570,950
Comparison Calibration Method
most common calibration method comparison energy reading meter under test against standard reference meter. Normally, standard, reference meter considerably higher pulse rate than meter under calibration. Reference meter output pulses then counted between consecutive pulses. facilitate calibration procedure, pulse counter provided MPIO block. this case, absolute calibration time calibration current relevant calibration cycle. basic calibration setup shown below:
AS82xx
Pulse Counter
Reference Meter
Figure
Basic setup comparison calibration method (using example input)
Note: used push-button input used input reference meter pulses during calibration. standard reference meter pulses counted between pulses from meter calibrated. Ideally pulses would exactly ratio between standard meter reference pulse rate pulse rate meter under test. From deviation corrected Pulse_lev calculated.
Pulse lev(corrected) Pulse lev(ideal)
where ideal number pulses actual number pulses (PCNT register MPIO).
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ideal number pulses ratio between pulse rates, which always formula follows:
PR(ref Pulse Rate(mconst
where PR(ref) reference meter constant.
Pulse_lev (ideal) calculated using following formula:
Pulse lev(ideal)
Pulse lev( default Vmains Imax
Example
reference meter pulse rate, which 10,000 times greater than pulse rate AS8218 AS8228 output. During calibration cycle measure 11,000 pulses between pulses. Therefore ideal Pulse_lev changed factor 10,000/11,000 0.909.
Meter Constant Selection (mconst, 9330h)
pulses derived directly from fast internal pulses (204,800i/kWh). `mconst' register SREG specifies pulse rate:
mconst[3] mconst[2] mconst[1]
mconst[0]
Symbol mconst[3]
Function used
used used used
Bit3
Bit2
Bit1
Bit0
Pulse Rate
204,800 102,400 51,200 25,600 12,800 6,400 3,200 1,600
mconst[2]
mconst[1]
mconst[0]
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target meter constant different from selectable (mconst) meter constants defined above: e.g. 1,000i/kWh (Target Pulse Rate)
same formula
PR(ref used, calculated using Target Pulse Rate: Pulse Rate(mconst
PR(ref Pulse Rate
(Important: Select pulse rate which close mconst, Target Pulse Rate, that Pulse_lev stays within reasonable limits.) After this calibration energy equivalent fast pulse (1i) different! Standard: internal pulse rate: 204,800i/klWh
1,000 3,600[Ws 17.58 204,800
When special pulse rate required, following formula applies:
1,000 3,600 PulseRate 204,800 etPulseRate
Example: Assuming pulse rate 1,000 required: 1,600 204,800 1,000 204,800 1,000/1,600
1,000 3,600[Ws 28.13 204,800 1,000 1,600
Mains Current Leads/Lags Mains Voltage
i_lead flag SREG/Status register determines mains current leads mains voltage lags mains voltage. data provided reactive power calculation, establish measured power capacitive inductive.
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Output Timing
pulses output indicate amount energy that been consumed over certain period time. Each pulse equivalent that SREG/mconst register exactly. unit impulses (i/kWh). This output used calibration. polarity pulses selected ledpol SREG/Select Register either positive negative going pulses.
Timing Diagram
Timing Parameters Parameter
Pulse width
Symbol
Unit
Notes
duty cycle enabled when period less than 160ms. mconst=0, will 17.9µs.
Register Interface
register block contains data Meter Data Register (MDR) Settings Register (SREG), hence only interface required.
Meter Data Register (MDR)
meter data register updated after `nsamp' samples. Then interrupt issued MCU, which take energy data process them further When interrupt generated `ack' SREG/Status register set. takes data, reset `ack' bit. `ack' been reset when data ready, previous value will added one. case flag SREG/Status register must reset order clear interrupt.
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following table shows data which available MDR:
Register Name
samptoend[7:0] samptoend[15:8] np[7:0] np[15:8] np[23:16] np[31:24] sos_v[7:0] sos_v[15:8] sos_v[23:16] sos_v[31:24] sos_v[35:32] sos_i1[7:0] sos_i1[15:8] sos_i1[23:16] sos_i1[31:24] sos_i1[39:32] sos_i1[47:40] sos_i1[53:48] sos_i2[7:0] sos_i2[15:8] sos_i2[23:16] sos_i2[31:24] sos_i2[39:32] sos_i2[47:40] sos_i2[53:48]
Address
9300h 9301h 9302h 9303h 9304h 9305h 9306h 9307h 9308h 9309h 930Ah 930Bh 930Ch 930Dh 930Eh 930Fh 9310h 9311h 9312h 9313h 9314h 9315h 9316h 9317h 9318h
Reset Value
Description
Indicates many samples left (until nsamp), before next interrupt generated. Using this information determine still time transfer data memory.
number fast pulses, equivalent energy information accumulated during nsamp samples
squares voltage channel samples
squares current channel samples
squares current channel samples
Notes: read-only MCU. (except `MCU debug mode', then register values described.) Unused addresses will simply ignored. following flowchart describes accumulators registers work together:
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Accumulate fast pulses (np); accumulate squares (sos)
reset MCU?
Reset np-register (MDR)
nsamp reached?
Transfer sosaccus registers (MDR/sos)
P_ACCU np-register
Clear accus P_ACCU
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Settings Register (SREG)
settings register contains data stored MCU, which used, example, calibration purposes, also general settings like input gain.
Register Name
pcorr_i1[7:0] pcorr_i1[8] pcorr_i2[7:0] pcorr_i2[8] cal_v[7:0] cal_v[15:8] cal_i1[7:0] cal_i1[15:8] cal_i2[7:0] cal_i2[15:8] pulselev_i1[7:0] pulselev_i1[15:8] pulselev_i1[23:16] pulselev_i2[7:0] pulselev_i2[15:8] pulselev_i2[23:16] mconst[3:0] nsamp[7:0] nsamp[15:8] vconst[7:0] vconst[13:8] Select Gains Status
Address
9320h 9321h 9322h 9323h 9324h 9325h 9326h 9327h 9328h 9329h 932Ah 932Bh 932Ch 932Dh 932Eh 932Fh 9330h 9331h 9332h 9333h 9334h 9335h 9336h 9337h 9338h
Reset Value
Description
Sets phase correction current channel
Sets phase correction current channel
Calibration factor voltage channel. Only acts sos_v data. Calibration factor current channel Only acts sos_i1 data. Calibration factor current channel Only acts sos_i2 data. Pulse_lev fast pulse generation current channel selected (sel_i).
Pulse_lev fast pulse generation current channel selected (sel_i). Meter constant pulse generation used Sets number samples before next update MDR. predefined voltage value which used energy calculation event Vmains being available. Select register Gain settings register Status register
Note: Unused addresses will simply ignored. Unspecified bits will also ignored.
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Select Register (Select, 9336h)
ledpol sel_p sel_i sel_v sel_hp
sel_equ
Symbol Function
ledpol sel_p Selects polarity pulses: negative going pulses used used Select between instantaneous real power pulse generation instantaneous power real power (low-pass filtered instantaneous power) Select current channel power calculation (Fast Pulse Gen) Select voltage channel data selects voltage channel analog input selects predefined constant `vconst' Select high-pass filter high-pass Select equalisation filter equalizer high-pass equalizer positive going pulses (default)
sel_i sel_v
sel_hp sel_equ
Gain Settings Register (Gains, 9337h)
gain_i2[1] gain_i2[0] gain_i1[1]
gain_i1[0]
Symbol Function
gain_i2[1] Gain setting current channel modulator used used used used
gain_i2[0]
Bit1 Bit1
Bit0 Bit0
Gain Gain
gain_i1[1] Gain setting current channel modulator
gain_i1[0]
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Status Register (Status, 9338h)
creep i_lead diro pddeton alarm
Symbol Function
creep Indicator creep situation, used disable signal pulse generation creep creep Debug Mode flag Enables written MCU. This useful debugging when programmer wants know exactly what received from block. normal mode debug mode described later data sheet. Indicates mains current leads lags mains voltage. mains current lags (inductive) mains current leads (capacitive) DIRO indicator, signals when voltage current phase 180° phase difference 180° phase difference only read MCU. Enables power-down detector functionality PD_DET functionality
i_lead diro
pddeton alarm
PD_DET
Indicates when Vmains falling below predefined threshold. this happens interrupt generated alarm flag set. interrupt will reset only when alarm flag reset. alarm alarm that Vmains Data Available Interrupt flag Indicates that interrupt been generated because meter data available. interrupt interrupt data only DSP. Resetable only software (MCU). clear `dai' means that back
Acknowledge bit, indicates transferred newly available data memory DSP, when data ready MDR. (not settable MCU!) Reset MCU, when data have been taken. When gets reset contents MDR-np zero. `P_ACCU' always adds contents MDR-np last value just before transfers data MDR. Thus, ack=0 MDR-np reset nothing added P_ACCU. been cleared data still available added P_ACCU.
Current Channel Comparison
current channels compared microcontroller (MCU), greater currents required energy calculation. This done comparing calculated values currents. threshold changing from visa versa) also MCU.
Creep Detection
standards specify that pulses must generated when there current flow (`creep'). Additionally there threshold current when meter must generate pulses case (`starting current'). Therefore detection circuit must guarantee that these situations under control. AS8218 AS8228 current channel data evaluated find there `creep' situation. related signal used stop pulse generation required.
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Debug Mode
When flag SREG/Status register set, block enters debug mode. Here written through interface. this mode block allowed write MDR. Special functionality: (i.e. must again MCU) when reset value doubled, i.e. shift left done. Note: Also debug mode interrupt generated after nsamp samples.
Power Supply Monitor (PSM)
AS8218 AS8228 have on-chip power supply monitor (PSM) that ensures reset generated independently supply voltage (VDD) rise fall times. built hysteresis provided accommodate slow changes VDD, ensure clean signal switching.
Parameter
Threshold positive edge Threshold negative edge Hysteresis
Table
Symbol
Vth,pos Vth,neg Hyst
Unit
Notes
Power supply monitor: Power-on reset specifications
ensure sufficient time available store meter data EEPROM during power-down, necessary detect falling supply voltage fast possible. Should only monitored, external capacitor 3.3V power supply could sustain supply voltage even after mains begun fall. this reason, AS8218 AS8228 allow monitoring mains ensure early power-down detection. power-down detector function (PD_DET) enabled SREG/Status register. alarm signal generated, when mains falls below specified mains voltage threshold, which enables react with sufficient time. also possible calculate energy during power-down detection, taking constant voltage value calculation energy value. mains voltage threshold calculated follows:
Vmains (alarm)
Vmains V(ideal)
173.8
External System Reset (RES_N)
external reset (RES_N) provided system reset. RES_N active (i.e. logic will initiate system reset). system reset RES_N OR-ed with main system power-on reset generated power supply monitor PSM. RES_N internally pulled high. used, RES_N should left unconnected.
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System Timing Real Time Clock (RTC)
power crystal oscillator using 4.0MHz crystal provides AS8218 AS8228 system timing. power oscillator internally connected power divider, which provides signal real time clock, which precision trimmed.
VDD_BAT
XOUT Power Oscillator Power Divider
div[19:0]
Register Interface
Mclk
Figure System timing block diagram
clk_1hz
Power Oscillator (LP_OSC)
power oscillator connected external 4.0MHz crystal. oscillator operated modes, namely normal mode power mode. power mode operational when remainder circuit (not operational). Should suitable external clock signal preferred, this directly connected pin, which through output `Mclk'. this case, XOUT left unconnected.
Parameter
Current consumption, normal mode Current consumption, power mode Frequency range Supply voltage range Duty cycle
Symbol
Iosc,norm Iosc,bat fosc VDD_BAT duty_cyc
Unit
Notes
VDD_BAT 2VDC 25°C
3.579545
Power Divider (LP_DIV, 9130h 9132h)
main oscillator output frequency (Mclk) divided down real time clock (RTC). option alternative crystal frequencies still derive clock signal real time clock (RTC), provided through this internally programmable divider. power-saving reasons, fast oscillator clock first divided down fixed ratio (divide then programmable divider follows.
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Mclk
div5
programmable divider
clk_1hz
div[19:0]
Parameter
Input frequency range Supply voltage range Division factor
Symbol
fMclk VDD_BAT
3.579545
1,048,575
Unit
Notes
setting div[19:0] located registers (addresses: 9132h 9130h) Note: division factor effective frequency Mclk/5. represents actual division factor minus Example: Calculate oscillator frequency 3,579,545Hz. frequency after div5 715,909Hz. Therefore, must 715,909 715,908. (Setting means division factor stops clock.
Real-Time Clock (RTC)
directly accessed from dedicated interface register. alarm registers provided indicate certain time instance, such start month. that case interrupt sent MCU. Constant frequency deviations crystal that used trimmed accuracy better than +/-1.4ppm. seconds counter provided which used certain meter calculations. There only interrupt output. source interrupt indicated Control/Status register.
Register Interface
Time/ Calendar Registers Alarm Registers Seconds Counter Frequency Trim LP_DIV Setting
LP_DIV
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Registers
Register Name
Seconds Minutes Hours Days Week Month Century Years Control Status Control Status Seconds Timer Byte Seconds Timer Byte Minute Alarm Hour Alarm Alarm Month Alarm Years Alarm Minute Alarm Hour Alarm Alarm Month Alarm Years Alarm Divider Register Byte Divider Register Byte Divider Register Byte Frequency Trim
Address
9100h 9101h 9102h 9103h 9104h 9105h 9106h 9110h 9111h 9112h 9113h 9114h 9115h 9116h 9117h 9118h 9119h 911Ah 911Bh 911Ch 911Dh 9130h 9131h 9132h 9133h
Reset Value
Notes
[7:0] [7:0] (LP_DIV) [7:0] [15:8] (LP_DIV) [3:0] [19:16] (LP_DIV)
Notes: illegal values (i.e. defined following tables, e.g. `0', code, correct last month, correct leap year) written time/date registers (00h 06h), they corrected first valid number (`automatic correction')! Then interrupt generated flag Control/Status register set. other registers corrected (e.g. alarm info incorrect alarm met). After power-up VDD_BAT time/date registers stopped, WAIT flag (Control/Status set. Unused addresses will simply ignored.
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Control Status Register (9110h)
WAIT
Symbol Function
WAIT used used used Indicates that waiting start signal. start signal WAIT being reset WAIT running normally. (Clear MCU.) WAIT when time/calendar information changed (access registers 9100h 9106h). While waiting start signal, clock still gated MPIOs. used used used used
Register assignment: (Unassigned bits registers marked with `-`. these bits read they will return zero value. Writing these bits effect.)
Control Status Register (9111h)
AIE2 AIE1
Symbol Function
Time Setting Alarm: Indicates when impossible time/date been been corrected automatically, e.g. February February. interrupt will generated interrupt cleared setting TSA=0 (done (software)).
used logic when alarm occurs maintains this value until software clears Indicates source interrupt. Cannot software. When flag cleared, also interrupt cleared. logic when alarm occurs maintains this value until software clears Indicates source interrupt. Cannot software. When flag cleared, also interrupt cleared. logic when seconds timer interrupt occurs maintains this value until software clears Indicates source interrupt. Cannot software. When flag cleared, also interrupt cleared. AIE2 alarm interrupt disabled AIE2 alarm interrupt enabled AIE1 alarm interrupt disabled AIE1 alarm interrupt enabled seconds counter interrupt disabled seconds counter interrupt enabled
AIE2 AIE1
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Note: Alarm interrupts only generated rising clk_1hz edges (using system clock detection). This means that enabling alarm after that will generate interrupt.
Seconds Register (9100h)
sec.6 sec.5 sec.4 sec.3 sec.2 sec.1
sec.0
Symbol Function
reliable clock calendar information guaranteed. clock calendar information guaranteed. This after power-up VDD_BAT. cleared software only. These bits represent current seconds value encoded format (values from 59).
sec.6 sec.5 sec.4 sec.3 sec.2 sec.1 sec.0
Minutes Register (9101h)
min.6 min.5 min.4 min.3 min.2 min.1 These bits represent current minute value encoded format (values from 59).
min.0
Hours Register (9102h)
hour.5 hour.4 hour.3 hour.2 hour.1 These bits represent current hours value encoded format (values from 23).
hour.0
Days Register (9103h)
day.5 day.4 day.3 day.2 day.1 These bits represent current value encoded format (values from 31). Note leap years: `00' years general leap years unless complete year divided (e.g. 2000). Since year 2000 passed already, this chip will consider leap year `00' years.
day.0
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Week Register (9104h)
weekd.2 weekd.1
weekd.0
Symbol
weekd.2
Function
used used used used used These bits represent current weekday value.
Bit2
Bit1
Bit0
Sunday Monday Tuesday Wednesday Thursday Friday Saturday
weekd.1
weekd.0
Month Century Register (9105h)
month.4 month.3 month.2 month.1
month.0
Symbol
Function
Century bit. indicates year 20xx indicates year 21xx `xx' indicates value held Years register. This modified when Years register overflows from
month.4
used used These bits represent current month value encoded format.
Bit4
Bit3
Bit2
Bit1
Bit0
Month
January February March April
month.3
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Symbol
month.2
Function
June July August September October November December
month.1
month.0
Year Register (9106h)
year.7 year.6 year.5 year.4 year.3 year.2 year.1 These bits represent current year value encoded format (value from 99). Alarm generated when programmed time been reached (seconds 0!).
year.0
Minute Alarm Register (1/2) (9114h/9119h)
mina.6 mina.5 mina.4 mina.3 mina.2 mina.1 These bits represent minute alarm information encoded format (values from 59).
mina.0
Hour Alarm Register (1/2) (9115h/911Ah)
houra.5 houra.4 houra.3 houra.2 houra.1 These bits represent hour alarm information encoded format (values from 23).
houra.0
Alarm Register (1/2) (9116h/911Bh)
daya.5 daya.4 daya.3 daya.2 daya.1 These bits represent alarm information encoded format (values from 31).
daya.0
Month Century Alarm Register (1/2) (9117h/911Ch)
mona.4 mona.3 mona.2 mona.1
mona.0
These bits represent current month alarm value encoded format (value from 12). Please also `month assignments' table above.
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Year Alarm Register (1/2) (9118h/911Dh)
yeara.7 yeara.6 yeara.5 yeara.4 yeara.3 yeara.2 yeara.1 These bits represent year alarm value encoded format (value from 99).
yeara.0
Setting Time
time writing respective time calendar registers. When this done clock stops, WAIT control waits WAIT reset through System Control). When WAIT reset clock gate will opened starts running.
Alarms
When time alarm registers match (seconds interrupt generated. source interrupt indicated A[1|2]F register bits Control/Status register. alarm generation disabled using AIE1/2 bits. When rest chip off, there clock interface, hence alarm will generated. interface reset with `res' signal which coming from PSM, i.e. Status bits reset default, which means that after power-up appropriate alarms again. (After power-up check what time decide what next appropriate alarms will be.)
Seconds Timer (9112h, 9113h)
seconds counter block, enabled (SIE Control/Status register), generates interrupt every seconds. number seconds specified Seconds Timer registers 9112h (Byte 9113h (Byte When interrupt sent, flag set. Seconds Timer register coded. Seconds counter start value: Seconds counter count direction: Condition interrupt generation: 0000h Seconds counter register value Seconds Timer register value
Note: 0000h timer register means that interrupt must generated.
Calibration (clk_1Hz)
When using real-time clock (RTC) essential that signal real-time clock accurate. There many possible external influences crystal oscillator frequency including absolute crystal frequency itself parasitic oscillator capacitor values. These influences alone contribute significant change oscillator frequency. this case, necessary perform calibration signal through `Programmable Divider' located 'Low Power Divider'. procedure trimming 'Programmable Divider' explained below: Assuming crystal frequency 3.579545
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Programmable Divider follows fixed 'Divide divider, thus default value Programmable Divider 3.579545 715909 (default value Programmable Divider) Therefore: change this default value equal 715909 1.397 Measure deviation clk_1Hz frequency output provided AS8218 AS8228 Assuming error +690 measured (faster than real-time) Thus +690 1.397 493.915 Therefore must added default value: 715909 716403 (dec) (hex) Divider Register Byte Divider Register Byte Divider Register Byte then calibrated within
Frequency Trimming (9133h)
further option clk_1Hz frequency trimming available. this case only lower bits register `Frequency Trim' (9133h) used defined following table.
FREQ_TRIM[4:0] Correction [ppm]
87.0 81.2 75.4 69.6 63.8 58.0 52.2 46.4 40.6 34.8 29.0 23.2 17.4 11.6 -5.8 -11.6 -17.4 -23.2 -29.0
Seconds
Seconds
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FREQ_TRIM[4:0] Correction [ppm]
-34.8 -40.6 -46.4 -52.2 -58.0 -63.8 -69.6 -75.4 -81.2 -87.0 -92.8
Seconds
Seconds
table specifies successive days with (possibly) different number seconds that have added subtracted day. `day1/day2' repeated continuously. always adjusted same time: 00:00 a.m. seconds (The seconds required avoid conflicts with alarm settings, which defined occur seconds.) Subtraction means that specified number pulses ignored. This effect that clock stands still specified number seconds. Example: crystal frequency that 30ppm higher than specified. Therefore will faster. Thus, correct negative direction, subtracting seconds. Value `11011' (-29.0) will chosen which means that day1, seconds subtracted, then next seconds subtracted, then seconds again
Battery Backup Operation
AS8218 AS8228 contain real-time clock (RTC) circuit, which must continue operate even when mains supply voltage mains interrupted. battery backup facility provided this purpose VDD_BAT. power oscillator (LP_OSC), power divider (LP_DIV) real time clock (RTC) supplied from VDD_BAT pin. recommended battery backup circuit shown below. battery connected VDD_BAT diodes. external also connected VDD_BAT diode, with battery backup only providing supply AS8218 AS8228 when external interrupted.
external VDD_BAT
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Driver (LCDD)
selvlcd lcdd_pd
VREG
LBP0
Voltage Level Generation
Drive
LBP1 LBP2 LBP3 LSD0
LSD23
LCDD Control
Data Register1 Data Register2
Figure driver block diagram
on-chip driver (LCDD) peripheral block, which interfaces almost liquid crystal display (LCD) having multiplex rate generates drive signals directly drive multiplexed LCDs containing four backplanes segments backplane. AS8218 LCDD, while AS8228 LCDD. data registers receive store display information, which sent display. LCDD control block decodes information into select lines single segments using specific timing. voltage selected adjust contrast display, required. selvlcd[2:0] register bits enable setting contrast selecting defined voltage levels. contrast improved with higher voltage, however contrast also dependent upon crystal frequency.
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Typical Display
above typical example those used electricity meter applications consists number digits (generally digits) including decimal points. Typically, annunciators (`kWh', `Volt', etc.) also included signify type data display.
Drive (LCD_DRIVE)
drive mode 1/4duty, 1/3bias. back planes segment drives (maximum) other parameters listed table below:
Parameter
frame frequency voltage segment back plane drive voltages
Symbol
fLCD VLCD
0.95 VLCD
39.4 VLCD
2.75 1.05 VLCD
Unit
Notes
selvlcd='000'
0.95 2/3VLCD 2/3VLCD 1.05 2/3VLCD 0.95 1/3VLCD 1/3VLCD 1.05 1/3VLCD
component drive impedance load each driver
VDCLCD RLCD Cload
Note: These frequencies derived from master clock (3MHz; 3.58MHz; 4MHz) using divider 90,909.
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LCDD Control (LCDD_CTRL) including Input Config Registers
control block driver there registers. Each these registers contain data displayed. With special (921Eh, possible select register banks display. Each register defines settings different segment plane select lines. following table specifies allocation register bits:
LSD0 LBP0 LBP1 LBP2 LBP3
reg[0] reg[1] reg[2] reg[3]
LSD1
reg[4] reg[5] reg[6] reg[7]
LSD2
reg[8] reg[9] reg[10] reg[11]
LSD3
reg[12] reg[13] reg[14] reg[15]
LSD4
reg[16] reg[17] reg[18] reg[19]
LSD5
reg[20] reg[21] reg[22] reg[23]
LSD6
reg[24] reg[25] reg[26] reg[27]
LSD7
reg[28] reg[29] reg[30] reg[31]
LSD8
reg[32] reg[33] reg[34] reg[35]
LSD9
reg[36] reg[37] reg[38] reg[39]
LSD10 LBP0 LBP1 LBP2 LBP3
reg[40] reg[41] reg[42] reg[43]
LSD11
reg[44] reg[45] reg[46] reg[47]
LSD12
reg[48] reg[49] reg[50] reg[51]
LSD13
reg[52] reg[53] reg[54] reg[55]
LSD14
reg[56] reg[57] reg[58] reg[59]
LSD15
reg[60] reg[61] reg[62] reg[63]
LSD16
reg[64] reg[65] reg[66] reg[67]
LSD17
reg[68] reg[69] reg[70] reg[71]
LSD18
reg[72] reg[73] reg[74] reg[75]
LSD19
reg[76] reg[77] reg[78] reg[79]
LSD20 LBP0 LBP1 LBP2 LBP3
reg[80] reg[81] reg[82] reg[83]
LSD21
reg[84] reg[85] reg[86] reg[87]
LSD22
reg[88] reg[89] reg[90] reg[91]
LSD23
reg[92] reg[93] reg[94] reg[95]
AS8228 only
Notes: Each register bits represents segments digits decimal point annunciators. reg[x]=0: Segment turned off; reg[x]=1: Segment turned
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complete register organized bytes according following table:
Register Name
reg1[7:0] reg1[15:8] reg1[23:16] reg1[31:24] reg1[39:32] reg1[47:40] reg1[55:48] reg1[63:56] reg1[71:64] reg1[79:72] reg1[87:80] reg1[95:88] reg2[7:0] reg2[15:8] reg2[23:16] reg2[31:24] reg2[39:32] reg2[47:40] reg2[55:48] reg2[63:56] reg2[71:64] reg2[79:72] reg2[87:80] reg2[95:88] use_reg
Address
9200h 9201h 9202h 9203h 9204h 9205h 9206h 9207h 9208h 9209h 920Ah 920Bh 9210h 9211h 9212h 9213h 9214h 9215h 9216h 9217h 9218h 9219h 921Ah 921Bh 921Eh
Reset Value
Description
AS8228 only
AS8228 only Selects register used. Data Register Data Register Select VLCD level. table Voltage Select Register. Power-down LCDD analog part. Display Display
selvlcd[2:0] lcdd_pd
921Fh 9220h
Notes: Unused registers will simply ignored. registers write only. Read operations always return
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Display Data Select Register (USE_REG, 921Eh)
use_reg register selects either Data Register Data Register display LCD. Select Data Register Data Register
use_reg
Voltage Select Register (SELVLCD, 921Fh)
voltage select register, SELVLCD enables variation contrast selecting preset voltage levels.
selvlcd.2 selvlcd.1
selvlcd.0
Symbol
selvlcd.2
Function
used used used used used These bits voltage level contract setting.
Bit2
Bit1
Bit0
VLCD
2.5V 2.5714V 2.6428V 2.7142V 2.7856V 2.8570V 2.9284V 3.0V
selvlcd.1
selvlcd.0
Power-Down (LCDD_PD, 9220h)
lcdd_pd register enables analog part LCDD powered-down. Select display display off.
lcdd_pd
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Drive Signals: Timing Levels
following graphic shows examples timing drive signals.
LSD0
LSD1
LSD2
LSD3
LSD4
LSD5
LBP0 LBP1 LBP2 LBP3 CLKLCD Frame LBP0 LBP1 LBP2 LBP3
Figure multiplexing waveform
LSD0 LSD1 LSD2 LSD3 LSD4 LSD5
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Programmable Multi-Purpose I/Os (MPIO)
Config Register sel_in sel_pupd en_io sel_drv
UART2
rxd2 txd2
en_io0
InputMultiplexer [11:0]
out_io0 in_io0
DATA REGISTERS Input Register [11:0]
out_mux
Output Register [11:0] Output Multiplexer [11:0]
clk_1hz
sel0_io[x] sel1_io[x] register[x] txd2 clk_1hz
IO11
out_io[x]
Pulse Counter sel_refp
[11:0]
Figure
MPIO block diagram
total bidirectional multi-purpose pins (MPIO) provided with AS8218 bidirectional multipurpose pins with AS8228, which used variety purposes. I/Os freely programmed inputs outputs, with option either pull-up pull-down resistor. drive strength individual pins also programmed. start-up pins disabled. Furthermore, pulse counter available, which used calibration purposes (`comparison calibration method': Between pulses pulses from reference meter with much higher pulse rate counted. result used calculate calibration factor.).
MPIO Registers
MPIO registers listed table below. individual register functions then described detail.
Register Name Config
MAKE_IRQ0 MAKE_IRQ1 OUT_MUX0 OUT_MUX1
Address
9500h 9501h 9502h 9503h
Reset Value
Notes
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Register Name
OUT_MUX2 SET_EN0 SET_EN1 SEL_DRV0 SEL_DRV1 SEL_PUPD0 SEL_PUPD1 SEL_IN_RXD2 SEL_IN_REFP
Address
9504h 9505h 9506h 9507h 9508h 9509h 950Ah 950Bh 950Ch
Reset Value
Notes
Input
950Dh 950Eh
Output
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 950Fh 9510h 9511h 9512h 9513h 9514h 9515h 9516h 9517h 9518h 9519h 951Ah AS8228 only
Pulse counter
PCNT0 PCNT1 PCNT2 951Bh 951Ch 951Dh
Status
STATUS0 STATUS1 951Eh 951Fh
Note: Unused addresses ignored.
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MAKE_IRQ0/MAKE_IRQ1 (9500h/9501h)
MAKE_IRQ registers specify interrupt should generated after related input changed. pin, which caused interrupt, will indicated STATUS0/STATUS1 flag registers. IOx: interrupt signal change generate interrupt signal change MAKE_IRQ0
MAKE_IRQ1 IO11 IO10 AS8228 only
OUT_MUX0/OUT_MUX1/OUT_MUX2 (9502h/9503h/9504h)
OUT_MUX registers specify source signal each outputs. Every bits used select signals 4-way output multiplexer designated I/O. OUT_MUX0
IO3: sel1 OUT_MUX1 IO3: sel0 IO2: sel1 IO2: sel0 IO1: sel1 IO1: sel0 IO0: sel1
IO0: sel0
IO7: sel1 OUT_MUX2 IO7: sel0 IO6: sel1 IO6: sel0 IO5: sel1 IO5: sel0 IO4: sel1
IO4: sel0
IO11: sel1 IO11: sel0 IO10: sel1 IO10: sel0 IO9: sel1 IO9: sel0 IO8: sel1 AS8228 only following table shows settings output signal options:
IO8: sel0
sel1
sel0
Output Signal Notes
register[x] txd2 clk_1hz 80ms pulse width
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SET_EN0/SET_EN1 (9505h/9506h)
SET_EN registers en_io signal related pin. en_io enables tri-state output buffer that pins operate outputs. IOx: disable output (I/O used input) enable output SET_EN0
SET_EN1
IO11 IO10 AS8228 only
SEL_DRV0/SEL_DRV1 (9507h/9508h)
SEL_DRV registers select current drive strength I/Os that have been selected outputs: IOx: SEL_DRV0
SEL_DRV1
IO11 IO10 AS8228 only
SEL_PUPD0/SEL_PUPD1 (9509h/950Ah)
SEL_PUPD registers select either pull-up pull-down resistor each pins: IOx: pull-down pull-up SEL_PUPD0
SEL_PUPD1
IO11 IO10 AS8228 only
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SEL_IN_RXD2 (950Bh)
SEL_IN_RXD2 register selects which input used special input signal `rxd2' (UART2 receive input). I/Os from IO11 selected this purpose. select bits defined following table:
sel3 sel2 sel1
sel0
Input IO10 IO11
AS8228 only
SEL_IN_REFP (950Ch)
SEL_IN_REFP register selects which input used reference pulses. I/Os from IO11 selected this purpose. select bits defined following table:
sel3 sel2 sel1
sel0
Input
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Input IO10 IO11
AS8228 only
IN0/IN1 (950Dh/950Eh)
registers (input registers) store input data from pins. These registers continuously updated `Mclk' (main clock).
IO11 IO10 AS8228 only
OUT0 OUT11 (950Fh 951Ah)
registers (output registers) contain output data sent pins (through multiplexers). OUT0
OUT1
OUT2
OUT3
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OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
AS8228 only OUT10
AS8228 only OUT11
IO10
AS8228 only
IO11
PCNT0/PCNT1/PCNT2 (951Bh/951Ch/951Dh)
PCNT registers (pulse counter registers) contain result pulse counting calibration purposes. PCNT0
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PCNT1
PCNT2
maximum reference pulse frequency defined below:
Parameter
Reference pulse frequency
Symbol
frefp
Unit
Notes
STATUS0/STATUS1 (951Eh/951Fh)
STATUS registers contain flag register bits each I/Os, COUNT register which signals when pulse counting should started CINT flag which indicates when pulse counting been completed. flag registers cleared software only (MCU), they cannot software. COUNT register reset software (MCU). COUNT register cleared, when pulse counter finished interrupt been generated. STATUS0
STATUS1
COUNT CINT IO11 IO10 AS8228 only
Notes: IOx: change input input changed When interrupt change been generated, signal reset after related flag been cleared. CINT flag, which indicates that pulse counting finished. When CINT cleared, cleared.
Pulse Counter
synchronous pulse counter used. started after COUNT been set. first pulse used synchronisation. second pulse starts counting reference pulses from specified input.
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Timing:
COUNT Gate refp counted refp CINT
Notes: COUNT signal synchronized with `led'. COUNT reset CINT using checking falling edge Gate. PCNT register only updated when counting finished. Example: Select pulse reference input. Meter 220V mains Meter constant: 1,600imp/kWh Reference meter constant: million imp/kWh Register settings: MPIO SET_EN0 SEL_IN_REFP mconst
(9505h): (950Ch): (9330h):
(output disabled)
(Ideal) Pulse_lev (932Ch 932Ah)
570,950
1,193,804 12374Ch
932Ah: 932Bh: 932Ch:
Procedure: Status1 (951Fh): starts pulse counting. When pulse counting completed CINT Status1 status CINT Status1 checked confirm that pulse counting complete. Alternatively, time between pulses calculated determine count cycle time (the first pulse used synchronization second pulse starts count cycle). Following pulse counting cycle, number pulses counted read from PCNT0/PCNT1/PCNT2 (951Bh/951Ch/951Dh).
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ideal number pulses counted assuming meter perfectly calibrated would
16,000,000 10,000 1,600
Assuming that count 11,000 pulses, (Ideal) Pulse_lev must changed factor: 10,000/11,000 0.909 Pulse_lev 1,193,804 0.909 1,085,168 108EF0h 932Ah: 932Bh: 932Ch:
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) represents synchronous, serial 4-wire interface full-duplex data transfer. It's primarily used here communicate with external EEPROM memory, which must fulfil requirements described below. EEPROM selectable size from 1kByte 32kByte binary steps. always operates master mode, whereas EEPROM works slave mode. bootloader controls during system start After that available free programming.
Signals
Name
Type
Input Output Output Output
Description
Serial input from slave device Serial output slave Clock output slave device Chip select output slave device (low active)
EEPROM
EEP_S_N EEP_SC EEP_SI EEP_SO 3.3V EEP_HOLD_N EEP_WP_N
Master
AS8218/ AS8228
Figure Typical connection EEPROM
Many EEPROMs provide HOLD_N (hold protocol) WP_N (write protect), which must held `1', otherwise operation blocked. During startup phase, bootloader takes control over generates read sequence automatically.
Features
Standard wire synchronous serial interface (SI, S_N) Master mode operation only 8-bit word length (variable transmit/receive word optional) Shift clock high when idle always transmitted first Four selectable clocking schemes (clock idle state clock phase) Selectable clock rate divider (from mcu_clk/2 mcu_clk/65536) Three maskable interrupts (transmission complete, overrun, collision)
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Each protocol starts putting level ends putting high again. goes high before normal protocol, current protocol terminated, internal state control logic reset. line state (don't care). When operating (S_N data shifted falling edge incoming data sampled rising edge
TS_N_setup 1/fSC=TSC Tbyte_to_byte TS_N_hold
(out)
Shift data with falling edge
(out)
Sample input data rising edge
(out)
(in)
Transfer Data byte
Transfer Data byte
Figure timing diagram
Note: shifted falling edge sampled rising edge (clock scheme: CPHA=1, CIDLE=1). mcu_clk (max)
Parameter
TS_N_setup TS_N_hold Tbyte_to_byte TSC_LOW TSC_HIGH
Description
Time between going first falling edge Time between last rising edge going high Time between data bytes (LSB last next) serial clock period 1/FSC) serial clock minimum time serial clock minimum high time
MCU_clk cycles
Units
Registers
Register Name
SSPCON SSPCLKDIV SSPSTAT SSPBUF
Address Description
9400h 9401h 9402h 9403h Control register Clock divider register Status register Data register
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Control Register (SSPCON, 9400h)
control register used enabling SPI-interrupts control chip select SPI.
IETR IEOV IECO IECS AUTO
Symbol Function
IETR Transmit interrupt enable Issued after data register been serially loaded with data (slave mode) data been shifted after write access (master mode) disable enable Overrun interrupt enable Issued ITRA still data serially arrived disable enable Write collision interrupt enable Issued data register written during transmission disable enable Chip select interrupt enable Issued chip-select activated during master/slave mode disable enable Chip select output state master mode AUTO Inverted state output signal (active) used Automatically activates '0') after data been written data register deactivates '1') after transfer completed depends manual setting) used
IEOV
IECO
IECS
AUTO
Recommended programming SSPCON with interrupts enabled:
Mode
Auto mode Manual S_N=1 (inactive) Manual S_N=0 (active)
SSPCON
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Clock Divider Register (SSPCLKDIV, 9401h)
clock divider register contains control bits configure clock-divider, set-up serial-clock enable select master slave mode.
ENBL CIDLE CPHA CLKDIV.3 CLKDIV.2 CLKDIV.1
CLKDIV.0
Symbol
ENBL
Function
enable. Enables interface enable disable Serial clock idle state idles high idles
CIDLE
CIDLE Bit6
CPHA Bit5
Idle
Data shifted Input sampled
falling rising rising falling rising falling falling rising
CPHA
Serial clock phase Data samples shifted according CIDLE/CPHA
Note: CIDLE/CPHA used internally most standard available EEPROMs
Master/Slave mode Master mode, must Slave mode (stops operation), there slave mode available CLKDIV.3 Clock divider exponent Bit3 Bit2 master mode, output clock CLKDIV+1 MCU_CLK
Bit1
Bit0
SC-Rate
1,024 2,048 4,096 8,192 16,384 32,768 65,536
CLKDIV.2
CLKDIV.1
CLKDIV.0
output clock which derived from clock (mcu_clk) divided down shown table above.
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important note, that mcu_clk also divided down described under MCUCLKDIV Register (`mcu_clk'). Therefore output clock also dependent programming mcu_clk frequency. Recommended programming 3.579545MHz clock rate, enabled, clock phase `11', master:
Value
1.74MHz 0.895MHz 0.447MHz
Clock Rate
Status Register (SSPSTAT, 9402h)
ITRA
IOVR ICOL
Symbol Function
ITRA1 IOVR ICOL
Transmission complete interrupt issued. Issued after data word available data-register (slave configuration), data-register been shifted after write access (master configuration) Overrun interrupt issued. Issued ITRA still from previous transmission data arrives (master slave configuration) Write-collision interrupt issued. Issued data-register written during receive (slave configuration) transmit (master configuration) used Always `0', effect used used used
Note: Flag-bits change state independent state corresponding interrupt-enable control register.
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interrupt status captured SSPSTAT register. Each interrupt status masked SSPCON register, which OR-ed single interrupt request signal (SPI_IRQ).
Register SSPSTAT ITRA SSPCON
IOVR
SPI_IRQ
ICOL IE.ESPI (=IE.3) IETR, IEOV, IECO
Figure Block diagram
Data Register (SSPBUF, 9403h)
data-register 8-bits wide shift-register with parallel load input parallel output. written read normal operation bootloader during startup phase.
parallel SPI_DATAIN from MCU/Bootloader
serial
serial
parallel SPI_DATAOUT MCU/Bootloader
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External EEPROM Requirements
external EEPROM with serial interface used non-volatile program data storage. master block that communicates with EEPROM specified above. This section explains requirement Serial EEPROMs. shows most important figures tables reference. details please turn data sheet your specifically applied EEPROM. following minimum requirements must fulfilled:
Pins
There must least typical pins like serial data input (EEP_SI), serial data output (EEP_SO) serial clock input (EEP_SC), chip select input (EEP_S_N)
Clock Rate
applicable clock rate EEP_SC must 1MHz allow correct bootloading maximum mcu_clk 4MHz.
Status Register
must look like this: don't care AS8218 AS8228 bootloader/SCT
must bit, indicating that write operation progress. Only this polled during EEPROM upload, means programming EEPROM. Status register accessed RDSR instruction.
Data Protection
write protection block size given table below:
Status Register Bits
Protected Block
None Upper quarter Upper half Whole memory
Array Addresses Protected Example only
None 6000h 7FFFh 4000h 7FFFh 0000h 7FFFh
Note: array addresses must referenced from data sheet specific EEPROM used.
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BP1, allows selection protection schemes. order protect against inadvertent programming user these bits. Please note that protected range EEPROM cannot overwritten command there anymore. Reprogramming must done with dedicated program then.
Instruction
There must least instructions with coding shown table they deployed bootloader download user program unit upload user program EEPROM.
Instruction Name
READ WRITE
Instruction Description Format
Read data from memory starting with selected address Write data memory beginning selected address. Most EEPROMs allow page writing pages even more bytes faster device programming. Before every page write operation WREN instruction must applied also bootloading uploading sequence details. Write enable EEPROM, enables write operation Read EEPROM Status register, required AS8218 AS8228
WREN RDSR
Modes
These devices driven microcontroller with peripheral running either following modes: CPOL CPHA CPOL CPHA recommended CPOL CPHA your program: build-in bootloader uses this setting well.) these modes, input data latched rising edge Serial Clock (SC), output data issued falling edge Serial Clock (SC). recommended mode shown Figure clock polarity when master Stand-by mode transferring data (idle state): remains (CPOL CPHA
EEP_SC(in) EEP_SI(in) EEP_SO(out
Figure modes recommended
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Address Roll Over
When highest address EEPROM reached, e.g. 7FFFh 32kB device, then address counter must roll over 0000h.
Unused Upper Address Bits
Unused upper address bits must ignored case. E.g. device maximum address 1FFFh must interpret 7FFFh 1FFFh, ignoring higher bits.
Program Length
program length stored topmost locations, means 32kB EEPROM 7FFEh 7FFFh. possible smaller EEPROM long guaranteed that upper unused address bits ignored address roll over performed after highest address
Timing AS8218 AS8228 Boot Sequence
Detailed timing generated AS8218 AS8228 section.
Figure Timing diagram
diagram shows sequence applied EEPROM after device reset. EEP_SI line see: (READ) (address high) (address low) EEP_SO line answer EEPROM. this case first values forming program length, means 0022h bytes fetched stored program memory (P_RAM). next values 02h, 00h, (LJMP 0016h) representing first bytes program code.
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Example List
Name
EEP_S_N
Type
Input
Functionality
Chip select, active
Description
When this input signal High, device deselected Serial Data Output (SO) high impedance. Unless internal Write cycle progress, device will Standby mode. Driving Chip Select (S_N) enables device, placing active power mode. This output signal used transfer data serially device. Data shifted falling edge Serial Clock (SC). This input signal used transfer data serially into device. receives instructions, addresses data written. Values latched rising edge Serial Clock (SC). This input signal provides timing serial interface. Instructions, addresses data present Serial Data Input (SI) latched rising edge Serial Clock (SC). Data Serial Data Output (SO) changes after falling edge Serial Clock (SC).
EEP_SO EEP_SI
Output Input
Serial data output Serial data input
EEP_SC
Input
Serial clock
EEP_WP_N
Input
Write protect, active main purpose this input signal freeze size area memory that protected against Write instructions specified values bits Status register). This must driven either High must stable during write operations. Hold, active Hold (HOLD_N) signal used pause serial communications with device without deselecting device. During Hold condition, Serial Data Output (SO) high impedance, Serial Data Input (SI) Serial Clock (SC) Don't Care. start Hold condition, device must selected, with Chip Select (S_N) driven Low.
EEP_HOLD_N
Input
EEP_VCC EEP_VSS
Supply Positive supply voltage Supply Negative supply voltage
Note: Write Protect (EEP_WP_N) Hold (EEP_HOLD_N) pins available AS8218 AS8228 ICs. These pins must tied `high' directly EEPROM device.
Instructions Timings
Write Enable (WREN)
EEP_S_N(in) EEP_SC(in) EEP_SI(in) EEP_SO(out
Figure Write enable (WREN) sequence
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Read Status Register (RDSR)
EEP_S_N(in) EEP_SC(in) EEP_SI(in) EEP_SO(out
Figure Read Status register (RDSR) sequence
Read from Memory Array (READ)
EEP_S_N(in) EEP_SC(in)
EEP_SI(in) EEP_SO(out
Figure Read from memory array (READ) sequence
Write Memory Array (WRITE)
EEP_S_N(in) EEP_SC(in)
EEP_SI(in) EEP_SO(out
Figure Byte write (WRITE) sequence
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EEP_S_N(in)
EEP_SC(in)
EEP_SI(in)
EEP_S_N(in)
EEP_SC(in)
EEP_SI(in)
Figure Page write (WRITE) sequence
Uploading Programs using
order allow direct access EEPROM standard RS232 interface AS8218 AS8228 provide UART protocol converter. system control (SCT) instructions involved called READ_P (F3h) WRITE_P (F4h), which used upload user software user data EEPROM. Doing READ_P allows verification written data, respectively. Example Write EEPROM UART Converter:
UART
EEP_SI EEP_SO
WRITE_P
WREN
Address
Block Length
Data1
Data2
WAIT Prog.Time
RDSR loop until WIP=0 `xxxx xxx0'
ACKN
Write
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WRITE_P
ADDRESS
BLOCK LENGTH
DATA1
DATA2
Read Status Register
Figure Timing diagram
After having finished write sequence, EEPROM goes programming state about 10ms (depending EEPROM type). AS8218 AS8228 read Status register loop until bit0 (write progress) goes low. Then UART transmits acknowledge instruction FAh. Example Read EEPROM Locations 1FF0 1FF1: EEP_SO expected transmitted.
UART
EEP_SI EEP_SO
READ_P
READ
Address
Block Length
Data1
Data2
don't care activity, idle
READ_P
ADDRESS
BLOCK LENGTH
DATA1
DATA2
1000
00000
(03)
(1F)
(F0) (21) (42)
Figure Timing diagram
stop
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8051 Microcontroller (MCU)
derivative well-known 8051 microcontroller. block consists 8051 compatible microprocessor core, program memory (P_RAM), data memory (X_RAM), squareroot calculation unit UARTs debugging communication purposes. Special Function Registers (SFR) section enfolds standard blocks like timer (Timer bytes internal data memory (I_RAM) serial interface (UART1). Furthermore, squareroot block second serial interface (UART2) also provided. Timer Port UART implemented exactly same original 8051. Instead, extension (Port single chip 8051) provides access on-chip periphery, which comprises serial peripheral interface (SPI), real time clock (RTC), nine general purpose I/Os (MPIO), driver (LCDD), block that interfaces analog front system control registers (SCT). block configured Neumann architecture with program memory (P_RAM) section staring from 0000h data memory (X_RAM) periphery section starting from 8000h FFFFh. 64kB memory accessed with both, MOVC instruction (for program fetches data read) MOVX instruction (for data read/store). interrupt controller enfolds internal interrupt sources, having necessary peripherals already chip.
Serial EEPROM Display
Internal Interrupt Sources
Interrupt Control
bytes I_RAM
Timer
24kB P_RAM
Boot Load
LCDD
Clock Divider
SQRT
UART2
X_RAM
UART1
MPIO
Mclk
rxd2
txd2 I/Os
Figure block diagram
Legend 8051 compatible microcontroller core I_RAM bytes static RAM, range 8051 X_RAM 1024 bytes static RAM, (extended) memory data storage P_RAM 24kB static RAM, primarily program storage, maybe used also data Timer timer (due 8051 standard) UART1 serial interface RS232 (due 8051 standard) with extended baudrate generator
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Data Sheet AS8218 AS8228
UART2 serial interface RS232 with extended baudrate generator SQRT square root calculation bytes bits) input, bytes bits) output SPI. serial peripheral interface, used access external EEPROM Bootload downloads program data after reset, combined with LCDD driver block real time clock, time/data UART1 (SCT) MPIO. multi-purpose pins, configurable inputs outputs digital signal processing unit interfaces analog front (AFE) AFE. analog front end, includes amplifiers converters system control unit, combined with UART1 used debugging/programming device
Features
8051 compatible oriented microcontroller core bytes internal data memory (I_RAM) 24kB program memory (P_RAM) data memory (X_RAM) Neumann architecture, shared program data memory Cycle optimized compared standard 8051, some instructions executed single clock cycle bytes range Standard SFRs: Timer UART1 (with baudrate reg.) Specific SFRs: UART2 (with baudrate reg.), SQRT block Fully compatible 8051 instruction including instruction internal interrupt sources Ports implemented accessible registers Register PCON implemented idle mode PCON Automatic bootload application program after power-on reset clock cycles instruction cycles standard 8051) data pointer DPTR
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Data Sheet AS8218 AS8228
Instruction
instruction fully compatible 8051 standard. This allows commonly available software development tools Assembler, C-Compiler code simulators. instructions marked with note cycle optimised execute single cycle compared cycles standard 8051 controllers.
Code
Mnemonic
AJMP LJMP ACALL LCALL AJMP
Operands
Code
Mnemonic
ACALL RETI ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC AJMP ACALL
Operands
addr, code addr code addr
code addr code addr addr, code code addr code addr addr, code code addr #data
#data code addr code addr dir, dir, #data #data code addr code addr dir, dir, #data #data
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Data Sheet AS8218 AS8228
Code
Mnemonic
AJMP ACALL SJMP AJMP MOVC
Operands
code addr code addr dir, dir, #data #data code addr code addr addr @A+DPTR #data dir, #data @R0, #data @R1, #data #data #data #data #data #data #data #data #data code addr code addr addr @A+PC dir, dir, dir, dir, dir, dir, dir, dir, dir, dir, dir,
Code
Mnemonic
ACALL MOVC SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB AJMP ACALL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE
Operands
DPTR, #data code addr addr, @A+DPTR #data /bit addr code addr addr DPTR (reserved) @R0, @R1, /bit addr code addr addr #data, code dir, code @R0, #data, code @R1, #data, code #data, code #data, code #data, code #data, code #data, code #data, code #data, code #data, code
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Data Sheet AS8218 AS8228
Code
Mnemonic
PUSH AJMP SWAP ACALL SETB SETB DJNZ XCHD XCHD DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ
Operands
Code
Mnemonic
MOVX AJMP MOVX MOVX MOVX ACALL MOVX MOVX
Operands
@DPTR code addr @DPTR, code addr @R0, @R1, dir, @R0, @R1,
code addr addr code addr addr dir, code addr code addr code addr code addr code addr code addr code addr code addr code addr
variable I_RAM code addr address code memory data immediate data addr. address bit-addressable I_RAM Notes: number bytes number cycles Optimised execution single cycle; normally cycles
Addressing Modes
comprises standard 8051 addressing modes. completeness they listed here. There five types. byte instructions destination specified first, then source.
Mode
Register addressing Direct addressing
Examples
Notes
Register I_RAM banks selected Moves contents
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Data Sheet AS8218 AS8228
Mode
Register indirect addressing Immediate addressing Index addressing
Examples
@R0, MOVX @DPTR, #data MOVC @A+DPTR MOVC @A+PC
Notes
Moves contents location addressed DPTR Moves immediate #data Moves contents location addressed A+DPTR, A+PC reading lookup tables, applies program memory only
Interrupt Controller
8051 core provides interrupt sources: them same standard 8051, others tied specific internal sources. Each interrupt causes program jump corresponding interrupt vector interrupt enabled interrupt enable register (IE). interrupt priority controlled interrupt priority register (IP) order override predefined priority, starting with IP.0 highest. further information interrupt sources refer appropriate chapters.
Interrupt Enable Register (IE)
Each interrupt sources individually enabled disabled setting corresponding register. This register contains global enable clearing this interrupts disabled once.
ERTC ESPI EIOX
EDSP
Enable disables interrupt Enable enables interrupt
Interrupt Priority Register (IP)
PRTC PSPI PIOX
PDSP
Priority assigns high priority Priority assigns priority
Interrupt Source Interrupt Vector
0033h
UART2 002Bh
UART1 0023h
001Bh
MPIO 0013h
Timer 000Bh
0003h
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Data Sheet AS8218 AS8228
Symbol
ERTC ESPI EIOX EDSP Note:
Position IE.7
IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
Function Disables interrupt when each interrupt individually enabled enable bit. real time clock, interrupt enable UART2, serial port, interrupt enable UART1, serial port, interrupt enable serial port, interrupt enable MPIO external pin, interrupt enable Timer interrupt enable data available
Priority
Lowest
Highest
Standard 8051 bits
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Data Sheet AS8218 AS8228
Interrupt Priorities
Each interrupt source individually assigned priority levels. priority interrupt always interrupted higher-priority interrupt, another priority interrupt. high-priority interrupt cannot interrupted other interrupt source. corresponding then this interrupt serviced first another interrupt request occurs same time where zero. Interrupt same priority level serviced internal polling sequence starting with highest down lowest.
Symbol
PRTC PSPI PIOX PDSP Note:
Position IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0
Function Real time clock, priority UART2 serial port, priority UART1 serial port, priority serial port, priority MPIO external pin, priority Timer priority priority
Source Flags
TSA, STF, A1F, ITRA Status Status dai, alarm
Standard 8051 bits
Source PDSP
Register
Register
Priority Level High Priority Level
High Priority Interrupt
PIOX
PSPI
Polling Sequence
PRTC Priority Interrupt
Global enable Individual enables
Figure Interrupt control system
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Data Sheet AS8218 AS8228
Memory Maps
MCU51 configured Neumann architecture merging program data range into 64kB address space. This space completely accessible MOVX partly accessible MOVC (0000h 5FFFh). Besides, there typical 8051 structure with bytes internal memory (I_RAM) special function registers (SFRs) also byte address space.
IDATA Memory FFFFh unused 9FFFh C000h unused Direct addressing A000h 9000h 8000h Internal Memory 6000h 5FFFh bytes I_RAM 24kB P_RAM 0000h unused X_RAM
9500h 9400h 9300h 9200h 9100h 9000h
SFRs
Special Function Registers
unused
MPIO LCDD
Direct addressing Register addressing banks) addressing
Register indirect addressing MOVX @DPTR MOVX @DPTR, MOVC @A+PC MOVC @A+DPTR MOVX @Ri, MOVXA, with {R0, R1}, represents upper address bits
only 0000h 5FFFh
Program Memory (P_RAM)
P_RAM shares address output data lines with X_RAM. 24kB 64kB addressable memory used: 0000h 5FFFh program storage.
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Data Sheet AS8218 AS8228
Data Memory (X_RAM) Block Interfaces
following table shows start (and stop) addresses X_RAM block interfaces. These locations accessed with MOVX instruction.
Start Address
8000h 9000h 9100h 9180h 9200h 9300h 9400h 9500h
Stop Address
83FFh 9002h 9133h 9181h 9220h 9338h 9403h 951Fh
Contents
X_RAM Registers Registers Registers LCDD Registers Registers Registers MPIO Registers
Detailed Memory map:
Address Contents
8000h 9000h 9100h 9104h 9108h 910Ch 9110h 9114h 9118h 911Ch 9130h 9180h 9200h 9204h 9208h 920Ch 9210h 9214h 9218h 921Ch 9220h Seconds/VL Weekdays Cont./Status1 Min.Alarm YearsAlarm Mon. Alarm DivReg WDTE reg1[7:0] reg1[39:32] reg1[71:64] reg2[7:0] reg2[39:32] reg2[71:64] lcdd_pd
Address Contents
83FFh 9001h 9101h 9105h 9109h 910Dh 9111h 9115h 9119h 911Dh 9131h 9181h 9201h 9205h 9209h 920Dh 9211h 9215h 9219h 921Dh X_RAM enable signals Minutes Months/Cent. Cont./Status2 Hour Alarm Min.Alarm YearsAlarm DivReg WDTCLK[1:0] reg1[15:8] reg1[47:40] reg1[79:72] reg2[15:8] reg2[47:40] reg2[79:72]
Address Contents
Address Contents
9002h 9102h 9106h 910Ah 910Eh 9112h 9116h 911Ah 911Eh 9132h
mcuclkdiv[2:0] Hours Years Sec.Tim.B Alarm Hour Alarm DivReg
9003h 9103h 9107h 910Bh 910Fh 9113h 9117h 911Bh 911Fh 9133h
Days Sec.Tim.B Mon. Alarm Alarm Freq. Trim
9202h 9206h 920Ah 920Eh 9212h 9216h 921Ah 921Eh reg1[23:16] reg1[55:48] reg1[87:80] reg2[23:16] reg2[55:48] reg2[87:80] use_reg 9203h 9207h 920Bh 920Fh 9213h 9217h 921Bh 921Fh reg1[31:24] reg1[63:56] reg1[95:88] reg2[31:24] reg2[63:56] reg2[95:88] selvlcd[2:0] LCDD
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Address Contents
9300h 9304h 9308h 930Ch 9310h 9314h 9318h 931Ch 9320h 9324h 9328h 932Ch 9330h 9334h 9338h 9400h 9500h 9504h 9508h 950Ch 9510h 9514h 9518h 951Ch samptoend [7:0] np[23:16] sos_v[23:16] sos_i1[15:8] sos_i1[47:40] sos_i2[23:16] sos_i2[53:48] pcorr_i1[7:0] cal_v[7:0] cal_i2[7:0] pulselev_i1 mconst[3:0] vconst[7:0] Status SSPCON make_irq0 out_mux2 sel_drv1 sel_refp out1 out5 out9 pcnt1
Address Contents
9301h 9305h 9309h 930Dh 9311h 9315h 9319h 931Dh 9321h 9325h 9329h 932Dh 9331h 9335h 9339h 9401h 9501h 9505h 9509h 950Dh 9511h 9515h 9519h 951Dh samptoend [15:8] np[31:24] sos_v[31:24] sos_i1[23:16] sos_i1[53:48] sos_i2[31:24] pcorr_i1[8] cal_v[15:8] cal_i2[15:8] pulselev_i2 vconst[13:8] SSPCLKDIV make_irq1 set_en0 sel_pupd0 out2 out6 out10 pcnt2
Address Contents
9302h 9306h 930Ah 930Eh 9312h 9316h 931Ah 931Eh 9322h 9326h 932Ah 932Eh 9332h 9336h 933Ah 9402h 9502h 9506h 950Ah 950Eh 9512h 9516h 951Ah 951Eh np[7:0] sos_v[7:0] sos_v[35:32] sos_i1[31:24] sos_i2[7:0] sos_i2[39:32] pcorr_i2[7:0] cal_i1[7:0] pulselev_i1 pulselev_i2 nsamp[7:0] Select SSPSTAT out_mux0 set_en1 sel_pupd1 out3 out7 out11 Status0
Address Contents
9303h 9307h 930Bh 930Fh 9313h 9317h 931Bh 931Fh 9323h 9327h 932Bh 932Fh 9333h 9337h 933Bh 9403h 9503h 9507h 950Bh 950Fh 9513h 9517h 951Bh 951Fh np[15:8] sos_v[15:8] sos_i1[7:0] sos_i1[39:32] sos_i2[15:8] sos_i2[47:40] pcorr_i2[8] cal_i1[15:8] pulselev_i1 pulselev_i2 nsamp[15:8] Gains SSPBUF out_mux1 sel_drv0 sel_in out0 out4 out8 pcnt0 Status1 MPIO
Note: Shaded addresses available with AS8228 only.
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Data Sheet AS8218 AS8228
Internal Memory (I_RAM)
bytes I_RAM provided, which accessed address modes. memory directly addressable. register addressable four banks. Bank switching done (Program Status Word). addressable, which means that each these registers set/cleared separately.
I_RAM Locations
40-47 00-07 48-4F 08-0F 50-57 10-17 58-5F 18-1F 60-67 20-27 68-6F 28-2F 70-77 30-37 78-7F 38-3F
first bytes internal memory addressed instructions using register addressing mode (register bank following bytes bits, address 2Fh) addressed instructions using direct-bit addressing mode. address space from accessible direct addressing mode only. Gray-shaded registers used register indirect addressing.
Special Function Registers (SFR)
following table shows locations Special Function Registers. SFRs bold style original 8051 registers. SFRs italic style additional registers specific AS8218 AS8228 ICs.
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Locations
SQRTIN0 SCON2 SOVR2 SCON SOVR TCON SQRTIN1 SBUF2 SBUF TMOD SQRTIN2 SBAUDL2 SBAUDL SQRTIN3 SBAUDH2 SBAUDH SQRTIN4 SQRTOUT0 SQRTOUT1 T0PRE SQRTOUT2
bytes address space available using direct addressing mode. following table describes register bytes:
Symbol
DPTR TMOD TCON SCON SBUF T0PRE SOVR SBaudL SBaudH SCON2 SBUF2
Register Name
Accumulator Register Program Status Word Stack Pointer Data Pointer Bytes Byte High Byte Port Port Interrupt Priority Control Interrupt Enable Control Timer Mode Control Timer Control Timer High Byte Timer Byte Serial Control (UART1) Serial Data Buffer (UART1) Timer Prescaler Serial Overflow (UART1) Serial Baudrate (UART1) Serial Baudrate High (UART1) UART2 Control UART2 Serial Data Buffer
Address Notes
Standard Registers
Custom Registers
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Data Sheet AS8218 AS8228
Symbol
SBaudL2 SBaudH2 SOVR2 SQRTIN0 SQRTIN1 SQRTIN2 SQRTIN3 SQRTIN4
Register Name
UART2 Baudrate UART2 Baudrate High UART2 Overflow Square Root Input [7:0] Square Root Input [15:8] Square Root Input [23:16] Square Root Input [31:24] Square Root Input [39:32]
Address Notes
Writing this location triggers squareroot calculation
SQRTOUT0 Square Root Output [7:0] SQRTOUT1 Square Root Output [15:8] SQRTOUT2 Square Root Output [23:16]
Notes: Ports exist. Timer implemented (and related SFRs). Ports connected pins. used register general. However, used X_RAM access, when `@Ri' used register indirect addressing mode (with being either R1). that case will form higher byte X_RAM address. IE/IP: sources interrupts defined interrupt controller section. TCON, TMOD, TH0, described section Timer SCON, SBUF, SBaudL, SBaudH, SOVR related UART1 described UART section. SCON2, SBUF2, SBaudL2, SBaudH2, SOVR2 related UART2 described UART2 section.
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Data Sheet AS8218 AS8228
Squareroot Block (SQRT)
This SQRT block calculates square root input value (mapped eight input registers). output number which mapped eight output registers. calculation starts immediately after least significant byte been written address E8h). square root calculation Gypsi- radicand algorithm used, which produces clock cycle. Thus after cycles result available SQRTOUT[2:0] registers. Note: interrupt signal connected interrupt controller MCU, because result available after defined period machine cycles. programmer take care correct timing. instance, instructions must inserted before reading result. When writing SQRTIN[39:36] don't care. When reading SQRTOUT[23:20] those bits equal zero.
Data Registers SFR-Address
Name
SQRTIN0 SQRTIN1 SQRTIN2 SQRTIN3 SQRTIN4 SQRTOUT0 SQRTOUT1 SQRTOUT2
Description
Input value[7:0] Input value[15:8] Input value[23:16] Input value[31:24] Input value[39:32] Output value[7:0] Output value[15:8] Output value[19:16]
SQRT4,
SQRT0,
SQRT2,
square root calculation
start calculation
Figure Timing diagram
result available
During time calculation data must overridden. soon register SQRT0 written, calculation sequence retriggered result calculated from latest contents input registers.
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Data Sheet AS8218 AS8228
Boot Loader (BOOTLOAD)
After power-up boot loader loads program data from EEPROM down on-chip P_RAM (Note: Parameters settings stored EEPROM will loaded BOOTLOAD, this will handled program.). Only when this finished chip start with normal operation. also possible trigger bootload during normal operation, when example program been written EEPROM (debugging!)) BOOTLOAD block seen direct interface between P_RAM.
AS8218/AS8228
P_RAM
boot_sel
BOOTLOAD
EEPROM
Figure BOOTLOAD block diagram
EEPROM Data Organisation
Program data stored beginning address 0000h. Program data size must bigger than 24,576 bytes (0000h 6000h-1), P_RAM size. length program must stored topmost bytes. program length given number bytes, expressed hexadecimal. lower byte goes lower address, higher byte higher address. 32kB EEPROM this means: 7FFEh: Length, lower byte, 7FFFh: Length, higher byte. length value bigger than 6000h, bootloader will just stop after 6000h program data bytes. lengt
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