General Description AS1120 direct-driver capable driving segments

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General Description AS1120 direct-driver capable driving segments

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46-Segment Driver
General Description
AS1120 direct-driver capable driving segments with non-multiplexed backplane. device contains integrated serial-to-parallel interface generates necessary signals drive panels. Internal synchronous backplane signal regeneration allows device different drivers with different LCDs superior brightness stability over wide temperature range. device also supports external backplane signals. AS1120 specifically designed easily interface with variety microprocessors wide range panel types. AS1120 available 64-pin LQFP package.
Features
46-Segment Driver Serial-to-Parallel Interface Integrated Oscillator External Backplane Input Supports Alphanumeric Bar-Graph Devices Data Transfer Configurations: Cascade Parallel Non-Multiplexed Backplane Very-Low Current Consumption Power Supply Range: -0.3 +7.0V Operating Temperature Range: 64-pin LQFP Package
Applications
device ideal industrial systems, portablesystem displays, panel meters with wide temperature ranges, high-performance optical displays, other space-limited application with power-consumption single-supply requirements. Figure Application Diagram
+VDD
AS1120
46-bit LCD[0:45]
TEST LOAD RESETN DATAIN CLKIN BPLIN REXT CEXT Divide Shift Register 46-bit DATAOUT BPLOUT VSSOSC Register 46-bit
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AS1120
Datasheet
Pinout Packaging
Assignments Markings
Figure Assignments (Top View) Markings
LCD41 LCD40 LCD39 LCD38 LCD37 LCD36 LCD35 LCD34 LCD33 LCD32 LCD31 LCD30 LCD29 LCD28 LCD27 LCD42 LCD43 LCD44 LCD45 TEST DATAOUT CLKIN LOAD DATAIN BPLIN BPLOUT RESETN VSSOSC
AS1120
LCD26 LCD25 LCD24 LCD23 LCD22 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15
Descriptions
Table Descriptions Number 17:31 34:41 44:47 50:64 Name LCD42:LCD45 TEST DATAOUT CLKIN LOAD DATAIN BPLIN BPLOUT RESETN VSSOSC LCD0:LCD14 LCD15:LCD22 LCD23:LCD26 LCD27:LCD41 Description Connected Output Segments 42:45 Test pin. This must tied VDD. Serial Data Output Shift Register Clock Load Strobe from Shift Register Latch Serial Data Input Backplane Input Backplane Output Active-Low Asynchronous Reset Internal Oscillator Power Ground Oscillator Pad. Internal clock (see page External clock; tied VSSOSC Output Segments 0:14 Output Segments 15:22 Power Ground Positive Power Supply Output Segments 23:26 Output Segments 27:41
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LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14
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AS1120
Datasheet
Absolute Maximum Ratings
Stresses beyond those listed Table cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated Section Electrical Characteristics page implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Table Absolute Maximum Ratings Symbol Parameter Positive Supply Voltage Ground -0.3 -200 +7.0 +200 +150 +150 1000 Unit reflow peak soldering temperature (body temperature) specified accordance with IPC/JEDED J-STD-020D "Moisture/Reflow Sensitivity Classification non-hermetic Solid State Surface Mount Devices" Package related Mil-Std883E 3015.7 methods Norm: JEDEC Comments
VIN, VOUT Digital Input Output Voltage Ground ISCR TJMAX TSTRG Input Current (Latchup Immunity) Maximum Junction Temperature Storage Temperature Package Power Dissipation (TJMAX TAMB)/RTH Electrostatic Discharge Humidity (Non-Condensing)
Package Body Temperature
+260
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AS1120
Datasheet
Electrical Characteristics
Table Electrical Characteristics Symbol TAMB fOSC CSEG Parameter Positive Supply Voltage Ambient Temperature Supply Current Oscillator Frequency Segment Capacitance Backplane Capacitance Verify that compatible with desired temperature range fBPL =50Hz, output connected, TAMB Bpfreq fOSC/16 Conditions +3.0 +5.5 Unit
CMOS Input Pin: TEST (VDD TAMB unless otherwise noted). ILEAK High Level Input Voltage Level Input Voltage Input Leakage Current Input Transition Time
CMOS Input with Schmitt Trigger, Pin: CLKIN, LOAD, DATAIN, BPLIN, RESETN (VDD TAMB unless otherwise noted). VTH+ VTLILEAK Positive-Going Threshold Negative-Going Threshold Input Leakage Current -4mA 3.3V, -2.8mA 3.3V, 3.2mA -25µA 3.3V, -16µA 22µA 3.3V, 17µA 4.5V 5.5V 4.5V 5.5V
CMOS Output Pins: BPLOUT, DATAOUT (VDD TAMB unless otherwise noted). High Level Input Voltage Level Input Voltage
CMOS Output Pin: LCDxx (VDD TAMB unless otherwise noted). High Level Input Voltage Level Input Voltage
Oscillator Pin: (VDD TAMB unless otherwise noted). REXT CEXT fOSC Level Output Voltage (open collector) External Resistance External Capacitance Frequency 1/fOSC 0.69 REXT CEXT
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AS1120
Datasheet
Table Timing Characteristics Symbol tCHP tCLP tSDC tHDC tSLC tHLC tRLP tSRC tDOUT Parameter Time CLKIN high pulse Time CLKIN pulse Time setup DATAIN CLKIN rising edge Time hold DATAIN from CLKIN rising edge Time setup LOAD CLKIN rising edge (active low) Time hold LOAD CLKIN rising edge (active low) Time RESETN pulse (active low) Time setup RESETN CLKIN rising edge Time from CLKIN falling edge DATAOUT
20000
Unit
LOAD must high while RESETN active (low). LOAD stay more than CLKIN cycle. Figure Signal Waveform Timing
tCHP CLKIN
tCLP
tSDC DATAIN
tHDC
tSLC LOAD
tHLC
tSRC tRLP RESETN
DATAOUT
tDOUT
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AS1120
Datasheet
Detailed Description
AS1120 drive segments multiple AS1120 devices cascaded (see Figure page increase number segments. Note: accurate delay balance between backplane input, backplane output, segments, possible segments different display crystal types.
Shift Register
Data accesses made serially pins DATAIN CLKIN. each CLKIN rising edge signal present DATAIN shifted first internal shift register other bits shifted ahead first bit. cascade multiple AS1120 devices (see Figure page last internal shift register presented DATAOUT falling edge same CLKIN pulse. entered first while last shifted into shift register. Note: shift register cleared when AS1120 reset.
Latch Register Error
When signal applied LOAD, data present shift register latched into internal latch register presented output segments (LCD[0:45]), also passing through gate with backplane signal (BPLIN). function necessary generate appropriate signals drive segments. Note: reset latch register cleared, thus segment will active power-on.
Synchronous Mode
Data shifted into internal shift register rising edge CLKIN signal. load shift register data bits clocked into register rising edge CLKIN (see Figure LOAD signal high CLKIN periods before bits. display will updated CLKIN rising edge after LOAD goes high shown Figure Note: During synchronous mode, clock BPLIN must applied avoid risk damaging crystal. Figure Synchronous Mode Timing Diagram
CLKIN Cycles CLKIN Cycles LOAD
DATAIN
LD45 LD44LD43
LD10
CLKIN
Stop
BPLIN
Display
Update
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Revision 1.05
AS1120
Datasheet
Asynchronous Mode
Data preloaded into AS1120 shift register then activated LOAD pulse. preload shift register LOAD signal must stay high data bits clocked into internal shift register rising edge CLKIN (see Figure Note: asynchronous mode, clock signal must applied BPLIN. Asynchronous mode does support AS1120 internal clock. Figure Timing Diagram Preloading Shift Register
CLKIN Cycles
LOAD Always High LOAD
DATAIN
LD45 LD45LD45
LD10 Stop
CLKIN
BPLIN
update display LOAD signal must held least periods clock applied BPLIN, CLKIN must low. Note that since BPLIN normally asynchronous respect LOAD, advisable keep LOAD BPLIN cycles. display will updated BPLIN rising edge while LOAD Low. case internal BPLIN generation through internal oscillator BPLIN fOSC/16. Figure Timing Diagram Updating Display Asynchronous Mode
BPLIN Cycles LOAD
DATAIN
CLKIN Always High CLKIN
BPLIN
Display
Update
Oscillator Backplane Generation
AS1120 generate backplane signal using internal oscillator, externally generated backplane signal supplied. When cascading multiple AS1120 devices (see Figure page only first device should have oscillator running; other devices must BPLIN regenerate backplane signal synchronize their output segments with common backplane.
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AS1120
Datasheet
selection internal external backplane signal (see Table initiated after RESETN disabled first rising edge after RESETN disabled will force BPLOUT deliver internally generated backplane signal. there rising edge OSC, BPLOUT will simply buffer signal BPLIN. Table Backplane Source Generation Selection Mode Internal External Running Tied BPLOUT fOSC/16 BPLIN
Note: should never supplied with static signals. Verify that signals pins BPLIN BPLOUT always running while supplied; note that BPLOUT stopped during reset.
Internal Mode Oscillator Running (Generating Backplane)
Connect external components shown Figure page When external REXT CEXT connected OSC, clock signal whose frequency equal fOSC divided will present BPLOUT. Note: Internal mode requires that BPLIN connected BPLOUT. oscillation period approximately tOSC 1/fOSC 0.69 REXT CEXT, error between expected frequency generated frequency increases indicated Table Table Oscillator Error Rate Expected Oscillator Frequency Figure AS1120 Clock Circuit Error
BPLIN
BPLOUT
Oscillator CLRN
fOSC/16 CLRN
RESETN
AS1120
External Mode: Oscillator Stopped (External Backplane)
Connect order block internal oscillator. this external mode, external backplane signal should presented BPLIN, which will regenerated presented BPLOUT.
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AS1120
Datasheet
Application Information
AS1120 support types static displays. Note: proper display operation, ensure that safely operate within full temperature range AS1120 (see page Figure Cascaded Configuration
Segments
Segments
Segments
LOAD LCD[0:45] +VDD LCD[0:45] +VDD 46-Bit TEST LOAD RESETN DATAIN CLKIN +VDD BPLIN Divide Register 46-Bit TEST LOAD RESETN DATAIN CLKIN BPLIN Divide Register 46-Bit LCD[0:45] +VDD 46-Bit TEST LOAD RESETN DATAIN CLKIN BPLIN Divide Register 46-Bit
AS1120
AS1120
AS1120
46-Bit
Shift Register 46-Bit
DATAOUT
Shift Register 46-Bit
DATAOUT
Shift Register 46-Bit
DATAOUT
BPLOUT
BPLOUT
BPLOUT
VSSOSC
VSSOSC
VSSOSC
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AS1120
Datasheet
Package Drawings Markings
devices available 64-pin LQFP package. Figure 64-pin LQFP Package
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0.05
AS1120
Datasheet
CONTROL DIMENSIONS MILLIMETERS
MILLIMETER SYMBOL MIN. NOM. MAX. 1.60 0.05 1.35 1.40 0.15 1.45
SYMBOL MILLIMETER MIN. NOM. MAX. 0.30 0.35 0.45
0.08 0.08
16.00 BSC. 14.00 BSC. 16.00 BSC. 14.00 BSC. 0.20
0.80 BSC. 12.00 12.00 0.20 0.20 0.10 0.20
3.5°
0.20
0.09 0.45 0.60 1.00 0.20
0.75
Notes: dimensioning tolerancing conform ANSI Y14.5M-1982. package smaller than bottom package 0.15mm. Datums determined datum plane -H-. Dimensions determined seating plane -C-. Dimensions include mold protrusion. Allowable mold protrusion 0.25mm side. body size dimensions including mold mismatch. Detail pin1 identifier optional must located within zone indicated. Dimension does include dambar protrusion. Allowable dambar protrusion 0.08mm excess dimension maximum material condition. Dambar cannot locatedon lower radius foot. Exact shape each corner optional. These dimensions apply flat section lead between 0.10 0.25mm from lead tip. dimensions millimeters.
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AS1120
Datasheet
Ordering Information
device available standard product shown Table Table Ordering Information Type AS1120 Description 46-Segment Driver Delivery Form Tape Reel Package 64-pin LQFP
devices RoHS compliant free halogene substances.
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AS1120
Datasheet
Copyrights
Copyright 1997-2009, austriamicrosystems Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered rights reserved. material herein reproduced, adapted, merged, translated, stored, used without prior written consent copyright owner. products companies mentioned trademarks registered trademarks their respective companies.
Disclaimer
Devices sold austriamicrosystems covered warranty patent indemnification provisions appearing Term Sale. austriamicrosystems makes warranty, express, statutory, implied, description regarding information forth herein regarding freedom described devices from patent infringement. austriamicrosystems reserves right change specifications prices time without notice. Therefore, prior designing this product into system, necessary check with austriamicrosystems current information. This product intended normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment specifically recommended without additional processing austriamicrosystems each application. shipments less than parts manufacturing flow might show deviations from standard production flow, such test flow test location. information furnished here austriamicrosystems believed correct accurate. However, austriamicrosystems shall liable recipient third party damages, including limited personal injury, property damage, loss profits, loss use, interruption business indirect, special, incidental consequential damages, kind, connection with arising furnishing, performance technical data herein. obligation liability recipient third party shall arise flow austriamicrosystems rendering technical other services.
Contact Information
Headquarters austriamicrosystems A-8141 Schloss Premstaetten, Austria Tel: 3136 Fax: 3136
Sales Offices, Distributors Representatives, please visit:
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General Description AS1120 direct-driver capable driving segments

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