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SSD1918

QVGA Graphic Controller with built-in RAM

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1918
Advance Information
QVGA Graphic Controller with built-in RAM
Apr 2006
CONTENTS 1 2 3 4 5 6 GENERAL DESCRIPTION .................................................... 6 FEATURES.................................................................. 6 ORDERING INFORMATION .................................................. 7 BLOCK DIAGRAM .......................................................... 8 DIE PAD FLOOR PLAN ...................................................... 9
5.1 SSD1918L1 LGA PIN OUT .................................................................10
PIN DESCRIPTIONS ........................................................ 13
6.1 6.2 6.3 6.4 6.5 BASEBAND PIN DESCRIPTION ...............................................................13 MAIN DISPLAY PIN DESCRIPTION ............................................................14 SUB DISPLAY PIN DESCRIPTION .............................................................14 POWER PIN DESCRIPTION ..................................................................15 MISCELLANEOUS PIN DESCRIPTION ...........................................................15
FUNCTIONAL BLOCK DESCRIPTIONS....................................... 16
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 BASE BAND INTERFACE ....................................................................16 MAIN DISPLAY INTERFACE .................................................................17 RGB INTERFACE.........................................................................17 GPO SPI...............................................................................17 GPO (DISPLAY CONTROL)..................................................................17 SUB DISPLAY INTERFACE AND BUFFER ........................................................17 GENERAL PURPOSE OUTPUT ................................................................18 DISPLAY TIMING GENERATOR & OSCILLATOR ..................................................18 GRAPHIC DISPLAY DATA RAM (GDDRAM)...................................................18 REGULATOR AND MUX....................................................................18
COMMAND TABLE ......................................................... 19 COMMAND DESCRIPTIONS................................................. 21
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 TOGGLE CODE ...........................................................................21 ON CHIP FREQUENCY GENERATOR (R00H) .....................................................21 ENABLE CHIP SELECT / INTERFACES SELECTION (R01H) ...........................................21 MAIN / SUB DISPLAY DRIVER COMMAND INTERFACE & FREQUENCY (R02H)............................22 GPO CONTROL MAIN (R03H) ...............................................................22 GPO CONTROL SUB (R04H)................................................................22 DOTCLK FREQUENCY (R05H) ..............................................................23 VERTICAL DISPLAY SETTING 1 (R06H) ........................................................24 MAIN DISPLAY CONTROL (R07H) ............................................................24 VERTICAL DISPLAY SETTING 2 (R09H) ........................................................26 HORIZONTAL SETTING 1 (R0AH) ............................................................27 HORIZONTAL SETTING 2 (R0BH) ............................................................27 SLEW RATE CONTROL (R0CH)...............................................................28 SLEW RATE CONTROL2 (R0DH) .............................................................28 ENTRY MODE (R0EH) .....................................................................28 2ND TOGGLE BYTE (R0FH)..................................................................31 VERTICAL DISPLAY SETTING 3 (R12H) ........................................................31 VERTICAL DISPLAY SETTING 4 (R13H) ........................................................31 HORIZONTAL RAM WINDOW SETTING (R14H)..................................................31 VERTICAL RAM WINDOW SETTING (R15H FOR VSA, R16H FOR VEA)...............................32 GDDRAM PAGING SETTING (R17H) .........................................................32 RAM HORIZONTAL ADDRESS SET (R20H) AND VERTICAL ADDRESS SET (R21H).........................32
Solomon Systech
Apr 2006
Rev 1.0
SSD1918
WRITE DATA TO GRAM (R22H).............................................................33 READ DATA FROM GRAM (R22H) ...........................................................33
MAXIMUM RATINGS..................................................... 34 DC CHARACTERISTICS................................................... 35 AC CHARACTERISTICS................................................... 36
12.1 CPU INTERFACE TIMING ..................................................................36 12.1.1 Baseband to Controller Interface Timing (6800 mode) .......................................36 12.1.2 Baseband to Controller Interface Timing (8080 mode) .......................................37 12.1.3 Controller to Main display interface timing (3-wire SPI mode) .................................38 12.1.4 Controller to Sub Display interface timing (6800 mode)......................................39 12.1.5 Controller to Sub Display interface timing (8080 mode)......................................40 12.1.6 Controller to Sub Display interface timing (4-wire SPI mode)..................................41 12.1.7 Controller to Sub Display interface timing (3-wire SPI mode)..................................42
APPLICATION EXAMPLES ................................................ 43
APPLICATION DIAGRAM ...................................................................43
FLOW CHART FOR SSD1918 POWER UP / DOWN............................. 45
SSD1918 POWER UP SEQUENCE .............................................................45 SSD1918 POWER DOWN SEQUENCE..........................................................46 SSD1918 ENTER TO POWER SAVE MODE ......................................................47 SSD1918 FROM SLEEP MODE RETURN TO NORMAL MODE ........................................48
GDDRAM ADDRESS ...................................................... 49 INTERFACE MAPPING.................................................... 49
MAPPING FOR WRITING AN INSTRUCTION TO SSD1918 ...........................................49 MAPPING FOR WRITING PIXEL DATA TO SSD1918................................................50
WSYNC APPLICATION.................................................... 50 WAIT / IRQ APPLICATION................................................. 51 SSD1918L1 LGA PACKAGE DRAWING...................................... 51
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
TABLES
TABLE 3-1: ORDERING INFORMATION ..................................................................7 TABLE 5-1 : SSD1918 BUMP DIE PAD COORDINATES (BUMP CENTER) ........................................11 TABLE 5-2 : SSD1918L1 PIN ASSIGNMENT TABLE .......................................................12 TABLE 6-1 : BASEBAND PIN DESCRIPTION..............................................................13 TABLE 6-2: MAIN DISPLAY PIN DESCRIPTION ...........................................................14 TABLE 6-3: SUB DISPLAY PIN DESCRIPTION ............................................................14 TABLE 6-4: POWER PIN DESCRIPTION .................................................................15 TABLE 6-5: MISCELLANEOUS PIN DESCRIPTION .........................................................15 TABLE 7-1 :DATA BUS SELECTION MODES ..............................................................16 TABLE 8-1 : COMMAND TABLE ......................................................................19 TABLE 8-2 : POWER ON RESET REGISTER VALUE ........................................................20 TABLE 10-1 : MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS) .........................................34 TABLE 11-1 : DC CHARACTERISTICS ..................................................................35 TABLE 12-1 : PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND TO CONTROLLER) ..........36 TABLE 12-2 : PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND TO CONTROLLER) ..........37 TABLE 12-3 : 3-WIRE SERIAL TIMING CHARACTERISTICS (CONTROLLER TO MAIN DISPLAY).......................38 TABLE 12-4 : PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER TO SUB DISPLAY) ........39 TABLE 12-5 : PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER TO SUB DISPLAY) ........40 TABLE 12-6 : 4-WIRE SERIAL TIMING CHARACTERISTICS (CONTROLLER TO SUB DISPLAY) ........................41
Solomon Systech
Apr 2006
Rev 1.0
SSD1918
FIGURES
FIGURE 4-1 : SSD1918 BLOCK DIAGRAM...............................................................8 FIGURE 5-1 : SSD1918 DIE PAD FLOOR PLAN ............................................................9 FIGURE 5-2 : SSD1918L1 PINOUT DIAGRAM - LGA (BOTTOM VIEW) ........................................10 FIGURE 7-1 : READ DISPLAY DATA ...................................................................16 FIGURE 7-2: SPI INTERFACE FOR MAIN DISPLAY ........................................................17 FIGURE 7-3: SWITCHING BETWEEN EXTERNAL VDDEXT & INTERNAL REGULATOR................................18 FIGURE 12-1 : PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND TO CONTROLLER) .........36 FIGURE 12-2 : PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND TO CONTROLLER) .........37 FIGURE 12-3 : 3-WIRE SERIAL TIMING CHARACTERISTICS (CONTROLLER TO MAIN DISPLAY).......................38 FIGURE 12-4 : PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER TO SUB DISPLAY) ........39 FIGURE 12-5 : PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER TO SUB DISPLAY) ........40 FIGURE 12-6 : 4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (CONTROLLER TO SUB DISPLAY)...............41 FIGURE 12-7 : 3-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (CONTROLLER TO SUB DISPLAY)...............42 FIGURE 13-1 : APPLICATION EXAMPLES I (SSD1918 APPLICATION CIRCUIT WITH 2.775V MCU)....................43 FIGURE 13-2 : APPLICATION EXAMPLES II (SSD1918 APPLICATION CIRCUIT WITH 1.8V MCU) .....................44 FIGURE 14-1 : SSD1918 POWER UP SEQUENCE ..........................................................45 FIGURE 14-2 : SSD1918 POWER DOWN SEQUENCE .......................................................46 FIGURE 14-3 : SSD1918 ENTER TO POWER SAVE MODE ...................................................47 FIGURE 14-4 : SSD1918 FROM SLEEP MODE RETURN TO NORMAL MODE ......................................48 FIGURE 20-1 : SSD1918L1 PACKAGE MECHANICAL DRAWING .............................................51
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
GENERAL DESCRIPTION
FEATURES
Solomon Systech
Apr 2006
Rev 1.0
SSD1918
ORDERING INFORMATION
Table 3-1: Ordering Information Ordering Part Number SSD1918Z SSD1918L1 Resolution 240RGBx320 240RGBx320 Package Form Gold Bump Die LGA Reference Figure 5-1 on Page 9 Figure 6-1 on Page 12 Remark
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
BLOCK DIAGRAM
Figure 4-1 : SSD1918 Block Diagram
VDD(MAIN)
OSCEXT
Display Timing Generator RGB Interface
VDD(BB)
Oscillator GPO (SPI) GDDRAM 176x220x2x18 GPO (Display Control)
Main Display Interface
RR5:0, GG5:0, BB5:0, DOTCLK, HSYNC, VSYNC, DEN SDI, SCK, CS, MRES GPO7:4 (SD, RL, TB, CM)
HD17:0 HE HR / W HCS HD / C RESET PS3:0 WAIT IRQ WSYNC
Base band Interface
Command Decoder
Buffer
Sub Display Interface
VDD(CORE1) VDD(CORE) VSS(CORE) VSS(BB) VSS(MAIN) VSS(SUB) VSSEXT Regulator and Mux General Purpose Output
Parallel Serial
SD8:0, SE, SR / W SCS6:0 SD / C SRES
VDDEXT
REGVDD
GPO3:0
VDD(SUB)
Solomon Systech
Apr 2006
Rev 1.0
SSD1918
DIE PAD FLOOR PLAN
Figure 5-1 : SSD1918 Die Pad Floor Plan
y (0, 0) x (256, 256)
Coordinate: x: -2405um y: -1955um
Coordinate: x: 2405um y: -1955um
Coordinate: x: -2405um y: 1955um x: 2405um y: 1955um
Die Size Die Thickness Typical Bump Height
Bump size (Pad 1- 162) 55 X 55 um2 Minimum bump pitch 100 um
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
SSD1918L1 LGA Pin Out
Figure 5-2 : SSD1918L1 Pinout Diagram - LGA (Bottom view)
Solomon Systech
Apr 2006 P 10 / 52
Rev 1.0
SSD1918
Table 5-1 : SSD1918 Bump Die Pad Coordinates (Bump center)
Pad # Pad Name X-pos Y-pos Pad # Pad Name X-pos Y-pos Pad # Pad Name X-pos Y-pos Pad # Pad Name X-pos Y-pos
GPO1 GPO2
GPO3 1000 GPO4 (CM) 1100 GPO5 (TB) GPO6 (RL) GPO7 (SD) VDD(MAIN) VDD(MAIN) VSS(MAIN) VSS(MAIN) VDD(CORE) VDD(CORE) VSS(CORE) VSS(CORE) VSS(CORE) VSS(CORE) DOTCLK 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2444 2444 2444
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
Table 5-2 : SSD1918L1 Pin Assignment Table Pin #
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
Signal Name
VSS(CORE) WAIT SCS6 SCS2 VSS(CORE) SRES SR / W SD3 SD6 SD8 VSS(CORE) OSCEXT WSYNC SCS5 SCS3 SD / C VSS(CORE) SD0 SD4 SD7 VDD(CORE) MRES RESET IRQ PS3 SCS4 SCS0 SE SD1 SD5 VSS(SUB) VDD(SUB) VSS(CORE)
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11
Signal Name
PS2 PS1 PS0 VSS(CORE) SCS1 TEST1 SD2 VSS(CORE) VDD(MAIN) VSS(CORE) CS HD / C HR / W VSS(BB) VDD(BB) BB0 VSS(MAIN) SDI SCK HCS VSS(CORE) HE HD0 BB1 BB2 BB3 BB4
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11
Signal Name
HD1 HD2 HD3 HD4 BB5 GG0 GG1 GG2 HD5 HD6 HD7 VSS(CORE) VDD(CORE) GPO0 GPO4 VSS(CORE) GG3 GG4 GG5 HD8 HD9 HD10 HD11 VDD(CORE1) GPO1 GPO5 GPO7 RR0 RR1 RR2
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
Signal Name
HD12 HD13 HD14 REGVDD VSSEXT GPO2 GPO6 VSS(CORE) RR3 RR4 RR5 VSS(CORE) HD15 HD16 HD17 VDDEXT GPO3 DOTCLK HVSYN VSYNC DEN VSS(CORE)
Solomon Systech
Apr 2006 P 12 / 52
Rev 1.0
SSD1918
PIN DESCRIPTIONS
Baseband Pin Description
Table 6-1 : Baseband Pin Description
Pin Bus Ty Function Name width pe HD5-0 6 IO HD6 1 IO (SDO) HD7 1 IO Data Bus (SCK) HD8 1 IO (SDI) HD17-9 9 IO HE (HRD) HR / W (HWR) HD / C HCS WAIT 1 1 1 1 1 I I I I O
Description Data bus connected to base band controller For parallel mode, 8 / 9 / 16 / 18 bit interface, refer to Section Interface Mapping for definition. For serial mode, HD6-HD8 are used. Unused pins should be connected to VSS
WSYNC RESET
PS3-0
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
Main Display Pin Description
Table 6-2: Main Display Pin Description Bus Type Function width 3 6 6 6 1 1 1 1 1 1 O O O O O O O O O O O O O Data Bus Graphic Display Data Display Timing Signal
Pin Name SDI, SCK, CS RR5-0 GG5-0 BB5-0 HSYNC VSYNC DEN GPO7(SD) GPO6(RL) GPO5(TB)
DOTCLK 1
GPO4(CM 1 ) MRES 1
Dot-clock signal and oscillator source for main display module. (polarity programmable) Line synchronization output signal. (polarity programmable) Frame synchronization output signal. (polarity programmable) Display enable output signal. (polarity programmable) Display shut down output signal. Panel Mapping Source driver data shift direction output signal. Control Gate driver scan direction output signal. Output signal to select 262k-color or 8-color display mode. If output to high (VDD(MAIN)), 8 colors mode is selected. If output to VSS, 262k colors mode is Logic selected. Note, during 8 color mode, the internal operation of this controller Control will also change to minimize the total power consumption, and the RR40 / GG4-0 / BB4-0 will be output VSS and ignore the content of RAM. Reset Active low reset pulse to reset main display module
Sub Display Pin Description
Table 6-3: Sub Display Pin Description
Bus Type Function Description Pin Name width SD0-6 Data bus connected to the sub display. SD7 (SSCK) 9 O Data Bus In SPI mode: SD7 is the serial clock input and SD8 is the serial data SD8 (SSDA) input 68-system : E (enable signal) 80-system : / RD (read strobe signal) SE (SRD) 1 O Serial mode : Not used and should be connected to VSS 68-system : R / W (indicates read cycle when High, write cycle when Low) Logic SR / W 1 O 80-system : / WR write strobe signal) Control (SWR) Serial mode : Not used and should be connected to VSS SD / C 1 O Data (high) and command (low) definition pin connected to sub display Chip select pin connected to sub display or another slave device (polarity SCS6-0 7 O programmable) SRES 1 O Reset Active low reset pulse to reset sub display module
Solomon Systech
Apr 2006 P 14 / 52
Rev 1.0
SSD1918
Power Pin Description
Table 6-4: Power Pin Description Bus width 3 12 3 4 4 2 25 4 4 3 2
Pin Name VDD(CORE1) VDD(CORE) VDDEXT VDD(BB) VDD(MAIN) VDD(SUB) VSS(CORE) VSS(BB) VSS(MAIN) VSS(EXT) VSS(SUB)
Description
Power supply pin output form Regulator. (must short to VDD(CORE) with cap) Power supply pin for core logic.(with cap) Power Power supply pin for internal regulator. Supply Power supply pin for baseband interface Power supply pin for main display interface Power supply pin for sub display interface Ground pin for core logic Ground of Ground pin for baseband interface Power Ground pin for main display interface Supply Ground pin for internal regulator Ground pin for sub display interface
Miscellaneous Pin Description
Pin Name OSCEXT
REGVDD
GPO7-0 TEST8-1 NC
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
FUNCTIONAL BLOCK DESCRIPTIONS Base band Interface
The Baseband Interface supports 8 / 9 / 16 / 18 bits 6800 / 8080 parallel interface, configure by PS3-0 pins. a) MPU Parallel 6800-series Interface The parallel Interface consists of 18 bi-directional data pins (HD17 - D0), HR / W, HD / C, HE and HCS. HR / W input high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or the status register. HR / W input low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of HDC input. The HE input serves as data latch signal (clock) when high provided that HCS is low. Please refer to Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of the GDDRAM with that of the MCU, pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in the following diagram.
Figure 7-1 : Read Display Data
DATA BUS
write column address
dummy read
data read 1
data read 2
data read 3
b) MPU Parallel 8080-series Interface The parallel interface consists of 18 bi-directional data pins HD17 - HD0, HRD, HWR, HD / C and HCS. HRD input serves as data read latch signal (clock) when low provided that HCS is low. Whether reading the display data from GDDRAM OR reading the status from the status register are controlled by HD / C. HWR input serves as data write latch signal (clock) when low provided that HCS is low. Whether writing the display data to the GDDRAM or writing the command to the command registers are controlled by HD / C. A dummy read is also required before the first actual display data read for 8080-series interface.
Table 7-1 :Data bus selection modes 6800 - series Parallel Interface 18 / 16 / 9 / 8-bits 18 / 16 / 9 / 8-bits Status only Yes 8080 - series Parallel Interface 18 / 16 / 9 / 8-bits 18 / 16 / 9 / 8-bits Status only Yes
Data Read Data Write Command Read Command Write
The interface is powered by VDD(BB) to match with the base band controller operating voltage. The Base band Interface also provide WAIT and IRQ handshaking signals with the base band controller such that the base band controller can stop data transfer until the SSD1918 is ready to accept new command or data.
Solomon Systech
Apr 2006 P 16 / 52
Rev 1.0
SSD1918
The WSYNC output can be used for data written synchronization to avoid display of incomplete RAM page.
Main Display Interface
The main interface consists of an RGB interface, SPI interface and some display control bits (SD, RL, TB, SM) by using four of the general purpose output pins. Commands can also be translate from parallel to SPI format by the command decoder. The SPI format is according to SSD1278 SPI interface format. The main display interface is operated by VDD(MAIN) to match with main display operating condition.
RGB Interface
The display data and frame position information send to the main display to control and synchronize the Gate Drive circuit and shift registered for the source driver circuit.
GPO SPI
GPO SPI provides the serial interface to control the main display. The clock synchronized serial peripheral interface (SPI) using the chip select line (CS) and serial transfer clock line (SCK), serial input data (SDI). SPID pin function uses as an ID pin. The serial data transfer starts at the falling edge of CS input and ends at the rising edge of CS. Please see Figure 7-2 for detail.
Figure 7-2: SPI Interface for Main Display Transfer starts
Transfer ends
MSB LSB
DEVID5:0
Device ID code Start byte
RS RW Index register setting / Instruction,
GPO (Display Control)
To provide the standard control signal to control the Main Display, GPO (Display Control) can work as General Purpose Output. Please see "General Purpose Output " for detail.
Sub Display Interface and Buffer
The sub display interface consists of an 8 / 9 bits, 6800 / 8080 parallel interface together with a 3 / 4 wires serial interface. (Refer to SSD1283 specification for the detail of bus interface) The data from base band MCU is first stored in a small buffer and then transmitted to the sub display depending on the color format. The sub display interface is operated by VDD(SUB) to match with sub display operating condition.
SSD1918 Rev 1.0 P 17 / 52 Apr 2006 Solomon Systech
General Purpose Output
There are totally eight general purpose output pins. The output is controlled by 8 bits register which can be programmed by the base band controller. The output high level for General Purpose Output is the same as VDD(MAIN).
Display Timing Generator & Oscillator
The Display Timing Generator (DTG) works with an internal oscillator to generate necessary timing information for the RGB interface of the main display. The DTG require a constant 32kHz clock input for operation. The display frequency of the main display can be programmed from 30Hz to 80Hz to match with high quality 262k color display and low power 8 color display mode, main display frame frequency will be affected by the selection / settings of internal clock freq, horizontal / vertical back / front porch and partial / full screen selection.
Graphic Display Data RAM (GDDRAM)
7.10 Regulator and MUX
In order to provide a 1.7~2.5V system core voltage (VDD(CORE)), SSD1918 integrated a regulator to generate the required voltage for internal operations. This regulator can be disabled by setting REGVDD to VSS, and the internal system core voltage will come from external VDDEXT pin.
Figure 7-3: Switching between external VDDEXT & internal regulator
~2.2V VDDEXT
Regulator
REGVDD
VDD(CORE) 4.7uF ~ 10uF
Solomon Systech
Apr 2006 P 18 / 52
Rev 1.0
SSD1918
COMMAND TABLE
Table 8-1 : Command Table
Register
R / HD / C IB15 IB14 IB13 W
IB7 IB6
Toggle Code - to Main / Sub Display RDAH R98H RDAH R99H Toggle Code - to Display controller Customer Command R00H On Chip Frequency generator Enable Chip Select / interface selection Main / Sub display driver command interface & frequency GPO Control GPO Control Sub DOTCLK Frequency Vertical Display Setting 1 Main Display Control Vertical Display Setting 2 Horizontal Setting 1 Horizontal Setting 2 Slew rate control 1 Slew rate control 2 Entry Mode 2nd toggle byte Vertical Display Setting 3 Vertical Display Setting 4 Horizontal RAM window setting Vertical RAM window setting W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCEN
DEVID5:0
SLEEP
SINTF2:0
RWC PCS
ESC2:0
GPENS
GPENM
SUBWT
DSSUB3:0
DSMAIN3:0
R03H R04H R05H R06H R07H R09H R0AH R0BH R0CH R0DH R0EH R0FH R12H
GPREGM3:0
GPREG2S3:0 GPREGS15:0
GPO7:0
0 EMX6:0
FDIV2:0 0 DS5:0 0 0 0 0 TNS3:0 TPM3:0 0 CDEPTH 0 TPO3:0 TY1:0 0 ID1:0
FSET7:0 FMX6:0 CM 0 0 SHUT
HIS IDOT IDEN
0 VFP6:0
VBP6:0 XL7:0 HBP6:0 TNM3:0 TNO3:0 AM MATCHID6:0 000
0 HFP6:0
ENWS PWAIT ENWAIT RAMTURBO 0 0 0 0 0 0 0 0
DENS8:0
DENE8:0
R14H R15H R16H R17H
HAS7:0 VSA8:0 VEA8:0 VSMODE1:0 0 MTYPE WSEL DSEL
GRAM Paging W setting RAM W R20H horizontal address set RAM vertical W R21H address set
AD7:0 AD16:8
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
Reg# R22H
Register
IB7 IB6
Write Data to GRAM Read Data to R22H GRAM Other of the above
WD17:0 mapping depends on the interface setting RD17:0 mapping depends on the interface setting Reserved
Table 8-2 : Power on Reset Register value
Reg# Register R00H On Chip Frequency generator R01H Enable Chip Select / interface selection R02H Main / Sub display driver command interface & frequency R03H GPO Control R04H GPO Control Sub R05H DOTCLK Frequency R06H Vertical Display Setting 1 R07H Main Display Control R09H Vertical Display Setting 2 R0AH Horizontal Setting 1 R0BH Horizontal Setting 2 R0CH Slew rate control 1 R0DH Slew rate control 2 R0EH Entry Mode R0FH 2 toggle byte R12H Vertical Display Setting 3 R13H Vertical Display Setting 4 R14H Horizontal RAM window setting R15H R16H R17H GRAM Paging setting R20H RAM horizontal address set R21H RAM vertical address set Vertical RAM window setting
Solomon Systech
Apr 2006 P 20 / 52
Rev 1.0
SSD1918
COMMAND DESCRIPTIONS Toggle Code
RDAH, R98H: After receiving such 2 command bytes, all commands / data will be buffered and sent to main / sub display driver, the display controller itself will not executes those commands and data until receive the other TOGGLE CODE(RDAH, R99H). RDAH, R99H: After receiving such 2 command bytes, all commands / data will be sent to this display controller and main / sub display driver interface will be received those followed commands / data.
On chip frequency generator (R00H)
OSCEN
OSCEN : set this to 1 and the onchip freq generator will start to lock the 32khz within 10ms. (Por 0)
Enable Chip Select / interfaces selection (R01H)
DEVID5
DEVID4
DEVID3
DEVID2
DEVID1
DEVID0
SLEEP SINTF2 SINTF1 SINTF0
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
Main / Sub display driver command interface & frequency (R02H)
IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10
GPENS GPENM SUBWT DSSUB3 DSSUB2 DSSUB1 DSSUB0 DSMAIN3 DSMAIN2 DSMAIN1 DSMAIN0
CYCLE DSMAIN 3-0 x 0 20 1 20 2 30 3(POR) 30 4 40 5 50 6 50 7 x 8 90 9 120 A 150 B 190 C 220 D 250 E 310 F
DSSUB3-0: select the parallel interface cycle time. (unit: ns)
CYCLE DSSUB 3-0 10 0 10 1 10 2 30 3(POR) 40 4 40 5 50 6 60 7 10 8 60 9 60 A 140 B 190 C 210 D 250 E 320 F
GPO Control Main (R03H)
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 GPREGM3 GPREGM2 GPREGM1 GPREGM0 0 0 0 0 GPO7GPO6GPO5GPO4 GPO3 GPO2 GPO1GPO0
GPO Control Sub (R04H)
GPREGS15
GPREGS14
GPREGS13
GPREGS12
GPREGS11
GPREGS10
GPREGS9
GPREGS8
GPREGS7
GPREGS6
GPREGS5
GPREGS4
GPREGS3
GPREGS2
GPREGS1
GPREGS0
Solomon Systech
Apr 2006 P 22 / 52
Rev 1.0
SSD1918
DOTCLK frequency (R05H)
FDIV2
FDIV1
FDIV0
FSET7
FSET6
FSET5
FSET4
FSET3
FSET2
FSET1
FSET0
FOSC / DOTCLK 1(POR) 1.33 1.5 2 2.5 2.66 3 4
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
Vertical Display Setting 1 (R06H)
IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 FMX6 FMX5 FMX4 FMX3 FMX2 FMX1 FMX0
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 W 1 0 EMX6 EMX5 EMX4 EMX3 EMX2 EMX EMX
FMX6-0: Specify number of lines for the LCD driver in multiple of 4. For full color display mode, the setting exceeds 320 lines will be treated as 320 lines. EMX6-0: Specify number of lines for the LCD driver in multiple of 4. For 8 colors display mode, the setting exceeds 320 lines will be treated as 320 lines. (OE width will be change according to this setting)
Main Display Control (R07H)
HD / C 1 IB15 IVS IB14 IHS IB13 IDOT IB12 IDEN IB11 0 IB10 0 IB9 DS5 IB8 DS4 IB7 DS3 IB6 DS2 IB5 DS1 IB4 DS0 IB3 CM IB2 0 IB1 0 IB0 SHUT
IVS : Set the polarity of the VSYNC signal. If the bit is 1, VSYNC will invert the Polarity of the corresponding Main display output signal. (POR 0) IHS : Set the polarity of the HSYNC signal. If the bit is 1, HSYNC will invert the Polarity of the corresponding Main display output signal. (POR 0) IDOT : Set the polarity of the DOTCLK signal. If the bit is 1, DOTCLK will invert the Polarity of the corresponding Main display output signal. (POR 0) IDEN : Set the polarity of the DEN signal. If the bit is 1, DEN will invert the Polarity of the corresponding Main display output signal. (POR 0) DS5:0 : Set R5:0, G5:0, B5:0 RGB data sequence and ordering to hardware pin RR5:0, GG5:0, BB5:0. DS2:0 set the RGB sequence to GDDRAM and DS5:0 set the data orientation to hardware pin RR5:0, GG5:0 and BB5:0. (000000 POR)
DS2:0 0 0 0 (POR) 001 010 011 100 101 110 111 RGB Ordering RGB RBG BRG GRB GBR BGR Reserved Reserved
Solomon Systech
Apr 2006 P 24 / 52
Rev 1.0
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
9.10 Vertical Display Setting 2 (R09H)
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 W 1 0 VFP6 VFP5 VFP4 VFP3 VFP2 VFP1 VFP0 0 VBP6 IB5 IB4 IB3 IB2 IB1 IB0
VBP5 VBP4 VBP3 VBP2 VBP1 VBP0
Cycle time of VSYNC Set by VBP6-0
VSYNC HSYNC
Dummy Lines 1st Line
Set by MUX6-0
Last Line
Dummy Lines
Solomon Systech
Apr 2006 P 26 / 52
Rev 1.0
SSD1918
9.11 Horizontal Setting 1 (R0AH)
HR / W HD / C IB15 IB14 IB13 IB12 IB11 W 1 0 0 0 0 0 IB10 0 IB9 0 IB8 0 IB7 XL7 IB6 XL6 IB5 XL5 IB4 XL4 IB3 XL3 IB2 XL2 IB1 XL1 IB0 XL0
XL7:0 : Set the number of valid pixel per line.
9.12 Horizontal Setting 2 (R0BH)
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 HFP6 HFP5 HFP4 HFP3 HFP2 HFP1 HFP0 0 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
Cycle time of HYSYNC Set by HBP7-0 Set by XL7-0
HYSNC Pixel Data DOTCLK
Default 176 pixels per line
Dummy D0 D1 D2 D173 D174 D175 Dummy
9.13 Slew rate control (R0CH)
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 TPS3 TPS2 TPS1 TPS0 TNS3 TNS2 TNS1 TNS0 TPM3 TPM2 TPM1 TPM0 TNM TNM TNM TNM
TNM3:0, TPM3:0 : control the high speed main output pins low & high output impedance (~ from 110ohm (1111) to 3000ohm (0000)). (POR 1111, 1111) Pins involved: RR5:0, GG5:0, BB5:0, VSYNC, HSYNC, DEN, DOTCLK TNS3:0, TPS3:0 : control the high speed sub output pins low & high output impedance (~ from 110ohm (1111) to 3000ohm (0000)). (POR 1111, 1111) Pins involved: SD8:0, SCS1:0, SE, SRW, SDC, SRES
9.14 Slew rate control2 (R0DH)
HR / W HD / C IB15 W 1 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 TPO3 TPO2 TPO1 TPO0 TNO3 TNO2 TNO1 TNO0
TNO3:0, TPO3:0 : Control all other output pins low & high output impedance (~ from 110ohm (1111) to 3000ohm (0000)). (POR 1111, 1111) Pins involved: SDI, SCK, CS, MRES, GPO7:4 ( SD, RL, TB, CM), GPO3:0, HD17-0, HE, HR / W, HD / C, HCS, WAIT, IRQ, WSYNC
9.15 Entry Mode (R0EH)
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 ENWS PWAIT ENWAIT RAMTURBO CDEPTH TY1 TY0 ID1 ID0 AM 0 0 0
Solomon Systech
Apr 2006 P 28 / 52
Rev 1.0
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
TY1:0: In 262k color mode, 16 bit parallel interface, there are three types of methods in writing data into the ram, Type A, B and C are described as below.
TY1 0 0 1 TY0 0 1 0 Writing mode Type A Type B (POR) Type C
Interface Color mode Cycle st 262k Type A 1 nd 2 rd 3 st 16 bit 262k Type B 1 nd 2 st 262k Type C 1 nd 2 Remark : x
Horizontal: decrement
Horizontal: increment
Vertical: decrement 0000h
Horizontal: decrement
Vertical: increment 0000h
Horizontal: increment
Vertical: increment 0000h
13FEFh 0000h 0000h
13FEFh 0000h
13FEFh
Solomon Systech
Apr 2006 P 30 / 52
Rev 1.0
SSD1918
9.16 2nd toggle byte (R0FH)
HR / W HD / C IB15 W 1 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 0 IB7 0 IB6 IB5 IB4 IB3 IB2 MATCHID IB1 IB0
MATCHID6:0 : this is the 7 MSB of the 2nd toggle byte, (R98h or R99h), this gives some flexibility for the choice of different main / sub display drivers (since R98, R99 may already been used as critical commands in some vendors TFT drivers). (POR 1001100)
9.17 Vertical Display Setting 3 (R12H)
HR / W HD / C IB15 W 1 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 DENS DENS DENS DENS DENS DENS DENS DENS DENS
VS8:0 : Vertical display offset, ie the starting position of DEN pulse (POR 00000000). This feature is usually only useful in partial display mode (ie. Less than full mux display)
9.18 Vertical Display Setting 4 (R13H)
HR / W HD / C IB15 W 1 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
DENE8 DENE7 DENE6 DENE5 DENE4 DENE3 DENE2 DENE1 DENE0
VE8:0 : Vertical display offset, ie the Ending position of DEN pulse (POR 0DBH).This feature usually only useful in partial display mode (ie. Less than full mux display)
9.19 Horizontal RAM window setting (R14H)
R / W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
9.20 Vertical RAM window setting (R15H for VSA, R16H for VEA)
R / W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 W 1 0 0 0 0 0 0 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0
9.21 GDDRAM Paging setting (R17H)
R / W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 0 0 0 VSMODE1 VSMODE0 0 MTYPE WSEL1 DSEL
VSMODE1:0 : It is used to synchronize the "DSEL" internally. VSMODE1:0 00 01 10 11 SYNC No SYNC SYNC per 1 frame (POR) SYNC per 2 frames SYNC per 4 frames
MTYPE: When MTYPE is set to 0, to select 176 x 220 x 18bits x 2 pages GDDRAM. When MTYPE is set to 1, to select 240 x 320 x 18bits GDDRAM. (POR 0) WSEL : When WSEL is set to 0, data will be written on RAMA. When WSEL is set to 1, data will be written on RAMB. (POR 0) DSEL : When DSEL is set to 0, data on RAMA will be sent to Main display. When DSEL is set to 1, data on RAMB will be sent to Main display. (POR 0) MTYPE 0 0 0 0 1 WSEL 0 0 1 1 x DSEL 0 1 0 1 x Write to RAMA RAMA RAMB RAMB x Display form RAMA RAMB RAMA RAMB x GDDRAM SIZE 176 X 220 X 18 bits x 2 pages 320 x 240 x 18 bits
9.22 RAM horizontal address set (R20H) and vertical address set (R21H)
HR / W HD / C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W 1 0 0 0 0 0 0 0 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
AD16:0 : Make initial settings for the GDDRAM address in the address counter (AC). After GRAM data are written, the address counter is automatically updated according to the settings with AM, I / D bits and setting for a new GDDRAM address is not required in the address counter. Therefore, data are written consecutively without setting an address. The address counter is not automatically updated when data are read out from the GDDRAM. (AD16:8 is vertical address, AD7:0 is horizontal) (POR 0 0000 0000 0000 0000) The address setting should be made within the area designated with window addresses.
Solomon Systech
Apr 2006 P 32 / 52
Rev 1.0
SSD1918
9.23 Write Data to GRAM (R22H)
HR / W HD / C W 1 D17:0 WD17:0 mapping depends on the interface setting
WD17:0 : Transforms all the GDDRAM data into 18-bit, and writes the data. Format for transforming data into 18-bit depends on the interface used. After writing data to GDDRAM, address is automatically updated according to AM bit and ID bit. Access to GDDRAM during stand-by mode is not available.
9.24 Read Data from GRAM (R22H)
HR / W HD / C R 1 D17:0 RD17:0 mapping depends on the interface setting
RD17:0 : Read 18-bit data from the GDDRAM. When the data is read to the microcomputer, the first-word read immediately after the GDDRAM address setting is latched from the GDDRAM to the internal read-data latch. The data on the data bus (DB17-0) becomes invalid and the second-word read is normal. No display data is available to main display driver (shut down) during reading ram. (so it assume the "SHUT" is 1 during reading ram through data pins) This reading of ram is for testing purpose rather than for normal application usage.
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
MAXIMUM RATINGS
Table 10-1 : Maximum Ratings (Voltage Referenced to VSS) Symbol VDDCORE VDDBB Parameter Supply Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Value -0.3 to +2.5 -0.3 to +3.6 -0.3 to +3.6 -0.3 to +3.6 25 -20 to +70 -65 to +150 Unit V V V V V mA o C
I TA Tstg
Solomon Systech
Apr 2006 P 34 / 52
Rev 1.0
SSD1918
11 DC CHARACTERISTICS
Conditions:
0.9 VDD 0 0.8V DD 0 50 -1 50
Note (1) FOSC stands for the frequency value of the internal oscillator
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
12 AC CHARACTERISTICS 12.1 CPU Interface Timing
12.1.1 Baseband to Controller Interface Timing (6800 mode) Conditions:
Figure 12-1 : Parallel 6800-series Interface Timing Characteristics (Baseband to Controller)
tF tCYCLE PWCSH tDSW
tR PWCSL tDH
HD0~HD17(WRITE)
Valid Data tACC
HD0~HD17(READ)
Valid Data tOH
Solomon Systech
Apr 2006 P 36 / 52
Rev 1.0
SSD1918
12.1.2 Baseband to Controller Interface Timing (8080 mode) Conditions:
Figure 12-2 : Parallel 8080-series Interface Timing Characteristics (Baseband to Controller) Write Cycle
HD / C tAS HCS HWR HRD tF tCYCLE PWCSL tAH tR PWCSH
tDSW Valid Data
HD0~HD17
Read Cycle
HD / C tAS HCS HWR PWCSL HRD tACC tCYCLE PWCSH tF tAH tR
HD0~HD17
Valid Data tOH
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
12.1.3 Controller to Main display interface timing (3-wire SPI mode) Conditions:
Typ 35 28 10 30 10 10 15 20
Max 320 50 160 160
Unit ns MHz ns ns ns ns ns ns
Figure 12-3 : 3-wire Serial Timing Characteristics (Controller to Main display) CS
tCSS tCYCLE
tCLKL SCK
tCLKH
tDSW SDI Valid Data
Transfer Start CS
Transfer End
tCSS SCK
Data23
Data22
Data21
Data0
Solomon Systech
Apr 2006 P 38 / 52
Rev 1.0
SSD1918
12.1.4 Controller to Sub Display interface timing (6800 mode) Conditions:
Figure 12-4 : Parallel 6800-series Interface Timing Characteristics (Controller to Sub display)
SCS tCYCLE SE PWCSH PWCSL
tDSW SD0~SD8(WRITE)
Valid Data
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
12.1.5 Controller to Sub Display interface timing (8080 mode) Conditions:
Figure 12-5 : Parallel 8080-series Interface Timing Characteristics (Controller to Sub display) Write Cycle
SD / C tAS SCS tCYCLE SWR PWCSL PWCSH tAH
SRD tDSW
SD0~SD8
Valid Data
Solomon Systech
Apr 2006 P 40 / 52
Rev 1.0
SSD1918
12.1.6 Controller to Sub Display interface timing (4-wire SPI mode) Conditions:
Figure 12-6 : 4-wire Serial Interface Timing Characteristics (Controller to Sub display) SD / C
tAS tAH tCSS tCYCLE tCSH
tCLKL
tCLKH
SCK(SD6)
tDSW tDHW
SDI(SD7)
Valid Data
SCK(SD6)
SDI(SD7)
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
12.1.7 Controller to Sub Display interface timing (3-wire SPI mode) Conditions:
Figure 12-7 : 3-wire Serial Interface Timing Characteristics (Controller to Sub display)
tCSS tCYCLE tCSH
tCLKL SCK(SD6) tDSW SDI(SD7) Valid Data
tCLKH
Solomon Systech
Apr 2006 P 42 / 52
Rev 1.0
SSD1918
13 APPLICATION EXAMPLES 13.1 Application Diagram
Figure 13-1 : Application Examples I (SSD1918 application circuit with 2.775V MCU)
Sub Display Interface
2.775V
32kHz
INT0 INT1 INT2 2.775V SD1-8 SE SR / W SD / C SRES SCS0 OSCEXT IRQ WSYNC WAIT PS3 PS2 PS1 PS0 VDD(SUB) VSS(SUB)
2.775V VDD VSS SDI SCK CS RES BB0-5 GG0-5 RR0-5 DEN VSYNC HSYNC DOTCLK SD RL TB CM
CS RESET D / C R / W E D0-17 2.775V
VDD(MAIN) VSS(MAIN
SDI SCK CS MRES
SSD1278 Interface
HCS RESET HD / C HR / W HE HD0-17
SSD1918
GP05(TB) GPO4(CM) VSSEXT VDDEXT REGVDD VDD(CORE1) VDD(CORE) VSS(CORE)
BB0-5 GG0-5 RR0-5 DEN VSYNC HSYNC DOTCLK
GP07(SD) GP06(RL)
VDD VSS
VDD(BB) VSS(BB)
2.775V
Other pins connection: Ground : SD0 Interface: Base Band : 18- bits 6800 PPI Main Display ( SSD1278) : SPI Sub display : 8-bits 6800 PPI
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
Figure 13-2 : Application Examples II (SSD1918 application circuit with 1.8V MCU)
Sub Display Interface
2.775V
32kHz
INT0 INT1 INT2
VSS(SUB) VDD(SUB)
2.775V
2.775V VDD(MAIN) VSS(MAIN) VDD VSS SDI SCK CS RES BB0-5 GG0-5 RR0-5 DEN VSYNC HSYNC DOTCLK SD RL TB CM
CS RESET D / C R / W E D0-17 2.775V VDD VSS
SD1-8 SE SR / W SD / C SRES SCS0 OSCEXT IRQ WSYNC WAIT PS3 PS2 PS1 PS0
SSD1278 Interface
SSD1918
SDI SCK CS MRES
BB0-5 GG0-5 RR0-5 DEN VSYNC HSYNC DOTCLK
HD0-17
GP07(SD) GP06(RL) GP05(TB) GPO4(CM) VSSEXT VDDEXT REGVDD VDD(CORE1) VDD(CORE) VSS(CORE)
2.775V
VDD(BB) VSS(BB)
Other pins connection: Ground : SD0 Interface: Base Band : 18- bits 6800 PPI Main Display ( SSD1278) : SPI Sub display : 8-bits 6800 PPI
Solomon Systech
Apr 2006 P 44 / 52
Rev 1.0
SSD1918
14. FLOW CHART FOR SSD1918 POWER UP / DOWN 14.1 SSD1918 Power Up Sequence
Figure 14-1 : SSD1918 power up sequence
Power up Sequence
Refer to the corresponding datasheet to control the Main / Sub Display driver
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
13.2 SSD1918 Power Down Sequence
Figure 14-2 : SSD1918 power down sequence
Power down Sequence
Toggle to Main Display (RDAH, 98H)
Turn off the Main display
(RDAH, 99H) toggle to SSD1918 (R01H, 7081H) set the register to select sub display (RDAH, 98H) toggle to sub display
Turn off Sub display Wait 10ms Toggle to the SSD1918 (RDAH, R99H)
Wait 1ms Disable on chip frequency generator (R00H, 0000H) Wait 1ms Enable Sleep mode (R01, 7180H)
Power off
Solomon Systech
Apr 2006 P 46 / 52
Rev 1.0
SSD1918
13.3 SSD1918 Enter To Power Save Mode
Figure 14-3 : SSD1918 Enter to Power save mode
Enter to power save mode
Toggle to Main Display (RDAH, R98H)
Turn off the Main display
Toggle to the SSD1918 (RDAH, R99H)
Disable on chip frequency generator (R00H, 0000H)
Enable Sleep mode (R01, 7180H)
Remark: In the power save mode, user can toggle to sub display and update the sub display. No signal / clock send to the Main display form SSD1918.
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
13.4 SSD1918 From Sleep Mode Return to Normal Mode
Figure 14-4 : SSD1918 From sleep mode return to normal mode
Return to normal mode
Wait 1ms Send Toggle code to control the Main Display drivers (RDAH, R98H)
Turn on the Main Display
Solomon Systech
Apr 2006 P 48 / 52
Rev 1.0
SSD1918
14 GDDRAM ADDRESS
316, 0 317, 0 318, 0 319, 0 Horizontal address 0
Note: The address is in x, y format, where x is the vertical address and y is the horizontal address
15 INTERFACE MAPPING 15.1 Mapping for Writing an Instruction to SSD1918
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
15.2 Mapping for Writing pixel data to SSD1918
16 WSYNC APPLICATION
WSYNC
Fast write MCU Slow write MCU Controller displaying
tn is the time when there is No Update of LCD screen from on-chip ram content. tu is the time when the LCD screen is updating based on on-chip ram content. For fast write MCU: MCU should start to write new frame of ram data just after rising edge of long WSYNC pulse and should be finished well before the rising edge of the next long WSYNC pulse. For slow write MCU (Half the write speed of fast write): MCU should start to write new frame ram data after the rising edge of the first short WSYNC pulse and must be finished within 2 frames time.
Solomon Systech
Apr 2006 P 50 / 52
Rev 1.0
SSD1918
17 WAIT / IRQ APPLICATION
SSD1918L1 LGA PACKAGE DRAWING
Figure 20-1 : SSD1918L1 Package Mechanical Drawing
SSD1918
Rev 1.0
Apr 2006
Solomon Systech
http://www.solomon-systech.com
Solomon Systech
Apr 2006 P 52 / 52
Rev 1.0
SSD1918