QVGA Graphic Controller with built-in This document contains info

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SSD1918
QVGA Graphic Controller with built-in
This document contains information product. Specifications information herein subject change without notice. http://www.solomon-systech.com SSD1918 1/52 Copyright 2006 Solomon Systech Limited
2006
CONTENTS GENERAL DESCRIPTION FEATURES. ORDERING INFORMATION BLOCK DIAGRAM FLOOR PLAN
SSD1918L1
DESCRIPTIONS
BASEBAND DESCRIPTION MAIN DISPLAY DESCRIPTION DISPLAY DESCRIPTION POWER DESCRIPTION MISCELLANEOUS DESCRIPTION
FUNCTIONAL BLOCK DESCRIPTIONS.
7.10 BASE BAND INTERFACE MAIN DISPLAY INTERFACE INTERFACE.17 SPI.17 (DISPLAY CONTROL).17 DISPLAY INTERFACE BUFFER GENERAL PURPOSE OUTPUT DISPLAY TIMING GENERATOR OSCILLATOR GRAPHIC DISPLAY DATA (GDDRAM).18 REGULATOR MUX.18
COMMAND TABLE COMMAND DESCRIPTIONS.
9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 TOGGLE CODE CHIP FREQUENCY GENERATOR (R00H) ENABLE CHIP SELECT/INTERFACES SELECTION (R01H) MAIN/SUB DISPLAY DRIVER COMMAND INTERFACE FREQUENCY (R02H).22 CONTROL MAIN (R03H) CONTROL (R04H).22 DOTCLK FREQUENCY (R05H) VERTICAL DISPLAY SETTING (R06H) MAIN DISPLAY CONTROL (R07H) VERTICAL DISPLAY SETTING (R09H) HORIZONTAL SETTING (R0AH) HORIZONTAL SETTING (R0BH) SLEW RATE CONTROL (R0CH).28 SLEW RATE CONTROL2 (R0DH) ENTRY MODE (R0EH) TOGGLE BYTE (R0FH).31 VERTICAL DISPLAY SETTING (R12H) VERTICAL DISPLAY SETTING (R13H) HORIZONTAL WINDOW SETTING (R14H).31 VERTICAL WINDOW SETTING (R15H VSA, R16H VEA).32 GDDRAM PAGING SETTING (R17H) HORIZONTAL ADDRESS (R20H) VERTICAL ADDRESS (R21H).32
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SSD1918
9.23 9.24
WRITE DATA GRAM (R22H).33 READ DATA FROM GRAM (R22H)
MAXIMUM RATINGS. CHARACTERISTICS. CHARACTERISTICS.
12.1 INTERFACE TIMING 12.1.1 Baseband Controller Interface Timing (6800 mode) 12.1.2 Baseband Controller Interface Timing (8080 mode) 12.1.3 Controller Main display interface timing (3-wire mode) 12.1.4 Controller Display interface timing (6800 mode).39 12.1.5 Controller Display interface timing (8080 mode).40 12.1.6 Controller Display interface timing (4-wire mode).41 12.1.7 Controller Display interface timing (3-wire mode).42
13.1
APPLICATION EXAMPLES
APPLICATION DIAGRAM
14.1 14.2 14.3 14.4
FLOW CHART SSD1918 POWER UP/DOWN.
SSD1918 POWER SEQUENCE SSD1918 POWER DOWN SEQUENCE.46 SSD1918 ENTER POWER SAVE MODE SSD1918 FROM SLEEP MODE RETURN NORMAL MODE
16.1 16.2
GDDRAM ADDRESS INTERFACE MAPPING.
MAPPING WRITING INSTRUCTION SSD1918 MAPPING WRITING PIXEL DATA SSD1918.50
WSYNC APPLICATION. WAIT/IRQ APPLICATION. SSD1918L1 PACKAGE DRAWING.
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TABLES
TABLE 3-1: ORDERING INFORMATION TABLE SSD1918 BUMP COORDINATES (BUMP CENTER) TABLE SSD1918L1 ASSIGNMENT TABLE TABLE BASEBAND DESCRIPTION.13 TABLE 6-2: MAIN DISPLAY DESCRIPTION TABLE 6-3: DISPLAY DESCRIPTION TABLE 6-4: POWER DESCRIPTION TABLE 6-5: MISCELLANEOUS DESCRIPTION TABLE :DATA SELECTION MODES TABLE COMMAND TABLE TABLE POWER RESET REGISTER VALUE TABLE 10-1 MAXIMUM RATINGS (VOLTAGE REFERENCED VSS) TABLE 11-1 CHARACTERISTICS TABLE 12-1 PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND CONTROLLER) TABLE 12-2 PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND CONTROLLER) TABLE 12-3 3-WIRE SERIAL TIMING CHARACTERISTICS (CONTROLLER MAIN DISPLAY).38 TABLE 12-4 PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER DISPLAY) TABLE 12-5 PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER DISPLAY) TABLE 12-6 4-WIRE SERIAL TIMING CHARACTERISTICS (CONTROLLER DISPLAY)
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SSD1918
FIGURES
FIGURE SSD1918 BLOCK DIAGRAM.8 FIGURE SSD1918 FLOOR PLAN FIGURE SSD1918L1 PINOUT DIAGRAM (BOTTOM VIEW) FIGURE READ DISPLAY DATA FIGURE 7-2: INTERFACE MAIN DISPLAY FIGURE 7-3: SWITCHING BETWEEN EXTERNAL VDDEXT INTERNAL REGULATOR.18 FIGURE 12-1 PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND CONTROLLER) FIGURE 12-2 PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (BASEBAND CONTROLLER) FIGURE 12-3 3-WIRE SERIAL TIMING CHARACTERISTICS (CONTROLLER MAIN DISPLAY).38 FIGURE 12-4 PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER DISPLAY) FIGURE 12-5 PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS (CONTROLLER DISPLAY) FIGURE 12-6 4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (CONTROLLER DISPLAY).41 FIGURE 12-7 3-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (CONTROLLER DISPLAY).42 FIGURE 13-1 APPLICATION EXAMPLES (SSD1918 APPLICATION CIRCUIT WITH 2.775V MCU).43 FIGURE 13-2 APPLICATION EXAMPLES (SSD1918 APPLICATION CIRCUIT WITH 1.8V MCU) FIGURE 14-1 SSD1918 POWER SEQUENCE FIGURE 14-2 SSD1918 POWER DOWN SEQUENCE FIGURE 14-3 SSD1918 ENTER POWER SAVE MODE FIGURE 14-4 SSD1918 FROM SLEEP MODE RETURN NORMAL MODE FIGURE 20-1 SSD1918L1 PACKAGE MECHANICAL DRAWING
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GENERAL DESCRIPTION
SSD1918 graphics controller support main display with resolution 240RGB subdisplay. This controller three separate power buses base band processor, main display display interface. Each interface operate 1.7V 3.6V voltage range. also integrated with 174,240 bytes display support 262k color main display using interface. This controller operated power standby mode extra power saving. This controller directly interface main display using SSD1278, display using SSD1283, ideal dual display cellular phone application it's power consumption. This controller available gold bump form package.
FEATURES
Power Supply: VDD(CORE) 1.7V 2.5V (power supply core logic) VDD(BB) 1.7V 3.6V (power supply base band) VDD(MAIN) 1.7V 3.6V (power supply main display) VDD(SUB) 1.7V 3.6V (power supply display) VDDEXT 1.7V 3.6V (power supply core logic regulator, depends VDDREG setting) Display Size Support Main 262k/65k color display (QVGA) Interface Base band 8/9/16/18 bits 6800/8080 parallel interface; WAIT/IRQ/WSYNC hand shaking Main display interface (VSYNC, HSYNC, DOTCLK, DEN, RR[5:0], GG[5:0] BB[5:0]); interface; SD/RL/TB/CM display control pins; display bits 6800/8080 parallel 3/4-wires serial interface Maximum base band interface frequency 1.875V Programmable main display frame frequency (30Hz levels programmable output slew rate control reduction Support pages 176x220 resolution On-Chip 174,240 bytes (176x220x2x18/8) Graphic Display Data On-Chip regulator core logic voltage generation On-Chip display timing generator from external 32.768 clock source Available package current display mode (Main display QVGA 262k color, 60Hz; base band halt) current standby mode
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ORDERING INFORMATION
Table 3-1: Ordering Information Ordering Part Number SSD1918Z SSD1918L1 Resolution 240RGBx320 240RGBx320 Package Form Gold Bump Reference Figure Page Figure Page Remark
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BLOCK DIAGRAM
Figure SSD1918 Block Diagram
VDD(MAIN)
OSCEXT
Display Timing Generator Interface
VDD(BB)
Oscillator (SPI) GDDRAM 176x220x2x18 (Display Control)
Main Display Interface
RR[5:0], GG[5:0], BB[5:0], DOTCLK, HSYNC, VSYNC, SDI, SCK, MRES GPO[7:4] (SD,
HD[17:0] HR/W HD/C RESET PS[3:0] WAIT WSYNC
Base band Interface
Command Decoder
Buffer
Display Interface
VDD(CORE1) VDD(CORE) VSS(CORE) VSS(BB) VSS(MAIN) VSS(SUB) VSSEXT Regulator General Purpose Output
Parallel Serial
SD[8:0], SR/W SCS[6:0] SD/C SRES
VDDEXT
REGVDD
GPO[3:0]
VDD(SUB)
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FLOOR PLAN
Figure SSD1918 Floor Plan
(0,0) (256,256)
(25,266)
112.5 37.5 37.5 37.5 37.5 37.5 37.5
37.5
37.5
37.5
37.5
Coordinate: -2405um; -1955um
Coordinate: 2405um; -1955um
Coordinate: -2405um; 1955um 2405um; 1955um
Size Thickness Typical Bump Height
5.03 4.13 (Typ.)
Tolerance: within
Bump size (Pad 162) Minimum bump pitch
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SSD1918L1
Figure SSD1918L1 Pinout Diagram (Bottom view)
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2006 10/52
SSD1918
Table SSD1918 Bump Coordinates (Bump center)
Name X-pos Y-pos Name X-pos Y-pos Name X-pos Y-pos Name X-pos Y-pos
VSS(CORE) VSS(CORE) VDD(CORE) VDD(CORE) VDD(CORE) VDD(CORE1) VDD(CORE1) VDD(CORE1) VDDEXT VDDEXT VDDEXT REGVDD VSSEXT VSSEXT VSSEXT VSS(CORE) VDD(CORE) TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 VDD(CORE) VSS(CORE) -2200 -2100 -2000 -1900 -1800 -1700 -1600 -1500 -1400 -1300 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1994 -1750 -1650 -1550 HSYNC VSYNC VSS(CORE) VSS(CORE) MRES VDD(MAIN) VDD(MAIN) VSS(MAIN) VSS(MAIN) VSS(CORE) VSS(CORE) VSS(CORE) VSS(CORE) VDD(CORE) VDD(CORE) VSS(SUB) VSS(SUB) VDD(SUB) VDD(SUB) 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2444 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 -1450 -1350 -1250 -1150 -1050 -950 -850 -750 -650 -550 -450 -350 -250 -150 1050 1150 1250 1350 1450 1550 1650 1750 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 VSS(CORE) VDD(CORE) SR/W SD/C SRES SCS0 SCS1 SCS2 SCS3 SCS4 SCS5 SCS6 VSS(CORE) OSCEXT VSS(CORE) WSYNC WAIT RESET VDD(CORE) VDD(CORE) VSS(CORE) VSS(CORE) VSS(CORE) VSS(CORE) VSS(BB) VSS(BB) VDD(BB) VDD(BB) HD/C HR/W VSS(CORE) -100 -200 -300 -400 -500 -600 -700 -800 -900 -1000 -1100 -1200 -1300 -1400 -1500 -1600 -1700 -1800 -1900 -2000 -2100 -2200 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1994 1750 1650 1550 1450 1350 1250 1150 1050 VSS(CORE) HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 VDD(BB) VDD(BB) VSS(BB) VSS(BB) VSS(CORE) VSS(CORE) -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -2444 -150 -250 -350 -450 -550 -650 -750 -850 -950 -1050 -1150 -1250 -1350 -1450 -1550 -1650 -1750
GPO0
GPO1 GPO2
GPO3 1000 GPO4 (CM) 1100 GPO5 (TB) GPO6 (RL) GPO7 (SD) VDD(MAIN) VDD(MAIN) VSS(MAIN) VSS(MAIN) VDD(CORE) VDD(CORE) VSS(CORE) VSS(CORE) VSS(CORE) VSS(CORE) DOTCLK 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2444 2444 2444
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Table SSD1918L1 Assignment Table
Signal Name
VSS(CORE) WAIT SCS6 SCS2 VSS(CORE) SRES SR/W VSS(CORE) OSCEXT WSYNC SCS5 SCS3 SD/C VSS(CORE) VDD(CORE) MRES RESET SCS4 SCS0 VSS(SUB) VDD(SUB) VSS(CORE)
Signal Name
VSS(CORE) SCS1 TEST1 VSS(CORE) VDD(MAIN) VSS(CORE) HD/C HR/W VSS(BB) VDD(BB) VSS(MAIN) VSS(CORE)
Signal Name
VSS(CORE) VDD(CORE) GPO0 GPO4 VSS(CORE) HD10 HD11 VDD(CORE1) GPO1 GPO5 GPO7
Signal Name
HD12 HD13 HD14 REGVDD VSSEXT GPO2 GPO6 VSS(CORE) VSS(CORE) HD15 HD16 HD17 VDDEXT GPO3 DOTCLK HVSYN VSYNC VSS(CORE)
Solomon Systech
2006 12/52
SSD1918
DESCRIPTIONS
Input =Output Bi-directional (input/output) Power
Key:
Baseband Description
Table Baseband Description
Function Name width HD5-0 (SDO) Data (SCK) (SDI) HD17-9 (HRD) HR/W (HWR) HD/C WAIT
Description Data connected base band controller parallel mode, 8/9/16/18 interface, refer Section Interface Mapping definition. serial mode, HD6-HD8 used. Unused pins should connected
WSYNC RESET
PS3-0
68-system (enable signal) 80-system (read strobe signal) Serial mode used should connected 68-system (indicates read cycle when High, write cycle when Low) 80-system (write strobe signal) Serial mode used should connected Data command definition connected base band controller Active chip select connected base band controller During data transfer, this output driven high (WAIT polarity Logic programmed R0EH) force system insert wait states. control switching from high high) means chip ready accept next command/data from host. (Can disabled save power) When chip busy (WAIT High) data transfer chip, driven high provide interrupt signal avoid data(s) lost. will reset when WAIT data transfer chip. polarity programmed R0EH. (Can disabled save power) display data written synchronization avoid flicker main display. This will output pulse (high) display first main display data each frame. (Can disabled save power) System Active input internal registers default state. Reset PS(3:0) 000x Reserved 0100 bits parallel interface 0101 bits parallel interface Interface 0110 bits parallel interface selection 0111 bits parallel interface 1000 bits parallel interface 1001 bits parallel interface 1010 bits parallel interface 1011 bits parallel interface
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Main Display Description
Table 6-2: Main Display Description Type Function width Data Graphic Display Data Display Timing Signal
Name SDI, SCK, RR5-0 GG5-0 BB5-0 HSYNC VSYNC GPO7(SD) GPO6(RL) GPO5(TB)
Description Connect main display module's serial interface Graphic Display Data connect main display module's interface
DOTCLK
GPO4(CM MRES
Dot-clock signal oscillator source main display module. (polarity programmable) Line synchronization output signal. (polarity programmable) Frame synchronization output signal. (polarity programmable) Display enable output signal. (polarity programmable) Display shut down output signal. Panel Mapping Source driver data shift direction output signal. Control Gate driver scan direction output signal. Output signal select 262k-color 8-color display mode. output high (VDD(MAIN)), colors mode selected. output VSS, 262k colors mode Logic selected. Note, during color mode, internal operation this controller Control will also change minimize total power consumption, RR40/GG4-0/BB4-0 will output ignore content RAM. Reset Active reset pulse reset main display module
Display Description
Table 6-3: Display Description
Type Function Description Name width SD0-6 Data connected display. (SSCK) Data mode: SD[7] serial clock input SD[8] serial data (SSDA) input 68-system (enable signal) 80-system (read strobe signal) (SRD) Serial mode used should connected 68-system (indicates read cycle when High, write cycle when Low) Logic SR/W 80-system write strobe signal) Control (SWR) Serial mode used should connected SD/C Data (high) command (low) definition connected display Chip select connected display another slave device (polarity SCS6-0 programmable) SRES Reset Active reset pulse reset display module
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Power Description
Table 6-4: Power Description width
Name VDD(CORE1) VDD(CORE) VDDEXT VDD(BB) VDD(MAIN) VDD(SUB) VSS(CORE) VSS(BB) VSS(MAIN) VSS(EXT) VSS(SUB)
Type
Type
Description
Power supply output form Regulator. (must short VDD(CORE) with cap) Power supply core logic.(with cap) Power Power supply internal regulator. Supply Power supply baseband interface Power supply main display interface Power supply display interface Ground core logic Ground Ground baseband interface Power Ground main display interface Supply Ground internal regulator Ground display interface
Miscellaneous Description
Table 6-5: Miscellaneous Description Type Function Description width Oscillator non-stop oscillator input timing generation.( OSCEXT(P-P) input VDD(BB) Internal VDDEXT regulator control signal. When connected VDDEXT, internal VDDEXT regulator will when VDDEXT 2.2V, VDDEXT will disconnected from VDD(CORE) internally. When VDDEXT 2.2V, internal VDDEXT regulator will will internally short VDDEXT VDD(CORE). Regulator When connected VSS, internal regulator will regardless VDDEXT control voltage level, VDDEXT will internally shorted VDD(CORE). normal operation, connect REGVDD system VDDEXT below 2.5V, connect REGVDD VDDEXT system VDDEXT will above 2.5V. (VDD(CORE) need have 4.7uF 10uF capacitor connected case using internal VDDEXT regulator) Logic General purpose output pins Test Test pins testing purpose Dummy pins corners mechanical balance.
Name OSCEXT
REGVDD
GPO7-0 TEST8-1
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FUNCTIONAL BLOCK DESCRIPTIONS Base band Interface
Baseband Interface supports 8/9/16/18 bits 6800/8080 parallel interface, configure PS3-0 pins. Parallel 6800-series Interface parallel Interface consists bi-directional data pins (HD17 D0), HR/W, HD/C, HCS. HR/W input high indicates read operation from Graphical Display Data (GDDRAM) status register. HR/W input indicates write operation Display Data Internal Command Registers depending status input. input serves data latch signal (clock) when high provided that low. Please refer Parallel Interface Timing Diagram 6800-series microprocessors. order match operating frequency GDDRAM with that MCU, pipeline processing internally performed which requires insertion dummy read before first actual display data read. This shown following diagram.
Figure Read Display Data
HR/W
DATA
write column address
dummy read
data read
data read
data read
Parallel 8080-series Interface parallel interface consists bi-directional data pins HD17 HD0, HRD, HWR, HD/C HCS. input serves data read latch signal (clock) when provided that low. Whether reading display data from GDDRAM reading status from status register controlled HD/C. input serves data write latch signal (clock) when provided that low. Whether writing display data GDDRAM writing command command registers controlled HD/C. dummy read also required before first actual display data read 8080-series interface.
Table :Data selection modes 6800 series Parallel Interface 18/16/9/8-bits 18/16/9/8-bits Status only 8080 series Parallel Interface 18/16/9/8-bits 18/16/9/8-bits Status only
Data Read Data Write Command Read Command Write
interface powered VDD(BB) match with base band controller operating voltage. Base band Interface also provide WAIT handshaking signals with base band controller such that base band controller stop data transfer until SSD1918 ready accept command data.
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WSYNC output used data written synchronization avoid display incomplete page.
Main Display Interface
main interface consists interface, interface some display control bits (SD, using four general purpose output pins. Commands also translate from parallel format command decoder. format according SSD1278 interface format. main display interface operated VDD(MAIN) match with main display operating condition.
Interface
display data frame position information send main display control synchronize Gate Drive circuit shift registered source driver circuit.
provides serial interface control main display. clock synchronized serial peripheral interface (SPI) using chip select line (CS) serial transfer clock line (SCK), serial input data (SDI). SPID function uses pin. serial data transfer starts falling edge input ends rising edge Please Figure detail.
Figure 7-2: Interface Main Display Transfer starts
Transfer ends
DEVID[5:0]
Device code Start byte
Index register setting Instruction,
(Display Control)
provide standard control signal control Main Display, (Display Control) work General Purpose Output. Please "General Purpose Output detail.
Display Interface Buffer
display interface consists bits, 6800/8080 parallel interface together with wires serial interface. (Refer SSD1283 specification detail interface) data from base band first stored small buffer then transmitted display depending color format. display interface operated VDD(SUB) match with display operating condition.
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General Purpose Output
There totally eight general purpose output pins. output controlled bits register which programmed base band controller. output high level General Purpose Output same VDD(MAIN).
Display Timing Generator Oscillator
Display Timing Generator (DTG) works with internal oscillator generate necessary timing information interface main display. require constant 32kHz clock input operation. display frequency main display programmed from 30Hz 80Hz match with high quality 262k color display power color display mode, main display frame frequency will affected selection/settings internal clock freq, horizontal/vertical back/front porch partial/full screen selection.
Graphic Display Data (GDDRAM)
GDDRAM mapped static holding pattern displayed. size 174,240 bytes. mechanical flexibility, re-mapping both Segment Common outputs selected software.
7.10 Regulator
order provide 1.7~2.5V system core voltage (VDD(CORE)), SSD1918 integrated regulator generate required voltage internal operations. This regulator disabled setting REGVDD VSS, internal system core voltage will come from external VDDEXT pin.
Figure 7-3: Switching between external VDDEXT internal regulator
~2.2V VDDEXT
Regulator
REGVDD
VDD(CORE) 4.7uF 10uF
(REGVDD VDDEXT) (VDDEXT 2.2V) then Regulator regulator VDDEXT 2.2V VDD(CORE) Else VDDEXT connect VDD(CORE)
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2006 18/52
SSD1918
COMMAND TABLE
Table Command Table
Reg#
Register
HD/C IB15 IB14 IB13
IB12
IB11
IB10
Toggle Code Main Display RDAH R98H RDAH R99H Toggle Code Display controller Customer Command R00H Chip Frequency generator Enable Chip Select/interface selection Main/Sub display driver command interface frequency Control Control DOTCLK Frequency Vertical Display Setting Main Display Control Vertical Display Setting Horizontal Setting Horizontal Setting Slew rate control Slew rate control Entry Mode toggle byte Vertical Display Setting Vertical Display Setting Horizontal window setting Vertical window setting OSCEN
R01H
DEVID[5:0]
SLEEP
SINTF[2:0]
ESC[2:0]
R02H
GPENS
GPENM
SUBWT
DSSUB[3:0]
DSMAIN[3:0]
R03H R04H R05H R06H R07H R09H R0AH R0BH R0CH R0DH R0EH R0FH R12H
GPREGM[3:0]
GPREG2S[3:0] GPREGS[15:0]
GPO[7:0]
EMX[6:0]
FDIV[2:0] DS[5:0] TNS[3:0] TPM[3:0] CDEPTH TPO[3:0] TY[1:0] ID[1:0]
FSET[7:0] FMX[6:0] SHUT
IDOT IDEN
VFP[6:0]
VBP[6:0] XL[7:0] HBP[6:0] TNM[3:0] TNO[3:0] MATCHID[6:0]
HFP[6:0]
TPS[3:0]
ENWS PWAIT ENWAIT RAMTURBO
DENS[8:0]
R13H
DENE[8:0]
R14H R15H R16H R17H
HEA[7:0]
HAS[7:0] VSA[8:0] VEA[8:0] VSMODE[1:0] MTYPE WSEL DSEL
GRAM Paging setting R20H horizontal address vertical R21H address
AD[7:0] AD[16:8]
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Reg# R22H
Register
HD/C IB15 IB14 IB13
IB12
IB11
IB10
Write Data GRAM Read Data R22H GRAM Other above
WD[17:0] mapping depends interface setting RD[17:0] mapping depends interface setting Reserved
Table Power Reset Register value
Reg# Register R00H Chip Frequency generator R01H Enable Chip Select/interface selection R02H Main/Sub display driver command interface frequency R03H Control R04H Control R05H DOTCLK Frequency R06H Vertical Display Setting R07H Main Display Control R09H Vertical Display Setting R0AH Horizontal Setting R0BH Horizontal Setting R0CH Slew rate control R0DH Slew rate control R0EH Entry Mode R0FH toggle byte R12H Vertical Display Setting R13H Vertical Display Setting R14H Horizontal window setting R15H R16H R17H GRAM Paging setting R20H horizontal address R21H vertical address Vertical window setting
IB15 IB14 IB13 IB12 IB11 IB10
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2006 20/52
SSD1918
COMMAND DESCRIPTIONS Toggle Code
RDAH,R98H: After receiving such command bytes, commands/data will buffered sent main/sub display driver, display controller itself will executes those commands data until receive other TOGGLE CODE(RDAH, R99H). RDAH,R99H: After receiving such command bytes, commands/data will sent this display controller main/sub display driver interface will received those followed commands/data.
HR/W
chip frequency generator (R00H)
HD/C
IB15
IB14
IB13
IB12
IB11
IB10
OSCEN
OSCEN this onchip freq generator will start lock 32khz within 10ms. (Por
HR/W
Enable Chip Select/interfaces selection (R01H)
HD/C
IB15
DEVID5
IB14
DEVID4
IB13
DEVID3
IB12
DEVID2
IB11
DEVID1
IB10
DEVID0
ECS2
ECS1
ECS0
SLEEP SINTF2 SINTF1 SINTF0
DEVID[5:0] 6bit device Main display drive interface. (POR 011100) SLEEP: SLEEP whole ssd1918 will lowest power consumption condition. only hold register content reliable write/read ram, frequency generator will (even oscen=1). SLEEP will leave sleep mode reliable write read ram. frequency generator will depended oscen bit. (POR SINTF[2:0] Display interface type selection. SINTF[2:0] Interface display 9bit parallel interface 8bit parallel interface 9bit parallel interface 8bit parallel interface (POR) wires interface wires interface
(Note main display driver interface fixed 24bit format interface, SINTF2-0 effect main display driver interface) RWC: clock selection parallel interface display. interface) interface) will become clock signal will static active level only. will become clock signal will static active level. (POR PCS: control polarity display driver signal. means active high SCS; while active (POR ECS[2-0] select display driver receive commands/data, once Toggle Code received. Total addressable display driver from with main driver mapped 000, driver (CS1) mapped 001, driver (CS2) mapped 010, etc) respectively. (POR 000)
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Main/Sub display driver command interface frequency (R02H)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10
GPENS GPENM SUBWT DSSUB3 DSSUB2 DSSUB1 DSSUB0 DSMAIN3 DSMAIN2 DSMAIN1 DSMAIN0
GPENS General purpose output enable driver. will ignore driver command interface will treat 16bit general purpose whose value defined GPREGS[15-0] (POR GPENM General purpose output enable main driver. will ignore interface main driver treat {SDI,SCK,CS,MRES} general purpose output whose value defined GPREGM[3-0] (POR SUBWT: display driver command data write through this will directly pass baseband input data/ command display driver without through buffer. DSSUB[3-0] will meaningless then. User should correct interface type driver match with base band data interface) before this (POR DSMAIN[3-0] select Main driver interface cycle time. (unit:
CYCLE DSMAIN [3-0] 3(POR)
DSSUB[3-0]: select parallel interface cycle time. (unit:
CYCLE DSSUB [3-0] 3(POR)
Control Main (R03H)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 GPREGM3 GPREGM2 GPREGM1 GPREGM0 GPO7GPO6GPO5GPO4 GPO3 GPO2 GPO1GPO0
GPREGM[3-0] output SDI,SCK,CS,MRES respectively GPENM=1. (POR 1111) GPENM GPREGM[0] also mapped MRES. Thus, Host reset main display controlling GPREGM[0]. during RESET MRES will also output reset main display driver. GPREG2S[3-0] output SCS6, SCS5, SCS4, SCS3 respectively GPENS=1. (POR 1111) GPO[7-0] Used control General Purpose Output pins output. (POR 01100000)
HR/W
Control (R04H)
HD/C
IB15
GPREGS15
IB14
GPREGS14
IB13
GPREGS13
IB12
GPREGS12
IB11
GPREGS11
IB10
GPREGS10
GPREGS9
GPREGS8
GPREGS7
GPREGS6
GPREGS5
GPREGS4
GPREGS3
GPREGS2
GPREGS1
GPREGS0
GPREGS[15-0]: GPREGS[15:0] mapped output pins respectively GPENS=1 (POR FFH) GPENS GPREGS[11] also mapped SRES. Thus, Host reset display controlling GPREGS[11]. during RESET SRES will also output reset display driver.
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HR/W
DOTCLK frequency (R05H)
HD/C
IB15
IB14
IB13
IB12
IB11
IB10
FDIV2
FDIV1
FDIV0
FSET7
FSET6
FSET5
FSET4
FSET3
FSET2
FSET1
FSET0
FSET[7:0] FDIV[2:0] Used control main display DOTCLK frequency DOTCLK frequency OSCEXT(External 32.768KHz clock source) FSET[7:0] FDIV[2:0]
FSET7 FSET6 FSET5 FSET4 FSET3 FSET2 FSET1 FSET0 FSET[7:0] 47(POR) FOSC/OSCEXT 80(POR) Step
FDIV2
FDIV1
FDIV0
FDIV[2:0] (POR)
FOSC/DOTCLK 1(POR) 1.33 2.66
Example OSCEXT 32.768kHz; FSET[7:0] (POR); FDIV[2;0] (POR) DOTCLK (POR) 32.768k 2.621MHz Example OSCEXT 32.768kHz; FSET[7;0] FDIV[2;0] DOTCLK 32.768k 2.195
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Vertical Display Setting (R06H)
FMX6 FMX5 FMX4 FMX3 FMX2 FMX1 FMX0
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 EMX6 EMX5 EMX4 EMX3 EMX2
FMX6-0: Specify number lines driver multiple full color display mode, setting exceeds lines will treated lines. EMX6-0: Specify number lines driver multiple colors display mode, setting exceeds lines will treated lines. width will change according this setting)
lines display Step 220(POR) Step=4
HR/W
Main Display Control (R07H)
HD/C IB15 IB14 IB13 IDOT IB12 IDEN IB11 IB10 SHUT
polarity VSYNC signal. VSYNC will invert Polarity corresponding Main display output signal. (POR polarity HSYNC signal. HSYNC will invert Polarity corresponding Main display output signal. (POR IDOT polarity DOTCLK signal. DOTCLK will invert Polarity corresponding Main display output signal. (POR IDEN polarity signal. will invert Polarity corresponding Main display output signal. (POR DS[5:0] R[5:0], G[5:0], B[5:0] data sequence ordering hardware RR[5:0], GG[5:0], BB[5:0]. DS[2:0] sequence GDDRAM DS[5:0] data orientation hardware RR[5:0], GG[5:0] BB[5:0]. (000000 POR)
DS[2:0] (POR) Ordering Reserved Reserved
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Data Sequence R0/G0/B0 R5/G5/B5. R5/G5/B5 R0/G0/B0. R0/G0/B0 R5/G5/B5 R5/G5/B5 R0/G0/B0 R0/G0/B0 R5/G5/B5 R5/G5/B5 R0/G0/B0 Hardware Pins
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SHUT: will stop internal display engine GDDRAM access save power. internal clock generator will also stop tuned setting will saved reused when SHUT=0 later. won't since (and RL,CM pin) will controlled another general purpose register) (POR When color depth main display will 262k color. When controller will output color data with most significant bits only. other bits will shorted power reduction. (POR
9.10 Vertical Display Setting (R09H)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 VFP6 VFP5 VFP4 VFP3 VFP2 VFP1 VFP0 VBP6
VBP5 VBP4 VBP3 VBP2 VBP1 VBP0
VBP6-0: delay period from falling edge VSYNC first valid line. line data within this delay period will treated dummy line. (POR 0000011 LINE) VFP6-0: delay period from last valid line falling edge VSYNC. line data within this delay period will treated dummy line. (POR 0000001 LINE) Note:
VBP6 VBP5 VBP4 VBP3 VBP3 VBP2 VBP1 VBP0 clock cycle HSYNC (Only allow when CAD=0) Step clock cycle HSYNC
VBP6
VBP5
VBP4
VBP2
VBP1
VBP0
Cycle time VSYNC VBP6-0
VSYNC HSYNC
Dummy Lines Line
MUX6-0
Last Line
Dummy Lines
VFP6
VFP5
VFP4
VFP3 VFP3
VFP2
VFP1
VFP0
VFP6
VFP5
VFP4
VFP2
VFP1
VFP0
clock cycle HSYNC (Only allow when CAD=0) Step clock cycle HSYNC
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9.11 Horizontal Setting (R0AH)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10
XL[7:0] number valid pixel line.
pixel line Step=1 176(POR) Step
9.12 Horizontal Setting (R0BH)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 HFP6 HFP5 HFP4 HFP3 HFP2 HFP1 HFP0 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0
HBP[6:0] delay period from falling edge HSYNC signal first valid data. (POR 0001001 clocks) HFP[6:0] delay period from last valid data falling edge HSYNC (POR 0001001 clocks)
HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 clock cycle DOTCLK Step clock cycle DOTCLK Step
HFP4
HFP0
HFP6
HFP5
HFP3 HFP2 HFP1
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Cycle time HYSYNC HBP7-0 XL7-0
HYSNC Pixel Data DOTCLK
Default pixels line
Dummy D173 D174 D175 Dummy
clock cycles DOTCLK HBP5-0 000110
9.13 Slew rate control (R0CH)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 TPS3 TPS2 TPS1 TPS0 TNS3 TNS2 TNS1 TNS0 TPM3 TPM2 TPM1 TPM0
TNM[3:0], TPM[3:0] control high speed main output pins high output impedance from 110ohm (1111) 3000ohm (0000)). (POR 1111, 1111) Pins involved: RR[5:0], GG[5:0], BB[5:0], VSYNC, HSYNC, DEN, DOTCLK TNS[3:0], TPS[3:0] control high speed output pins high output impedance from 110ohm (1111) 3000ohm (0000)). (POR 1111, 1111) Pins involved: SD[8:0], SCS[1:0], SRW, SDC, SRES
9.14 Slew rate control2 (R0DH)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 TPO3 TPO2 TPO1 TPO0 TNO3 TNO2 TNO1 TNO0
TNO[3:0], TPO[3:0] Control other output pins high output impedance from 110ohm (1111) 3000ohm (0000)). (POR 1111, 1111) Pins involved: SDI, SCK, MRES, GPO[7:4] CM), GPO[3:0], HD[17-0], HR/W, HD/C, HCS, WAIT, IRQ, WSYNC
9.15 Entry Mode (R0EH)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 ENWS PWAIT ENWAIT RAMTURBO CDEPTH
ENWS used enable WSYNC function. ENWS then enable WSYNC output pulse (high) after send last rows display data main display driver. ENWS WSYNC always output low. (POR RAMTURBO: This used fully utilized bandwidth baseband (host) data when writing pixel data display driver interface. (POR RAMTURBO fully utilize bandwidth baseband. RAMTURBO normal usage bandwidth baseband. Fully Utilize Mode(RAMTURBO host interface 18bit, interface 8bit spi, then host cycle will convert three 8bit interface cycle, with each cycle only significant padding zero bits.
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Example: Data send Baseband interface cycle HD17-0 110011101010111111 Data send sub-display (8bits): cycle SD8-1 110011 cycle SD8-1 101010 cycle SD8-1 111111 host interface 9bit, interface 8bit spi, then host cycle will convert three 8bit interface cycle with each cycle only significant padding zero bits Example: Data send Baseband interface HD8-0 110011101 HD8-0 010111111 Data send sub-display (8bits): cycle SD8-1 110011 cycle SD8-1 101010 cycle SD8-1 111111 Normal Usage Mode (RAMTURBO host interface 18bit, interface 8bit spi, then host cycle will convert 8bit interface cycle Example: cycle HD17-0 110011101010111111 Data send sub-display (8bits): cycle SD8-1 11001110 cycle SD8-1 01011111 host interface 9bit, interface 8bit spi, then host cycle will convert 8bit interface cycle Example: cycle HD8-0 010111111 Data send sub-display (8bits): cycle SD8-1 01011111 PWAIT: this used polarity WAIT signals. WAIT both active low. WAIT both active high (POR ENWAIT: this used enable/disable WAIT IRQ. enable WAIT IRQ. disable WAIT IRQ. (POR CDEPTH: control color depth write GDDRAM from Baseband interface. CDEPTH bits data will written into GDDRAM. CDEPTH bits data will written into GDDRAM
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TY[1:0]: 262k color mode, parallel interface, there three types methods writing data into ram, Type described below.
Writing mode Type Type (POR) Type
Interface Color mode Cycle 262k Type 262k Type 262k Type Remark
Hardware pins
Don't care bits connected pins
ID[1:0]: address counter automatically incremented after data written GDDRAM when ID[1:0] "1". address counter automatically decremented after data written GDDRAM when ID[1:0] "0". setting incrementing decrementing address counter made independently each upper lower address. direction address when data written GDDRAM with bits.(POR direction which address counter updated automatically after data written GDDRAM. When "0", address counter updated horizontal direction. When "1", address counter updated vertical direction. When window addresses selected, data written GDDRAM area specified window addresses manner specified with ID[1:0] bits. (POR
I/D[1:0]="00" I/D[1:0]="01" I/D[1:0]="10" I/D[1:0]="11"
Horizontal: decrement
Vertical: decrement 0000h AM="0" Horizontal 13FEFh 0000h AM="1" Vertical 13FEFh
Horizontal: increment
Vertical: decrement 0000h
Horizontal: decrement
Vertical: increment 0000h
Horizontal: increment
Vertical: increment 0000h
13FEFh 0000h 0000h
13FEFh 0000h
13FEFh
13FEFh
13FEFh
13FEFh
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9.16 toggle byte (R0FH)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 MATCHID
MATCHID[6:0] this toggle byte, (R98h R99h),this gives some flexibility choice different main/sub display drivers (since R98,R99 already been used critical commands some vendors drivers). (POR 1001100)
9.17 Vertical Display Setting (R12H)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 DENS DENS DENS DENS DENS DENS DENS DENS DENS
VS[8:0] Vertical display offset, starting position pulse (POR 00000000). This feature usually only useful partial display mode (ie. Less than full display)
9.18 Vertical Display Setting (R13H)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10
DENE8 DENE7 DENE6 DENE5 DENE4 DENE3 DENE2 DENE1 DENE0
VE[8:0] Vertical display offset, Ending position pulse (POR 0DBH).This feature usually only useful partial display mode (ie. Less than full display)
9.19 Horizontal window setting (R14H)
IB15 IB14 IB13 IB12 IB11 IB10 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
HSA[7:0]/HEA[7:0]: Specify start/end positions window address horizontal direction address unit. Data written GDDRAM within area determined addresses specified HEA[7:0] HSA[7:0]. These addresses must before write. setting these bits, make sure that "00"h HSA[7:0] HEA[7:0] "EF"h. (POR HAS[7:0] 00000000 HEA[7:0] 10101111)
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9.20 Vertical window setting (R15H VSA, R16H VEA)
IB15 IB14 IB13 IB12 IB11 IB10 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0
VSA[8:0]/VEA[8:0]: Specify start/end positions window address vertical direction address unit. Data written GRAM within area determined addresses specified VEA[7:0] VSA[7:0]. These addresses must before write. setting these bits, make sure that "00"h VSA[7:0] VEA[7:0] "13F"h. (POR VSA[8:0] 000000000 VEA[8:0] 011011011)
9.21 GDDRAM Paging setting (R17H)
IB15 IB14 IB13 IB12 IB11 IB10 VSMODE1 VSMODE0 MTYPE WSEL1 DSEL
VSMODE[1:0] used synchronize "DSEL" internally. VSMODE[1:0] SYNC SYNC SYNC frame (POR) SYNC frames SYNC frames
MTYPE: When MTYPE select 18bits pages GDDRAM. When MTYPE select 18bits GDDRAM. (POR WSEL When WSEL data will written RAMA. When WSEL data will written RAMB. (POR DSEL When DSEL data RAMA will sent Main display. When DSEL data RAMB will sent Main display. (POR MTYPE WSEL DSEL Write RAMA RAMA RAMB RAMB Display form RAMA RAMB RAMA RAMB GDDRAM SIZE bits pages bits
9.22 horizontal address (R20H) vertical address (R21H)
HR/W HD/C IB15 IB14 IB13 IB12 IB11 IB10 AD16 AD15 AD14 AD13 AD12 AD11 AD10
AD[16:0] Make initial settings GDDRAM address address counter (AC). After GRAM data written, address counter automatically updated according settings with bits setting GDDRAM address required address counter. Therefore, data written consecutively without setting address. address counter automatically updated when data read from GDDRAM. (AD[16:8] vertical address, AD[7:0] horizontal) (POR 0000 0000 0000 0000) address setting should made within area designated with window addresses.
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9.23 Write Data GRAM (R22H)
HR/W HD/C D[17:0] WD[17:0] mapping depends interface setting
WD[17:0] Transforms GDDRAM data into 18-bit, writes data. Format transforming data into 18-bit depends interface used. After writing data GDDRAM, address automatically updated according bit. Access GDDRAM during stand-by mode available.
9.24 Read Data from GRAM (R22H)
HR/W HD/C D[17:0] RD[17:0] mapping depends interface setting
RD[17:0] Read 18-bit data from GDDRAM. When data read microcomputer, first-word read immediately after GDDRAM address setting latched from GDDRAM internal read-data latch. data data (DB17-0) becomes invalid second-word read normal. display data available main display driver (shut down) during reading ram. assume "SHUT" during reading through data pins) This reading testing purpose rather than normal application usage.
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MAXIMUM RATINGS
Table 10-1 Maximum Ratings (Voltage Referenced VSS) Symbol VDDCORE VDDBB Parameter Supply Voltage Current Drain Excluding Operating Temperature Storage Temperature Value -0.3 +2.5 -0.3 +3.6 -0.3 +3.6 -0.3 +3.6 +150 Unit
Tstg
Maximum ratings those values beyond which damages device occur. Functional operation should restricted limits Electrical Characteristics tables Description section This device contains circuitry protect inputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high impedance circuit. proper operation recommended that VOUT constrained range VOUT. Reliability operation enhanced unused input connected appropriate logic voltage level (e.g., either VDD). Unused outputs must left open. This device light sensitive. Caution should taken avoid exposure this device light source during normal operation. This device radiation protected.
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CHARACTERISTICS
Conditions:
Voltage referenced 3.6V 85°C Table 11-1 Characteristics Symbol VDD(core) VDD(BB) VDD(main) VDD(sub) VDDEXT VDDEXT VOH1 VOL1 VIH1 VIL1 IVDDEXT(slp) IVDDEXT(std) IVDDEXT(dp) IVDDMAIN(dp) IVDDSUB(dp) IVDDBB(dp) IIL/IIH f32k Parameter Test Condition System power supply pins logic block Power supply base band interface logic. Power supply main display interface logic. Power supply display interface logic. Power supply system power VDDREG regulator Power supply system power VDDREG VDDEXT regulator Logic High Output Voltage Logic Output Voltage Logic High Input voltage Logic Input voltage Logic High Output Current Source Logic Output Current Drain Logic Output Tri-state Current Drain Source VDDEXT Sleep mode Current VDDEXT Stand Current VDDEXT Display Current VDDMAIN Display Current VDDSUB Display Current VDDBB Display Current Logic Input Current Logic Pins Input Capacitance Constant 32kHz input Vout VDD-0.4V Vout 0.4V Iout=-100A Iout=100A 0.1*V 0.2*V 1000 Unit
0.9* 0.8*V
VDDEXT/VDDBB/VDDMAIN/VDDSUB =2.6 Without panel loading
Note FOSC stands frequency value internal oscillator
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CHARACTERISTICS 12.1 Interface Timing
12.1.1 Baseband Controller Interface Timing (6800 mode) Conditions:
Voltage referenced VDD(Core)=1.7V 2.5V -40°C 85°C Table 12-1 Parallel 6800-series Interface Timing Characteristics (Baseband Controller) Symbol tCYCLE PWCSL PWCSH tCYCLE PWCSL PWCSH tDSW tDHW tACC Parameter Clock Cycle Time (write cycle) Control Pulse Width (write cycle) Control Pulse High Width (write cycle) Clock Cycle Time (read cycle) Control Pulse Width (read cycle) Control Pulse High Width (read cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Data Access Time Output Hold time Fall time Rise time Unit
Figure 12-1 Parallel 6800-series Interface Timing Characteristics (Baseband Controller)
HD/C
HR/W
tCYCLE PWCSH tDSW
PWCSL
HD0~HD17(WRITE)
Valid Data tACC
HD0~HD17(READ)
Valid Data
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12.1.2 Baseband Controller Interface Timing (8080 mode) Conditions:
Voltage referenced VDD(Core)=1.7V 2.5V -40°C 85°C Table 12-2 Parallel 8080-series Interface Timing Characteristics (Baseband Controller) Symbol tCYCLE PWCSL PWCSH tCYCLE PWCSL PWCSH tDSW tDHW tACC Parameter Clock Cycle Time (write cycle) Control Pulse Width (write cycle) Control Pulse High Width (write cycle) Clock Cycle Time (read cycle) Control Pulse Width (read cycle) Control Pulse High Width (read cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Data Access Time Output Hold time Fall time Rise time Unit
Figure 12-2 Parallel 8080-series Interface Timing Characteristics (Baseband Controller) Write Cycle
HD/C tCYCLE PWCSL PWCSH
tDSW Valid Data
tDHW
HD0~HD17
Read Cycle
HD/C PWCSL tACC tCYCLE PWCSH
HD0~HD17
Valid Data
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12.1.3 Controller Main display interface timing (3-wire mode) Conditions:
Voltage referenced VDD(Core)=1.7V 2.5V -40°C 85°C Table 12-3 3-wire Serial Timing Characteristics (Controller Main display) Symbol tCYCLE fCLK tCSS tCSH tDSW tDHW tCLKL tCLKH Parameter Clock Cycle Time Serial Clock Cycle Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Time Clock High Time
Unit
Figure 12-3 3-wire Serial Timing Characteristics (Controller Main display)
tCSS tCYCLE
tCLKL
tCLKH
tDSW Valid Data
tDHW
Transfer Start
Transfer
tCSS
tCSH
Data23
Data22
Data21
Data0
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12.1.4 Controller Display interface timing (6800 mode) Conditions:
Voltage referenced VDD(Core)=1.7V 2.5V -40°C 85°C Table 12-4 Parallel 6800-series Interface Timing Characteristics (Controller display) Symbol tCYCLE PWCSL PWCSH tDSW tDHW Parameter Clock Cycle Time (write cycle) Control Pulse Width (write cycle) Control Pulse High Width (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time
Figure 12-4 Parallel 6800-series Interface Timing Characteristics (Controller display)
SD/C SR/W
tCYCLE PWCSH PWCSL
tDSW SD0~SD8(WRITE)
tDHW
Valid Data
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12.1.5 Controller Display interface timing (8080 mode) Conditions:
Voltage referenced VDD(Core)=1.7V 2.5V -40°C 85°C Table 12-5 Parallel 8080-series Interface Timing Characteristics (Controller display) Symbol tCYCLE PWCSL PWCSH tDSW tDHW Parameter Clock Cycle Time (write cycle) Control Pulse Width (write cycle) Control Pulse High Width (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time
Figure 12-5 Parallel 8080-series Interface Timing Characteristics (Controller display) Write Cycle
SD/C tCYCLE PWCSL PWCSH
tDSW
tDHW
SD0~SD8
Valid Data
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12.1.6 Controller Display interface timing (4-wire mode) Conditions:
Voltage referenced VDD(Core)=1.7V 2.5V -40°C 85°C Table 12-6 4-wire Serial Timing Characteristics (Controller display) Symbol tCYCLE fCLK tCSS tCSH tDSW tDHW tCLKL tCLKH Parameter Clock Cycle Time Serial Clock Cycle Time Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Time Clock High Time Unit
Figure 12-6 4-wire Serial Interface Timing Characteristics (Controller display) SD/C
tCSS tCYCLE tCSH
tCLKL
tCLKH
SCK(SD6)
tDSW tDHW
SDI(SD7)
Valid Data
SCK(SD6)
SDI(SD7)
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12.1.7 Controller Display interface timing (3-wire mode) Conditions:
Voltage referenced VDD(Core)=1.7V 2.5V -40°C 85°C Table 12-7 3-wire Serial Timing Characteristics (Controller display) Symbol tCYCLE fCLK tCSS tCSH tDSW tOHW tCLKL tCLKH Parameter Clock Cycle Time Serial Clock Cycle Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Time Clock High Time Unit
Figure 12-7 3-wire Serial Interface Timing Characteristics (Controller display)
tCSS tCYCLE tCSH
tCLKL SCK(SD6) tDSW SDI(SD7) Valid Data
tCLKH
tDHW
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APPLICATION EXAMPLES 13.1 Application Diagram
Figure 13-1 Application Examples (SSD1918 application circuit with 2.775V MCU)
Display Interface
D0-7 D0-7
2.775V
32kHz
INT0 INT1 INT2 2.775V SD1-8 SR/W SD/C SRES SCS0 OSCEXT WSYNC WAIT VDD(SUB) VSS(SUB)
2.775V BB0-5 GG0-5 RR0-5 VSYNC HSYNC DOTCLK
RESET D0-17 2.775V
VDD(MAIN) VSS(MAIN
MRES
SSD1278 Interface
RESET HD/C HR/W HD0-17
SSD1918
GP05(TB) GPO4(CM) VSSEXT VDDEXT REGVDD VDD(CORE1) VDD(CORE) VSS(CORE)
BB0-5 GG0-5 RR0-5 VSYNC HSYNC DOTCLK
GP07(SD) GP06(RL)
VDD(BB) VSS(BB)
2.775V
Other pins connection: Ground Interface: Base Band bits 6800 Main Display SSD1278) display 8-bits 6800
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Figure 13-2 Application Examples (SSD1918 application circuit with 1.8V MCU)
Display Interface
D0-7 D0-7
2.775V
32kHz
INT0 INT1 INT2
VSS(SUB) VDD(SUB)
2.775V
2.775V VDD(MAIN) VSS(MAIN) BB0-5 GG0-5 RR0-5 VSYNC HSYNC DOTCLK
RESET D0-17 2.775V
SD1-8 SR/W SD/C SRES SCS0 OSCEXT WSYNC WAIT
RESET HD/C HR/W
SSD1278 Interface
SSD1918
MRES
BB0-5 GG0-5 RR0-5 VSYNC HSYNC DOTCLK
HD0-17
GP07(SD) GP06(RL) GP05(TB) GPO4(CM) VSSEXT VDDEXT REGVDD VDD(CORE1) VDD(CORE) VSS(CORE)
2.775V
VDD(BB) VSS(BB)
Other pins connection: Ground Interface: Base Band bits 6800 Main Display SSD1278) display 8-bits 6800
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FLOW CHART SSD1918 POWER UP/DOWN 14.1 SSD1918 Power Sequence
Figure 14-1 SSD1918 power sequence
Power Sequence
Supply (VDDEXT, VDD(BB), VDD(MAIN), VDD(SUB) Wait 10ms Leave Sleep mode (R01, 7080H) Wait DOTCLK freq. (R05H, 002FH); Vertical Display Setting; Horizontal Setting; display interface. Wait 10ms Enable chip frequency generator (R00H, 0001H); Wait 20ms Normal Write then start internal Display engine (SHUT Wait Send Toggle code control Main/Sub Display drivers (RDAH, R98H)
Refer corresponding datasheet control Main/Sub Display driver
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13.2 SSD1918 Power Down Sequence
Figure 14-2 SSD1918 power down sequence
Power down Sequence
Toggle Main Display (RDAH, 98H)
Turn Main display
(RDAH, 99H) toggle SSD1918 (R01H, 7081H) register select display (RDAH, 98H) toggle display
Turn display Wait 10ms Toggle SSD1918 (RDAH, R99H)
Stop internal display engine (SHUT
Wait Disable chip frequency generator (R00H, 0000H); Wait Enable Sleep mode (R01, 7180H)
Power
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13.3 SSD1918 Enter Power Save Mode
Figure 14-3 SSD1918 Enter Power save mode
Enter power save mode
Toggle Main Display (RDAH, R98H)
Turn Main display
Toggle SSD1918 (RDAH, R99H)
Stop internal Display engine (SHUT
Disable chip frequency generator (R00H, 0000H);
Enable Sleep mode (R01, 7180H)
Remark: power save mode, user toggle display update display. signal clock send Main display form SSD1918.
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13.4 SSD1918 From Sleep Mode Return Normal Mode
Figure 14-4 SSD1918 From sleep mode return normal mode
Return normal mode
Leave Sleep mode (R01, 7080H) Wait 10ms Enable chip frequency generator (R00H, 0001H); Wait 20ms Start internal display engine SHUT
Wait Send Toggle code control Main Display drivers (RDAH, R98H)
Turn Main Display
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GDDRAM ADDRESS
Vertical address
316, 317, 318, 319, Horizontal address
316, 317, 318, 319,
316, 317, 318, 319,
316, 317, 318, 319,
316, 317, 318, 319,
Note: address format, where vertical address horizontal address
INTERFACE MAPPING 15.1 Mapping Writing Instruction SSD1918
Interface bits bits bits bits Remark Cycle IB15 IB14 IB13 IB12 IB11 IB10 IB15 IB14 IB13 IB12 IB11 IB10 Don't care bits connected pins Hardware pins IB15 IB14 IB13 IB12 IB11 IB10 IB15 IB14 IB13 IB12 IB11 IB10
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15.2 Mapping Writing pixel data SSD1918
Interface Color mode Cycle bits 262k 262k bits 262k bits 262k bits Remark Hardware pins
Don't care bits connected pins
WSYNC APPLICATION
WSYNC
100% Memory Access
Fast write Slow write Controller displaying
time when there Update screen from on-chip content. time when screen updating based on-chip content. fast write MCU: should start write frame data just after rising edge long WSYNC pulse should finished well before rising edge next long WSYNC pulse. slow write (Half write speed fast write): should start write frame data after rising edge first short WSYNC pulse must finished within frames time.
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SSD1918
WAIT/IRQ APPLICATION
Under following conditions, WAIT will asserted until internal operation completed. Writing serial command main display using host's parallel interface; Writing memory command display when width host wider than width display Host frequency higher than display frequency;
SSD1918L1 PACKAGE DRAWING
Figure 20-1 SSD1918L1 Package Mechanical Drawing
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Solomon Systech reserves right make changes without further notice products herein. Solomon Systech makes warranty, representation guarantee regarding suitability products particular purpose, does Solomon Systech assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Solomon Systech does convey license under patent rights rights others. Solomon Systech products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Solomon Systech product could create situation where personal injury death occur. Should Buyer purchase Solomon Systech products such unintended unauthorized application, Buyer shall indemnify hold Solomon Systech offices, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Solomon Systech negligent regarding design manufacture part.
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Solomon Systech
2006 52/52
SSD1918

QVGA Graphic Controller with built-in This document contains info

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