logic supply range Power reset (POR) data input rate CMOS, compatible

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logic supply range Power reset (POR) data input rate CMOS, compatible

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A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers
logic supply range Power reset (POR) data input rate CMOS, compatible -40°C operation available Schmitt trigger inputs improved noise immunity Low-power CMOS logic latches High-voltage current-sink outputs Internal pull-up/pull down resistors
merged combination bipolar technology gives these devices interface flexibility beyond reach standard logic buffers power driver arrays. Typical applications include driving multiplexed displays incandescent lamps. A6821 eight-bit CMOS shift register CMOS control circuitry, eight CMOS data latches, eight bipolar current-sinking Darlington output drivers. CMOS inputs compatible with standard CMOS logic levels. circuits require appropriate pull-up resistors. using serial data output, drivers cascaded interface applications requiring additional drive lines.
Applications:
Multiplexed displays Incandescent lamps
Packages:
Package 16-pin Package 16-pin SOICW
A6821SA furnished standard 16-pin plastic DIP. A6821EA 16-pin plastic DIP, capable operation from -40°C 85°C. A6821SLW 16-lead wide-body SOIC, surface-mount applications. These devices lead (Pb) free, with 100% matte plated leadframes.
scale
Functional Block Diagram
OUND
IAL-P ALLE
LOW) OLAR OUND
26185.112D
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Selection Guide
Part Number Package Ambient Packing
A6821SA-T 16-pin pieces tube A6821EA-T* 16-pin pieces tube A6821SLWTR-T 16-pin wide body SOIC 1000 pieces reel *Variant production been determined DESIGN. This classification indicates that sale variant currently restricted existing customer applications. variant should purchased design applications because obsolescence near future probable. Samples longer available. Status change: 2009.
Absolute Maximum Ratings
Characteristic Logic Supply Voltage Input Voltage Range Output Voltage Continuous Output Current Power Dissipation Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VOUT IOUT TJ(max) Tstg package package Range Range Caution: CMOS devices have input-static protection, susceptible damage when exposed extremely high static-electrical charges. Notes Rating -0.3 Unit
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: 25°C, logic supply operating voltage
Characteristic
Output Leakage Current Collector-Emitter Saturation Voltage Input Voltage Input Resistance Serial Data Output Voltage Maximum Clock Frequency2 Logic Supply Current
Typ.
4.75 0.15
Symbol
ICEX VCE(SAT) VIN(1) VIN(0) VOUT(1) VOUT(0) IDD(1) IDD(0) tdis(BQ) ten(BQ) tp(STH-QL) tp(STH-QH) tp(CH-SQX)
Test Conditions
VOUT IOUT IOUT IOUT
Min.
Typ.
3.05 0.15
Max. Min.
Max.
Units
IOUT -200 IOUT output outputs off, through IOUT ±200
Output Enable-to-Output Delay Strobe-to-Output Delay Output Fall Time Output Rise Time Clock-to-Serial Data Delay
1Positive
(negative) current defined conventional current going into (coming specified device pin. 2Operation clock frequency greater than specified minimum value possible warranteed.
Truth Table
Serial Data Clock Input Input Shift Register Contents Serial Data Output
Logic Level High Logic Level Irrelevant Present State Previous State Output Enable Strobe
Latch Contents Strobe Input
Output Enable Input
Output Contents
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Timing Requirements Specifications
(Logic Levels Ground)
CLOCK SERIAL DATA DATA
p(CH-SQX) SERIAL DATA STROBE
DATA
OUTPUT ENABLE
OUTP NABLE tp(STH-QH) tp(STH-QL)
DATA
HIGH OUTP BLANKE (DIS ABLE OUTPUT ENABLE
en(BQ) dis(BQ)
DATA
Description Data Active Time Before Clock Pulse (Data Set-Up Time) Data Active Time After Clock Pulse (Data Hold Time) Clock Pulse Width Time Between Clock Activation Strobe Strobe Pulse Width
Symbol tsu(D) th(D) tw(CH) tsu(C) tw(STH)
Time (ns)
NOTE: Timing representative clock. Higher speeds attainable; operation high temperatures will reduce specified maximum clock frequency. Powering-on with inputs state ensures that registers latches power-on state (POR). Serial Data present input transferred shift register logical logical transition CLOCK input pulse. succeeding CLOCK pulses, registers shift data information towards SERIAL DATA OUTPUT. SERIAL DATA must appear input prior rising edge CLOCK input waveform.
Information present register transferred respective latch when STROBE high (serial-to-parallel conversion). latches will continue accept data long STROBE held high. Applications where latches bypassed (STROBE tied high) will require that OUTPUT ENABLE input high during serial data entry. When OUTPUT ENABLE input high, output buffers disabled (OFF). information stored latches shift register affected OUTPUT ENABLE input. With OUTPUT ENABLE input low, outputs controlled state their respective latches.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Maximum Allowable Duty Cycle, IOUT
Number Outputs
A6821SA/A6821EA
100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
mbient emperature 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
100% 100% 100% 100% 100% 100% 100%
A6821SLW
Terminal List Table
Name Description Clock Serial Data Logic Ground* OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Logic Supply Serial Data Strobe Output Enable (active low) Power Ground* Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output
There indeterminate resistance between logic ground power ground. proper operation, these terminals must externally connected together.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Package 16-pin
Package 16-pin Wide Body SOIC
CLOCK SERIAL DATA LOGIC GROUND LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE POWER GROUND
OUND OUND
SHIFT REGISTER
LATCHES
Typical Input Circuits
Typical Output Driver
STROBE OUTPUT ENABLE
CLOCK SERIAL DATA
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Package
16-pin
19.05±0.25 +0.10 0.25 -0.05 +0.76 6.35 -0.25 +0.38 10.92 -0.25 7.62
5.33 +0.51 3.30 -0.38 1.27 +0.25 1.52 -0.38 0.46 ±0.12 2.54
Reference Only (reference JEDEC MS-001 Dimensions inches, metric dimensions (mm) brackets, reference only Dimensions exclusive mold flash, gate burrs, dambar protrusions Exact case lead configuration supplier discretion within limits shown Terminal mark area
16-pin Wide Body SOIC
10.30±0.20 +0.07 0.27 -0.06 0.65 1.27
Package
7.50±0.10
10.30±0.33 +0.44 0.84 -0.43 2.25
9.50
0.25
Layout Reference View
0.10 0.41 ±0.10 1.27
SEATING PLANE 2.65 0.20 ±0.10
SEATING PLANE GAUGE PLANE
Reference Only Dimensions millimeters (reference JEDEC MS-013 Dimensions exclusive mold flash, gate burrs, dambar protrusions Exact case lead configuration supplier discretion within limits shown
Terminal mark area
Reference layout (reference SOIC127P1030X265-16M) pads minimum 0.20 from adjacent pads; adjust necessary meet application process requirements layout tolerances
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Copyright ©2004-2009, Allegro MicroSystems, Inc. products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro's products used life support devices systems, failure Allegro product reasonably expected cause failure that life support device system, affect safety effectiveness that device system. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use. latest version this document, visit website: www.allegromicro.com
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com

logic supply range Power reset (POR) data input rate CMOS, compatible

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