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A6A259 8-Bit Addressable, DMOS Power Driver
Date status change: October 2007
Recommended Substitutions:
NOTE: detailed information purchasing options, contact your local Allegro field applications engineer sales representative.
Allegro MicroSystems, Inc. reserves right make, from time time, revisions anticipated product life cycle plan product accommodate changes production capabilities, alternative product availabilities, market demand. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringements patents other rights third parties which result from use.
6A259
PRELIMINARY INFORMATION
(Subject change without notice) March 2003
8-BIT ADDRESSABLE DMOS POWER DRIVER
A6A259KA A6A259KLB combine 3-to-8 line CMOS decoder accompanying data latches, control circuitry, DMOS outputs multi-functional power driver capable storing single-line data addressable latches decoder demuliplexer. Driver applications include relays, solenoids, other medium-current high-voltage peripheral power loads. CMOS inputs latches allow direct interfacing with microprocessor-based systems. with require appropriate pullup resistors ensure input logic high. Four modes operation selectable with CLEAR ENABLE inputs. addressed DMOS output inverts DATA input with unaddressed outputs remaining their previous states. output drivers disabled (the DMOS sink drivers turned off) with CLEAR input ENABLE input high. A6A259KA/KLB DMOS open-drain outputs capable sinking A6A259KA furnished 20-pin dual in-line plastic package. A6A259KLB furnished 24-lead wide-body, smalloutline plastic batwing package (SOIC) with gull-wing leads surfacemount applications. Copper lead frames, reduced supply current requirements, on-state resistance allow both devices sink from outputs continuously, ambient temperatures over 85°C.
Data Sheet 26186.121
A6A259KA (DIP)
OUT2 OUT3 LOGIC GROUND POWER GROUND POWER GROUND (MSB) ENABLE OUT4 OUT5 OUT1 OUT0 (LSB) LOGIC SUPPLY POWER GROUND POWER GROUND CLEAR DATA OUT7 OUT6
DECODER
LATCHES
Dwg. PP-050-4
ABSOLUTE MAXIMUM RATINGS 25°C
Output Voltage, Output Drain Current, Continuous, Peak, 1100 Peak, Single-Pulse Avalanche Energy, Logic Supply Voltage, Input Voltage Range, -0.3 +7.0 Package Power Dissipation, Graph Operating Temperature Range, -40°C +125°C Storage Temperature Range, -55°C +150°C
*Each output, outputs Pulse duration duty cycle Caution: These CMOS devices have input static protection (Class still susceptible damage exposed extremely high static electrical charges.
FEATURES
Minimum Output Clamp Voltage Output Current (all outputs simultaneously) Typical rDS(on) Internal Short-Circuit Protection Power Consumption Replacements TPIC6A259N TPIC6A259DW
Always order complete part number: Part Number Package A6A259KA 20-pin 55°C/W A6A259KLB 24-lead SOIC 55°C/W
25°C/W
6°C/W
6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
A6A259KLB (SOIC)
ALLOWABLE PACKAGE POWER DISSIPATION WATTS
SUFFIX 'LB', 6.0°C/W
OUT2 OUT3
DECODER LATCHES
OUT1 OUT0 (LSB) LOGIC SUPPLY POWER GROUND POWER GROUND POWER GROUND POWER GROUND CLEAR DATA OUT7 OUT6
SUFFIX 'A', 25°C/W
LOGIC GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND
55°C/W
(MSB) ENABLE
TEMPERATURE
Dwg. GP-049-5
OUT4 OUT5
Dwg. PP-050-3A
Dwg. EP-063-5
Dwg. EP-010-15
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
Inputs CLEAR ENABLE DATA
LATCH SELECTION TABLE
Function
Addressable Latch Memory 8-Line Demultiplexer Clear Previous State
Addressed OUTPUT
Other OUTPUTs
Select Inputs Addressed (MSB) (LSB) OUTPUT
Logic Level
High Logic Level
Irrelevant
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright 2003 Allegro MicroSystems, Inc.
6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
(LSB)
(MSB) LOGIC GROUND DATA ENABLE
(ACTIVE LOW)
CURRENT LIMIT CHARGE PUMP
LOGIC SUPPLY
POWER GROUND
Dwg. FP-047-2
CLEAR
(ACTIVE LOW)
Power grounds must connected externally single point.
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6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range Logic Supply Voltage Range, High-Level Input Voltage, 0.85VDD Low-level input voltage, 0.15VDD
ELECTRICAL CHARACTERISTICS +25°C, (unless otherwise specified).
Limits Characteristic Logic Supply Voltage Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Source-to-Drain Diode Voltage Nominal Output Current Output Current Logic Input Current Symbol V(BR)DSX IDSX Test Conditions Operating 125°C Min. Typ. 0.75 Max. -1.0 Units
rDS(on)
125°C
IO(nom) IO(chop)
VDS(on) 85°C which chopping starts, 25°C Outputs Outputs
Prop. Delay Time
tPLH tPHL
Output Rise Time Output Fall Time Supply Current
IDD(off) IDD(on)
Typical Data design information only. NOTE Pulse test, duration duty cycle
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
FUNCTIONAL DESCRIPTION INPUT REQUIREMENTS
ENABLE
Four modes operation selectable controlling CLEAR ENABLE inputs shown above.
DATA
ADDRESSED OUTPUT
addressable-latch mode, data DATA input written into addressed transparent latch. addressed output inverts data input with other outputs remaining their previous states.
Dwg. WP-036
OUTPUT SWITCHING TIME
memory mode, outputs remain their previous states unaffected DATA address (Sn) inputs. prevent entering erroneus data latches, ENABLE should held HIGH while address lines changing. demultiplexing/decoding mode, addressed output inverts data input other outputs OFF.
ENABLE su(D) DATA
h(D)
clear mode, outputs unaffected DATA address (SN) inputs.
Dwg. WP-037
w(D)
DATA INPUT REQUIREMENTS
Data Active Time Before Enable (Data Set-Up Time), tsu(D) Data Active Time After Enable (Data Hold Time), th(D) Data Pulse Width, tw(D) Input Logic High, 0.85VDD Input Logic Low, 0.15VDD
Given appropriate inputs, when DATA given address, output OFF; when DATA HIGH, output sink current. LOGIC SYMBOL
ENABLE DATA CLEAR 9,0D 10,0R 9,1D 10,1R 9,2D 10,2R 9,3D 10,3R 9,4D 10,4R 9,5D 10,5R 9,6D 10,6R 9,7D 10,7R
Dwg. FP-046-2
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6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
TEST CIRCUITS
INPUT
Dwg. EP-066-2
V(BR)DSX
VO(ON)
V(BR)DSX tAV/2
Single-Pulse Avalanche Energy Test Circuit Waveforms
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
A6A259KA (DIP) Terminal A6A259KLB (SOIC) Terminal
Terminal Name OUT2 OUT3 LOGIC GROUND
Function Current-sinking, open-drain DMOS output, address 010. Current-sinking, open-drain DMOS output, address 011. Binary-coded output-select input. Reference terminal input voltage measurements.
POWER GROUND Reference terminal output voltage measurements (OUT0-3). POWER GROUND Reference terminal output voltage measurements (OUT4-7). ENABLE OUT4 OUT5 OUT6 OUT7 DATA Binary-coded output-select input, most-significant bit. Mode control input; Function Table. Current-sinking, open-drain DMOS output, address 100. Current-sinking, open-drain DMOS output, address 101. Current-sinking, open-drain DMOS output, address 110. Current-sinking, open-drain DMOS output, address 111. CMOS data input addressed output latch. When enabled, addressed output inverts data input (DATA HIGH, OUTPUT LOW). Mode control input; Function Table.
CLEAR
POWER GROUND Reference terminal output voltage measurements (OUT4-7). POWER GROUND Reference terminal output voltage measurements (OUT0-3). LOGIC SUPPLY OUT0 OUT1 (VDD) logic supply voltage (typically Binary-coded output-select input, least-significant bit. Current-sinking, open-drain DMOS output, address 000. Current-sinking, open-drain DMOS output, address 001.
NOTE -Power grounds must connected together externally.
www.allegromicro.com
6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
A6A259KA (DIP)
Dimensions Inches (controlling dimensions)
0.014 0.008
0.430 0.280 0.240
0.300
0.070 0.045
0.100 1.060 0.980
0.005
0.210
0.015
0.150 0.115 0.022 0.014
Dwg. MA-001-20
Dimensions Millimeters (for reference only)
0.355 0.204
10.92 7.11 6.10
7.62
1.77 1.15
2.54 26.92 24.89
0.13
5.33
0.39
3.81 2.93 0.558 0.356
Dwg. MA-001-20
NOTES:1.
Exact body lead configuration vendor's option within limits shown. Lead spacing tolerance non-cumulative. Lead thickness measured seating plane below. Supplied standard sticks/tubes devices.
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
A6A259KLB (SOIC)
Dimensions Inches (for reference only)
0.0125 0.0091
0.2992 0.2914
0.419 0.394 0.050 0.016
0.020 0.013
0.6141 0.5985
0.050
NOTE NOTE
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-25A
Dimensions Millimeters (controlling dimensions)
0.32 0.23
7.60 7.40
10.65 10.00 1.27 0.40
0.51 0.33
15.60 15.20
1.27
NOTE NOTE
2.65 2.35 0.10 MIN.
Dwg. MA-008-25A
NOTES:1.
Webbed lead frame. Leads internally piece. Lead spacing tolerance non-cumulative. Exact body lead configuration vendor's option within limits shown. Supplied standard sticks/tubes devices, "TR" part number tape reel.
www.allegromicro.com
6A259 8-BIT ADDRESSABLE DMOS POWER DRIVER
products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro products authorized critical components life-support devices systems without express written approval. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use.
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

Date status change: October 2007 Recommended Substitutions:

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