RDS(ON) outputs Automatic current decay mode detection/selection Mixed

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RDS(ON) outputs Automatic current decay mode detection/selection Mixed

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A4983 DMOS Microstepping Driver with Translator
RDS(ON) outputs Automatic current decay mode detection/selection Mixed Slow current decay modes Synchronous rectification power dissipation Internal UVLO Crossover-current protection compatible logic supply Very thin profile package Thermal shutdown circuitry
A4983 complete microstepping motor driver with built-in translator easy operation. designed operate bipolar stepper motors full-, half-, quarter-, eighth-, sixteenth-step modes, with output drive capacity A4983 includes fixed off-time current regulator which ability operate Slow Mixed decay modes. translator easy implementation A4983. Simply inputting pulse STEP input drives motor microstep. There phase sequence tables, high frequency control lines, complex interfaces program. A4983 interface ideal applications where complex microprocessor unavailable overburdened. chopping control A4983 automatically selects current decay mode (Slow Mixed). When signal occurs STEP input pin, A4983 determines that step results higher lower current each motor phases. change higher current, then decay mode Slow decay. change lower current, then current decay Mixed (set initially fast decay period amounting 31.25% fixed off-time, then
Continued next page.
Package: 28-pin (suffix
Approximate size
Typical Application Diagram
0.22 VREG Microcontroller Controller Logic SLEEP STEP RESET ENABLE ROSC
OUT1A OUT1B
A4983
OUT2A OUT2B
4983DS, Rev.
A4983
DMOS Microstepping Driver with Translator
lockout (UVLO), crossover-current protection. Special poweron sequencing required. A4983 supplied 0.90 nominal surface mount package with exposed thermal (suffix ET). package lead (Pb) free (suffix -T), with 100% matte plated leadframe.
Description (continued) slow decay remainder off-time). This current decay control scheme results reduced audible motor noise, increased step accuracy, reduced power dissipation. Internal synchronous rectification control circuitry provided improve power dissipation during operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage
Selection Guide
Part Number A4983SETTR-T Pb-free Package 28-pin with exposed thermal Packing 1500 pieces 7-in. reel
Absolute Maximum Ratings
Characteristic Load Supply Voltage Output Current Logic Input Voltage Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature Symbol IOUT VSENSE VREF TJ(max) Tstg Range Duty Cycle Notes Rating ±2.5 -0.3 Units
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.22 VREG ROSC
Current Regulator
Charge Pump DMOS Full Bridge VBB1
OUT1A OUT1B Latch Blanking Mixed Decay Gate Drive Control Logic DMOS Full Bridge
SENSE1
STEP RESET Translator
VBB2
OUT2A OUT2B
ENABLE SLEEP Latch Blanking Mixed Decay
SENSE2
VREF
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS1 25°C, (unless otherwise noted)
Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output Resistance Body Diode Forward Voltage Symbol Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT -1.5 Sink Driver, IOUT Source Diode, -1.5 Sink Diode, fPWM Operating, outputs disabled Sleep Mode fPWM Outputs Sleep Mode Min. VDD0.7 VDD0.7 2.35 0.05 Typ.2 0.350 0.300 <1.0 <1.0 0.10 Max. 0.450 0.370 VDD0.3 Units
RDSON
Motor Supply Current
Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Microstep Select Microstep Select Input Hysteresis Blank Time Fixed Off-Time Reference Input Voltage Range Reference Input Current Current Trip-Level Error3 Crossover Dead Time Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis
VIN(1) VIN(0) IIN(1) IIN(0) RMS2 RMS3 VHYS(IN) tBLANK tOFF VREF IREF
errI
VDD0.3
ROSC
VREF %ITripMAX 38.27% VREF %ITripMAX 70.71% VREF %ITripMAX 100.00%
TJHYS UVLO UVHYS rising
1Negative current defined coming (sourcing from) specified device pin. 2Typical data initial design estimations only, assume optimum manufacturing application conditions. Performance vary
3err
individual units, within specified maximum minimum limits. (ITrip IProg IProg where IProg %ITripMAX ITripMAX.
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
THERMAL CHARACTERISTICS require derating maximum conditions
Characteristic Package Thermal Resistance Symbol Test Conditions* Package 4-layer PCB, based JEDEC standard Value Units
still air. Additional thermal information available Allegro site.
Maximum Power Dissipation, PD(max)
Power Dissipation,
Temperature (°C)
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
STEP
MS1, MS2, MS3, RESET,
Time Duration STEP minimum, HIGH pulse width STEP minimum, pulse width Setup time, input change STEP Hold time, input change STEP Figure Logic Interface Timing Diagram
Symbol
Typ.
Unit
Table Microstep Resolution Truth Table
Microstep Resolution Full Step Half Step Quarter Step Eighth Step Sixteenth Step Excitation Mode Phase Phase W1-2 Phase 2W1-2 Phase 4W1-2 Phase
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Functional
Device Operation. A4983 complete microstepping Microstep Select (MS1, MS2, MS3). Selects
motor driver with built-in translator easy operation with minimal control lines. designed operate bipolar stepper motors full-, half-, quarter-, eighth-, sixteenth-step modes. currents each output full-bridges N-channel DMOS FETs regulated with fixed offtime (pulse width modulated) control circuitry. each step, current each full-bridge value external current-sense resistor (RS1 RS2), reference voltage (VREF), output voltage (which turn controlled output translator). power-on reset, translator sets DACs phase current polarity initial Home state (shown figures through current regulator Mixed Decay Mode both phases. When step command signal occurs STEP input, translator automatically sequences DACs next level current polarity. (See table current-level sequence.) microstep resolution combined effect inputs MS1, MS2, MS3, shown table When stepping, output levels DACs lower than their previous output levels, then decay mode active full-bridge Mixed. output levels DACs higher than equal their previous levels, then decay mode active full-bridge Slow. This automatic current decay selection improves microstepping performance reducing distortion current waveform that results from back motor. logic circuits pulled VDD, good practice high value pull-up resistor order limit current logic inputs, should overvoltage event occur. Logic inputs include: MSx, SLEEP, DIR, ENABLE, RESET, STEP. microstepping format, shown table have pull-down resistance. changes made these inputs take effect until next STEP rising edge. pins pulled VDD, good practice high value pull-up resistor order limit current these pins, should overvoltage event occur.
Direction Input (DIR). This determines direction
rotation motor. When low, direction will clockwise when high, counterclockwise. Changes this input take effect until next STEP rising edge.
Internal Current Control. Each full-bridge
controlled fixed off-time current control circuit that limits load current desired value, ITRIP Initially, diagonal pair source sink outputs enabled current flows through motor winding current sense resistor, RSx. When voltage across equals output voltage, current sense comparator resets latch. latch then turns either source FETs (when Slow Decay Mode) sink source FETs (when Mixed Decay Mode). maximum value current limiting selection voltage VREF pin. transconductance function approximated maximum value current limiting, ITripMAX (A), which ITripMAX VREF
RESET Input (RESET). RESET input sets translator predefined Home state (shown figures through turns outputs. STEP inputs ignored until RESET input high. Step Input (STEP). low-to-high transition STEP
input sequences translator advances motor increment. translator controls input DACs direction current flow each winding. size increment determined combined state inputs MS1, MS2, MS3.
where resistance sense resistor VREF input voltage (V). output reduces VREF output current sense comparator precise steps, such that Itrip (%ITripMAX 100)
ITripMAX
(See table %ITripMAX each step.)
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
critical that maximum rating (0.5 SENSE1 SENSE2 pins exceeded.
Fixed Off-Time. internal current control circuitry uses one-shot circuit control duration time that DMOS FETs remain off. shot off-time, tOFF, determined selection external resistor connected from ROSC timing ground. ROSC tied external voltage then tOFF defaults ROSC safely connected this purpose. value tOFF approximately
tOFF ROSC
Shutdown. event fault, overtemperature (excess undervoltage VCP), outputs A4983 disabled until fault condition removed. power-on, UVLO (undervoltage lockout) circuit disables outputs resets translator Home state. Sleep Mode (SLEEP). minimize power consumption when motor use, this input disables much internal circuitry including output FETs, current regulator, charge pump. logic SLEEP puts A4983 into Sleep mode. logic high allows normal operation, well start-up which time A4983 drives motor Home microstep position). When emerging from Sleep mode, order allow charge pump stabilize, provide delay before issuing Step command.
SLEEP pulled VDD, good practice high value pull-up resistor order limit current pin, should overvoltage event occur.
Blanking. This function blanks output current sense
comparators when outputs switched internal current control circuitry. comparator outputs blanked prevent false overcurrent detection reverse recovery currents clamp diodes, switching transients related capacitance load. blank time, tBLANK (s), approximately tBLANK
Charge Pump (CP1 CP2). charge pump used
generate gate supply greater than that driving source-side gates. ceramic capacitor, should connected between CP2. addition, ceramic capacitor required between VBB, reservoir operating high-side gates.
Mixed Decay Operation. bridge operate Mixed Decay mode, depending step sequence, shown figures through trip point reached, A4983 initially goes into fast decay mode 31.25% off-time. tOFF. After that, switches Slow Decay mode remainder tOFF. timing dagram this feature appears next page. Synchronous Rectification. When PWM-off cycle
VREG (VREG). This internally-generated voltage used
operate sink-side outputs. VREG must decoupled with 0.22 ceramic capacitor ground. VREG internally monitored. case fault condition, outputs A4983 disabled.
triggered internal fixed-off-time cycle, load current recirculates according decay mode selected control logic. This synchronous rectification feature turns appropriate FETs during current decay, effectively shorts body diodes with RDS(ON). This reduces power dissipation Enable Input (ENABLE). This input turns significantly, eliminate need external Schottky outputs. When logic high, outputs disabled. When logic low, internal control enables outputs diodes many applications. Synchronous rectification turns when load current approaches zero preventing reversal required. translator inputs STEP, DIR, MS1, MS2, MS3, well internal sequencing logic, remain active, indepen- load current. timing dagram this feature appears next page. dent ENABLE input state.
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Current Decay Modes Timing Chart
VPHASE
IOUT Enlargement
Enlargement
toff IPEAK
Slow Decay
IOUT
Mixed Decay
Symbol toff IPEAK IOUT Device fixed off-time Maximum output current Slow decay interval Fast decay interval Device output current
Characteristic
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Application Layout
Layout printed circuit board should heavy groundplane. optimum electrical thermal performance, A4983 must soldered directly onto board. underside A4983 package exposed pad, which provides path enhanced thermal dissipation. thermal should soldered directly exposed surface PCB. Thermal vias used transfer heat other layers PCB. Thermal vias should have thermal relief should connected internal layers, available, maximize dissipation area. Grounding order minimize effects ground bounce offset issues, important have impedance singlepoint ground, known star ground, located very close device. making connection between exposed thermal groundplane directly under A4983, that area becomes ideal location star ground point.
impedance ground will prevent ground bounce during high current operation ensure that supply voltage remains stable input terminal. recommended layout shown diagram below, illustrates create star ground under device, serve both impedance ground point thermal path.
A4983
Solder Trace oz.) Signal oz.) Ground oz.) Thermal oz.)
Thermal Vias
OUT2A SENSE2 OUT1A SENSE1 VBB2
VBB1
OUT2B ENABLE RESET SLEEP ROSC VREG
OUT1B
A4983
STEP
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
STEP
100.00 70.71
STEP
100.00 70.71
Slow
Slow Mixed
Slow Mixed
Home Microstep Position
Home Microstep Position
-70.71 -100.00 100.00 70.71
Home Microstep Position
-70.71 -100.00 100.00 70.71
Slow Slow Mixed Mixed
Slow Mixed
Slow
Phase IOUT2A Direction
0.00
Slow
-70.71
Phase IOUT2B Direction
0.00
-70.71 -100.00
-100.00
Figure Decay Mode Full-Step Increments
STEP
100.00 92.39 70.71 38.27
Figure Decay Modes Half-Step Increments
-38.27 -70.71 -92.39 -100.00 100.00 92.39 70.71 38.27
Slow Mixed Slow Mixed Slow Mixed
Phase IOUT2B Direction
0.00
-38.27 -70.71 -92.39 -100.00
Figure Decay Modes Quarter-Step Increments
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Home Microstep Position
Phase IOUT1A Direction
Slow
0.00
Mixed
Slow
Mixed
Slow
Home Microstep Position
Phase IOUT1A Direction
Slow
0.00
Phase IOUT1A Direction
Mixed
0.00
A4983
DMOS Microstepping Driver with Translator
STEP
100.00 92.39 83.15 70.71 55.56
-38.27 -55.56 -70.71 -83.15 -92.39 -100.00 100.00 92.39 83.15 70.71 55.56
Phase IOUT2B Direction
38.27 19.51 0.00 -19.51 -38.27 -55.56 -70.71 -83.15 -92.39 -100.00
Mixed
Slow
Home Microstep Position
Phase IOUT1A Direction
38.27 19.51 0.00 -19.51
Slow
Mixed
Slow
Mixed
Mixed
Slow
Figure Decay Modes Eighth-Step Increments
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
STEP
100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51
Phase IOUT1A Direction
Slow
0.00 -9.8 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -95.69 -100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51
Mixed
Slow
Mixed
Phase IOUT2B Direction
0.00 -9.8 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -95.69 -100.00
Slow Mixed Slow Mixed Slow
Figure Decay Modes Sixteenth-Step Increments
Home Microstep Position
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Table Step Sequencing Settings
Home microstep position Step Angle
Full Step
Half Step
Step
Step
1/16 Step
Phase Current
ItripMax]
Phase Current
ItripMax]
100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52
0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80
Step Angle 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4
Full Step
Half Step
Step
Step
1/16 Step
Phase Current
ItripMax]
Phase Current
ItripMax]
Step Angle
-100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52
0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52 -100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80
180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Pin-out Diagram
SENSE2 SENSE1 OUT2A OUT1A VBB2 VBB1 OUT1B STEP RESET ROSC SLEEP
OUT2B ENABLE
Terminal List Table
Name VREG RESET ROSC SLEEP STEP OUT1B VBB1 SENSE1 OUT1A OUT2A SENSE2 VBB2 OUT2B ENABLE Number Description Charge pump capacitor terminal Charge pump capacitor terminal Reservoir capacitor terminal Regulator decoupling terminal Logic input Logic input Logic input Logic input Timing Logic input Logic supply Logic input reference voltage input Ground* Logic input DMOS Full Bridge Output Load supply Sense resistor terminal Bridge DMOS Full Bridge Output DMOS Full Bridge Output Sense resistor terminal Bridge Load supply DMOS Full Bridge Output Logic input connection Exposed enhanced thermal dissipation*
*The pins must tied together externally connecting ground plane under device.
VREG
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Package, 28-Pin with Exposed Thermal
0.30 5.00 ±0.15 1.15 0.50
5.00 ±0.15
3.15 4.80
3.15 0.08 +0.05 0.25 -0.07 0.50 SEATING PLANE 0.90 ±0.10 4.80 Layout Reference View
+0.20 0.55 -0.10
Reference Only (reference JEDEC MO-220VHHD-1) Dimensions millimeters Exact case lead configuration supplier discretion within limits shown 3.15 3.15 Terminal mark area Exposed thermal (reference only, terminal identifier appearance supplier discretion) Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); pads minimum 0.20 from adjacent pads; adjust necessary meet application process requirements layout tolerances; when mounting multilayer PCB, thermal vias exposed thermal land improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Coplanarity includes exposed thermal terminals
Copyright ©2007-2008, Allegro MicroSystems, Inc. products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro's products used life support devices systems, failure Allegro product reasonably expected cause failure that life support device system, affect safety effectiveness that device system. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use. latest version this document, visit website: www.allegromicro.com
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RDS(ON) outputs Automatic current decay mode detection/selection Mixed

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