Extremely fast load-transient response with minimal output voltage del

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Extremely fast load-transient response with minimal output voltage del

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A4403 Valley Current Mode Control Buck Converter
Extremely fast load-transient response with minimal output voltage delta Achieves high step-down ratios with on-times User-configurable on-time, achieving switching frequencies Minimal external components required Optimized value filter capacitors inductors Wide input voltage range: Output Current: standby current <100 Supplied thermally-enhanced package
A4403 buck converter that uses valley current-mode control. This control scheme allows very short switch on-times achieved, making ideal applications that require high switching frequencies combined with high input voltages output voltages. cost accomplished through high switching frequencies MHz, allowing smaller lower value inductors capacitors. addition, minimal external components required through high levels integration. Optimal drive circuits utilized minimize switching losses. switching frequency maintained constant, on-time modulated input voltage. This feed-forward control ensures excellent line correction. on-time external resistor pulled-up input supply. When power initially applied device enabled, user-configurable soft-start function occurs minimize inrush current prevent output overshoot. Internal housekeeping bootstrap supplies provided which only require addition small ceramic capacitor. top-off charge pump also provide ensure correct operation light loads. Internal diagnostics provide comprehensive protection against overcurrents, input undervoltages, overtemperatures. device package 16-contact, 0.75 nominal overall height QFN, with exposed enhanced thermal dissipation. lead (Pb) free, with 100% matte leadframe plating.
Applications:
Printers, scanners Cable, modems/routers Network telecom Industrial control Distributed power systems High power supply Battery chargers Infotainment
Package 16-contact (suffix EU):
0.75
Typical Application Diagram
BOOT
VOUT
4403
90.00
3.92
Efficiency versus Output Current
ISEN
85.00
Efficiency
80.00 75.00 70.00 65.00
SGND
60.00 Output Current
capacitors ceramic Resistors should surface mount, inductance type, rated 70°C
4403-DS, Rev.
A4403
Valley Current Mode Control Buck Converter
Selection Guide
Part Number
A4403GEU-T A4403GEUTR-T
Packing
pieces tube 1500 pieces 7-in. reel
Package
16-contact with exposed thermal
Absolute Maximum Ratings (reference GND)
Characteristic Supply Voltage Switching Node Voltage ISEN Current Sense Voltage Disable Voltage On-Time Voltage Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VISEN VDIS VTON TJ(max) Tstg Range Notes Rating -0.3 -1.0 -0.3 -0.3 Units
Recommended Operating Conditions
Characteristic Supply Voltage Switching Node Switching Frequency Range Operating Ambient Temperature Junction Temperature Symbol Continuous conduction mode Conditions Min. -0.7 0.45 Typ. Max. Units
Thermal Characteristics require derating maximum conditions, application information
Characteristic
Package Thermal Resistance, Junction Ambient Package Thermal Resistance, Junction
Symbol
Test Conditions*
4-layer based JEDEC standard 4-layer based JEDEC standard
Value
Units
*Additional thermal information available Allegro website.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
Functional Block Diagram
44.1
Linear Regulator Fitted Sleep Circuit Driver BOOT Top-off Charge Pump
VOUT
Timer Timer Control Logic Blank ISEN SGND 2.37
Switch Closed
Overvoltage Comparator
UVLO Linear Fault
Regulator Comparator
Amplifier
Soft-Start
Switching Frequency capacitors ceramic Resistors should surface mount, inductance type, rated 70°C optional speed-up capacitor, improve transient response
Terminal List Table
Number Name ISEN SGND BOOT Input supply connection; Terminal on-time setting with external resistor Terminal soft-start setting with external capacitor Feedback terminal Ground terminal Current sense input Current sense ground reference Disable logic input; active high Bootstrap supply node Switch node Exposed thermal pad; connect ground plane (GND) through-hole vias
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
Pin-out Diagram
BOOT SGND
(Top View)
ISEN
Function
A4403
Valley Current Mode Control Buck Converter
ELECTRICAL CHARACTERISTICS1 valid 25°C, unless otherwise noted
Characteristic General Quiescent Current Feedback Voltage Feedback Input Bias Current Output Voltage Tolerance2 On-Time Tolerance Minimum On-Time Period Minimum Off-Time Period Buck Switch On-Resistance Current Limit Threshold Soft Start Current Source Input Input Voltage Threshold Open-Circuit Voltage Input Current Protection Overvoltage Shutdown Undervoltage Shutdown Threshold Undervoltage Shutdown Hysteresis Overtemperature Shutdown Threshold Overtemperature Shutdown Hysteresis
1Specifications
Symbol IVINOFF IVINON IBIAS VOUT Ton(min) Toff(min) RDS(on) ILIM VDIS VDISOC VFBOV VINUV VINUV(hys) TJTSD TJTSD(hys) Temperature rising Voltage rising Device enabled Device disabled ILOAD
Conditions high, low, ILOAD= 25°C
Min. 0.792 -400 -2.5
Typ. -100 0.88
Max. 0.808
Units
Based selected value
25°C, ILOAD 125°C, ILOAD Valley current external sense resistors
Recovery TJTSD TJTSD(hys)
over junction temperature range -40°C 125°C assured design characterization. 2Average value relative target voltage. Note that tolerance effects feedback resistors taken into account. This figure does include feedback voltage tolerance.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
Functional
Basic Operation A4403 buck converter that utilizes valley current-mode control. on-time amount current that flows into pin. This determined value resistors chosen Functional Block diagram) magnitude input voltage, VIN. Under specific conditions, on-time that then dictates switching frequency. This switching frequency remains reasonably constant throughout load line conditions on-time varies inversely with input voltage. Switch On-Time Switching Frequency section provides more details this subject. beginning switching cycle, buck switch turned fixed period that determined current flowing into TON. Once current comparator trips, one-shot monostable, Timer, reset, turning switch. current through inductor then decays. This current sensed through external sense resistors R4), then compared against current-demand signal. current-demand signal generated comparing output voltage against accurate bandgap reference. After current through sense resistors decreases valley current-demand signal, Timer turn buck switch back again cycle repeated. Under light load conditions, converter automatically operates pulse frequency modulation (PFM) mode maintain regulation. This mode operation ensures optimum efficiency switching losses reduced. Overcurrent Protection converter utilizes pulse-by-pulse valley current limiting, which operates when current through sense resistors, (set resistors parallel), increases above typical valley point. corresponding sense voltage ISEN pin) that creates current limiting condition typical. possible, careful selection sense resistors, reduce current limit systems with maximum loads less than During overload condition, switch turned period determined constant on-time circuitry. switch off-time extended until current decays current limit value typical (which corresponds sense voltage mV). switch then turned again. Because slope compensation required this control scheme, current limit maintained reasonably constant level across input voltage range.
Figure illustrates current limited during overload condition. current decay (period with switch off) proportional output voltage. overload increased, output voltage tends decrease switching period increases. Output Voltage Selection output voltage converter selecting appropriate feedback resistors, using following formula: where (refering Functional Block diagram): value between connected between pins), dependent value connected between output rail pin), VOUT user-configured output regulator voltage, reference voltage. tolerance feedback resistors influences voltage setpoint. therefore important consider tolerance selection when targeting overall regulation figure.
Inductor current operating maximum load
Current Limit level Maximum load Current
Constant On-Time Constant period
Time
Inductor current operating "soft" overload
Overload Current Limit level Current
Constant On-Time
Extended period
Time
Figure Current limiting during overload
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
example, limited IVIN assumed VOUT COUT soft start time could determined tCHARGE 0.25
general, feedback resistors should have lowest resistance possible, minimize noise pick-up effects minimize voltage offsets output caused bias current, IBIAS, flowing node into Reducing feedback resistances does introduce another loading effect output, which effect standby current. should noted that minimum load required (see Light Load Operation section). This provided feedback resistors. example, this guarantees load current. Disable converter enabled pulling low. Once enabled, output converter started-up under control soft-start routine. disable converter, simply disconnected (open circuit). Soft Start soft-start routine initiated when: thermal shutdown exists, internal housekeeping supplies above minimum values. Note that overcurrent event does initiate soft start, unless converter recovering from thermal shutdown condition. soft-start routine controls rate rise reference voltage, which turn controls output voltage. This function minimizes amount inrush current drawn from potential voltage overshoot output rail, VOUT. soft-start period, internal current source that charges external capacitor (C5) connected pin. Control soft-start routine completed when reaches duration selecting appropriate capacitance, according formula:
This means soft-start duration greater than should selected ensure inrush current less than Shutdown converter disabled event either overtemperature event, undervoltage (VINUVR) internal housekeeping supply. soon above faults have been removed assuming output voltage, VOUT brought-up under control soft-start routine. Output Overvoltage Protection event overvoltage condition appearing output rail, terminal will also experience overvoltage, scaled feedback resistors. terminal voltage rises above nominal voltage (typical), on-time buck switch will terminate switch will remain until voltage reduces correct range. Switch On-Time Switching Frequency switch on-time effectively determines operating frequency converter. selection operating frequency generally trade-off between size external passive components (inductor, input output capacitors) switching losses. Another consideration selecting switching frequency ensure that none off-time limits reached under extreme conditions. minimum on-time occurs maximum input voltage minimum load. Consider following example. Given: (max) VOUT MHz, and: Ton(min)
Note: soft start function required application, resistor should connected between GND. Without soft start, with soft start period that rapid, coupled with high load that present during start-up, converter operate current limit, placing maximum stress input circuit. Assuming load drawn until start-up process complete, current drawn from input supply determined quickly output capacitors charged. output capacitors charged according following formula: tCHARGE COUT VOUT IVIN
where voltage drop recirculation diode (D1) sense resistors R4).
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
where IVIN input supply current.
A4403
Valley Current Mode Control Buck Converter
Then, minimum on-time Ton(min)
Top-Off Charge Pump During light load operation, when operating mode, top-off charge pump provides enough charge drive buck switch. Light Load Operation avoid output voltage peak charging leakage effects from buck switch charge pump recirculation current, minimum load must applied output. output feedback resistor network provides some loading. Depending values selected, this network provide all, least some, minimum loading requirement. Control Loop process closing control loop A4403 been greatly simplified through integration compensation components into device. control loop bandwidth been optimized operation across full input output voltage range switching frequencies between MHz. Loop optimization achieved with ceramic capacitor placed across output (VOUT GND) power inductor that achieves peak peak ripple current around example, output operating frequency MHz, power inductor Larger output capacitors used; however, this tends decrease bandwidth control loop. Note that output capacitance should exceed 1000 less than this cause loop instability occur.
2000 1800
Switching Frequency (kHz)
specified minimum on-time, Ton(min) maximum, there reasonable margin this case. specified minimum off-time, Toff(min) maximum, also considered. minimum off-time occurs minimum input voltage maximum load. shown minimum on-time calculation (equation have examine extreme operating conditions ensure adequate margin exists. switch on-time, Ton, current flowing into pin. current determined input voltage, VIN, resistor on-time found 2.05 10-9
switching frequency slightly modulated load changes. on-time always constant given input voltage across load range. compensate losses circuitry (for example, series switch inductor, voltage drop across recirculation diode), off-time, hence switching frequency, adjusted. This effect most noticeable input voltages high output currents. calculate actual switching frequency, equation used conjunction with transfer function converter: VOUT
1600 1400 1200 1000
VOUT
alternative approach selecting resistor (R1), accomplish approximate switching frequency found following formula: VOUT 2.05 1010
Resistor
1000
Figure illustrates range switching frequencies that achieved with various resistances output voltages.
Figure Switching frequencies versus resistor values, various levels VOUT
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
When output voltage typical bandwidth with phase margin full load. load reduced, bandwidth remains largely constant; however, phase margin tends reduce slightly because output power pole shifted down frequency, introducing phase sooner. light loads, before pulse frequency modulation occurs, phase margin reduces approximately 40°, which reasonable given that worst-case condition. Note that when pulse frequency modulation occurs, system longer operates linear system, therefore, control laws apply. When output voltage higher voltages, gain reduced resistor feedback network from output. This effectively reduces bandwidth control loop. optional speed-up capacitor (C6) used parallel with feedback resistor (R5) compensate this effect. addition this capacitor introduces additional zero which increases gain extends bandwidth maintain region kHz. position zero depends values following time constants should used various output voltages:
Output Voltage Time Constant 10-5 10-5 10-5 10-5 required
good starting point selecting inductance given application specify maximum peak-to-peak ripple current about maximum load. equates ripple current approximately maximum load This often gives good compromise between size, cost, performance. maximum peak peak ripple current, IRIPP occurs maximum input voltage. Therefore duty cycle, should found under these conditions: (min) VOUT+Vf VIN(max)+Vf
where forward voltage drop recirculation diode sense resistor. required inductance found: (min) VOUT (min) IRIPP fSW(min) (10)
Note that manufacturers inductance tolerance should also taken into account. This value high ±20%. addition, because control dependant valley signal, important consider minimum peak peak valley voltage that developed across sense resistor. minimum peak peak ripple current occurs minimum input voltage. peak peak voltage simply peak peak current multiplied sense resistor value. recommended that peak peak sense voltage should greater than recommended that gapped ferrite solutions used opposed powdered iron solutions. latter exhibit relatively high core losses that have large impact long term reliability. Inductors typically specified current levels: current. important understand current level specified, terms ambient temperature. Some manufacturers quote ambient only, whilst others quote temperature that includes self-temperature rise. example, inductor rated 85°C includes self-temperature rise 25°C maximum load, then inductor cannot safely operated beyond ambient temperature 60°C full load. current assumed simply maximum load
example, assume target output voltage 3.92 achieve that voltage. Then 9.18 10-9. nearest commonly available value applications that require output voltages (VOUT) other than what defined above, following formula should used calculate time constant: VOUT 10-6
Inductor main factor selecting inductance value ripple current. ripple current affects output voltage ripple also effect current limit. Because slope compensation used, ripple current constrained this factor.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
current, with perhaps some margin allow overloads, forth. saturation current. worst case maximum peak current should exceed saturation current indeed some margin should allowed. maximum peak current found ensure saturation current level chosen inductor exceeded: Isat ILOAD IRIPPLE (11)
reduce bandwidth therefore compromise transient response performance. general output capacitance should exceed 1000 less than this cause loop instability occur. output ripple largely determined output capacitance, effects largely ignored assuming good layout practice observed. help reduce effects good idea split capacitance into separate components. output voltage ripple approximated VRIPPLE IRIPPLE COUT (13)
important ensure that, under worst-case conditions (minimum input voltage, maximum load current, minimum inductance, minimum switching frequency), that minimum current limit exceeded fact some margin. current limit measured valley level. maximum current valley found from: Ivalley IRIPPLE ILOAD (12)
where IRIPPLE found Inductor section. When using ceramic capacitors, negligible heating effects ESR, there generally need consider current carrying capability. Also, current flowing into output capacitor extremely low. Input Capacitor recommended that ceramic capacitors used, least that they used conjunction with some other capacitor technology; example, aluminum electrolytic. Note that self-resonance electrolytics tend occur 100s kHz, therefore effects become apparent switching frequencies region MHz. value input capacitance determines amount ripple voltage that appears source terminals. system designed correctly, input capacitor should supply switching current minus input average current during on-time power switch. During off-time power switch, input capacitor charged-up. current that flows input capacitor found from: Irms IOUT VOUT
minimum current limit threshold should least above this level. Recommended inductor manufacturers ranges are: Tayo Yuden: NR6045 series Sumida: CDR7D43MN series Output Capacitor interests size, cost, performance, this control architecture been designed ceramic capacitors. imperative that ceramic capacitors used. account should Y5V, Y5U, Z5U, similar types used. When using ceramic capacitors, another important consideration E-field effects actual value capacitor. minimize effects capacitance being reduced with output voltage, recommended that working voltage capacitor considerably more than output voltage. Check with vendor obtain this information. output capacitor determines output voltage ripple used close control loop. outlined Control Loop section, bandwidth been optimized output capacitance particular application requires extremely output voltage, output capacitor increased. increase will tend
(14)
amount ripple voltage that appears across input terminals depends amount charge removed during switch on-time actual capacitor value. capacitor technology such electrolytic used, then effects also have considered.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
amount capacitance required given ripple voltage found: Irms VRIPPLE (15)
mentioned previous section, E-field biasing effects reduce actual capacitance this should taken into account when making selection. Again, there generally need consider heating effects current flowing through ceramic capacitor. electrolytic device used, then ripple current rating should considered. Note that most manufacturers only consider current rating kHz. Recirculation Diode This diode (D1) conducts during switch off-time. Schottky diode recommended minimize both forward drop switching losses. worst-case dissipation occurs maximum when duty cycle minimum. average current through diode found: IDIODE(av) ILOAD (min)) (16)
sense resistor value selected depending maximum output load current. typical sense voltage that causes current limit example, value would appropriate maximum load allows margin between maximum load current limit. tolerance acceptable. power rating resistor considered. current flowing resistor essentially same current flowing through recirculation diode, although power dissipation worked using current. first approximation, sense resistor dissipation worked PSENSE ILOAD2 (min)) RSENSE (18)
converter working with load very narrow duty cycle, sense resistor power dissipation would optimal solution from cost perspective 1206-style resistors connected parallel. Each resistor generally rated 70°C ambient. Check vendor datasheet verify maximum ambient full power. When laying PCB, essential that sense resistor connections, carrying power current (see figure short wide possible minimize effects leakage inductance noise. addition, Kelvin sense circuit connections should close sense resistor pads possible.
forward voltage drop, found from diode characteristics using actual load current (not average current). static power dissipation found: PSTAT IDIODE(av) (17)
also important take into account thermal rating package, ambient temperature, ensure that enough heatsinking provided maintain diode junction temperature within safe operating area device. minimize heating effects from A4403 diode vice-versa, recommended that diode mounted reverse side printed circuit board. Sense Resistor sense resistor should surface mount package, with inductance. account should wirewound through hole package used. prevent potential mistriggering problems from occurring noisy systems, recommended that filter applied across sense resistor, shown figure
Kelvin connection ISEN RFILTER A4403 RSENSE CFILTER SGND Kelvin connection Power current
Figure filter added current sense circuit
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
RFILTER CFILTER Typical Application diagram) should placed close A4403 pins. ground sense should connect directly SGND power ground. Support Components bootstrap capacitor (C2) softstart capacitor (C5) should ceramic X7R. Thermal Considerations ensure A4403 operates safe operating area, which effectively means restricting junction temperature less than 150°C, several checks should made. general approach work what thermal impedance, required maintain junction temperature given level, particular power dissipation. (Another factor worth considering that other power dissipating components system influence thermal performance A4403. example, power loss contribution from recirculation diode sense resistor cause junction temperature A4403 higher than expected.) should noted that this process usually iterative achieve optimum solution. following steps used guideline determining suitable thermal solution. Estimate maximum ambient temperature, TA(max) application. Define maximum junction temperature, TJ(max). Note that absolute maximum 150°C. Determine worst case power dissipation, PD(max). This will occur maximum load minimum VIN. Contributors are: Switch static losses Estimate maximum duty cycle: (max) VOUT (min) (19)
Estimate RDS(on) buck switch given junction temperature: RDS(on)TJ RDS(on)25C (20) static loss each switch determined: PSTAT ILOAD2 (max) RDS(on)TJ where ILOAD load. Switch dynamic losses Both turn-on turn-off losses estimated: PDYN VIN(min) ILOAD (22) (21)
where switching frequency. Diode capacitance turn-on loss turn-on, additional current spike flows into switch, causing loss follows: PDIODECAP CDIODE VIN2 (23)
where CDIODE body capacitance Schottky diode (D1). Control losses control losses estimated follows: PCTRL IVINON Gate charge losses Estimate charge losses follows: PGATE (25) (24)
where IVINON quiescent current with converter enabled.
where forward voltage drop Schottky diode (D1) sense resistor (R2, under given load current.
where charge that required turn buck switch.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
total losses estimated: PTOTAL PSTAT PDYN PDIODECAP PCTRL PGATE (26) thermal impedance required solution determined:
Diode capacitance turn-on loss (equation 23): PDIODECAP 0.132
Control losses (equation 24): PCTRL 0.004 0.168 Gate charge losses (equation 25): PGATE 0.21 Total losses (equation 26): PTOTAL 0.433 0.504 0.132 0.168 0.21 1.447 Thermal impedance (equation 27):
PTOTAL
(27)
Note that four-layer high thermal efficiency board used, thermal impedance around 30°C/W achieved. Example Given selected parameters: VIN(min) VOUT MHz, 70°C, Target junction temperature, 115°C, 0.55 CDIODE then: Switch static losses Maximum duty cycle (equation 19): 0.55 (max) 0.09 0.55 RDS(on) buck switch (equation 20): 0.535 RDS(on)TJ Static loss each switch (equation 21): PSTAT 0.09 0.535 0.433 Switch dynamic losses (equation 22): PDYN 1000 0.504
31°C/W 1.447
this particular solution, with high thermal efficency required ensure junction temperature kept below 115°C. maximum effectiveness, area underneath thermal A4403 should flooded with copper. Several thermal vias (say between should used connect thermal internal ground plane. possible, further thermal copper plane should applied bottom side connected thermal A4403 through vias. This calculation assumes thermal influence from other components. possible, advisable mount recirculation diode (D1) reverse side printed circuit board. Ensure impedance electrical connections implemented between board layers. Layout Guidelines ground plane largely dictated thermal requirements previous section. ground-referenced power components should referenced star ground, located away from A4403 minimize ground bounce issues. small, local, relatively quiet ground plane near A4403 should used ground-referenced support components, minimize interference effects ground noise from power circuitry. Figure illustrates recommended grounding architecture.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
avoid ground offset issues output voltage, highly recommended that ground-referenced feedback resistor should connected directly connection A4403. other words, ground return should avoid internal ground plane. ground-referenced support components switch) should also located close connection possible. "local quiet" ground plane around these components implemented; however, this ground plane should have high impedance connection star ground connection power stages, referenced below. sense resistor connections should connected Kelvin circuit (see figure corresponding pins A4403
(ISEN SGND). Note that imperative that traces between sense resistor pads sense connections short possible minimize effects leakage inductance. noisy systems, highly recommended that filter used filter signal produced across ISEN pin. Sense Resistor section Typical Application schematic. internal ground plane used, recommended that does overlap switching node, avoid possibility noise pick minimize possibility noise injection issues, recommended isolate ground plane around high impedance nodes, such
A4403 Support Components
Switch
Power Circuitry
Star Connection
Cout
A4403
SGND
Local `quiet' Ground Plane
Thermal Vias
Internal Ground Plane
Figure Ground plane configurations
Input Voltage
VOUT
Input Voltage
VOUT
COUT RLOAD
COUT
RLOAD
Star Connection
Star Connection
Figure on-cycle current conduction paths
Figure off-cycle current conduction paths
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
terms grounding power components, star connection should made minimize ground loop impedances. Note that, although ground plane required meet thermal characteristics solution, still imperative implement star ground connection power components. Figures illustrate importance keeping ground connections short possible forming good star connections. Figure also illustrates current conduction paths during on-cycle switching FET. following points should noted: capacitor should placed close possible terminal.
inductor should placed close possible terminal output capacitors COUT. Good separation should exist between connection adjacent components traces. Figure shows current conduction path during off-cycle switching FET. following points should noted: diode should placed close possible both switching inductor. resistor should placed close possible diode boostrap capacitor, soft start capacitor, should located close possible their respective terminal connections. ground reference soft start capacitor should connected close terminal possible.
BOOT
VOUT
4403
ISEN
SGND
3.92
Switching Frequency capacitors ceramic Resistors should surface mount, inductance type, rated 70°C
Figure Typical application
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4403
Valley Current Mode Control Buck Converter
Package 16-Contact
0.35 4.00 ±0.15 4.00 ±0.15 0.95 2.70 4.10 0.65
2.70 4.10 0.08 0.30 ±0.05 0.65 SEATING PLANE 0.75 ±0.05 Layout Reference View
Reference Only (reference JEDEC MO-220WGGC) Dimensions millimeters Exact case lead configuration supplier discretion within limits shown Terminal mark area Exposed thermal (reference only, terminal identifier appearance supplier discretion)
0.40 ±0.10 2.70
Reference land pattern layout (reference IPC7351 QFN65P400X400X80-17W2M) pads minimum 0.20 from adjacent pads; adjust necessary meet application process requirements layout tolerances; when mounting multilayer PCB, thermal vias exposed thermal land improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Coplanarity includes exposed thermal terminals
2.70
Copyright ©2008-2009, Allegro MicroSystems, Inc. products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro's products used life support devices systems, failure Allegro product reasonably expected cause failure that life support device system, affect safety effectiveness that device system. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use.
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Extremely fast load-transient response with minimal output voltage del

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