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AK4201 Stereo Cap-less HP-Amp GENERAL DESCRIPTION AK4201 aud
Top Searches for this datasheet[AK4201] AK4201 Stereo Cap-less HP-Amp GENERAL DESCRIPTION AK4201 audio stereo cap-less headphone amplifier. AK4201 eliminates need large DC-blocking capacitors with built-in Charge-pump circuit. 100dB PSRR (Power Supply Rejection Ratio) achieved built-in regulator, 2Vrms outputs available with excellent linearity when AK4201 used lineout amplifier. AK4201 available tiny 12-pin USON (2.2 2.9mm), saving board space, cost, reducing component height. FEATURE Stereo Cap-less Amplifier DC-blocking capacitors required) High PSRR (100dB 217Hz) Output Power: AVDD=PVDD=5.0V, THD+N=-60dB AVDD=PVDD=3.3V, THD+N=-60dB Output Noise Level: 11µVrms (Ri=20k, Rf=30k) Line-Out level: 2.0Vrms AVDD=PVDD=5.0V 2.0Vrms AVDD=PVDD=3.3V Regulator built-in THD+N: -60dB 50mW, AVDD=PVDD=5.0V -60dB 20mW, AVDD=PVDD=3.3V -100dB 2Vrms, AVDD=PVDD=5.0V -100dB 2Vrms, AVDD=PVDD=3.3V Power Shutdown Mode 0.1µA (typ) Mute function shutdown mode: -88dB attenuation external component required Zero offset ground-referenced output noise free power-ON/OFF Power Supply: 2.6V 3.6V 4.5V 5.5V 85°C Package: 12pin USON (2.2 2.9mm, 0.5mm pitch) MS1077-E-00 2009/05 [AK4201] Block Diagram AVDD Regulator LOUT VSS2 AK4201 Regulator ROUT PVDD Charge Pump VSS1 PVEE Figure AK4201 Block Diagram MS1077-E-00 2009/05 [AK4201] Ordering Guide AK4201EU AKD4201 +85°C 12pin USON (2.2mm 2.9mm, 0.5mm pitch) Evaluation board AK4201 Layout LOUT ROUT AVDD View PVEE VSS1 VSS2 PVDD MS1077-E-00 2009/05 [AK4201] PIN/FUNCTION Name LOUT AVDD VSS1 PVDD Function L-channel analog input L-channel analog output Headphone positive power supply Ground Charge-pump positive power supply Negative charge-pump capacitor terminal Positive charge-pump capacitor terminal Power-down mode "H": Power-up, "L": Power-down Ground Charge-pump circuit negative voltage output R-channel analog output R-channel analog input VSS2 PVEE ROUT Note. must floated. Handling Unused unused pins must processed appropriately below. Classification Analog Name LIN, RIN, LOUT, ROUT Setting Connect Output Input when channel used other used. (Example) Connect ROUT used. MS1077-E-00 2009/05 [AK4201] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2 (Note Parameter Power Supplies: Analog (Note Charge Pump Input Current, Except Supplies Input Voltage (Note Ambient Temperature (powered applied)(Note Storage Temperature Symbol AVDD PVDD Tstg -0.3 -0.3 -0.3 (AVDD 0.3) 70(Note 85(Note Units Note voltages respect ground. should held when powered-up, should after power supplies powered-up. should held "L", when powered-down. Note VSS1 VSS2 must connected same analog plane. Note LIN, maximum value smaller value between (AVDD+0.3)V 6.0V. Note wiring density should 150% more. Device back should connected ground. Note Headphone Output Power should below 65mW/ch. Note Headphone Output Power should below 50mW/ch. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. RECOMMEND OPERATING CONDITIONS (VSS1=VSS2 (Note Parameter Power Supplies (Note Analog, Charge Pump Difference Symbol AVDD, PVDD AVDD PVDD Symbol Gain Csum -0.3 Units Units Parameter External Input Resistance External Feedback Resistance Gain Range Load Resistance (LOUT, ROUT pins) Capacitance (LOUT, ROUT pins) Capacitance (LIN, pins) Note AVDD PVDD must range from 3.6V 4.5V. Note: assumes responsibility usage beyond conditions this datasheet. MS1077-E-00 2009/05 [AK4201] ANALOG CHARACTERISTICS (AVDD=PVDD=5.0V) (AVDD=PVDD=5.0V; PDN=5.0V; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz 20kHz; Gain=+3.5dB (Ri=20k, Rf=30k); Headphone-Amp: =16; Charge Pump Circuit External Capacitance: C1=C2= (Figure unless otherwise specified) Parameter Units Output Power =16, 0.68Vrms Input THD+N 0.68Vrms Input; 65mW 0.60Vrms Input; 50mW -100 1.33Vrms Input; 2.0Vrms (Signal-to-Noise Ratio) (A-weighted) (Note (A-weighted) (Note PSRR (Power Supply Rejection Ratio) (Note 217Hz 1kHz Interchannel Isolation Output Offset Voltage Start-up time (Note Power Supplies AVDD PVDD (Normal Mode; Output) AVDD PVDD (Power-Down Mode, =0V) Note case 0.68Vrms Input (Po=65mW). Note case 1.33Vrms Input (Vo=2Vrms). Note applied AVDD PVDD with 300mVpp sine wave. Note time from pin= when AK4201 output signals. MS1077-E-00 2009/05 [AK4201] ANALOG CHARACTERISTICS (AVDD=PVDD=3.3V) (AVDD=PVDD=3.3V; PDN=3.3V; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz 20kHz; Gain=+3.5dB (Ri=20k, Rf=30k); Headphone-Amp: =16; Charge Pump Circuit External Capacitance: C1=C2= (Figure unless otherwise specified) Parameter Units Output Power =16, 0.46Vrms Input THD+N 0.46Vrms Input; 30mW 0.27Vrms Input; 10mW -100 1.33Vrms Input; 2.0Vrms (Signal-to-Noise Ratio) (A-weighted) (Note (A-weighted) (Note PSRR (Power Supply Rejection Ratio) (Note 217Hz 1kHz Interchannel Isolation Output Offset Voltage Start-up time (Note Power Supplies AVDD PVDD (Normal Mode; Output) AVDD PVDD (Power-Down Mode, =0V) Note case 0.46Vrms Input (Po=30mW). Note case 1.33Vrms Input (Vo=2Vrms). Note applied AVDD PVDD with 100mVpp sine wave. Note time from pin= when AK4201 output signals. MS1077-E-00 2009/05 [AK4201] SWITCHING CHARACTERISTICS (Ta= 85°C; AVDD=PVDD=2.6 3.6V 5.5V, Note Parameter Symbol High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Power-down (PDN pulse Width) Note Apply pin. Units Timing Diagram Figure Power-down Timing MS1077-E-00 2009/05 [AK4201] OPERATION OVERVIEW Charge Pump Circuit charge pump operates output regulator which uses PVDD voltage. negative power supply (PVEE) headphone amplifiers generated from internal charge pump circuit. external capacitors showed Figure (Equivalent Series Resistance) capacitors with 2.2uF (+/-35% less difference including temperature drift deviation over samples) recommended minimum value capacitors should more than 0.65uF temperature drifts deviation over samples big. Headphone-amp negative voltage PVEE Charge Pump Circuit VSS1 Figure Charge Pump Circuit External Capacitor Headphone-Amp (LOUT/ROUT pins) Power supply voltage headphone amplifiers supplied regulator positive power charge-pump negative power. headphone amplifier output single-ended centered VSS1(0V). Therefore, capacitor AC-coupling removed. minimum load resistance output impedance (typ) when powered-down. MS1077-E-00 2009/05 [AK4201] Power-Up/Down Sequence must keep until power supply pins (AVDD, PVDD) supplied, must after. Power Supply Device front AK4201 Device front AK4201 Click noise PVEE PVEE Output =-3.3V(Typ.) Don't Care Power Signal Output) Normal Operation Don't Care LOUT/ROUT pins Normal Operation(0V Common) Figure Power-up/down Sequence example interval from power time 150ns more needed reset AK4201. power should when "L". should after power supply (AVDD, PVDD) interval from power-up signal source device front AK4201 AK4201's transition from other device should powered with signal (e.g. MUTE). When step wave instant level change) output from other device power-up, high pass filter response wave will occur timing Figure according time constant input coupling capacitor (Ci) input resistor(Ri) front AK4201. order prevent this noise through AK4201, wait time "Ta" required after other devices powered-up. AK4201 attenuate noises other device built-in mute circuit during shutdown mode (PDN pin= "L"). calculation example: case =0.22uF, 20k) =0.22u 4.4ms 33ms (When noise level former device= response wave level= 1mV. 7.6* needed) waiting time sufficient, noise might occur, there problem normal operation. AK4201 normal operation 50ms (max) after goes "H". other device front AK4201 should still muted during this interval (50ms). other device front AK4201 should start outputting signal after AK4201 starts Normal Operation. click noise generated former device when MUTE canceled, will output from AK4201. "L". LOUT/ROUT pins short VSS1 with 20(typ.). After 50ms (max.), PVEE will according capacitor which connected PVEE internal resistance (typ. 17.5k). AK4201 powered again after 150ns more from "L". MS1077-E-00 2009/05 [AK4201] SYSTEM DESIGN Analog Input 0.22µ View 0.22µ Analog Input LOUT AVDD ROUT PVEE VSS2 Power Supply 4.55.5V, 2.63.6V 0.1µ VSS1 0.1µ Power Supply 4.55.5V, 2.63.6V PVDD Note: should held when powered-up. should after power supplies powered-up. When power-down AK4201, should held "L". Refer "Power-Up/Down Sequence" avoid noise when power-up/down AK4201. Power-Up power should when "L". should 150ns after power supplies (AVDD, PVDD) 150ns time more needed reset AK4201. Power-Down AK4201 should powered-down when "L". 1uF~2.2uF ceramic capacitors (±35% including temperature characteristics piece-to-piece variations) should connected between pins, VSS1 PVEE1 pins, respectively. Both lines from each Input resistance feedback resistance should short possible better PSRR. coupling capacitors should connected pins, respectively. MS1077-E-00 2009/05 [AK4201] PACKAGE 12pin USON (2.2mm 2.9mm, 0.5mm pitch) 2.9± 0.05 0.05 0.225 0.05 0.175 0.05 0.05 0.05 0.05 0.50 Exposed 0.08 0.05 0.25 0.05 1.35 0.05 0.05 Note) exposed bottom surface package must connected ground. MS1077-E-00 0.6MAX 2009/05 [AK4201] MARKING 4201 XXXX XXXX: Date code digit) REVISION HISTORY Date (YY/MM/DD) 09/05/12 Revision Reason First Edition Page Contents IMPORTANT NOTICE These products their specifications subject change without notice. When consider application these products, please make inquiries sales office Asahi Kasei Microdevices Corporation (AKM) authorized distributors current status products. assumes liability infringement patent, intellectual property, other rights application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical componentsNote1) safety, life support, other hazard related device systemNote2), assumes responsibility such use, except approved with express written consent Representative Director AKM. used here: Note1) critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. Note2) hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. responsibility buyer distributor products, distributes, disposes otherwise places product with third party, notify such third party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification. MS1077-E-00 2009/05 Other recent searchesTSM6970D - TSM6970D TSM6970D Datasheet SLLS667B - SLLS667B SLLS667B Datasheet Si7724DN - Si7724DN Si7724DN Datasheet L934MD - L934MD L934MD Datasheet L934MD - L934MD L934MD Datasheet L934MD - L934MD L934MD Datasheet L934MD - L934MD L934MD Datasheet 2SRD - 2SRD 2SRD Datasheet B9014 - B9014 B9014 Datasheet 1KSMBJ - 1KSMBJ 1KSMBJ Datasheet series - series series Datasheet
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