AK4118 High Feature 192kHz 24bit Digital Audio Transceiver G

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AK4118 High Feature 192kHz 24bit Digital Audio Transceiver G

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[AK4118]
AK4118
High Feature 192kHz 24bit Digital Audio Transceiver
GENERAL DESCRIPTION AK4118 digital audio transceiver supporting 192kHz, 24bits. channel status decoder supports both consumer professional modes. AK4118 automatically detect Non-PCM stream. When combined with multi channel codec (AK4626A AK4628A), chips provide system solution AC-3 applications. dedicated pins serial control mode setting. small package, 48pin LQFP saves system space. *AC-3 trademark Dolby Laboratories. FEATURES AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible jitter Analog Lock Range: 8kHz 192kHz Clock Source: X'tal 8-channel Receiver input 2-channel Transmission output (Through output DIT) Auxiliary digital input De-emphasis 32kHz, 44.1kHz, 48kHz 96kHz Detection Functions Non-PCM Stream Detection DTS-CD Stream Detection Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) Unlock Parity Error Detection Validity Flag Detection Start Detection 24bit Audio Data Format Audio I/F: Master Slave Mode 42-bit Channel Status Buffer Burst Preamble Buffer Non-PCM stream Q-subcode Buffer stream Serial (I2C, SPI) Master Clock Outputs: 64fs/128fs/256fs/512fs Operating Voltage: 3.6V with tolerance 8GPIO Port Data Input Detection Small Package: 48pin LQFP 70°C
MS1042-E-01
2009/02
[AK4118]
Block Diagram
AVDD Decoder DAUX Audio Input Selector LRCK BICK SDTO Clock Recovery X'tal Oscillator Clock Generator MCKO1 MCKO2
DVDD DVSS TVDD AC-3/MPEG Detect Error TATUS Detect Q-subcode buffer CCLK CDTO CDTI
B,C,U,VOUT
GP0,1,2,3,4,5,6,7 INT0
INT1
P/S="L"
Serial Control Mode
AVSS AVDD IPS0 DIF0 DIF1 DIF2 Input Selector
X'tal
Clock Recovery
Oscillator Clock Generator MCKO1 MCKO2
DAIF Decoder
Audio
LRCK BICK SDTO
DAUX
OCKS0
DVDD DVSS TVDD
AC-3/MPEG Detect
Error STATUS Detect
OCKS1
B,C,U,VOUT
INT0
INT1
P/S="H" IPS1
Parallel Control Mode
MS1042-E-01
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[AK4118]
Ordering Guide
AK4118VQ AKD4118 48pin LQFP (0.5mm pitch) Evaluation Board AK4118
Layout
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
MCKO2
DAUX
SDTO
BICK
INT0
AVDD VCOM VSS3 TEST1 VSS4
LRCK MCKO1 VSS2 DVDD VOUT/GP7 UOUT/GP6 COUT/GP5 BOUT/GP4 TX1/ TX0/GP2
AK4118EQ
TEST2
VSS1
XTL1
DIF0/RX5
DIF1/RX6
IPS0/RX4
DIF2/RX7
MS1042-E-01
VIN/GP0
IPS1/IIC
XTL0
2009/02
[AK4118]
PIN/FUNCTION
Name IPS0 DIF0 TEST2 DIF1 VSS1 DIF2 IPS1 XTL0 XTL1 TVDD BOUT COUT UOUT VOUT DVDD VSS2 MCKO1 LRCK Function Input Channel Select Parallel Mode Receiver Channel Serial Mode (Internal biased pin) Connect internal bonding. This should connected VSS3. Audio Data Interface Format Parallel Mode Receiver Channel Serial Mode (Internal biased pin) TEST This should connect VSS3. Audio Data Interface Format Parallel Mode Receiver Channel Serial Mode (Internal biased pin) Ground Audio Data Interface Format Parallel Mode Receiver Channel Serial Mode (Internal biased pin) Input Channel Select Parallel Mode Select Serial Mode. "L": 4-wire Serial, "H": Parallel/Serial Select "L": Serial Mode, "H": Parallel Mode X'tal Frequency Select X'tal Frequency Select V-bit Input Transmitter Output GPIO0 Serial Mode Input Buffer Power Supply Pin, DVDD ~5.5V GPIO1 pin1in Serial Mode Transmit Channel (Through Data) Output GPIO2 Serial Mode When "0", Transmit Channel (Through Data) Output Pin. When "1", Transmit Channel (DAUX Data) Output (Default). bit= "1": Default) GPIO3 Serial Mode Block-Start Output Receiver Input during first flames. GPIO4 Serial Mode C-bit Output Receiver Input GPIO5 Serial Mode U-bit Output Receiver Input GPIO6 Serial Mode V-bit Output Receiver Input GPIO7 Serial Mode Digital Power Supply Pin, 2.7V 3.6V Ground Master Clock Output Channel Clock
MS1042-E-01
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[AK4118]
PIN/FUNCTION (Continued)
Function Audio Serial Data Output Audio Serial Data Clock Master Clock Output Auxiliary Audio Data Input X'tal Output X'tal Input Power-Down Mode When "L", AK4118 powered-down, output pins registers initialized. Master Clock Operation Mode Parallel Mode CDTO Control Data Input Serial Mode, IIC= "L". CAD1 Control Data Serial Mode, IIC= "H". Master Clock Operation Mode Parallel Mode CDTI Control Data Input Serial Mode, IIC= "L". Control Data Serial Mode, IIC= "H". OCKS1 Output Clock Select Parallel Mode CCLK Control Data Clock Serial Mode, IIC= Control Data Clock Serial Mode, IIC= OCKS0 Output Clock Select Parallel Mode Chip Select Serial Mode, IIC="L". CAD0 Chip Address Serial Mode, IIC= "H". INT0 Interrupt INT1 Interrupt AVDD Analog Power Supply Pin, 2.7V 3.6V External Resistor +/-1% resistor should connected VSS3 externally. Common Voltage Output VCOM 0.47µF capacitor should connected VSS3 externally. VSS3 Ground Receiver Channel (Internal biased pin) This channel default serial mode. Connect internal bonding. This should connected VSS3. Receiver Channel (Internal biased pin) TEST pin. TEST1 This should connected VSS3. Receiver Channel (Internal biased pin) VSS4 Ground eceiver Channel (Internal biased pin) Note input pins except internal biased pins (RX0-7 pins)should left floating. Name SDTO BICK MCKO2 DAUX
MS1042-E-01
2009/02
[AK4118]
ABSOLUTE MAXIMUM RATINGS
(VSS1-4=0V; Note Parameter Symbol Power Supplies: Analog AVDD Digital DVDD Input Buffer TVDD |VSS3-VSS2| (Note Input Current (Any pins except supplies) Input Voltage (Except pin) Input Voltage (XTI pin) VINX Ambient Temperature (Power applied) Storage Temperature Tstg Note voltages with respect ground. Note VSS1-4 must connected same ground. -0.3 -0.3 -0.3 -0.3 -0.3 TVDD+0.3 DVDD+0.3 Units
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1-4=0V; Note Parameter Symbol Power Supplies: Analog AVDD Digital DVDD Input Buffer TVDD DVDD Note voltages with respect ground. There level shifter. AVDD Units
S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.7~3.6V; TVDD=2.7~5.5V) Parameter Symbol Input Resistance Input Voltage Input Hysteresis Input Sample Frequency
Units mVpp
CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.7~3.6V; TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol Power Supply Current Normal operation: (Note Power down: (Note High-Level Input Voltage 70%DVDD TVDD Low-Level Input Voltage VSS2-0.3 30%DVDD DVDD-0.4 High-Level Output Voltage (Iout=-400A) Low-Level Output Voltage (Except pin: Iout=400A) pin: Iout= 3mA) Input Leakage Current Note AVDD=DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=192kHz, X'tal=24.576MHz, Clock Operation Mode OCKS1=1, OCKS0=1. AVDD=7mA (typ), DVDD=25mA (typ), TVDD=10A (typ). DVDD=36mA (typ) when circuit Figure attached both pins. Note inputs open digital input pins held DVDD VSS2.
Units
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[AK4118]
SWITCHING CHARACTERISTICS (Ta=25°C; DVDD=AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 External Clock Frequency (Note fECLK 8.192 Duty dECLK MCKO1 Output Frequency fMCK1 4.096 Duty dMCK1 MCKO2 Output Frequency fMCK2 2.048 Duty dMCK2 Clock Recover Frequency (RX0-7) Fpll LRCK Frequency Duty Cycle dLCK Audio Interface Timing Slave Mode BICK Period tBCK BICK Pulse Width tBCKL Pulse Width High tBCKH tLRB LRCK Edge BICK (Note tBLR BICK LRCK Edge (Note tLRM LRCK SDTO (MSB) tBSD BICK SDTO tDXH DAUX Hold Time tDXS DAUX Setup Time Master Mode BICK Frequency fBCK 64fs BICK Duty dBCK tMBLR BICK LRCK tBSD BICK SDTO tDXH DAUX Hold Time tDXS DAUX Setup Time Control Interface Timing (4-wire serial mode) CCLK Period tCCK CCLK Pulse Width tCCKL Pulse Width High tCCKH CDTI Setup Time tCDS CDTI Hold Time tCDH Time tCSW tCSS CCLK tCSH CCLK tDCD CDTO Delay tCCZ CDTO Hi-Z Note When fECLK=8.192MHz, sampling frequency detect function (page16) disable. Note BICK rising edge must occur same time LRCK edge.
24.576 24.576 24.576 24.576
Units
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[AK4118]
SWITCHING CHARACTERISTICS (Continued) (Ta=25°C; DVDD=AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol Control Interface Timing (I2C mode): Clock Frequency fSCL Free Time Between Transmissions tBUF Start Condition Hold Time tHD:STA (prior first clock pulse) Clock Time tLOW Clock High Time tHIGH Setup Time Repeated Start Condition tSU:STA Hold Time from Falling (Note tHD:DAT Setup Time from Rising tSU:DAT Rise Time Both Lines Fall Time Both Lines Setup Time Stop Condition tSU:STO Capacitive load Pulse Width Spike Noise Suppressed Input Filter Reset Timing Pulse Width Note Data must held sufficient time bridge transition time SCL. Note registered trademark Philips Semiconductors.
Units
MS1042-E-01
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[AK4118]
Timing Diagram
1/fECLK tECLKH tECLKL dECLK tECLKH fECLK tECLKL fECLK
1/fMCK1
MCKO1 tMCKH1 tMCKL1
50%DVDD dMCK1 tMCKH1 fMCK1 tMCKL1 fMCK1
1/fMCK2
MCKO2 tMCKH2 tMCKL2
50%DVDD dMCK2 tMCKH2 fMCK2 tMCKL2 fMCK2
1/fs tLRH tLRL dLCK tLRH tLRL
LRCK
Figure Clock Timing
tBCK tBLR BICK tLRB tBCKL tBCKH tLRM tBSD 50%DVDD tDXS tDXH
LRCK
SDTO
DAUX
Figure Serial Interface Timing (Slave Mode)
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[AK4118]
LRCK
50%DVDD
tMBLR BICK 50%DVDD
tBSD 50%DVDD
SDTO tDXS tDXH
DAUX
Figure Serial Interface Timing (Master Mode)
tCSS tCCK tCCKL tCCKH CCLK tCDH tCDS
CDTI
CDTO
Hi-Z
Figure WRITE/READ Command Input Timing 4-wire serial mode
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[AK4118]
tCSW tCSH
CCLK
CDTI
CDTO
Hi-Z
Figure WRITE Data Input Timing 4-wire serial mode
CCLK
CDTI
tDCD
CDTO
Hi-Z
50%DVDD
Figure READ Data Output Timing 4-wire serial mode
tCSW tCSH CCLK
CDTI
tCCZ
CDTO
50%DVDD
Figure READ Data Input Timing 4-wire serial mode
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[AK4118]
tBUF tLOW tHIGH tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
Figure mode Timing
Figure Power Down Reset Timing
MS1042-E-01
2009/02
[AK4118]
OPERATION OVERVIEW
Non-PCM (AC-3, MPEG, etc.) DTS-CD Bitstream Detection
AK4118 Non-PCM steam auto-detection function. When 32bit mode Non-PCM preamble based Dolby "AC-3 Data Stream IEC60958 Interface" detected, AUTO goes "1". 96bit sync code consists 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 0x4E1F. Detection this pattern will AUTO "1". Once AUTO "1", will remain until 4096 frames pass through chip without additional sync pattern being detected. When those preambles detected, burst preambles that follow those sync codes stored registers. AK4118 also DTS-CD bitstream auto-detection function. When AK4118 detects DTS-CD bitstreams, DTSCD goes "1". When next sync code does come within 4096 flames, DTSCD goes until when AK4118 detects stream again. AK4118 detects 14bit Sync Word 16bit Sync Word DTS-CD bitstream. Serial control mode this detect function ON/OFF DTS14 DTS16 bit.
192kHz Clock Recovery
integrated jitter wide lock range from 8kHz 192kHz lock time depend sampling frequency FAST setting (Figure 10). FAST useful lower sampling frequency fixed parallel control mode. serial control mode, AK4118 sampling frequency detection function (8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) that uses either clock comparison against X'tal oscillator channel status information from setting XTL1-0 bits. parallel control mode, sampling frequency detected using reference frequency, 24.576MHz. When sampling frequency more than 64kHz, FS96 goes "H". When sampling frequency less than 54kHz, FS96 goes "L". loses lock when received sync interval incorrect. FAST Lock Time (default) 384/fs) 1/fs) Figure Lock Time (fs: Sampling Frequency)
Master Clock
AK4118 clock outputs, MCKO1 MCKO2. MCKO2 output mode selected XMCK bit. XMCK "0", AK4118 clock outputs, MCKO1 MCKO2. These clocks derived from either recovered clock from X'tal oscillator. frequencies master clock outputs (MCKO1 MCKO2) OCKS0 OCKS1 shown Table 512fs clock will output when 96kHz 192kHz. 256fs clock will output when 192kHz. OCKS1 OCKS0 MCKO1 256fs 256fs 512fs 128fs MCKO2 256fs 128fs 256fs 64fs X'tal 256fs 256fs 512fs 128fs (max)
(default)
Table Master Clock Frequency Select (Stereo mode)
MS1042-E-01
2009/02
[AK4118] XMCK "1", MCKO2 outputs input clock regardless OCKS1-0 settings. output frequency. MCKO1 outputs clock according CM1-0 OCKS1-0 settings. XMCK MCKO2 Clock Source MCKO2 Frequency X'tal X'tal Table MCKO2 Output Frequency Setting
Clock Operation Mode
CM0/CM1 pins bits) select clock source data source SDTO. Mode clock source switched from X'tal when goes unlock state. Mode3, clock source fixed X'tal, also operating recovered data such bits monitored. Mode2 Mode3, recommended that frequency X'tal different from recovered frequency from PLL. UNLOCK X'tal Clock source SDTO (default) ON(Note) X'tal DAUX X'tal DAUX X'tal DAUX Oscillation (Power-up), OFF: STOP (Power-Down) Note: When X'tal used clock comparison detection (i.e. XTL1/0 pins= "H"), X'tal off. Table Clock Operation Mode select Mode
MS1042-E-01
2009/02
[AK4118]
Clock Source
clock generated following methods: X'tal
AK4118
Figure X'tal Mode Note: External capacitance depends crystal oscillator (Max. 30pF)
External clock
External Clock
AK4118
Figure External clock mode Note: Input clock must exceed DVDD.
Fixed Clock Operation Mode
AK4118
Figure Mode
MS1042-E-01
2009/02
[AK4118]
Sampling Frequency Pre-emphasis Detection
AK4118 methods detecting sampling frequency follows. Clock comparison between recovered clock X'tal oscillator Sampling frequency information channel status Those could selected XTL1/0 pins. detected frequency reported FS3-0 bits. XTL1 XTL0 X'tal Frequency 11.2896MHz 12.288MHz 24.576MHz (Use channel status) Table Reference X'tal frequency XTL1-0 "11" Register output Clock comparison (Note Consumer mode (Note Byte3 Bit3,2,1,0 0000 0001 0010 0011 0100
(default)
XTL1-0 "11" Professional mode (Note Byte0 Bit7,6 Byte4 Bit6,5,4,3 0000 (Others) 0000 0000 1001
44.1kHz 44.1kHz Reserved 48kHz 48kHz 32kHz 32kHz 22.05kHz 22.05kHz 11.025kHz 11.025kHz 24kHz 0110 0001 24kHz 16kHz 16kHz 88.2kHz 1000 1010 88.2kHz 8kHz 8kHz 96kHz 1010 0010 96kHz 64kHz 64kHz 176.4kHz 1100 1011 176.4kHz 192kHz 1110 0011 192kHz Note least frequency range identified values Table FS3-0 bits indicate nearer frequency intermediate frequency values. When frequency over range 32kHz 192kHz, FS3-0 bits indicate "0001". Note When consumer mode, Byte3 Bit3-0 copied FS3-0. Note professional mode, FS3-0 bits always "0001" except frequencies listed table. Table Sampling Frequency Information pre-emphasis information detected reported bit. This information extracted from channel default. switched channel CS12 control register. Pre-emphasis Byte Bits
0X100 0X100 Table Consumer Mode Pre-emphasis Byte Bits
Table Professional Mode
MS1042-E-01
2009/02
[AK4118]
De-emphasis Filter Control
AK4118 digital de-emphasis filter (tc=50/15µs) which corresponds four sampling frequencies (32kHz, 44.1kHz, 48kHz 96kHz) filter. When DEAU bit="1", de-emphasis filter enabled automatically sampling frequency pre-emphasis information channel status. AK4118 this mode default. Therefore, Parallel Mode, AK4118 always placed this mode status bits channel control de-emphasis filter. Serial Mode, DEM0/1 bits control de-emphasis filter when DEAU "0". internal de-emphasis filter bypassed recovered data output without change either pre-emphasis de-emphasis Mode OFF. (Others) Mode 44.1kHz 48kHz 32kHz 96kHz
Table De-emphasis Auto Control DEAU (default) DEM1 DEM0 Mode 44.1kHz 48kHz 32kHz 96kHz
(default)
Table De-emphasis Manual Control DEAU
System Reset Power-Down
AK4118 power-down mode circuits pin, partially powerd-down bit. RSTN initializes register resets internal timing. Parallel Mode, only control enabled. AK4118 should reset once bringing upon power-up. Pin: analog digital circuit placed power-down reset mode bringing pin= "L". registers initialized, clocks stopped. Reading/Witting register disabled. RSTN (Address 00H; D0): registers except RSTN initialized bringing RSTN "0". internal timings also initialized. Witting register available except RSTN. Reading register disabled. (Address 00H; D1): clock recovery part initialized bringing "0". this case, clocks stopped. registers initialized mode settings kept. Writing Reading registers enabled.
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[AK4118]
Biphase Input Through Output
Eight receiver inputs (RX0-7) available Serial Control Mode. Each input includes amplifier corresponding unbalance mode accept signal 200mV more. IPS2-0 selects receiver channel. When BCUV "1", Block start signal, output from each pins. RXDE7-0 bits indicate input signal status pin. When signal input pin, RXDE "1". IPS2 IPS1 IPS0 INPUT Data
(default)
Table Recovery Data Select
1/4fs COUT U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
(Normal mode) SDTO R190 L191 R191
LRCK (except LRCK (I2S)
R190 (Mono mode) SDTO (except I2S) LRCK (except I2S) LRCK
L191
R191
Figure output timings
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[AK4118]
Biphase Output
AK4118 outputs data either through output (from DIR) transmitted output (DIT; data from DAUX transformed IEC60958 format.) from TX1/0 pins. selected bit. source data through output from selected among RX0-8 OPS00, bits, selected OPS10, bits respectively. When AK4118 outputs DAUX data, controlled first bytes controlled CT39-CT0 bits control registers (Figure 15). When bit0= "0"(consumer mode), bit20-23(Audio channel) controlled directly controlled CT20 bit. When CT20 "1", AK4118 outputs "1000" C20-23 frame 1(left channel) output "0100" C20-23 frame (right channel) automatically. When CT20 "0", AK4118 outputs "0000". bits controlled UDIT follows; When UDIT "0", bits always "0". When UDIT "1", recovered bits used DIT( DIR-DIT loop mode bit). This mode only available when locked master mode. OPS02 OPS01 OPS00 Output Data
(default)
Table Output Data Select OPS12 Output Data DAUX (default) Don't care) Table Output Data Select
(Mono mode)
OPS11
OPS10
(Normal mode) LRCK (except I2S) LRCK DAUX
R191
L191/R191
L0/R0
L1/R1
Figure DAUX input timings
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[AK4118]
Double Sampling Frequency Mode
When MONO "1", AK4118 outputs data double speed according "Single channel double sampling frequency mode" AES3. example, when 192kHz mono data transmitted received, channels 96kHz biphase data used. this case, frame 96kHz LRCK frequency 192kHz. When MONO "1", AK4118 outputs mono data from SDTO follows.
frame
Biphase (Image)
MONO
LRCK (except IIS) LRCK (IIS) SDTO
LRCK
Figure MONO Mode (RX)
AK4118 (Master)
MCKO MCLK BICK LRCK
(AK4397)
SDTI
AK4118 (Slave)
Figure MONO mode Connection Example (RX)
MS1042-E-01
2009/02
[AK4118] When MONO "0", AK4118 outputs data through biphase signal. When MONO "1", then data output.
LRCK
LRCK (except IIS) LRCK (IIS) Serial Data DAUX
MONO TLR=0 Biphase (Image)
MONO TLR=1 Biphase (Image)
frame
Figure MONO Mode (TX)
AK4118 DAUX (Master)
MCKO MCLK BICK LRCK
(AK5394A)
SDATA
AK4118 DAUX (Slave)
Figure MONO Mode Connection Example (TX) Note: case connection example (Figure when more than AK4118's used, LRCK BICK should input after reset that phase outputs aligned. AK4118's should following sequence (Figure 20).
MS1042-E-01
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[AK4118] When Powered
Mode
LRCK, BICK
Stereo mode Mono mode
During Operation
RSTN Mode
LRCK, BICK
Stereo mode Mono mode
Reset AK4118's RSTN "1". AK4118's MONO mode while they still slave mode. AK4118 master mode that LRCK input other AK4118's same time, Input LRCK externally AK4118's same time. Figure MONO Mode Setup Sequence (TX)
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[AK4118]
Biphase Signal Input/Output Circuit
0.1uF Coax
AK4118
Figure Consumer Input Circuit (Coaxial Input) Note: case coaxial input, coupling level this input from next input line pattern exceeds 50mV, there possibility occur incorrect operation. this case, possible lower coupling level adding this decoupling capacitor.
Optical Receiver Optical Fiber
AK4118
Figure Consumer Input Circuit (Optical Input) coaxial input, input level line small Serial Mode, cross-talking among input lines have avoided. example, inserting shield pattern among them effective. Parallel Mode, four channel inputs (RX0/1/2/3) available RX4-7 change other pins audio format control. Those pins must fixed "L". AK4118 includes output buffer. output level meets 0.5V+/-20% using external resistors. Figure transformer 1:1.
DVSS cable
3.3V 3.0V
Figure External Resistor Network Note: When AK4118 power-down mode (PDN pin= "L"), power supply current suppressed using couple capacitor following figure since output becomes uncertain power-down mode.
0.1uF DVSS cable
3.3V 3.0V
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[AK4118]
Q-subcode Buffers
AK4118 Q-subcode buffer application. AK4118 takes Q-subcode into registers following conditions. sync word (S0,S1) constructed least "0"s. start "1". Those 7bits follows start bit. distance between start bits 8-16 bits. QINT control register goes when Q-subcode differs from one, goes when QINT read.
number min=0; max=8. Figure Configuration (CD)
CTRL ADRS TRACK NUMBER INDEX
MINUTE SECOND FRAME ZERO ABSOLUTE MINUTE ABSOLUTE SECOND ABSOLUTE FRAME G(x)=x16+x12+x5+1
Figure Q-subcode Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame Figure Q-subcode register
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[AK4118]
Error Handling
following nine events cause INT0 INT1 pins show status interrupt condition. When (Clock Operation Mode INT0 INT1 pins "L". UNLCK unlock state detect when loses lock. AK4118 loses lock when distance between preamble correct when those preambles correct. Parity error bi-phase coding error detection when parity error bi-phase coding error detected, updated every sub-frame cycle. Non-Linear DTS-CD Stream detection function NPCM DTSCD bits available AUTO bit. Validity flag detection when validity flag detected. Updated every sub-frame cycle. Non-audio detection when "AUDION" recovered channel status indicates "1". Updated every block cycle. Sampling frequency pre-emphasis information change detection When either FS3-0 changed, maintains during sub-frame. U-bit Sync flag when Q-subcode differs from one. Updated every sync code cycle Q-subcode. Channel status sync flag when received differs from one. Updated every block cycle. Start detect when category code indicates "DAT" "DAT Start detected. When DCNT "1", does indicate even "DAT Start detected again within "3841 LRCK". When "DAT Start detected again after "3840 LRCK" passed, indicates "1". When DCNT "0", indicates every "DAT Start detection.
AUTO AUDION QINT CINT
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[AK4118]
Parallel control mode parallel control mode, INT0 outputs ORed signal between UNLCK PAR. INT1 outputs ORed signal between AUTO AUDION. Once INT0 goes "H", maintains 1024/fs cycles after error events removed. Table shows state each output pins when INT0/1 "H". Event UNLCK AUTO AUDION INT0 INT1 SDTO Note Previous Data Output Output Output Note Note Note Note INT1 outputs accordance with ORed signal between AUTO AUDION. Note INT0 outputs accordance with ORed signal between UNLCK PAR. Note SDTO outputs "L", "Previous Data" "Normal Data" accordance with ORed signal between UNLCK PAR. Note outputs "Normal operation" accordance with ORed signal between UNCLK. Table Error Handling parallel control mode Don't care) Serial control mode serial control mode, INT1 INT0 pins output ORed signal based above nine interrupt events. When masked, interrupt event does affect operation INT1-0 pins (the masks affect registers bit). Once INT0 goes "H", remains 1024/fs (this value changed with EFH1-0 bits) after events masked mask bits cleared. INT1 immediately goes when those events cleared. UNLCK, PAR, AUTO, AUDION bits Address=07H indicate interrupt status events above real time. Once QINT, CINT bits goes "1", stays until register read. When AK4118 loses lock, channel status bit, user bit, initialized. this initial state, INT0 outputs ORed signal between UNLCK bits. INT1 outputs ORed signal between AUTO AUDION bits. Event Others SDTO Output Previous Data Output Output Output Output Output Table Error Handling serial control mode Don't care)
UNLCK
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[AK4118]
Error (UNLOCK, PAR,.) INT0
(Error)
Hold Time (max: 4096/fs)
INT1 Register (PAR,CINT,QINT) Register (others) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) Vpin (UNLOCK) Vpin (except UNLOCK) Previous Data
Hold Time
Hold
Reset
READ
Free (fs: around 5kHz)
Normal Operation
Figure INT0/1 Timing
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[AK4118]
="L" Initialize Read
INT0/1 ="H"
Release Muting
Mute output
Read
(Each Error Handling)
Read (Resets registers)
INT0/1 ="H"
Figure Error Handling Sequence Example
MS1042-E-01
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[AK4118]
="L" Initialize Read
INT1 ="H"
Read Detect QSUB=
(Read Q-buffer)
QCRC INT1 ="L" data valid
data invalid
Figure Error Handling Sequence Example (for Q/CINT)
MS1042-E-01
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[AK4118]
Audio Serial Interface Format
DIF0, DIF1 DIF2 pins select eight serial data formats shown Table formats serial data MSB-first, compliment format. SDTO clocked falling edge BICK DAUX latched rising edge BICK. BICK outputs 64fs clock Mode 0-5. Mode Slave Modes, BICK available 128fs fs=48kHz. format equal less than 20bit (Mode0-2), LSBs sub-frame truncated. Mode 3-7, last 4LSBs auxiliary data (Figure 30). When Parity Error, Biphase Error Frame Length Error occurs sub-frame, AK4118 continues output last normal sub-frame data from SDTO repeatedly until error removed. When Unlock Error occurs, AK4118 output from SDTO. case using DAUX pin, data transformed output from SDTO. DAUX used Clock Operation Mode unlock state Mode input data format DAUX should left justified except Mode5 7(Table 15). Mode5 both input data format DAUX output data format SDTO I2S. Mode6 Slave Mode that corresponding Master Mode Mode4 salve Mode, LRCK BICK should with synchronizing MCKO1/2.
sub-frame IEC60958
Aux.
preamble
AK4118 Audio Data (MSB First)
Figure Configuration LRCK BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs
Mode
DIF2
DIF1
DIF0
DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, Left justified 24bit,
SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 24bit, Left justified 24bit,
(default)
Table Audio Data Format
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[AK4118]
LRCK(0)
BICK (0:64fs)
SDTO(0)
15:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK(0)
BICK (0:64fs)
SDTO(0)
23:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK (64fs)
SDTO(0)
23:MSB, 0:LSB Data Data
Figure Mode Timing
Mode4: LRCK, BICK (Output) Mode6: LRCK, BICK (Input)
LRCK
BICK (64fs) SDTO(0)
23:MSB, 0:LSB Data Data
Figure Mode Timing
Mode5: LRCK, BICK (Output) Mode7: LRCK, BICK (Input)
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[AK4118]
GPIO controller
AK4118 input/output port pins. GP0~GP7 pins GPDR register data direction, GPSCR register level setting GPLR register level reading. Table 37~40 shows state setting internal node state GPIO registers, bit, TX1E/TX0E bit. VINE TX0/1 GP2/3 Register Setting Register Read State GPDR GPSCR GPLR Valid GPSCR GPSCR Table TX0/1 GP2/3 Internal Statement Don't care) B/C/U/VOUT GP4/5/6/7 Register Setting Register Read State BCUV GPDR GPSCR GPLR BCUV Data Hold Valid GPSCR GPSCR Table B/C/U/VOUT GP4/5/6/7 Internal Statement Don't care) Register Setting Register Read State GPDR GPSCR GPLR GPSCR GPSCR Table Internal Statement Don't care) Register Setting Register Read Internal Node State GPDR GPSCR GPLR Valid GPSCR Table VINGP0 Internal Statement Don't care) GPSCR
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[AK4118]
Serial Control Interface
(1). 4-wire serial control mode (IIC pin= "L") internal registers either written read 4-wire interface pins: CSN, CCLK, CDTI CDTO. data this interface consists Chip address (1bit, fixed "0"), Read/Write (1bit), Register address (MSB first, 5bits) Control data (MSB first, 8bits). Address data clocked rising edge CCLK data clocked falling edge. write operations, data latched after 16th rising edge CCLK, after high-to-low transition CSN. read operations, CDTO output goes high impedance after low-to-high transition CSN. maximum speed CCLK 5MHz. pin= resets registers their default values. When state changed, AK4118 should reset pin= "L".
CCLK
CDTI WRITE CDTO CDTI READ CDTO
Hi-Z
Hi-Z
Hi-Z
R/W: A5-A0: D7-D0:
Chip Address (Fixed "0") READ/WRITE (0:READ, 1:WRITE) Register Address Control Data
Figure 4-wire Serial Control Timing
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[AK4118] (2). control mode (IIC= "H") AK4118 supports High speed mode I2C-bus (max: 400kHz). (2)-1. Data transfer order access devices BUS, input start condition first, followed single Slave address that includes Device Address. devices compare this Slave address with their addresses device that identical address with Slave-address generates acknowledgement. device with identical address executes either read write operation. After command execution, input Stop condition. (2)-1-1. Data Change Change data line while line "L". line condition must stable fixed while clock "H". Change Data line condition between only when clock signal line "L". Change line condition while line only when start condition stop condition input.
DATA LINE STABLE DATA VALID
CHANGE DATA ALLOWED
Figure Data Transfer (2)-1-2. START STOP condition Start condition generated transition line while line "H". instructions initiated Start condition. Stop condition generated transition line while line "H". instructions Stop condition.
START CONDITION
STOP CONDITION
Figure START STOP condition
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[AK4118] (2)-1-3. Acknowledge external device that sending data AK4118 releases line ("H") after receiving one-byte data. external device that receives data from AK4118 then sets line next clock. This operation called "acknowledgement", enables verification that data transfer been properly executed. AK4118 generates acknowledgement upon receipt Start condition Slave address. write instruction, acknowledgement generated whenever receipt each byte completed. read instruction, succeeded generation acknowledgement, AK4118 releases line after outputting data designated address, monitors line condition. When Master side generates acknowledgement without sending Stop condition, AK4118 outputs data next address location. When acknowledgement generated, AK4118 ends data output (not acknowledged).
Clock pulse acknowledge
FROM MASTER
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER START CONDITION acknowledge
Figure Acknowledge I2C-bus (2)-1-4. First Byte First Byte which includes Slave-address input after Start condition set, target device that will accessed selected Slave-address. Slave-address configured with upper 7-bits. Data upper 5-bits "00100". next bits address bits that select desired which CAD1 CAD0 pins. When Slave-address inputted, external device that identical device address generates acknowledgement instructions then executed. First Byte (lowest bit) allocated Bit. When "1", read instruction executed, when "0", write instruction executed.
CAD1
CAD0
(Those CAD1/0 should match with CAD1/0 pins.) Figure First Byte
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[AK4118] (2)-2. WRITE Operations WRITE operation AK4118. After receipt start condition first byte, AK4118 generates acknowledge, awaits second byte (register address). second byte consists address control registers AK4118. format first, those most significant 3-bits "Don't care".
Don't care) Figure Second Byte After receipt second byte, AK4118 generates acknowledge, awaits third byte. Those data after second byte contain control data. format first, 8bits.
Figure Byte structure after second byte AK4118 capable more than byte write operation sequence. After receipt third byte, AK4118 generates acknowledge, awaits next data again. master transmit more than words instead terminating write cycle after first data word transferred. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten.
Slave Address
Register Address(n)
Data(n)
Data(n+1)
Data(n+x)
Figure WRITE Operation
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[AK4118] (2)-3. READ Operations READ operation AK4118. After transmission data, master read next address's data generating acknowledge instead terminating write cycle after receipt first data word. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten. AK4118 supports basic read operations: CURRENT ADDRESS READ RANDOM READ. (2)-3-1. CURRENT ADDRESS READ AK4118 contains internal address counter that maintains address last word accessed, incremented one. Therefore, last access (either read write) address "n", next CURRENT READ operation would access data from address "n+1". After receipt slave address with "1", AK4118 generates acknowledge, transmits 1byte data which address internal address counter increments internal address counter master does generate acknowledge generate stop condition, AK4118 discontinues transmission.
Slave Address Data(n+x)
Data(n)
Data(n+1)
Data(n+2)
Figure CURRENT ADDRESS READ (2)-3-2. RANDOM READ Random read operation allows master access memory location random. Prior issuing slave address with "1", master must first perform "dummy" write operation. master issues start condition, slave address(R/W="0") then register address read. After register address's acknowledge, master immediately reissues start condition slave address with "1". Then AK4118 generates acknowledge, 1byte data increments internal address counter master does generate acknowledge generate stop condition, AK4118 discontinues transmission.
Slave Address Word Address(n) Slave Address Data(n+x)
Data(n)
Data(n+1)
Figure RANDOM READ
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[AK4118]
Register
Addr
Register Name Power Down CS12 Control Format De-em Control MONO Input/ Output Control Input/ Output Control INT0 MASK INT1 MASK Receiver status Receiver status Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte
Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte
DIF2 OPS12 EFH0
DIF1 OPS11 UDIT MCIT0 MCIT1 CINT CR13 CR21 CR29 CR37
CT13 CT21 CT29 CT39
DIF0 OPS10
OCKS1 DEAU TX0E
OCKS0 DEM1 OPS02 IPS2 MPE0 MPE1 CR10 CR18 CR26 CR34
CT10 CT18 CT26 CT39
DEM0 OPS01 IPS1
RSTN OPS00 IPS0
TX1E EFH1
MQIT0 MAUT0 MQIT1 MAUT1 QINT CR15 CR23 CR31 CR39
CT15 CT23 CT31 CT39
MULK0 MDTS0 MULK1 MDTS1 UNLCK DTSCD CR12 CR20 CR28 CR36
CT12 CT20 CT28 CT39
MAUD0 MPAR0 MAUD1 MPAR1 AUDION QCRC CR17 CR25 CR33
CT17 CT25 CT39
AUTO CR14 CR22 CR30 CR38
CT14 CT22 CT30 CT39
CCRC CR16 CR24 CR32
CT16 CT24 CT32
CR11 CR19 CR27 CR35
CT11 CT19 CT27 CT39
Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame
PC15 PD15
PC14 PD14
PC13 PD13
PC12 PD12
PC11 PD11
PC10 PD10
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[AK4118] Addr GPDR GPSCR GPLR Mask Detect Detect Detect Channel Status Byte Channel Status Byte Register Name GPL7 XMCK RXDE7 RXDETE RXDE6 VINE MED1 FAST MDR0
MSTC1
MSTC0
DTS16
MDAT1
DTS14
MDAT0
EXCKMD DCNT
RXDE5 RXDE4
RXDE3
RXDE2 RXDE1 RXDE0 CR41 CT41 CR40 CT40
Note: When goes "L", registers initialized their default values. When RSTN goes "0", internal timing reset registers initialized their default values. data written register even "0".
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[AK4118]
Register Definitions
Reset Initialize
Addr Register Name Power Down Control Default CS12 OCKS1 OCKS0 RSTN
RSTN: Timing Reset Register Initialize Reset Initialize Normal Operation PWN: Power Down Power Down Normal Operation OCKS1-0: Master Clock Frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start Output Mode When BCU=1, three Output Pins(BOUT, COUT, UOUT) become enabled. block signal goes high start frame remains high until frame CS12: Channel Status Select Channel Channel Selects which channel status used derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, de-emphasis filter controlled channel Parallel Mode.
Format De-emphasis Control
Addr Register Name Format De-em Control Default MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0
DFS: 96kHz De-emphasis Control DEM1-0: 44.1, 48kHz De-emphasis Control (Table DEAU: De-emphasis Auto Detect Enable Disable Enable DIF2-0: Audio Data Format Control (Table MONO: Double sampling frequency mode enable Stereo mode Mono mode
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[AK4118]
Input/Output Control
Addr Register Name Input/ Output Control Default TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00
OPS02-00: Output Through Data Select OPS12-10: Output Through Data Select TX0E: Output Enable Disable. outputs "L". Enable TX1E: Output Enable Disable. outputs "L". Enable Addr Register Name Input/ Output Control Default EFH1 EFH0 UDIT IPS2 IPS1 IPS0
IPS2-0: Input Recovery Data Select DIT: Through data/Transmit data select Through data data). Transmit data (DAUX data). TLR: Double sampling frequency mode channel select DIT(stereo) channel channel UDIT: control fixed Recovered used (loop mode bit) EFH1-0: Interrupt Hold Count Select LRCK 1024 LRCK 2048 LRCK 4096 LRCK
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[AK4118]
Mask Control INT0
Addr Register Name INT0 MASK Default MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0
MPR0: Mask Enable MAN0: Mask Enable AUDN MPE0: Mask Enable MDTS0: Mask Enable DTSCD MUL0: Mask Enable UNLOCK MCI0: Mask Enable CINT MAT0: Mask Enable AUTO MQI0: Mask Enable QINT Mask disable Mask enable
Mask Control INT1
Addr Register Name INT1 MASK Default MQI1 MAT1 MCI1 MUL1 MDTS1 MPE1 MAN1 MPR1
MPR1: Mask Enable MAN1: Mask Enable AUDN MPE1: Mask Enable MDTS1: Mask Enable DTSCD MUL1: Mask Enable UNLOCK0 MCI1: Mask Enable CINT MAT1: Mask Enable AUTO MQI1: Mask Enable QINT Mask disable Mask enable
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[AK4118]
Receiver Status
Addr Register Name Receiver status Default QINT AUTO CINT UNLCK DTSCD AUDION
PAR: Parity Error Biphase Error Status 0:No Error 1:Error Parity Error Biphase Error detected sub-frame. AUDION: Audio Output Audio Audio This made encoding channel status bits. PEM: Pre-emphasis Detect. This made encoding channel status bits. DTSCD: DTS-CD Auto Detect detect Detect UNLCK: Lock Status Locked Unlocked CINT: Channel Status Buffer Interrupt change Changed AUTO: Non-PCM Auto Detect detect Detect QINT: Q-subcode Buffer Interrupt change Changed QINT, CINT bits initialized when read.
Receiver Status
Addr Register Name Receiver status Default QCRC CCRC
CCRC: Cyclic Redundancy Check Channel Status 0:No Error 1:Error QCRC: Cyclic Redundancy Check Q-subcode 0:No Error 1:Error Validity channel status 0:Valid 1:Invalid FS3-0: Sampling Frequency detection (Table
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[AK4118]
Receiver Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CR15 CR23 CR31 CR39 CR14 CR22 CR30 CR38 CR13 CR21 CR29 CR37 CR12 CR20 CR28 CR36 CR11 CR19 CR27 CR35 CR10 CR18 CR26 CR34 CR17 CR25 CR33 CR41 CR16 CR24 CR32 CR40
initialized
CR41-0: Receiver Channel Status Byte
Transmitter Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CT15 CT23 CT31 CT39 CT14 CT22 CT30 CT38 CT13 CT21 CT29 CT37 CT12 CT11 CT20 CT19 CT28 CT27 CT36 CT35 CT10 CT18 CT26 CT34 CT17 CT25 CT33 CT41 CT16 CT24 CT32 CT42
CT41-0: Transmitter Channel Status Byte
Burst Preamble Pc/Pd non-PCM encoded Audio Bitstreams
Addr Register Name Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Default PC15 PD15 PC14 PD14 PC13 PD13 PC12 PD12 PC11 PD11 PC10 PD10
initialized
PC15-0: Burst Preamble Byte PD15-0: Burst Preamble Byte
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[AK4118]
Q-subcode Buffer
Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame Default
initialized
GPIO Control
Addr Register Name Default RXDETE VINE FAST EXCKMD DCNT DTS16 DTS14
DTS14: DTS-CD 14bit Sync Word Detect Disable Enable (default) DTS16: DTS-CD 16bit Sync Word Detect Disable Enable (default) DCNT: Start Counter Disable Enable (default) EXCKMD: X'tal Oscillator Setting Power (default) Power Down FAST: Lock Time Select (Figure (15ms 384/fs) (default) (15ms 1/fs) VINE: Input Enable Disable Enable (default) RXDETE: Input Detect Enable Disable Enable (default) GPE: GPIO mode Enable GPIO mode Disable (default) GPIO mode Enable GPIO mode GP2-7 pins enabled when bit= bit= TX1E bit= TX0E bit= "0". GPIO mode regardless state when VINE bit= "0". always GPIO mode.
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[AK4118]
Addr Register Name GPDR Default
IO7-0: GPIO Input/Output Setting Input (default) Output Addr Register Name GPSCR Default
SC7-0: GPIO Output Level Setting (default) This effective only when setting output mode (21H: GPDR= "1"). Actual level read GPLR register. Addr Register Name GPLR Default GPL7 GPL6 GPL5 GPL4 GPL3 GPL2 GPL1 GPL0
GPD7-0: GPIO Input Level Read GLP7-0 bits read only register that read input signal level corresponding GPIO pins (GP7-0 pins). GPIO mode enabled GP2-7 pins read input signal level when TX1E TX0E "0". When VINE "0", GPIO mode enabled GPLO read input signal level. GPL1 always read input signal level pin. GPL2-7 bits GPL0 always when GPIO mode disable.
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[AK4118]
Mask Detect Addr Register Name Mask Detect XMCK Default
MRDT1 MRDT0 MSTC1 MSTC0 MDAT1 MDAT0
MDAT0: Mask enable Mask disable Mask enable (default) When Mask enabled "1", state reflected INT0 pin. MDAT1: Mask enable Mask disable Mask enable (default) When Mask enabled "1", state reflected INT1 pin. MSTC0: Mask enable Disable Enable (default) When Mask enabled "1", state reflected INT0 pin. MSTC1: Mask enable Disable Enable (default) When Mask enabled "1", state reflected INT1 pin. MRDT0: Mask enable Detect Disable Enable (default) When Mask enabled "1", input detection resault reflected INT0 pin. MRDT1: Mask enable Detect Disable Enable (default) When Mask enabled "1", input detection resault reflected INT1 pin. DIV: MCKO2 Frequency Dividing Ratio X'tal mode (Table (default) XMCK: MCKO2 Output Setting (Table Setting CM1-0 bits OCKS1-0 bits (default) Fixed X'tal mode
Detect Addr Register Name Detect Default
RXDE7 RXDE6 RXDE5 RXDE4 RXDE3 RXDE2 RXDE1 RXDE0
RXDE7-0: Input Detect Detect Detect When RXDETE "0", input detection function disabled register fixed "0". When unused open, AK4118 able detect input signal correctly. unused should connected GND.
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[AK4118]
Detect Addr Register Name Detect Default
DAT: Start Detect detect Detect initialized when Addr= READ. STC: Change Detection Sampling Frequency pre-emphasis information detect Detect When FS3-0 bits changed, goes "1". initialized when Addr=26H READ.
Burst Preambles non-PCM Bitstreams
sub-frame IEC60958
preamble Aux.
bits bitstream
Burst_payload
stuffing
repetition time burst
Figure Data structure IEC60958 Preamble word Length field Contents bits sync word bits sync word bits Burst info bits Length code Table Burst preamble words Value 0xF872 0x4E1F Table numbers bits
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[AK4118] Bits Value 16-31 Contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 data MPEG-2 without extension MPEG-2 data with extension MPEG-2 ADTS MPEG-2, Layer1 sample rate MPEG-2, Layer2 sample rate reserved type type type ATRAC ATRAC2/3 reserved reserved, shall error-flag indicating valid burst_payload error-flag indicating that burst_payload contain errors data type dependent info stream number, shall Table Fields burst info Repetition time burst IEC60958 frames 4096 1536 1152 1152 1024 1152 1024 2048 1024
8-12 13-15
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[AK4118]
Non-PCM Bitstream Timing
When Non-PCM preamble data coming within 4096 frames,
stream
Repetition time
>4096 frames
AUTO
Register
Register
Figure Timing Example When Non-PCM bitstream stops (when MULK0 "0"),
INT0 <20mS (Lock time) stream Stop Syncs (B,M AUTO <Repetition time INT0 hold time
Register
Register
Figure Timing Example
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[AK4118]
SYSTEM DESIGN
Figure shows example system connection diagram Serial Mode.
Analog Ground Digital Ground
+3.3V Analog Supply
10µF 0.1µF
(Shield)
(SPDIF Sources)
VCOM TEST1 VSS4 AVDD
INT1
Microcontroller
INT0
(SPDIF Sources)
TEST2 P/SN
CCLK CDTI
AK4118
CDTO DAUX MCKO2 BICK MCKO1 SDTO LRCK DVDD VSS2
X'tal=11.2896MHz SDTO MCLK BICK SDTI1 SDTI2 LRCK SDTI3
CODEC (AK4626A)
(Micro controller)
XTL0 XTL1
10µF
+3.3V Digital Supply
10µF
0.1µF
0.1µF +3.3V Digital Supply
(SPDIF out) (Microcontroller)
Figure Typical Connection Diagram (Serial Mode) Notes XTL0 XTL1settings, refer Table value dependent crystal. VSS1-4 must connected same ground plane. Digital signals, especially clocks, should kept away from order avoid effect clock jitter performance.
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[AK4118]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max 0.13 0.13 1.40 0.05
0.22 0.08
0.09~0.20 0.10
0.10
0.3~0.75
Material Lead finish
Package molding compound: Epoxy, Halogen (bromine chlorine) free Lead frame material: Lead frame surface treatment: Solder free) plate
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[AK4118]
MARKING
AK4118EQ XXXXXXX
XXXXXXXX: Date code identifier
REVISION HISTORY
Date (YY/MM/DD) 08/12/17 09/02/26 Revision Reason First Edition Error Correct Page Contents FEATURES Lock Range: 32kHz~192kHz 8kHz 192kHz S/PDIF RECEIVER CHARACTERISTICS Input Sample Frequency: (min) SWITCHING CHARACTERISTICS Clock Recover Frequency: (min) LRCK Frequency: (min)
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[AK4118]
IMPORTANT NOTICE These products their specifications subject change without notice. When consider application these products, please make inquiries sales office Asahi Kasei Corporation (AKEMD) authorized distributors current status products. AKEMD assumes liability infringement patent, intellectual property, other rights application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. AKEMD products neither intended authorized critical componentsNote1) safety, life support, other hazard related device systemNote2), AKEMD assumes responsibility such use, except approved with express written consent Representative Director AKEMD. used here: Note1) critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. Note2) hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. responsibility buyer distributor AKEMD products, distributes, disposes otherwise places product with third party, notify such third party advance above content conditions, buyer distributor agrees assume responsibility liability hold AKEMD harmless from claims arising from said product absence such notification.
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AK4118 High Feature 192kHz 24bit Digital Audio Transceiver G

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