Asahi Kasei User Manual AK4115 High Performance AES3/EBU, S/PDIF
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User Manual AK4115 High Performance AES3/EBU, S/PDIF Transceiver
AK4115 AKM's highest performance AES/EBU transceiver. AK4115 contains very high performance that less than 70ps jitter. AK4115 offers several unique features that included earlier generation AK4114. crystal oscillator circuits, which enable complete clocking solution capable generating multiple 44.1kHz 48kHz master clocks. receiver transmitter operate fully asynchronously, where transmitter master. device lock either clock word clock (studio sync). There input selector with support fully differential (balanced) input. output transmitter integrated differential RS422 output.
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Semiconductor Table Contents Section Introduction What AK4115? Purpose Document Section Choose your control mode: Parallel (H/W) Serial (S/W)? Section Features Uses AK4115 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6
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AES3/EBU Receive Input Source Selection (Sync Audio Serial Interface Format Setup (Sync Audio Serial Interface Clocking Source Setup (Sync Audio Serial MCLK Ratio Setup (Manual Auto "ACKS") Channel Status Bits User Bits AES3/EBU Output Source Selection Async Audio Serial Interface Format Setup Async Audio Serial Interface Clocking Setup Async Audio Serial Interface MCLK Ratio Control Channel Status Bits User Bits Synchronous Rx/Tx Mode Asynchronous Rx/Tx Mode (Not available Parallel mode)
AES/EBU Input/Output Loop-through 3.5.1 Direct Rx-to-Tx Loop-through Routing 3.5.2 Full Recovery/Regeneration Rx-to-Tx Loop-thru Routing 3.6.1 3.6.2 3.6.3 3.6.4 3.7.1 3.7.2 3.7.3 Crystal Clock Generation Control Hardware Setup Crystal Clock Operation (Sync Audio Serial Interface Format Setup Crystal Clock Operation (Sync Audio Serial Interface Clocking Setup Crystal Clock Operation (Sync Audio Serial Interface MCLK Ratio Control Crystal Clock Operation Word Clock Input (Sync Audio Serial Interface Format Setup Word Clock Operation (Sync Audio Serial Interface Clocking Source Setup Word Clock Operation (Sync Audio Serial MCLK Ratio Setup (Manual Auto "ACKS") Auto Detection Word Clock Input Sample Rate Auto Detection Input non-Audio Format (AC-3, DTS, etc.) Auto Detection Input Pre-emphasis, Auto switching De-emphasis Filter Auto Switch Crystal Clock UNLOCK
Section Ancillary Features Uses AK4115
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Section Introduction What AK4115?
AK4115 AKM's latest highest performing AES3/EBU transceiver. includes many problem solving features beyond what typically provided transceiver device. These features include clock generator functions supporting selectable clock sources 44.1kHz-base 48kHz-base rate crystal operation, Word Clock input, addition AES3/EBU Receive input clock source.
What's purpose this document?
This document intended utilized designers Audio products conjunction with AK4115 product datasheet. will highlight practical problem solving features available AK4115, detail these incorporated into real-world product designs. Topics shall explained with reference similar information within datasheet. Sections through explain supporting features AK4115. Occasionally, these explanations shall make references similar features other devices, such AK4114, comparison.
Section Choose your control mode: Parallel (H/W) Serial (S/W)? Serial Parallel Control Modes
available features differ depending upon whether Serial (software) control Parallel (H/W pin) control utilized. control method important design decision that should made early design process. features AK4115 available Serial control mode, while only subset available Parallel mode. comparison, refer block diagrams from AK4115 datasheet pages (Serial mode) three (Parallel mode) shown here page four convenience. following sections features AK4115 shall described both Serial Parallel control modes applicable. description given control shall referred control "bit" Serial mode control "pin" Parallel mode. facilitate decision which control mode best required given application, note shall made features unavailable Parallel control mode. Also, keep mind that some AK4115 functions simultaneously controllable their control well control bit. such functions control method does necessarily override other; rather both typically considered logical basis. Note shall made this descriptions features applicable.
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Parallel Mode Block Diagram (AK4115 Datasheet Page
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Section Features AK4115
3.1.1
AES3/EBU Receive Input
Source Selection AK4115 receive AES3/EBU source with 216kHz sample rate eight multiplexed inputs RX7, with supporting balanced operation, while others unbalanced. Note that only inputs available Parallel control mode. selection, these lines routed AK4115's clock data recovery serial control mode IPS[2:0] control bits, parallel mode IPS[1:0] control pins (selection logical between bit). AK4115 datasheet Tables (page specify IPS[x:0] settings needed select each available line. Also shown from datasheet page register location IPS[2:0] control bits. Selector Control (AK4115 Datasheet Page
Register Location Selector Control Bits (AK4115 Datasheet Page
3.1.2
(Sync Audio Serial Interface Format Setup Once with desired source routing, configure audio serial interface pins MCKO1/2, BICK LRCK, collectively referred this document (Sync Tx)" audio serial I/F, desired format, clocking, output path recovered data SDTO pin. Format options include Master, Slave, AES3, I2S, MSB-Justified, controlled
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DIF[2:0] AES3 control bits Serial mode, DIF[1:0] control pins Parallel mode with limited format options. These settings same whether AK4115 Synchronous Rx/Tx mode Asynchronous mode (defined Sections 3.4). AK4115 datasheet Tables (for Serial mode) (for Parallel mode) from page shown here listing interface format options supported their respective control settings. Also shown from datasheet page register locations DIF[2:0] AES3 control bits. (Sync Audio Serial Interface Format Control (AK4115 Datasheet Page
Reg. Location (Sync Audio Format Cntrl. Bits (AK4115 Datasheet
3.1.3
(Sync Audio Serial Interface Clock Source Setup Clock source data routing (Sync. serial audio interface controlled Clock Mode CM[1:0] PSEL control bits/pins. state PSEL pulled down LOW, Serial control mode default setting control PSEL selects input source AK4115's PLL. Additional functionality PSEL further explained Section regarding Word Clock input support. Clock Modes applicable normal Receive operation. Mode default basic Receive operation, selection Mode adds capability revert clock source crystal oscillator case loss lock (removed invalid input). Setup crystal clocking explained Section 3.6. Note that Mode Mode with valid input only clocking modes which allow data routing SDTO output pin. other Clock Modes DAUX fixed data source looped SDTO pin. AK4115 datasheet Table from page
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shown below specifying Clock Mode control options CM[1:0] Also shown from datasheet page register location CM[1:0] control bits. (Sync Clock Mode CM[1:0] Control (AK4115 Datasheet Page
Register Locations (Sync Audio Clock Mode Control Bits (AK4115 Datasheet Pages
3.1.4
(Sync Audio Serial Interface MCLK Ratio Setup (Manual Auto "ACKS") recovered master clock provided output pins MCKO1 MCKO2, which equal frequency MCKO1 allow ease applications with converters with differing MCLK ratio requirements such AK5394A AK4396 DAC. MCLK ratio present MCKO1 MCKO2 either manually controlled OCKS[1:0] bits/pins, automatically -overriding OCKS[1:0] settings- Master Clock Frequency Auto Setting Mode enabled ACKS bit/pin. order Master Clock Frequency Auto Setting Mode operate necessary also related function Automatic Sample Rate Detection, which explained Section 4.1. AK4115 datasheet Tables from page shown below. Table shows MCKO1 MCKO2 MCLK ratios, well maximum available sample rate, combinations OCKS[1:0] control settings controlled manually when ACKS disabled. Table shows MCKO1 MCKO2 MCLK ratios that automatically over sample rate range 216kHz
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ACKS enabled. Also shown from datasheet page register locations OCKS[1:0] ACKS control bits. (Sync Audio Serial Interface MCLK Ratio Control (AK4115 Datasheet Page
Register Locations (Sync Audio MCLK Ratio Control Bits (AK4115 Datasheet Page
3.1.5
Channel Status Bits Serial control mode bits Channel Status Data captured readable from AK4115 registers. Shown below from datasheet page their register locations. Register Locations Channel Status Bits (AK4115 Datasheet Page
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Channel Status data also available either Serial Parallel control modes, framed signal outputted pin. This format fixed Parallel control mode enabled Serial control mode default settings BCU_IO (both `1'). pin, pin, have shared function between Receiver Transmitter. these Receive, pins should Output mode, Transmit they should Input mode. direction controlled BCU_IO control bit. Shown below from AK4115 datasheet pages register locations BCU_IO (I/O direction) (enable) control bits. Register Locations Rx/Tx Mode Control Bits (AK4115 Datasheet Pages
3.1.6
User Bits Serial control mode there register dedicated User bits. User bits available either Serial Parallel control modes framed pin. This format fixed Parallel control mode enabled Serial control mode default settings BCU_IO bit. Shown above register locations these control bits.
3.2.1
AES3/EBU Transmit Output
Source Selection AK4115 transmit AES3/EBU stream through integrated RS-422 balanced line driver output TX1. Audio serial interface data into transmitter DAUX pin. This routing path through AK4115 fixed Parallel mode enabled default Serial mode when Serial mode, alternatively accept input source Rx-to-Tx loop-through, explained Section 3.5. There another transmit output that dedicated Rx-to-Tx loop-through, also explained Section 3.5. Shown below from AK4115 datasheet page register location control bit. Register Location Data Source Control (AK4115 Datasheet
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Semiconductor 3.2.2 Audio Serial Interface Format Setup
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proper MCLK, BICK LRCK interface pins mode control associated with DAUX data AES3/EBU transmission depend upon operation mode either Synchronous Rx/Tx Asynchronous Rx/Tx, defined Sections 3.4. Synchronous Rx/Tx Mode, clocking synchronous active synchronous crystal-based clocking inactive unused). operation synchronous audio serial interface setup details covered Section 3.1.2 apply. operation synchronous crystalbased clocking audio serial interface setup details covered Section apply. Asynchronous Rx/Tx mode, dedicated audio serial interface pins EMCK crystal X'tal X'tal #2), EBICK ELRCK (collectively referred "Async audio serial this document) used. Serial control mode, Asynchronous Rx/Tx clocking mode enabled setting control ASYNC `1'. Asynchronous Rx/Tx mode unavailable Parallel control mode. Format options Async audio serial interface Master, Slave, MSB-Justified, controlled EDIF[1:0] control bits. Shown below from AK4115 datasheet page register location ASYNC control bit. AK4115 datasheet Table from page also shown, listing interface format options supported their respective EDIF[1:0] control settings. Also shown from datasheet page register locations EDIF[1:0] control bits. Register Location Rx/Tx Audio Async. Mode Cntrl. (AK4115 Datasheet
Asynchronous Audio Serial Interface Format Control (AK4115 Datasheet Page
Reg. Location Async Audio Format Control Bits (AK4115 Datasheet Page
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3.2.3
Async Audio Serial Interface Clocking Setup following clocking setup explanation applies operation Asynchronous Rx/Tx mode (defined Section 3.4). Synchronous Rx/Tx Mode (defined Section 3.3), setup details covered Section 3.1.3 apply operation. clock source "Async serial audio interface operation Asynchronous Rx/Tx Mode either crystal (default) supplied X'tal X'tal external MCLK provided EMCK pin. Asynchronous Rx/Tx mode unavailable Parallel control mode. Clock source selection controlled MSEL control bit. MSEL crystal selected master clock source frequency will either X'tal X'tal depending upon another selector setting, XSEL bit/pin. MSEL clock provided EMCK selected master clock source. AK4115 datasheet Table from page specifying control options MSEL control bit, shown below. Also shown below register location MSEL. Async Clock Source Control (AK4115 Datasheet Page
Register Location Async Clock Source Control (AK4115 Datasheet Page
AK4115 pins XTL0 XTL1 should tied HIGH according datasheet Table determine which supported crystal frequencies present. AK4115 datasheet Table from page shown below listing supported crystal frequencies generating clocking standard 44.1kHz- 48kHz-base audio sample rates. Supported Crystal Frequencies XTL[1:0] Strapping (AK4115 Datasheet Page
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crystal clock operation (control MSEL `0') X'tal master clock source XSEL control `1'(or XSEL tied HIGH) X'tal selected XSEL XSEL tied LOW). From AK4115 datasheet page crystal clock selection behavior XSEL bit/pin, from page register location XSEL control bit. Async Crystal Clock Select (AK4115 Datasheet Page
Register Location Async Crystal Select Control (AK4115 Datasheet Page
3.2.4 Async Audio Serial Interface MCLK Ratio Control order Asynchronous clocking, MCLK ratio needs manually specified setting ECKS[1:0] control bits. This setting applies Asynchronous mode MCLK sources: EMCK, X'tal X'tal audio sample rate determined MCLK ratio setting combined with MCLK frequency. AK4115 datasheet Table from page shown below specifying MCLK ratio selection options, along with maximum supported sample rate each. Async MCLK Ratio Control (AK4115 Datasheet Page
Register Location Async MCLK Ratio Cntrl. Bits (AK4115 Datasheet
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Semiconductor 3.2.5 Channel Status Bits
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Serial control mode, bits Channel Status Data written AK4115 registers then transferred into next frame stream. Shown below from datasheet page their register locations. Register Locations Channel Status Bits (AK4115 Datasheet Page
Channel Status data also (only Serial control mode), then framed signal supplied pin. This enabled setting BCU_IO `0', controlling direction pins Input mode, default value `1'. pin, pin, have shared function between Transmitter Receiver. these Receive, pins should placed Output mode setting BCU_IO `1'. Shown below from AK4115 datasheet page register locations BCU_IO (I/O direction) (enable) control bits. Register Location Rx/Tx Mode Control Bits (AK4115 Datasheet Page
3.2.6
User Bits Serial control mode there register dedicated User bits. User bits entered through Serial control mode only) then framed signal supplied pin. This enabled setting BCU_IO `0', controlling direction pins Input mode. Shown above register location BCU_IO control bit.
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Synchronous Rx/Tx Mode
default Serial control mode, AK4115 transmitter synchronous receiver with audio serial interface sharing common MCKO1/2, BICK LRCK clocking pins, aside from their respective data pins DAUX SDTO. These interface pins collectively referred this document (Sync Tx)" audio serial interface. Parallel control mode AK4115 operates solely Synchronous Rx/Tx mode. previous generation transceiver (AK4114) operates solely Synchronous Rx/Tx mode.
Asynchronous Rx/Tx Mode
Serial control mode, setting control ASYNC allows AK4115 transmitter operate independently from receiver with dedicated audio serial interface pins EMCLK, EBICK, ELRCK, addition transmit data DAUX. These interface pins collectively referred "Async audio serial interface. This mode useful for: allowing simultaneously operate different sample rates, allowing operate while inactive and, allowing clock master slave user situations where another AES-connected system, such digital rack effect, inserted between digital processing loop. Asynchronous Rx/Tx mode unavailable Parallel control mode. AK4115 Transmitter functional block primarily affected Asynchronous Rx/Tx mode setting. operation details Transmitter Asynchronous Rx/Tx mode covered Section 3.2. Receiver operation Asynchronous Rx/Tx mode same Synchronous Rx/Tx mode.
3.5.1
AES/EBU Input/Output Loop-through
Direct Rx-to-Tx Loop-through Routing Parallel mode, direct Rx-to-Tx loop-through routing fixed limited source destination. Serial control mode, input directly loop-through routed transmitter output control bits OPS0[2:0], independently routable OPS1[2:0]. This routing independent source routing selection AK4115's clock data recovery SDTO output. Direct Rx-to-Tx loop-through routing bypasses PLL. Intentional Rx-to-Tx loop-through routing through PLL, such stream regeneration, covered next subsection. AK4115 datasheet Tables from page shown below specifying OPS0[2:0] settings needed select input TX0, likewise OPS1[2:0] TX1. Table control then sourced audio serial interface with data DAUX pin, overriding direct Rx-to-Tx loopthrough settings OPS1[2:0]; loop through TX1. Also shown below AK4115 register locations OPS0[2:0], OPS1[2:0] control bits.
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Transmit Output Loopback Routing Control (AK4115 Datasheet Page
Register Locations Rx-to-Tx Loop-through Control (AK4115 Datasheet Page
3.5.2
Full Recovery/Regeneration Rx-to-Tx Loop-thru Routing previous section explained simplest method route stream from which passes through signal directly does regenerate "cleaned-up" version stream. route AES3/EBU stream from input through back output full regeneration stream, select desired input, Synchronous Rx/Tx mode, electrically connect route system controller/DSP) receiver's data output SDTO transmitter's data input DAUX. input selected either Serial Parallel control mode IPS[2:0] bits IPS[1:0] pins, respectively, Section 3.1.1. serial audio interface must setup desired format,
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which must same both SDTO DAUX. Format options include I2S, MSB-Justified AES3 controlled DIF[2:0] AES3 control bits Serial mode, DIF[1:0] control pins Parallel mode with limited format options. Either Master mode Slave mode used; however, Slave mode used, valid BICK LRCK signals need provided externally. Serial control mode possible pass from bits continuously setting AES3 `1', configuring AK4115 pass these bits along with stream data over SDTO-to-DAUX signal connection. Parallel control mode passing bits possible. AK4115 datasheet Tables (for Serial mode) (for Parallel mode) from page shown below highlighting compatible interface format options supported their respective control settings. Also shown from datasheet page register locations DIF[2:0] AES3 control bits. Rx-to-Tx Audio Serial Interface Format Options (AK4115 Datasheet Page
Register Location Rx-to-Tx Audio Format Control Bits (AK4115 Datasheet
With SDTO signal routed DAUX, complete data path from selected input through output preconfigured Serial mode default setting fixed such Parallel control mode. Shown below from AK4115 datasheet page register location control bit.
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Register Location Data Source Control (AK4115 Datasheet
Crystal Clock Generation Control
AK4115 capable generating needed clocking system operation mode Internal Clock, where external clock sources clocking typically sourced locally crystal oscillators. this way, AK4115 plays unique role system clock generator, rather than merely typical AES/EBU transceiver. Crystal clocking also used "fall back" clock source event sudden loss Word clock input. Clocking derived crystal oscillators supported AK4115 provide both 44.1kHz- 48kHz-based sample rates. AK4115 programmable, providing required clocking, including required MCLK ratios, serial audio interfaces, either (Sync Tx)", "Async both, operate interfacing system's DAC's, ADC's, DSP's, etc. supporting common sample rates 192kHz. crystal clock operation mode, AK4115 synchronously transmit AES3/EBU data output. However, Receiver cannot output recovered AES3/EBU data SDTO pin.
3.6.1
Hardware Setup Crystal Clock Operation crystals (X'tal X'tal supported AK4115 XTI1/XTO1, XTI2/XTO2 pins. AK4115 logic input pins XTL0 XTL1 tied HIGH according AK4115 datasheet Table indicate which supported crystal frequencies present application. Selection control either X'tal X'tal separate issue handled XSEL control bit/pin, explained Section 3.6.3. AK4115 datasheet Table from page shown below listing supported crystal frequencies generating clocking standard 44.1kHz- 48kHz-base audio sample rates. Supported Crystal Frequencies XTL[1:0] Strappings (AK4115 Datasheet Page
3.6.2
(Sync Audio Serial Interface Format Setup Crystal Clock Operation This subsection explains formatting setup (Sync Tx)" audio serial interface operating crystal clocking applies either Synchronous Rx/Tx mode Asynchronous Rx/Tx mode (defined Sections 3.4). Parallel control mode, Asynchronous Rx/Tx
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operation unavailable. Formatting setup "Async audio serial interface, available Asynchronous Rx/Tx mode, AES3/EBU transmission operating crystal clocking explained Section 3.2. (Sync audio serial interface format options include Master, Slave, AES3, I2S, MSB-Justified, among others controlled DIF[2:0] AES3 control bits Serial mode, DIF[1:0] control pins Parallel mode with limited format options. AK4115 datasheet Tables (for Serial mode) (for Parallel mode) from page shown below listing interface format options supported their respective control settings. Also shown from datasheet page register locations DIF[2:0] AES3 control bits. (Sync Audio Serial Interface Format Control (AK4115 Datasheet Page
Reg. Location (Sync Audio Format Cntrl. Bits (AK4115 Datasheet
3.6.3
(Sync Audio Serial Interface Clocking Setup Crystal Clock Operation Clock source selection (Sync Tx)" audio serial interface controlled Clock Mode CM[1:0] Source Select PSEL control bits/pins. This control behavior same whether operating AK4115 Synchronous Rx/Tx Mode Asynchronous Rx/Tx Mode. Crystal clocking "Async audio serial interface operation Asynchronous Rx/Tx Mode explained Section 3.2. Additional functionality PSEL further explained Section regarding Word Clock input support. Referring below AK4115 datasheet Table Clock Modes applicable crystal clock operation (Sync Tx)" serial audio interface. these crystal clocking modes, data recovery unavailable from
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input. While Mode default basic Receive operation (without crystal clock), selection Mode adds capability revert clocking source crystal clock case loss lock removed invalid input. Mode simplest crystal clocking mode, where input data ignored data DAUX looped data source SDTO pin. Mode adds capability monitoring Channel Status bits, while SDTO data source must still DAUX. Mode equivalent Mode Mode applies Word Clock operation (covered Section 3.7) allows clocking source revert crystal clock case loss lock removed invalid Word Clock input. AK4115 datasheet Table from page shown below specifying control options CM[1:0] Also shown from datasheet pages register location CM[1:0] PSEL control bits. Clock Mode CM[1:0] Control Crystal Clock Source (AK4115 Datasheet Page
Reg. Locations Audio Clock Mode Control Bits (AK4115 Datasheet
crystal clock operation, X'tal master clock source XSEL control `1'(or XSEL tied HIGH) X'tal selected XSEL XSEL tied LOW). From AK4115 datasheet page crystal clock selection status XSEL bit/pin, from page register location XSEL control bit.
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Register Location Crystal Clock Select Control (AK4115 Datasheet Page
3.6.4
(Sync Audio Serial Interface MCLK Ratio Control Crystal Clock Operation crystal-sourced master clock provided output pins MCKO1 MCKO2, which equal frequency MCKO1 allow ease applications with converters with different MCLK ratio requirements such AK5394A AK4396 DAC. initial setup subsequent change sample rate, MCLK ratio required MCKO1 MCKO2 manually controlled OCKS[1:0] bits/pins. Master Clock Frequency Auto Setting Mode ACKS bit/pin does apply. MCLK ratio setting combined with frequency selected MCLK source determines audio sample rate. AK4115 datasheet Table from page shown below listing MCKO1 MCKO2 MCLK ratios, well maximum available sample rate, combinations OCKS[1:0] control bit/pin settings. Also shown from datasheet page register locations OCKS[1:0] control bits. Audio Serial Interface MCLK Ratio Control (AK4115 Datasheet Page
Register Locations Audio MCLK Ratio Cntrl. Bits (AK4115 Datasheet Page
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Word Clock Input
AK4115 ELRCK used accept frame clock input, commonly called "Word Clock", into generation output clocking (Sync Tx)" audio serial interface outputting MCLKO1 MCKO2, plus BICK LRCK operating Master mode. input source selection either input ELRCK input controlled PSEL bit/pin. Either setting PSEL control pulling PSEL HIGH selects ELRCK input source (selector OR'd logic internally). ELRCK input electrically enhanced compared standard logic pin, support AC-coupled operation accommodating Word Clock signals ranging amplitude from 0.5Vp-p 5Vp-p. While ELRCK associated with "Async audio serial interface, intended generating clocking (Sync Tx)" audio serial interface when AK4115 Synchronous Rx/Tx mode. (for Word Clock operation, naming convention this document (Sync Tx)" misnomer since input unavailable PLL.)
3.7.1
(Sync Audio Serial Interface Format Setup Word Clock Operation This subsection explains formatting setup (Sync Tx)" audio serial interface operating Word clock (supplied ELRCK input pin) applies Synchronous Rx/Tx mode only. AK4115 supports operation synchronous Word clock source. However, data recovery unavailable since AK4115's sole becomes busy with Word clock input. DAUX available data synchronous Word clock, while DAUX also fixed data source SDTO pin. DAUX data should framed LRCK (Sync audio serial interface, with format options including Master, Slave, AES3, I2S, MSB-Justified, controlled DIF[2:0] AES3 control bits Serial mode, DIF[1:0] control pins Parallel mode with limited format options. AK4115 datasheet Tables (for Serial mode) (for Parallel mode) from page shown below listing interface format options supported their respective control settings. formats listed SDTO column apply, data merely uninterpreted pass-through DAUX data. Also shown from datasheet page register locations DIF[2:0] AES3 control bits.
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(Sync Audio Serial Interface Format Control (AK4115 Datasheet Page
Reg. Location (Sync Audio Format Cntrl. Bits (AK4115 Datasheet
3.7.2
(Sync Audio Serial Interface Clocking Setup Word Clock Operation Clock source selection (Sync Tx)" audio serial interface controlled Clock Mode CM[1:0] Source Select PSEL control bits/pins. Control settings Word clock operation only applicable Synchronous Rx/Tx Mode. Referring below AK4115 datasheet Table Clock Modes applicable Word clock operation (Sync Tx)" serial audio interface. Mode basic Word clock operation, selection Mode adds capability revert clocking source crystal clock case loss lock removed invalid Word clock input. Crystal clock operation covered Section 3.6. both Word clock operating modes, data recovery unavailable from input. AK4115 datasheet Table from page shown below specifying control options CM[1:0] control bits/pins combined with PSEL bit/pin. Also shown from datasheet pages register location CM[1:0] PSEL control bits.
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(Sync Clock Mode CM[1:0] Control Word Clock (AK4115 Datasheet Page
3.7.3
(Sync Audio Serial Interface MCLK Ratio Setup (Manual Auto "ACKS") When Word clock input PLL, master clock output provided output pins MCKO1 MCKO2, which equal frequency MCKO1 allow ease applications with converters differing MCLK ratio. MCLK ratio present MCKO1 MCKO2 either manually controlled OCKS[1:0] bits/pins, automatically -overriding OCKS[1:0] settings- Master Clock Frequency Auto Setting Mode enabled ACKS bit/pin. order Master Clock Frequency Auto Setting Mode operate necessary also related function Automatic Sample Rate Detection, which explained Section 4.1. AK4115 datasheet Tables from page shown below. Table shows MCKO1 MCKO2 MCLK ratios, well maximum available sample rate, combinations OCKS[1:0] control settings controlled manually with ACKS disabled. MCLK ratio setting combined with frequency selected MCLK source shall determine audio sample rate. Table shows MCKO1 MCKO2 MCLK ratios that automatically over sample rate range 216kHz ACKS enabled. Also shown from datasheet page register locations OCKS[1:0] ACKS control bits. (Sync Audio Serial Interface MCLK Ratio Control (AK4115 Datasheet Page
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Register Locations (Sync Audio Serial MCLK Ratio Control Bits (AK4115 Datasheet Page
Section Ancillary Features Uses AK4115 Automatic Sample Rate Detection
AK4115 features automatic sample rate detection incoming sample rate into sourced either Word clock input setting PSEL control bit/pin. Auto detect feature operates only standard sample rates (within 3%), supports them within range 22.05kHz 192kHz. This feature useful sources means determining reporting system software incoming sample rate, especially such information unavailable inaccurate within stream Channel Status bits. This feature useful Word clock source only means determining reporting system software incoming Word clock sample rate. Reporting detected sample rate only available Serial control mode FS[3:0] control bits. auto detection mechanism works comparing incoming Word clock sample rate fixed frequency reference either X'tal X'tal 4.1.1 Hardware Configuration Automatic Sample Rate Detection hardware configuration Automatic Sample Rate Detection requires that least crystals X'tal X'tal supported AK4115 XTI1/XTO1 XTI2/XTO2 pins must present. AK4115 logic control input pins XTL0 XTL1 must hardwired HIGH according AK4115 datasheet Table (shown below) determine which supported crystal frequencies present application. Selection control either X'tal X'tal handled XSEL control bit/pin. purpose selecting reference crystal Auto detection does matter whether X'tal X'tal chosen, long either them supported crystal datasheet Table AK4115 datasheet Table from page shown below listing supported crystal frequencies implementing Revision AK4115 User Manual
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Automatic Sample Rate Detection. These crystals supported frequencies also used generating crystal-based clocking standard 44.1kHz- 48kHz-base audio sample rates explained Section 3.6. Supported Crystal Frequencies XTL[1:0] Strappings (AK4115 Datasheet Page
4.1.2 Setup operation Automatic Sample Rate Detection Enabling Auto detection active source done simply settings XTL[1:0] pins supported crystal configuration other than XTL1=HIGH, XTL0=HIGH datasheet Table above. specific purpose configuring AK4115 Master Clock Frequency Auto Setting Mode, there further Auto detection setup requirements. detected sample rate frequency exclusively reported serial control mode FS[3:0] bits according AK4115 datasheet Table shown below. Also shown below from AK4115 datasheet page register location FS[3:0] bits.
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Auto Detect Sample Rate Frequencies FS[3:0] Values (AK4115 Datasheet Page
Reg. Location Word Clock Sample Rate Indication Bits (AK4115 Datasheet
Auto Detection Input Non-Audio Non-PCM Streams
AK4115 features automatic detection non-audio automatic format type detection non-PCM incoming streams. detected presence non-audio input steam (when Channel Status Bit1='1') indicated Serial control mode AUDION read-only bit. non-audio stream detected AUDION shall contain value `1'. Presence nonaudio stream Parallel control mode indicated solely INT1 interrupt state HIGH. non-PCM input stream stream encoded audio known format type, such Dolby Digital DTS. input stream recognized non-PCM, detection indicated Serial control mode non-PCM read-only bit. encoded audio format type indicated AK4115 Burst Preamble Byte Byte registers. Parallel control mode, while possible AK4115 specify which encoded audio format type detected, non-PCM state reflected INT1 (same non-audio). Shown below from AK4115 datasheet page Table Table Table lists known format types encoded audio their corresponding values Burst Preamble data. Table shows where within stream data found. Detected Stream Non-PCM Format Type Burst Preamble Data AK4115 User Manual
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Asahi Kasei
Auto Detection Input Pre-emphasis, Auto switching De-emphasis Filter
AK4115 automatically detect pre-emphasis present input stream within Channel Status bits 32kHz, 44.1kHz 48kHz sample rates. AK4115 also activate appropriate de-emphasis filter either automatically, manually, all. Parallel control mode, automatic handling pre-emphasis de-emphasis fixed where AK4115 will automatically detect pre-emphasis present activate appropriate deemphasis filter based pre-emphasis sample rate info within Channel Status data bits. Serial control mode, automatic de-emphasis enabled DEAU control disabled, manual control handled DEM[1:0] bits. presence pre-emphasis reflected read-only bit. Shown below from AK4115 datasheet Table page DEM[1:0] control bits settings manual de-emphasis control. Also shown below from AK4115 datasheet page register locations DEAU DEM[1:0] control bits, read-only bit. DEM[1:0] Manual De-emphasis Control (AK4115 Datasheet Page
Register Locations DEAU DEM[1:0] Control Bits (AK4115 Datasheet Page
Register Location Read-Only (AK4115 Datasheet Page
Auto Switch Crystal Clock UNLOCK
AK4115 automatically revert crystal based clocking event sudden loss lock either Word Clock sources. Implementation details explained Section 3.1.3 source, Section 3.7.2 Word Clock source.
Revision
AK4115 User Manual
Semiconductor
Asahi Kasei
Additional Support Information
This manual provided practical information about detailed features AK4115. further support needed, refer product datasheet: dedicated technical support schematic layout review, contact Applications: E-mail: icinfo@akm.com Telephone: 1-888-256-7364 pricing, delivery, request samples, contact your local authorized sales representative. listing representatives: http://www.akm.com/sales.asp contact sales management directly: E-mail: sales@akm.com other inquiries, please visit website: http://www.akm.com/index.asp
Revision
AK4115 User Manual
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