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Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
General Description Design Description Implementation Details Customizing Design Interface Description Utilization Details Testing Scheme Conclusion
General Description
system cost, power, performance drive development smaller semiconductor process geometries, complexity system-level power supply design increases greatly. Applications that incorporate latest generations components, which powered lower lower supply voltages, must continue interface with legacy components legacy interface voltages. only systems burdened with supplying many different power rails, they must also follow strict power sequencing requirements involved components. many cases, power regulators offer enough flexibility handle unique requirements each system, power supply designs become complex. Actel IGLOO ProASIC3 FPGAs offer alternative solution that provides system designers with completely customizable, integrated solution manage power supply sequencing. This solution made possible leveraging embedded 1,024 bits FlashROM found every reprogrammable IGLOO ProASIC3 FPGA. This document describes FPGA-based design that controls power sequencing system, multiple-supply device. FPGA stores power sequencing data internal FlashROM generates enable signals upon power-up power regulators used board, predefined time interval. Even Actel's smallest FPGAs accommodate extremely small logic. Since Actel's FPGAs live power-up power sequencing begin soon supplies available; unlike SRAM-based FPGAs, there need wait configuration complete. Design files this design example downloaded from Actel website:
Design Description
top-level block diagram design shown Figure page Data patterns that include chip select timing information stored FlashROM block inside FPGA. address generator block
April 2009 2009 Actel Corporation
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
generates address FlashROM. chip select generator block reads decodes data patterns from FlashROM enables chip selects (CS) with prescribed timing delay.
Reference PORESET_N Address Generator FlashROM DATA Chip Selector Generator FlashPRO JTAG
Figure Top-Level Block Diagram
block generates basic frequencies required design. This design contains clock frequencies that used control timing domains. first timing domain used control chip selects millisecond timing range; second, MHz, used control chip selects microsecond range. time difference between chip selects will integer multiples either Refer examples described "Customizing Design" page varying time periods between chip select outputs. required element design, this design modified work devices that contain PLL. Simply build frequency dividers using logic tiles create timing derivatives. content FlashROM used define power sequencing system. This design contains eight chip select outputs: four with microsecond resolution another four with millisecond resolution. this design, first four locations FlashROM reserved generating chip select signals microseconds remaining four locations FlashROM reserved generating chip select signals milliseconds. REFERENCE_OUT signal acts reference measuring time chip select outputs. After power-up core initializes REFERENCE_OUT immediately enabled. time delays make absolute reference REFERENCE_OUT signal rather than relative reference between chip selects. Assume following values must generated with respect REFERENCE_OUT signal: required generate after after after after after after after after content FlashROM shown Table
Table FlashROM Content Generation Address Data (decimal) Generation with Respect REFERENCE_OUT After goes High After goes High After goes High After goes High After goes High After goes High After goes High After goes High
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
Implementation Details
This design contains mainly three components (RTL): top-level, FlashROM control block: power_sequencer.vhd block: pll_4_40.vhd FlashROM block: FlashROM_cmp.vhd
level integrates lower blocks together generates chip select signals. used within FPGA generates clocks from external clock source. output frequency further divided generate clocks clock frequency generated address generator block that generates addresses reading FlashROM contents, which later stored registers. chip selector block, clock used generate chip select signals CS1, CS2, CS3, CS4. clock used generate chip select signals CS5, CS6, CS7,
Customizing Design
This section explains fine tune design parameters basic clock configuration FlashROM configuration.
Basic Clock Configuration
change basic clock configuration required. default basic clock frequency core MHz. With this frequency, minimum time difference that achieved between chip selects This output frequency further divided generate clock generate time differences between reconfigure block with different input output frequencies. Open project files this design example. Right-click pll_4_4 component left side window select Open Component. This opens Static window (Figure
Figure Configuration
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
Change values defined your requirements. Press Generate button update block with values. Press Close close Static pop-up window. more details configuring block, refer SmartGen Cores Reference Guide from Actel.
FlashROM Configuration
change FlashROM configuration required. This FlashROM configured using Actel Libero® Integrated Design Environment (IDE). Using Libero IDE, create top-level module. Cores tab, expand Memory Controllers, right click FlashROM, select Configure core. This opens FlashROM: Create Core window. FlashROM region divided into eight pages, each with bytes memory locations. Each memory location configured with different values, Figure
Figure Creating FlashROM Core
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
Press Generate generate netlist (output format should match type specified when created your project). This opens Generate Core dialog (Figure Specify name click
Figure Generating FlashROM Core
Close FlashROM: Create Core window.
Figure Configuration Final Window
Press Close. next step instantiate FlashROM component top-level module.
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
Hierarchy tab, right-click <FashROM_name>, select Open File view source code component. Instantiate FlashROM component top-level module. Assign constraint, Compile Layout. Download *.stp file into FPGA using FlashPro.
Interface Description
Table gives port descriptions.
Table Signal Descriptions Port PORESET_N REFERENCE_OUT CS1, CS2, CS3, CS4, CS5, CS6, CS7, Direction Input Input Output Output Output Description input reference clock FPGA Active reset signal from push-button present board. Active High output reference signal Active High output chip select signals with microsecond time interval Active High output chip select signals with millisecond time interval
Utilization Details
This design verified IGLOO M1AGL600V2-484FBGA device. Table lists utilization results targeted device.
Table Logic Utilization Resource Core I/Os Differential Global (chip quadrant) RAM/FIFO Static FlashROM User JTAG Used Total 13,824 Percentage 3.05% 4.68% 0.00% 27.78 100.00 0.00 0.00 100.00 0.00
Testing Scheme
Simulation Flow Best case worst case timing simulation completed this design. Testbench waveform files included simulation project folder. testbench, click Simulation icon Libero design flow window. This invokes ModelSim®, where best case worst case simulation results verified.
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
Figure shows FlashROM read cycles.
Figure FlashROM Read Cycle
Figure shows timing generation CS1, CS2, CS3, CS4.
Figure CS1, CS2, CS3, Generation (microseconds)
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
Figure gives timing generation CS5, CS6, CS7, CS8.
Figure CS5, CS6, CS7, Generation (milliseconds)
Hardware Verification This design tested verified ARM® CortexTM-M1-Enabled IGLOO FPGAs Development Kit. Output chip select signals connected general purpose outputs
Using IGLOO® ProASIC®3 FPGAs System Power Sequencer Design Example
available with Bank0, which connected connector board. oscilloscope screen shot shown Figure
Figure Oscilloscope Waveform
Only REFERENCE_OUT yellow) three chip select signals (CS1 blue, pink, green) shown. generated after from reference out. generated after generated after
Conclusion
Actel's embedded FlashROM enables true single-chip, programmable, low-cost, low-power solution system-level power sequence control. This design easily modified support various application requirements.
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
Actel leader low-power mixed-signal FPGAs offers most comprehensive portfolio system power management solutions. Power Matters. Learn more www.actel.com. Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. River Court, Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Building 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 +852 2185 6488 www.actel.com.cn
51900185-1/4.09
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