Detailed Specifications Table Features Comparison Assignment LVTT
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RTAX-S/SL RadTolerant FPGAs
Detailed Specifications
Table Features Comparison Assignment LVTTL LVCMOS2.5 LVCMOS1.8 LVCMOS1.5 (JESD8-11) Voltage-Referenced Input Buffer Differential, LVDS/LVPECL, Input Differential, LVDS/LVPECL, Output Notes: Default setting clamp diode PCI. LVTTL clamp diode enabled default. allow tolerance, LVTTL clamp diode needs enabled using settings Designer. Hot-insertion cold-sparing supported when clamp diode enabled. implemented with external resistor. input output buffer automatically deasserted Designer. input output buffer automatically asserted Designer. Clamp Diode
Insertion Cold Sparing
Tolerance
Input Buffer
Output Buffer
Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled Disabled Disabled3 Enabled4
Yes2
Tolerance
LVTTL (with clamp diode enabled) standards directly allow tolerance. example, 3.3V standard provides internal clamp diode between input VCCI that voltage input clamped below absolute maximum input voltage (Table page 2-2). example input voltage level shown 2-1: Vinput VCCI Vdiode
2-Non-Actel Part
Actel FPGA
clamp diode
Rext
clamp diode
internal clamp diode only enabled while device powered voltage input will clamped VCCI powered off. external series resistor (~100 required between input signal source limit current less than (Figure 2-1). resistor chosen meet input Tr/Tf requirement (Table 2-20 page 2-22). tolerance allowable VCCI greater than input signals greater than
Figure External Resistor Tolerance
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RTAX-S/SL RadTolerant FPGAs
Operating Conditions
Absolute Maximum Conditions
Stresses beyond those listed Table cause permanent damage device. Exposure Absolute Maximum rated conditions extended periods affect device reliability. Devices should operated outside recommended operating conditions Table 2-3.
Table Absolute Maximum Ratings Symbol VCCA VCCA VCCI VREF TSTG VCCDA2 VPUMP Notes: transient VCCA limit radiation-induced transients less than duration intended repetitive use. Core voltage spikes from single event transient will negatively affect reliability device this non-repetitive event, transient does exceed time total time that transient exceeds 1.575 does exceed duration. VCCDA must greater than equal highest VCCI voltage Table RTAX-S/SL Recommended Operating Conditions Parameter Range Junction Temperature (TJ) Ambient Temperature (TA)1 Core Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage VCCDA Supply Voltage differential used) VCCDA Supply Voltage (differential voltage-referenced used) VPUMP Supply Voltage Notes: Ambient temperature (TA) used commercial industrial grades; case temperature (TC) used military grades. Please "VCCDA Supply Voltage" page 2-11 more detail.
Parameter Junction Temperature Core Supply Voltage1 Core Supply Voltage Supply Voltage Reference Voltage Input Voltage Output Voltage Storage Temperature Supply Voltage Differential I/Os Supply Voltage External Pump
Limits +135 -0.3 -0.3 -0.3 3.75 -0.3 3.75 -0.5 -0.5 3.75 +150 -0.3 3.75 -0.3 3.75
Units
Military +125 +125 1.425 1.575 1.425 1.575 1.71 1.89 2.375 2.625 2.375 2.625
Units
Overshoot/Undershoot Limits
signals, input signal undershoot during transitions -1.0 longer than period (whichever smaller). Current during transition must exceed signals, input signal overshoot during transitions VCCI longer than
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period (whichever smaller). Current during transition must exceed Note: above specification does apply standard. RTAX-S/SL I/Os compliant standard including overshoot/undershoot specifications.
RTAX-S/SL RadTolerant FPGAs
Power-Up/Down Sequence
VCCA, VCCI, VCCDA powered powered down sequence. During power-up, RTAX-S/SL I/Os tristated until they reach state defined design.
Calculating Power Dissipation
Table RTAX-S Standby Current Device RTAX4000S Temperature Typical RTAX2000S Typical RTAX1000S Typical RTAX250S Typical Notes: IIH, IIL, values measured with inputs same level VCCI IOZ. Above values maximum. Values ICCDIFFA column refer current addition ICCDA) flowing pair through differential amplifiers only when using differential pairs voltage references pins. ICCA (mA) ICCI (mA) ICCDA (mA) ICCDIFFA (mA) IIH, IIL, (µA)1 3.13 3.13 3.13 3.13
Table RTAX-SL Standby Current Device RTAX4000SL Temperature Typical RTAX2000SL Typical RTAX1000SL Typical RTAX250SL Typical Notes: IIH, IIL, values measured with inputs same level VCCI IOZ. Above values maximum. Values ICCDIFFA column refer current addition ICCDA) flowing pair through differential amplifiers only when using differential pairs voltage references pins. ICCA (mA) ICCI (mA) ICCDA (mA) ICCDIFFA (mA) 3.13 3.13 3.13 3.13 IIH, IIL, (µA)1
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RTAX-S/SL RadTolerant FPGAs
Table Default Cload VCCI Cload (pF) Single-Ended without VREF LVCMOS (JESD8-11) LVCMOS LVCMOS LVTTL Slew LVTTL Slew LVTTL Slew LVTTL Slew LVTTL High Slew LVTTL High Slew LVTTL High Slew LVTTL High Slew PCI-X Single-Ended with VREF SSTL2-I SSTL2-II SSTL3-I SSTL3-II HSTL-I GTLP Differential LVPECL LVDS Note: *PI/O Cload Table Symbol VCCI2
VCCI
Pload (µW/MHz) 78.8 113.4 218.8 381.2 381.2 381.2 381.2 381.2 381.2 381.2 381.2 108.9 108.9
(µW/MHz) 49.5 73.4 148.0 118.7 138.6 150.8 169.2 130.3 165.9 225.1 267.5 218.5 162.9 171.2 147.8 327.2 288.4 40.9 68.5 260.6 145.8
PI/O (µW/MHZ)* 128.3 186.8 366.8 499.9 519.8 532.0 550.4 511.5 547.1 606.3 648.7 327.4 271.8 171.2 147.8 327.2 288.4 40.9 68.5 260.6 145.8
Different Components Contributing Total Power Consumption RTAX-S/SL Devices Device-Specific Value µW/MHz) Power Component Core tile HCLK power component R-cell power component HCLK signal power dissipation Core tile RCLK power component R-cell power component RCLK signal power dissipation Power dissipation switching activity R-cell Power dissipation switching activity C-cell Power component associated with input voltage Power component associated with output voltage Power component associated with read operation block Power component associated with write operation block RTAX250S/SL 85.8 10.0 25.0 30.0 RTAX1000S/SL 227.5 23.2 227.5 25.7 10.0 25.0 30.0 RTAX2000S/SL RTAX4000S/SL 378.0 31.0 378.0 34.3 10.0 25.0 30.0 25.0 30.0
Table Table page contribution.
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RTAX-S/SL RadTolerant FPGAs
Ptotal ICCA VCCA ICCI VCCI ICCDA VCCDA ICCDIFFA VCCDA Nb_da_pairs PHCLK PCLK PR-cells PC-cells Pinputs Poutputs Pmemory
Nb_da_pairs number differential pairs voltage referenced pins used PHCLK= sqrt[s]) number R-cells clocked this clock clock frequency
PCLK sqrt[s]) number R-cells clocked this clock clock frequency
PR-cells number R-cells switching each cycle clock frequency
PC-cells number C-cells switching each cycle clock frequency
Pinputs number inputs average input frequency
Poutputs (P10 Cload VCCI2) Cload VCCI output load (technology dependent) output voltage (technology dependent) number outputs average output frequency
Pmemory Nblock FRCLK Nblock FWCLK Nblock FRCLK FWCLK number RAM/FIFO blocks block read-clock frequency memory write-clock frequency memory
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RTAX-S/SL RadTolerant FPGAs
Power Estimation Example
This example employs RTAX1000S/SL shift-register design with 1,080 R-cells, C-cell, reset input, output. This design also uses single clock (HCLK) operated under room temperature. 1,080 shift register 100% R-cells toggling each clock cycle) 1,080 PHCLK sqrt[s]) 163.8 PR-cells 172.8 C-cell this design) PC-cells 0.14 reset input this Pinputs Cload VCCI= Poutputs (P10 Cload VCCI2) 23.6 RAM/FIFO this shift-register Pmemory PHCLK PCLK PR-cells PC-cells Pinputs Poutputs Pmemory 360.4 ICCA VCCA ICCI VCCI ICCDA VCCDA ICCDIFFA VCCDA Nb_da_pairs 101.1 Ptotal 360.4 101.1 461.5
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RTAX-S/SL RadTolerant FPGAs
Thermal Characteristics
temperature variable Actel Designer software refers junction temperature, ambient, case board temperature. This important distinction because dynamic static power consumption causes chip's junction temperature higher than ambient, case board temperature. 2-2, 2-3, show relationship between thermal resistance, temperature, power.
Where:
Thermal resistance from junction Thermal resistance from junction case Thermal resistance from junction board Junction Temperature Ambient Temperature Case Temperature Board Temperature Power
Table Package Thermal Characteristics Product RTAX250S/SL Package Type CQ208 CQ352 CG624 RTAX1000S/SL CQ352 CG624 RTAX2000S/SL CQ256 CQ352 CG624 CG1152 RTAX4000S/SL CQ352 CG1272 Notes: 19.9 16.8 13.7 13.3 10.8 15.8 12.3 12.3 0.25 Units
estimated still air. CQFP refers thermal resistance between junction bottom surface package. packages refers thermal resistance between junction surface package. values table simulated under conduction heat transfer only.
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RTAX-S/SL RadTolerant FPGAs
Calculation Power
Sample Case Convection sample calculation power dissipation allowed RTAX1000S/SL-CG624 still shown below. Assume that maximum junction temperature maintained 110°C ambient temperature 50°C. maximum power allowed estimated using equation below. 110°C 50°C 110°C 50°C 10.8°C/W
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Solder Columns
Figure Heat Flow when Present
Sample Case Convection sample calculation power dissipation when there environment shown below. RTAX1000S/ SL-CQ352 attached board with thermal adhesive between package body. thermal resistance paste 0.58°C/W. Since present environment, most heat will flowing through bottom package, through thermal paste, board. Neglecting heat flowing through package leads, maximum power allowed estimated shown equations below. 110°C Thermal resistance thermal paste from case board (i.e., 0.58°C/W) 70°C
(Total) 110°C 70°C 110°C 70°C 0.4°C/W 0.58°C/W 110°C 70°C (Total) 40.8
Thermal Adhesive
Figure Heat Flow Vacuum
thermal resistances, shown Table page 2-7, based simulations done with test conditions test boards configurations specified JEDEC specification JESD51.
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RTAX-S/SL RadTolerant FPGAs
Timing Characteristics
RTAX-S/SL devices manufactured CMOS process, therefore, device performance varies according temperature, voltage, process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, worst-case processing. derating factors shown Table should applied timing data contained within this datasheet.
Table Temperature Voltage Timing Derating Factors (Normalized Worst-Case Military, 125°C, VCCA Junction Temperature VCCA 1.4V 1.425V 1.5V 1.575V 1.6V Notes: user junction temperature Designer software integer value range -55°C 125°C. user core voltage Designer software value between 1.4V 1.6V. -55°C 0.74 0.72 0.69 0.66 0.65 -40°C 0.75 0.74 0.71 0.68 0.67 0.80 0.79 0.75 0.72 0.71 25°C 0.84 0.82 0.78 0.75 0.74 70°C 0.89 0.88 0.84 0.80 0.79 85°C 0.92 0.91 0.86 0.83 0.82 125°C 1.00 0.98 0.94 0.90 0.89
timing numbers listed this datasheet represent sample timing characteristics RTAX-S/SL devices. Actual timing delay values design-specific derived from Timer tool Actel's Designer software after place-androute.
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RTAX-S/SL RadTolerant FPGAs
Timing Model
Module (Nonregistered) Carry Chain Combinatorial Cell tPDC 0.70 Module (Registered) 1.83 tRD2 0.84 Buffer Module tBFPD 0.17 LVTTL 1.85 tICLKQ 0.91 tSUD 0.31 Combinatorial Cell 0.95 tBFPD 0.17 tRD1 0.66 tRD2 0.84 tRD3 1.07 Buffer Module tCCY 0.76 Module (Nonregistered) 3.51 LVTTL Output Drive Strength (24mA) High Slew Rate Combinatorial Cell 2.45 LVPECL
LVPECL
Routed Hardwired
tHCKH 3.65 FMAX (external) FMAX (internal) Module (Non- registered)
Register Cell
Combinatorial Cell tRD1 0.66 0.95
Register Cell tRCO 0.96 tSUD 0.21 Buffer Module
Module tOCLKQ 0.91 tSUD 0.31 tBPFD 0.21ns 1.26 3.3V
LVDS
tRCKH 3.71 tRCKL 3.54 2.00
tRCO 0.96 tSUD 0.21 Routed Clock LVTTL 1.85
tRCKL 3.54 FMAX (external) FMAX (internal)
tHCKL 3.48 LVTTL 1.85 tRCKL 3.55
Hardwired Routed Clock
Note: Timing data RTAX2000S/SL, speed. Figure Timing Model
Hardwired ClockExternal Setup (tDP tRD2 tSUD) tHCKH (1.85 0.84 0.31) 3.65 -0.61 tHCKH tRCO tRD1 3.65 0.96 0.66 3.51 8.78
Routed ClockExternal Setup (tDP tRD2 tSUD) tRCKH (1.85 0.84 0.31) 3.54 -0.71 tRCKH tRCO tRD1 3.71 0.96 0.66 3.51 8.84
Clock-to-Out (Pad-to-Pad)
Clock-to-Out (Pad-to-Pad)
Calculations examples calculate related parameters necessary match path represented "Timing Model".
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RTAX-S/SL RadTolerant FPGAs
Specifications
Descriptions
Supply Pins
Ground
User-Defined Supply Pins
VREF Supply Voltage
supply voltage.
VCCA Supply Voltage
Reference voltage banks. VREF pins configured user from regular pins; VREF fixed locations. There more VREF pins bank.
Supply voltage array (1.5
VCCIBx Supply Voltage
Global Pins
HCLKA/B/C/D Dedicated (Hardwired) Clocks
Supply voltage I/Os. Bank "User I/Os" page 2-12 more information. Unused VCCIBX banks tied tied other used VCCIBX banks within same device.
VCCDA Supply Voltage
Supply voltage differential amplifier JTAG probe interfaces. VCCDA either must when voltage-referenced and/or differential used. Additionally, VCCDA must greater than equal VCCI voltages (i.e. VCCDA VCCIBx).
VPUMP Supply Voltage (External Pump)
These pins clock input sequential modules. Input levels compatible with supported standards (there pair support differential standards). This input directly wired each R-cell offers clock speeds independent number R-cells being driven. HCLK pins used either HCLK inputs user I/Os. they being used either purpose, Actel recommends that they tied ground.
CLKE/F/G/H Global Clocks
low-power mode, VPUMP will used access external charge pump user desires bypass internal charge pump further reduce power). device starts using external charge pump when voltage level VPUMP reaches normal device operation, when using internal charge pump, VPUMP directly tied through resistor GND.
These pins clock inputs clock distribution networks. Input levels compatible with supported standards (there pair support differential standards). clock input buffered prior clocking R-cells. pins used either inputs user I/Os. they being used either purpose, Actel recommends that they tied known state.
When VPUMP 3.3V, shuts internal charge pump.
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RTAX-S/SL RadTolerant FPGAs
JTAG/Probe Pins
PRA/B/C/D3 Probes
Special Functions
Connection
dedicated probe pins used output data from user-defined design node within device (controlled with Silicon Explorer II). These independent diagnostic pins used allow real-time diagnostic output signal path within device. pins' probe capabilities permanently disabled protect programmed design confidentiality. Refer Table 2-102 page 2-100 recommendations status flight boards.
TCK2 Test Clock
This connected circuitry within device. These pins driven voltage left floating with effect operation device.
User I/Os4
Introduction
RTAX-S/SL family features flexible structure, supporting range mixed voltages (1.5 with bank-selectable I/Os. Table 2-10 page 2-13 contains standards supported RTAX-S/SL family. Unused I/Os configured follows: Output buffer disabled (with tristated value Hi-Z) Input buffer disabled (with tristated value Hi-Z) pull-up/pull-down programmed
Test clock input JTAG boundary-scan testing diagnostic probe (Silicon Explorer II).
TDI2 Test Data Input
Serial input JTAG boundary-scan testing diagnostic probe. equipped with internal pullup resistor with approximately resistance.
TDO2 Test Data Output
Serial output JTAG boundary-scan testing.
Test Mode Select
Actel Designer Software, unused RTAX-S/SL I/Os configured tristate with pull-up resistors. Each provides programmable slew rates, drive strengths, weak pull-up weak pull-down circuits. standards tolerant, standards, except PCI, capable insertion cold sparing. also tolerant with external resistor (see Tolerance" page 2-1). Each includes three registers: input (InReg), output (OutReg), enable register (EnReg). design, user flip-flops RTAX-S/SL FPGAs immune SEUs including following three registers located every cell buffer: InReg, OutReg, EnReg. I/Os organized into banks, there eight banks device side (Figure page 2-21). Each bank common VCCI, supply voltage I/Os.
controls IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). equipped with internal pull-up resistor with approximately resistance.
TRST Boundary Scan Reset
TRST functions active-low input asynchronously initialize reset boundary scan circuit. TRST equipped with programmable pull-up resistor with approximately resistance (i.e. with without pull-up resistor). This must hardwired ground flight.
Actel recommends that series termination resistor every probe connector (TDI, TCK, TDO, PRA, PRB, PRC, PRD). series termination used prevent data transmission corruption (i.e., reflection from FPGA probe connector) during probing reading back checksum. With internal setup have seen 70-ohm termination resistor improved signal transmission. Since series termination depends setup, Actel recommends users calculate termination resistor their setup. Below guideline calculate resistor value. resistor value should chosen that probe signal's driver impedance equals effective trace impedance. trace impedance (silicon explorer's breakout cable's resistance trace impedance), series termination, probe signal's driver impedance. termination resistor should placed close possible driver. Among probe signals, TDI, TCK, driven Silicon Explorer. A54SX16 used Silicon Explorer hence driver impedances needs calculated from RTAX-S IBIS Models (Mixed Voltage Operation). PRA, PRB, PRC, PRD, driven FPGA driver impedance also calculated from IBIS Model. Silicon explorer's breakout cable's resistance usually close ohm. external resistor pull above VCCI higher logic voltage level. desired higher logic voltage level will degraded small current, which exists when pulled above VCCI.
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RTAX-S/SL RadTolerant FPGAs
voltage-referenced I/Os, each bank also common reference-voltage bus, VREF. While VREF must have common voltage entire bank, location user-selectable. other words, user bank selected VREF. location VREF should selected according following rules: that assigned VREF control maximum eight user locations each direction total maximum) within same bank. package locations listed no-connects counted part maximum. many cases, this leads fewer than eight user package pins each direction being controlled VREF pin. Dedicated pins (GND, VCCI.) counted part user immediately adjacent either side VREF only used input. exception when there VCCI/GND pair
Input/Output Supply Voltage (VCCI)
separating VREF user location. differential amplifier supply voltage VCCDA should connected When neither voltage-referenced differential I/Os used, VCCDA connected when VCCI given bank; however, still recommended connect VCCDA user gain access various standards three ways: Instantiate specific library macros that represent desired specific standard generic macros then Actel Designer's PinEditor specify desired standards. (Please note that this applicable differential standards.) combination first methods
Please refer Features Axcelerator Family Devices application note Antifuse Macro Library Guide more details.
Table 2-10 Standards Supported RTAX-S/SL Family Standard LVTTL LVCMOS LVCMOS LVCMOS (JDEC8-11) GTL+ GTL+ HSTL Class SSTL3 Class SSTL2 Class1 LVDS LVPECL Input Reference Voltage (VREF) 0.75 1.25 Board Termination Voltage (VTT) 0.75 1.25
Note: GTL+ supported across full military temperature range.
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2-13
RTAX-S/SL RadTolerant FPGAs
Simultaneous Switching Outputs (SSO)
Actel defines SSOs outputs that transition phase within window. measurements made Actel based following worst-case conditions: switching outputs adjacent quiet output either side. unused buffers tristated they help either ground VCC. worst-case package used. When multiple output drivers switch simultaneously, they induce voltage drop chip/package power distribution. This simultaneous switching momentarily raises ground voltage within device relative system ground. This apparent shift ground potential non-zero value known simultaneous switching noise (SSN) more commonly, ground bounce. becomes more issue high count packages when using high performance devices such RTAX-S/SL family. Please refer Simultaneous Switching Noise Signal Integrity application note more information.
Table 2-12 Compatible Standards Different VCCI Values VCCI1 Notes: VCCI used both inputs outputs. VCCI tolerance ±5%. Compatible Standards LVTTL, PCI, LVPECL, GTL+ 3.3V SSTL (Class II), LVTTL, PCI, LVPECL LVCMOS 2.5V, GTL+ 2.5V, LVDS LVCMOS 1.8V LVCMOS 1.5V, HSTL Class
VREF LVDS2 1.25 0.75
LVCMOS 2.5V, SSTL (Classes II),
Table 2-13 page 2-15 summarizes different combinations voltages standards that used together same bank. Note that standards compatible Their VCCI values identical Their VREF standards identical applicable)
example, LVTTL (VREF= 1.0V) used, then other available (i.e. compatible) standards same bank LVTTL PCI, GTL+, LVPECL. Also note that when multiple standards used within bank, voltage tolerance will limited minimum tolerance standards used bank. instance, when using LVCMOS2.5 (+/-8% VCCI tolerance) LVDS (+/-5% VCCI tolerance) within bank, maximum voltage tolerance bank will +/-5% VCCI.
Banks Compatibility
Since each bank user-assigned input reference voltage (VREF) input/output supply voltage (VCCI), only I/Os with compatible standards assigned same bank. Table 2-11 shows compatible standards common VREF (for voltage-referenced standards). Similarly, Table 2-12 shows compatible standards common VCCI.
Table 2-11 Compatible Standards Different VREF Values VREF 1.25 0.75 Compatible Standards SSTL (Class SSTL (Class GTL+ (2.5 Outputs) HSTL (Class
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RTAX-S/SL RadTolerant FPGAs
Table 2-13 Legal Usage Matrix LVCMOS1.5 (JESD8-11) SSTL2 Class (2.5 SSTL3 Class (3.3
HSTL Class (1.5
LVDS (2.5 ±5%)
Standard LVTTL (VREF=1.0V) LVTTL 3V(VREF=1.5V) LVCMOS (VREF=1.0V) LVCMOS (VREF=1.25V) LVCMOS1.8 LVCMOS1.5 (VREF=1.75 (JESD8-11) (VREF=1.0V) (VREF=1.5V) GTL+ (3.3 GTL+ (2.5 HSTL Class SSTL2 Class SSTL3 Class LVDS (VREF=1.0 LVDS (VREF=1.25 LVPECL (VREF=1.0 LVPECL (VREF=1.5 Notes:
Note that GTL+2.5 supported across full military temperature range. indicates whether standards used within bank same time. Examples: LVTTL used with GTL+ (3.3 when VREF (GTL+ requirement). LVTTL used with SSTL3 Class when VREF (SSTL3 requirement). LVDS VCCI ±5%.
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LVPECL (3.3
2-15
LVCMOS
LVCMOS1.8
(3.3
(2.5
LVTTL
RTAX-S/SL RadTolerant FPGAs
Clusters
Each cluster incorporates modules, four modules modules, buffer module. turn, each module contains Input Register (InReg), Output Register (OutReg), Enable Register (EnReg) (Figure 2-5).
CLUSTER
Routed Input Track
EnReg YOUT
Routed Input Track
Routed Input Track
OutREg YOUT
Routed Input Track
Slew Rate Drive Strength
Output Track
InReg DCIN
Output Track
VREF
FPGA LOGIC CORE
Routed Input Track
EnReg YOUT
Routed Input Track
Routed Input Track
Routed Input Track
OutREg YOUT
Slew Rate Drive Strength
Output Track
InReg DCIN
Output Track
VREF
Figure Cluster Interface
Using Register
access registers, registers must instantiated netlist then connected I/Os. Usage each register (register combining) individually controlled selected/deselected using PinEditor tool Actel's Designer software. register combining also controlled device level, affecting I/Os. Please note, register option deselected default given design.5 addition, Designer software provides global option enable/disable usage registers I/Os. This option design specific. setting each individual overrides this global option. Furthermore, Global Fuse option Designer software, when checked, causes registers output logic HIGH device power-up.
Using Weak Pull-Up Pull-Down Circuits
Each RTAX-S/SL comes with weak pull-up/down circuit order macros provided combinations pull up/down LVTTL, LVCMOS (2.5 standards. These macros instantiated keeper circuit input buffer required.
Please note that register combining multi fanout nets supported.
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RTAX-S/SL RadTolerant FPGAs
Customizing
five-bit programmable input delay element associated with each I/O. value this delay bank-wide basis (Table 2-14). optional each input buffer within bank (i.e. user enable disable delay element When input buffer drives register within I/O, delay element activated default ensure zero hold-time. default setting this property Designer. When input buffer does drive register, delay element deactivated provide higher performance. Again, this overridden changing default setting this property Designer. slew-rate value LVTTL output buffer programmed either slow fast. drive strength value LVTTL output buffers programmed well. There four different drive strength values 8mA, 12mA, 16mA, 24mA that specified Designer.6
Table 2-14 Bank Wide Delay Values Setting 4.38 4.60 4.67 4.90 5.01 5.23 5.32 5.55 5.66 5.88 Delay (ns) 5.14 5.41 5.49 5.76 5.89 6.15 6.26 6.52 6.65 6.92 Std.
Note: Data RTAX2000S/SL shown table above; measured VCCA 1.425 125°C.
Using Differential Standards
Differential macros should instantiated netlist. settings these standards cannot changed inside Designer. Note that there tristated bidirectional buffers differential standards.
Table 2-14 Bank Wide Delay Values Setting 0.88 1.10 1.21 1.44 1.53 1.75 1.86 2.09 2.16 2.38 2.49 2.72 2.81 3.04 3.15 3.37 3.39 3.61 3.72 3.95 4.04 4.27 These values minimum drive strengths.
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Std. Delay (ns) 1.03 1.29 1.42 1.69 1.80 2.06 2.19 2.46 2.54 2.80 2.93 3.20 3.30 3.57 3.70 3.96 3.98 4.25 4.38 4.64 4.75
Using Voltage-Referenced Standards
Using these standards similar that singleended standards. Their settings changed Designer.
Using (Double Data Rate)
Double Data Rate mode, data present every transition clock signal. Clock data lines have identical bandwidth signal integrity requirements, making very efficient implementing very highspeed systems. implement DDR, users must following: Instantiate input buffer (with required standard). Instantiate DDR_REG macro (Figure 2-6). Connect output from Input buffer input macro. supports standards. macro SmartGen used implement DDR. width standard chosen SmartGen.
Macros Specific Standards
There different macro types standard feature that determine required VCCI VREF voltages I/O. generic buffer macros require LVTTL standard with slow slew rate mA-drive
2-17
RTAX-S/SL RadTolerant FPGAs
Figure Register
strength. LVTTL support high slew rate this should only used critical signals. Most macro symbols represent variations generic symbol types: CLKBUF: Clock Buffer HCLKBUF: Hardwired Clock Buffer INBUF: Input Buffer OUTBUF: Output Buffer TRIBUFF: Tristate Buffer BIBUF: Bidirectional Buffer Differential standard macros: LVDS LVPECL macros either have pair differential inputs (e.g. INBUF_LVDS) pair differential outputs (e.g. OUTBUF_LVPECL). Pull-up pull-down variations INBUF, BIBUF, TRIBUFF macros. These available only with LVCMOS thresholds. They used model behavior pull-up pull-down resistors available architecture. Whenever input left unconnected, output will either high rather than unknown. This allows users leave inputs unconnected without having negative effect simulation propagating unknowns. DDR_REG macro. connected standard input buffers (i.e., INBUF) implement double data rate register. Designer software will module same maps other registers module.
Other macros include following:
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RTAX-S/SL RadTolerant FPGAs
Table 2-15, Table 2-16, Table 2-17 page 2-20 list available macro names differentiated standard, type, slew rate, drive strength.
Table 2-15 Macros Single-Ended Standards Standard LVTTL VCCI Macro Names CLKBUF, HCLKBUF INBUF, OUTBUF, OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24, OUTBUF_F_8, OUTBUF_F_12, OUTBUF_F_16, OUTBUF_F_24, TRIBUFF, TRIBUFF_S_8, TRIBUFF_S_12, TRIBUFF_S_16, TRIBUFF_S_24, TRIBUFF_F_8, TRIBUFF_F_12, TRIBUFF_F_16, TRIBUFF_F_24, BIBUF, BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24, BIBUF_F_8, BIBUF_F_12, BIBUF_F_16, BIBUF_F_24, CLKBUF_PCI, HCLKBUF_PCI, INBUF_PCI, OUTBUF_PCI, TRIBUFF_PCI, BIBUF_PCI CLKBUF_LVCMOS25, HCLKBUF_LVCMOS25, INBUF_LVCMOS25, OUTBUF_LVCMOS25, TRIBUFF_LVCMOS25, BIBUF_LVCMOS25 CLKBUF_LVCMOS18, HCLKBUF_LVCMOS18, INBUF_LVCMOS18, OUTBUF_LVCMOS18, TRIBUFF_LVCMOS18, BIBUF_LVCMOS18 CLKBUF_LVCMOS15, HCLKBUF_LVCMOS15, INBUF_LVCMOS15, OUTBUF_LVCMOS15, TRIBUFF_LVCMOS15, BIBUF_LVCMOS15
3.3V
LVCMOS25
LVCMOS18
LVCMOS15 (JESD8-11)
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RTAX-S/SL RadTolerant FPGAs
Table 2-16 Macros Differential Standards Standard LVPECL LVDS VCCI Macro Names CLKBUF_LVPECL, HCLKBUF_LVPECL, INBUF_LVPECL, OUTBUF_LVPECL CLKBUF_LVDS, HCLKBUF_LVDS, INBUF_LVDS, OUTBUF_LVDS
Table 2-17 Macros Voltage-Referenced Standards Standard GTL+ GTL+ SSTL2 Class SSTL2 Class SSTL3 Class SSTL3 Class HSTL Class VCCI VREF CLKBUF_GTP33, BIBUF_GTP33 CLKBUF_GTP25, BIBUF_GTP25 HCLKBUF_GTP33, HCLKBUF_GTP25, Macro Names INBUF_GTP33, INBUF_GTP25, OUTBUF_GTP33, OUTBUF_GTP25, TRIBUFF_GTP33, TRIBUFF_GTP25,
1.25 CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, TRIBUFF_SSTL2_I, BIBUF_SSTL2_I, INBUF_SSTL2_I, OUTBUF_SSTL2_I 1.25 CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, TRIBUFF_SSTL2_II, BIBUF_SSTL2_II, INBUF_SSTL2_II, OUTBUF_SSTL2_II CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, TRIBUFF_SSTL3_I, BIBUF_SSTL3_I, INBUF_SSTL3_I, OUTBUF_SSTL3_I CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, TRIBUFF_SSTL3_II, BIBUF_SSTL3_II, INBUF_SSTL3_II, OUTBUF_SSTL3_II 0.75 CLKBUF_HSTL_I, TRIBUFF_HSTL_I BIBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I,
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RTAX-S/SL RadTolerant FPGAs
User Naming Conventions
complex flexible nature RTAX-S/SL family's user I/Os, naming scheme used show details I/O. naming scheme explains which bank belongs, well pairing polarity differential I/Os (Figure 2-7).
PUMP CCDA
VCCDA
CCDA
TRST Corner1 VCCA
BANK
VCCA
VCCA
BANK
BANK
Corner2
CCDA
VCCA VCCDA
BANK
VCCDA VCCA BANK
RTAX-S/SL
BANK
VCCA
CCDA
Corner4
BANK
BANK
Corner3
CCDA
Figure Bank Dedicated Layout
Pair number bank, starting clockwise from Positive Pin/ Negative Bank through clockwise from refers unimplemented feature ignored
Figure General Naming Schemes
VCCDA
IOxxXBxFx
CCDA
CCDA
Examples:
IO12PB1F1 positive thirteenth pair first bank (IOB NE). IO12PB1 combined with IO12NB1 form differential pair. those I/Os that employed either user special function, following nomenclature used: IOxxXBxFx/special_function_name IOxxPB1Fx/CLKx This configured clock input user
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RTAX-S/SL RadTolerant FPGAs
Standard Electrical Specifications
Table 2-18 Input Capacitance Symbol CINCLK Parameter Input Capacitance Input Capacitance Clock Conditions =1.0 =1.0 Min. Max. Units
Table 2-19 Weak Pull-Up/Pull-Down Resistances1 Minimum Maximum Weak Pull-Up/Pull-Down Resistance Values R(Pull (k)2 Configuration (VCCI) Notes: These maximum values provided informational reasons only. Minimum output buffer resistance values depend VCCI, drive strength selection, temperature, process. board design considerations detailed output buffer resistances, corresponding IBIS models located Actel website R(PULL-DOWN-MAX) (VOLspec) IOLspec R(PULL-UP-MAX) (VCCImax VOHspec) IOHspec Table 2-20 Input Rise Time Fall Time* Input Buffer LVTTL LVCMOS LVCMOS LVCMOS PCIX GTL+ HSTL SSTL2 HSTL3 LVDS LVPECL Input Rise/Fall Time (Min) Requirement Requirement Requirement Requirement Requirement Requirement Requirement Requirement Requirement Requirement Requirement Requirement Input Rise/Fall Time (Max) Min. Max. R(Pull down) (k)3 Min. Max.
Note: *Input Rise/Fall time applies inputs, including clock data. Inputs have ramp up/down linearly, monotonic way. Glitches plateau cause double-clocking. They must avoided. Output Rise/Fall time, refer IBIS Models extraction.
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RTAX-S/SL RadTolerant FPGAs
INBUF
Input High Vtrip VCCA (Rising) (Falling) Vtrip
Figure Input Buffer Delays
TRIBUF
test loads (shown below)
VCCA Vtrip
(tDLH)
VCCA VCCI/VTT Vtrip
(tDHL)
VCCA GND/VTT
tENHZ
Vtrip
Vtrip
tENHZ
tENLZ
tENLZ
Figure 2-10 Output Buffer Delays
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RTAX-S/SL RadTolerant FPGAs
Module Timing Characteristics
OutReg
EnReg InReg
(Routed Hardwired)
Figure 2-11 Timing Model
tSUD
tICLKQ tHASYN tWASYN tCLR PRESET tSUE tREASYN
tCPWHL
tCPWLH
tPRESET tWASYN
tHASYN
tREASYN
Figure 2-12 Input Register Timing Characteristics
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RTAX-S/SL RadTolerant FPGAs
tSUD
tOCLKQ tHASYN tWASYN tCLR PRESET tSUE tREASYN
tCPWHL
tCPWLH
tPRESET tWASYN
tHASYN
tREASYN
Figure 2-13 Output Register Timing Characteristics
tSUD
tOCLKQ tHASYN tWASYN tCLR PRESET tSUE tREASYN
tCPWHL
tCPWLH
tPRESET tWASYN
tHASYN
tREASYN
Figure 2-14 Output Enable Register Timing Characteristics
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RTAX-S/SL RadTolerant FPGAs
LVTTL
Low-Voltage Transistor-Transistor Logic general purpose standard (EIA/JESD) applications. uses LVTTL input buffer push-pull output buffer.
Table 2-21 Input Output Levels Min,V -0.3 Max,V Min,V Max,V Max,V 0.4* Min,V
Note: RTAX250S/SL-CQ352 devices only, limits across operating temperatures.
Loadings
Test Point Test Point tristate VCCI tplz/tpzl tphz/tpzh tpzh/tpzl tphz/tplz
Figure 2-15 Test Loads Table 2-22 Waveforms, Measuring Points, Capacitive Load Input Measuring Point Vtrip Input High Measuring Point* 1.40 VREF (typ) Cload (pF)
v5.4
RTAX-S/SL RadTolerant FPGAs
Timing Characteristics
Table 2-23 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter Description Min. Max. Std. Speed Min. Max. Units
LVTTL Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.85 15.82 16.64 15.56 1.63 1.97 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.17 18.60 19.56 18.29 1.64 1.97 1.07 1.07 0.37 0.41 0.00 0.00
LVTTL Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold 1.85 13.26 13.56 13.28 1.81 2.24 0.91 0.91 0.31 0.35 0.00 0.00 2.17 15.58 15.94 15.61 1.82 2.24 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-23 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Description Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q Min. 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Max. Std. Speed Min. 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Max. Units
LVTTL Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.85 12.04 12.46 12.05 1.95 2.52 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.17 14.16 14.65 14.17 1.96 2.53 1.07 1.07 0.37 0.41 0.00 0.00
LVTTL Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z 1.85 11.41 11.58 11.43 2.01 2.59 2.17 13.41 13.61 13.43 2.02 2.60
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RTAX-S/SL RadTolerant FPGAs
Table 2-23 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Description Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Min. Max. 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Std. Speed Min. Max. 1.07 1.07 0.37 0.41 0.00 0.00 Units
LVTTL Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.85 4.78 5.06 4.61 1.98 2.03 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.17 5.62 5.95 5.42 1.99 2.03 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-23 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter Description Min. Max. Std. Speed Min. Max. Units
LVTTL Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.85 3.87 4.08 3.34 1.98 2.31 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.17 4.55 4.79 3.93 1.99 2.31 1.07 1.07 0.37 0.41 0.00 0.00
LVTTL Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High 0.39 0.39 1.85 3.66 2.47 3.03 2.00 4.07 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 2.17 4.31 2.48 3.57 2.01 4.79 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-23 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tWASYN tREASYN tHASYN tCLR tPRESET Description Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q Min. 0.37 0.17 0.00 0.31 0.31 Max. Std. Speed Min. 0.37 0.21 0.00 0.37 0.37 Max. Units
LVTTL Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.85 3.51 2.34 1.91 2.96 4.17 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.17 4.12 2.35 1.92 3.48 4.90 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
LVCMOS
Low-Voltage Complementary Metal-Oxide Semiconductor extension LVCMOS standard (JESD8-5) used general-purpose applications. uses tolerant CMOS input buffer push-pull output buffer.
Table 2-24 Input Output Levels Min,V -0.3 Max,V Min,V Max,V Max,V Min,V
Loadings
Test Point Test Point tristate VCCI tplz/tpzl tphz/tpzh tpzh/tpzl tphz/tplz
Figure 2-16 Test Loads Table 2-25 Waveforms, Measuring Points, Capacitive Loads Input Input High Measuring Point* 1.25 VREF (typ) Cload (pF)
Note: *Measuring Point Vtrip
v5.4
RTAX-S/SL RadTolerant FPGAs
Timing Characteristics
Table 2-26 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter Description Min. Max. Std. Speed Min. Max. Units
LVCMOS25 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 2.13 21.66 22.81 20.47 4.53 4.92 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.51 25.46 26.81 24.07 4.53 4.92 1.07 1.07 0.37 0.41 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37
LVCMOS25 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold 2.13 18.09 19.05 17.40 4.53 4.92 0.91 0.91 0.31 0.35 0.00 2.51 21.26 22.39 20.46 4.53 4.92 1.07 1.07 0.37 0.41 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-26 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Description Min. Max. 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Std. Speed Min. Max. 0.00 Units
LVCMOS25 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.13 16.62 17.50 15.84 4.53 4.92 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.51 19.53 20.57 18.62 4.53 4.92 1.07 1.07 0.37 0.41 0.00 0.00
LVCMOS25 Module Drive Strength Slew Rate tENZL tENZH tENLZ Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW 2.13 15.66 16.49 15.09 4.53 2.51 18.41 19.38 17.74 4.53
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RTAX-S/SL RadTolerant FPGAs
Table 2-26 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Description Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Min. Max. 4.92 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Std. Speed Min. Max. 4.92 1.07 1.07 0.37 0.41 0.00 0.00 Units
LVCMOS25 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.13 6.32 3.36 4.26 6.72 7.72 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.51 7.44 3.37 4.27 7.90 9.08 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-26 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter Description Min. Max. Std. Speed Min. Max. Units
LVCMOS25 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.13 4.43 2.61 2.99 6.72 7.72 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.51 5.21 2.62 3.00 7.90 9.08 1.07 1.07 0.37 0.41 0.00 0.00
LVCMOS25 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High 0.39 2.13 3.91 2.46 2.64 6.72 7.72 0.91 0.91 0.31 0.35 0.00 0.00 0.39 2.51 4.59 2.47 2.64 7.90 9.08 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-26 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Description Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q Min. 0.39 0.37 0.17 0.00 0.31 0.31 Max. Std. Speed Min. 0.39 0.37 0.21 0.00 0.37 0.37 Max. Units
LVCMOS25 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.13 3.59 2.34 2.43 6.72 7.72 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.51 4.22 2.35 2.43 7.90 9.08 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
LVCMOS
Low-Voltage Complementary Metal-Oxide Semiconductor extension LVCMOS standard (JESD8-5) used general-purpose applications. uses tolerant CMOS input buffer push-pull output buffer.
Table 2-27 Input Output Levels Min,V -0.3 Max,V 0.2VCCI Min,V 0.7VCCI Max,V Max,V Min,V VCCI-0.2 -8mA
Loadings
Test Point Test Point tristate VCCI tplz/tpzl tphz/tpzh tpzh/tpzl tphz/tplz
Figure 2-17 Test Loads Table 2-28 Waveforms, Measuring Points, Capacitive Loads Input Input High Measuring Point* 0.5VCCI VREF (typ) Cload (pF)
Note: *Measuring Point Vtrip
v5.4
RTAX-S/SL RadTolerant FPGAs
Timing Characteristics
Table 2-29 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter Description Min. Max. Std. Speed Min. Max. Units
LVCMOS18 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 3.57 33.79 35.58 26.65 4.74 5.02 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 4.19 39.72 41.83 31.33 4.75 5.02 1.07 1.07 0.37 0.41 0.00 0.00
LVCMOS18 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High
v5.4
3.57 31.06 32.70 24.32 4.74 5.02 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39
4.19 36.51 38.44 28.59 4.75 5.02 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-29 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Description Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q Min. 0.39 0.37 0.17 0.00 0.31 0.31 Max. Std. Speed Min. 0.39 0.37 0.21 0.00 0.37 0.37 Max. Units
LVCMOS18 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 3.57 29.73 31.31 23.23 4.74 5.02 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 4.19 34.95 36.80 27.31 4.75 5.02 1.07 1.07 0.37 0.41 0.00 0.00
LVCMOS18 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register 3.57 6.54 3.06 4.41 7.04 7.88 0.91 4.19 7.69 3.07 4.41 8.27 9.26 1.07
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RTAX-S/SL RadTolerant FPGAs
Table 2-29 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Description Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Min. Max. 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Std. Speed Min. Max. 1.07 0.37 0.41 0.00 0.00 Units
LVCMOS18 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 3.57 5.55 2.85 3.74 7.04 7.88 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 4.19 6.52 2.86 3.75 8.27 9.26 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-29 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter Description Min. Max. Std. Speed Min. Max. Units
LVCMOS18 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 4.97 4.97 2.65 3.35 7.04 7.88 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 5.85 5.85 2.66 3.36 8.27 9.26 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
LVCMOS (JESD8-11)
Low-Voltage Complementary Metal-Oxide Semiconductor extension LVCMOS standard (JESD8-5) used general-purpose applications. uses tolerant CMOS input buffer push-pull output buffer.
Table 2-30 Input Output Levels Min,V -0.5 Max,V 0.35VCCI Min,V 0.65VCCI Max,V 1.95 Max,V Min,V VCCI-0.4 -8mA
Loadings
Test Point Test Point tristate VCCI tplz/tpzl tphz/tpzh tpzh/tpzl tphz/tplz
Figure 2-18 Test Loads Table 2-31 Waveforms, Measuring Points, Capacitive Loads Input Input High Measuring Point* 0.5VCCI VREF (typ) Cload (pF)
Note: *Measuring Point Vtrip
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RTAX-S/SL RadTolerant FPGAs
Timing Characteristics
Table 2-32 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter Description Min. Max. Std. Speed Min. Max. Units
LVCMOS15 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 3.93 60.38 63.58 44.80 5.02 5.17 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 4.62 70.98 74.74 52.67 5.02 5.17 1.07 1.07 0.37 0.41 0.00 0.00
LVCMOS15 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold 3.93 53.29 56.12 37.88 5.02 5.17 0.91 0.91 0.31 0.35 0.00 4.62 62.65 65.97 44.53 5.02 5.17 1.07 1.07 0.37 0.41 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-32 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Description Min. Max. 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Std. Speed Min. Max. 0.00 Units
LVCMOS15 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 3.93 48.90 51.50 34.84 5.02 5.17 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 4.62 57.49 60.54 40.95 5.02 5.17 1.07 1.07 0.37 0.41 0.00 0.00
LVCMOS15 Module Drive Strength Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register
v5.4
3.93 47.21 49.71 33.18 5.02 5.17
4.62 55.49 58.43 39.01 5.02 5.17 1.07
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RTAX-S/SL RadTolerant FPGAs
Table 2-32 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Description Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Min. Max. 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Std. Speed Min. Max. 1.07 0.37 0.41 0.00 0.00 Units
LVCMOS15 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 3.93 14.59 8.38 14.59 5.02 5.17 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 4.62 17.15 9.85 17.15 5.02 5.17 1.07 1.07 0.37 0.41 0.00 0.00
LVCMOS15 Module Drive Strength High Slew Rate Input buffer 3.93 4.62
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RTAX-S/SL RadTolerant FPGAs
Table 2-32 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Description Min. Max. 9.12 3.69 9.12 5.02 8.12 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 Std. Speed Min. Max. 10.73 3.70 10.73 5.02 9.54 1.07 1.07 0.37 0.41 0.00 0.00 Units
LVCMOS15 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width 0.39 0.39 0.37 3.93 7.62 3.42 7.62 5.02 8.12 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 4.62 8.96 3.42 8.96 5.02 9.54 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Table 2-32 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter tREASYN tHASYN tCLR tPRESET Description Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q Min. Max. 0.17 0.00 0.31 0.31 Std. Speed Min. Max. 0.21 0.00 0.37 0.37 Units
LVCMOS15 Module Drive Strength High Slew Rate tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 3.93 6.60 3.12 4.45 7.45 8.12 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 4.62 7.76 3.13 4.46 8.76 9.54 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
Peripheral Component Interface standard specifies support applications. uses LVTTL input buffer push-pull output buffer. input output buffers tolerant with external components. RTAX-S/SL buffer compliant with Local Specification Rev. 2.1.
Table 2-33 Input Output Levels Min,V -0.5 Max,V 0.3VCCI Min,V 0.5VCCI Max,V VCCI+0.5 Max,V Min,V
(per specification)
Loadings
Specification except tristate. Actel loading tristate figure below.
Test Point tristate
VCCI tplz/tpzl tphz/tpzh tpzl/tpzh tphz/tplz
Test point data
Figure 2-19 Test Loads Table 2-34 Waveforms, Measuring Points, Capacitive Loads Input Input High (Per Spec) Note: *Measuring Point Vtrip Measuring Point* VREF (typ) Cload (pF)
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RTAX-S/SL RadTolerant FPGAs
Timing Characteristics
Table 2-35 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter 3.3V Module Timing tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.72 2.25 1.52 1.42 2.98 4.12 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.02 2.64 1.52 1.43 3.50 4.84 1.07 1.07 0.37 0.41 0.00 0.00 Description Min. Max. Std. Speed Min. Max. Units
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RTAX-S/SL RadTolerant FPGAs
Table 2-36 Worst-Case Military Conditions VCCA VCCI 125°C Speed Parameter 3.3V PCI-X Module Timing tENZL tENZH tENLZ tENHZ tIOCLKQ tIOCLKY tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Enable delay through Output Buffer-HIGH Enable delay through Output Buffer-Z HIGH Enable delay through Output Buffer-LOW Enable delay through Output Buffer-Z Sequential clock-to-Q input register Clock-to-output output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.72 2.30 1.52 1.56 3.10 3.64 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.02 2.71 1.52 1.57 3.65 4.28 1.07 1.07 0.37 0.41 0.00 0.00 Description Min. Max. Std. Speed Min. Max. Units
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RTAX-S/SL RadTolerant FPGAs
Voltage-Referenced Standards GTL+
Gunning Transceiver Logic Plus high-speed standard (JESD8-3). requires differential amplifier input buffer open drain output buffer. VCCI should connected Note that GTL+ supported across full military temperature range.
Table 2-37 Input Output Levels Min,V Max,V VREF-0.1 Min,V VREF+0.1 Max,V Max,V 0.6* Min,V
Note: high temperature 125°C only, limits other temperatures applies.
Loadings
Test Point
Figure 2-20 Test Loads Table 2-38 Waveforms, Measuring Points, Capacitive Loads Input VREF-0.2 Note: *Measuring Point Vtrip Input High VREF+0.2 Measuring Point* VREF VREF (typ) Cload (pF)
Timing Characteristics
Table 2-39 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter GTL+ Module Timing tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.01 1.26 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.36 1.49 1.07 1.07 0.37 0.41 0.00 0.00 Description Min. Max. 'Std.' Speed Min. Max. Units
v5.4
RTAX-S/SL RadTolerant FPGAs
HSTL Class
High-Speed Transceiver Logic general-purpose high-speed standard (EIA/JESD8-6). RTAX-S/SL devices support Class This requires differential amplifier input buffer push-pull output buffer.
Table 2-40 Input Output Levels Min,V -0.3 Max,V VREF-0.1 Min,V VREF+0.1 Max,V Max,V Min,V VCC-0.4
Loadings
Test Point
Figure 2-21 Test Loads Table 2-41 Waveforms, Measuring Points, Capacitive Loads Input VREF-0.5 Note: *Measuring Point Vtrip Input High VREF+0.5 Measuring Point* VREF VREF (typ) 0.75 Cload (pF)
Timing Characteristics
Table 2-42 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Description Min. Max. 2.12 5.35 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 HSTL Class Module Timing 2.49 6.29 1.07 1.07 0.37 0.41 0.00 0.00 'Std.' Speed Min. Max. Units
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RTAX-S/SL RadTolerant FPGAs
SSTL2
Stub Series Terminated Logic general-purpose memory standard (JESD8-9). RTAX-S/SL devices support both classes this standard. This requires differential amplifier input buffer push-pull output buffer.
Class
Table 2-43 Input Output Levels Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 Max,V Max,V VREF-0.57 Min,V VREF+0.57 -7.6
Loadings
Test Point
Figure 2-22 Test Loads Table 2-44 Waveforms, Measuring Points, Capacitive Loads Input VREF-0.75 Note: *Measuring Point Vtrip Input High VREF+0.75 Measuring Point* VREF VREF (typ) 1.25 Cload (pF)
Timing Characteristics
Table 2-45 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Description Min. Max. 2.14 2.61 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 SSTL2 Class Module Timing 2.52 3.07 1.07 1.07 0.37 0.41 0.00 0.00 'Std.' Speed Min. Max. Units
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RTAX-S/SL RadTolerant FPGAs
Class
Table 2-46 Input Output Levels Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 Max,V Max,V VREF-0.8 Min,V VREF+0.8 15.2 -15.2
Loadings
Test Point
Figure 2-23 Test Loads Table 2-47 Waveforms, Measuring Points, Capacitive Loads Input VREF-0.75 Note: *Measuring Point Vtrip Input High VREF+0.75 Measuring Point* VREF VREF (typ) 1.25 Cload (pF)
Timing Characteristics
Table 2-48 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units
SSTL2 Class Module Timing tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.22 2.61 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.61 3.07 1.07 1.07 0.37 0.41 0.00 0.00
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RTAX-S/SL RadTolerant FPGAs
SSTL3
Stub Series Terminated Logic general-purpose memory standard (JESD8-8). RTAX-S/SL devices support both classes this standard. This requires differential amplifier input buffer push-pull output buffer.
Class
Table 2-49 Input Output Levels Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 Max,V Max,V VREF-0.6 Min,V VREF+0.6
Loadings
Test Point
Figure 2-24 Test Loads Table 2-50 Waveforms, Measuring Points, Capacitive Loads Input VREF-1.0 Note: *Measuring Point Vtrip Input High VREF+1.0 Measuring Point* VREF VREF (typ) 1.50 Cload (pF)
Timing Characteristics
Table 2-51 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 Description Min. Max. 2.09 2.55 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 SSTL3 Class Module Timing 2.46 2.99 1.07 1.07 0.37 0.41 0.00 0.00 'Std.' Speed Min. Max. Units
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RTAX-S/SL RadTolerant FPGAs
Class
Table 2-52 Input Output Levels Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 Max,V Max,V VREF-0.8 Min,V VREF+0.8
Loadings
Test Point
Figure 2-25 Test Loads Table 2-53 Waveforms, Measuring Points, Capacitive Loads Input VREF-1.0 Note: *Measuring Point Vtrip Input High VREF+1.0 Measuring Point* VREF VREF (typ) 1.50 Cload (pF)
Timing Characteristics
Table 2-54 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units
SSTL3 Class Module Timing tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.17 2.55 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.55 2.99 1.07 1.07 0.37 0.41 0.00 0.00
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Differential Standards Physical Implementation
Implementing differential standards requires configuration pair external pads, resulting single internal signal. facilitate construction differential pair, single cluster contains resources pair I/Os. Configuration Cluster differential pair handled Actel's Designer software when user instantiates differential macro design. Differential I/Os also used conjunction with embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg). However, there support bidirectional I/Os tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) high-speed differential standard. requires that data carried through signal lines, pins needed. also requires external resistor termination. voltage swing between these signal lines approximately
OUTBUF_LVDS
FPGA
FPGA
INBUF_LVDS
Figure 2-26 LVDS Circuit
LVDS circuit consists differential driver connected terminated receiver through constantimpedance transmission line. receiver widecommon-mode-range differential amplifier. common-mode range from differential input with swing. implement driver LVDS circuit, drivers from adjacent cells used generate differential signals (Note that driver currentmode driver). This driver provides nominal constant
Table 2-55 Input Output Levels Parameter VCCI VODIFF VOCM VICM2 VIDIFF Notes: Differential input voltage ±400
current When this current flows through termination resistor receiver side, voltage swing developed across resistor. direction current flow controlled data driver. external-resistor network (three resistors) needed reduce voltage swing about Therefore, four external resistors required, three driver receiver.
Description Supply voltage Output voltage Output high voltage Input voltage Differential output voltage Output common mode voltage Input common mode voltage Differential input voltage
Min. 2.375 1.25 1.125
Typ. 1.075 1.425
Max. 2.625 1.25 2.925
Units
1.25 1.25
1.375
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Loadings
test loads, above LVDS circuit.
Table 2-56 Waveforms, Measuring Points, Capacitive Loads Input 1.2-0.125 Note: *Measuring Point Vtrip Input High 1.2+0.125 Measuring Point* Cload (pF)
Timing Characteristics
Table 2-57 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter LVDS Module Timing tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 2.00 2.54 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.35 2.99 1.07 1.07 0.37 0.41 0.00 0.00 Description Min. Max. 'Std.' Speed Min. Max. Units
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LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) another differential standard. requires that data carried through signal lines. Like LVDS, pins needed. also requires external resistor termination. voltage swing between these signal lines approximately
FPGA
OUTBUF_LVPECL
FPGA
INBUF_LVPECL
Figure 2-27 LVPECL Circuit
LVPECL circuit similar LVDS scheme. requires four external resistors, three driver receiver. values three driver resistors different from that LVDS, since output voltage levels different. Please note that levels below standard LVPECL levels.
Table 2-58 Input Output Levels Min. Parameter VCCI Differential Input Voltage Min. 0.96 1.49 0.86 Max. 2.11 1.27 2.72 2.125 Min. 1.92 1.06 1.49 0.86 Typ. Max. 2.28 1.43 2.72 2.125 Min. 2.13 1.49 0.86 Max. Max. 2.41 1.57 2.72 2.125 Units
Loadings
test loads, above LVPECL circuit.
Table 2-59 Waveforms, Measuring Points, Capacitive Loads Input 1.6-0.3 Note: *Measuring Point Vtrip Input High 1.6+0.3 Measuring Point* Cload (pF)
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Timing Characteristics
Table 2-60 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter LVPECL Module Timing tICLKQ tOCLKQ tSUD tSUE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input buffer Output buffer Clock-to-Q input register Clock-to-Q output register enable register Data input setup Enable input setup Data input hold Enable input hold Clock pulse width High Clock pulse width High Asynchronous pulse width Asynchronous recovery time Asynchronous removal time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.39 0.39 0.37 0.17 0.00 0.31 0.31 1.83 2.45 0.91 0.91 0.31 0.35 0.00 0.00 0.39 0.39 0.37 0.21 0.00 0.37 0.37 2.15 2.88 1.07 1.07 0.37 0.41 0.00 0.00 Description Min. Max. 'Std.' Speed Min. Max. Units
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Module Specifications
C-Cell
Introduction
C-cell logic module types RTAX-S/SL architecture. combinatorial logic resource RTAX-S/SL device. RTAX-S/SL architecture implements Combinatorial Cell that extension C-cell implemented A54SX-A family. main enhancement C-cell addition carry-chain logic. C-cell used carry-chain mode construct arithmetic functions. carry-chain logic required, disabled. C-cell features following (Figure 2-28): Eight-input (data: D0-D3, select: B1). User signals routed these inputs. C-cell inputs (D0-D3, tied four routed clocks (CLKE/F/G/H). Inverter input) used drive complement signal inputs C-cell. carry input carry output. carry input signal C-cell carry output from C-cell directly north. Carry connect carry-chain logic with signal propagation time less than hardwired connection (direct connect) adjacent R-cell (Register Cell) C-cells east side SuperCluster with signal propagation time less than
This layout C-cell (and C-cell Cluster) enables implementation over 4,000 functions five bits. example, C-cells used together implement four-input function single cell delay. carry-chain configuration handled automatically user with extensive Actel macro library. Refer Actel Antifuse Macro Library Guide complete listing available RTAX-S/SL macros.
Figure 2-28 C-Cell
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Timing Model Waveforms
VCCA VCCA tPD, tPDC
Figure 2-29 C-Cell Timing Model Waveforms
tPD, tPDC VCCA tPD, tPDC
tPD, tPDC
Timing Characteristics
Table 2-61 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter C-Cell Propagation Delays tPDC tPDB tCCY input output input carry chain output (FCO) input thorough when input used Input carry chain (FCI) Input carry chain (FCI) carry chain output (FCO) 0.95 0.70 1.49 0.76 0.10 1.11 0.82 1.75 0.90 0.12 Description Min. Max. 'Std.' Speed Min. Max. Units
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Carry-Chain Logic
RTAX-S/SL dedicated carry-chain logic offers very compact solution implementing arithmetic functions without sacrificing performance. implement carry-chain logic, C-cells Cluster connected together (i.e., carry out) bits generated Carry Look-ahead scheme achieve minimum propagation delay from (i.e., carry into two-bit Cluster. two-bit carry logic shown Figure 2-30. C-cell pair driven C-cell pair immediately above Similarly,
C-cell pair, drives input C-cell pair immediately below (Figure page Figure 2-31 page 2-65). carry-chain logic selected input. When carry logic required, this signal deasserted save power. Again, this configuration handled automatically user through Actel macro library. signal propagation delay between C-cells carry-chain sequence
DCOUT
Figure 2-30 RTAX-S/SL Two-Bit Carry Logic
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C-cell
C-cell2 DCOUT
R-cell1 DCIN
FCI3
FCO2
DCOUT
DCIN
FCO4
FCI5
Clusters
FCI(2n-1)
C-cell (2n-1)
C-cell2n DCOUT
R-celln CDIN
FCO2n
Note: carry-chain sequence either C-cell. Figure 2-31 Carry-Chain Sequencing C-Cells
Timing Characteristics
Refer C-cell timing characteristics Table 2-61 page 2-63 more information carry-chain timing.
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R-Cell
Introduction
R-cell, sequential logic resource RTAX-S/SL devices, second logic module type RTAX-S/SL family architecture. RTAX-S/SL R-cell enhanced version A54SX-A R-cell. includes additional clock inputs eight global resources RTAX-S/SL architecture well global presets clears (Figure 232). main features R-cell include following: Direct connection adjacent logic module through hardwired connection DCIN. DCIN driven DCOUT adjacent C-cell Direct-Connect routing resource, providing connection with less than routing delay. R-cell used standalone flip-flop. driven C-cell modules through regular routing structure (using routable data input). This gives option using R-cell MUXed flip-flop well. Provision data enable-input (S0). Independent active asynchronous clear (CLR). Independent active asynchronous preset (PSET). both PSET low, higher priority. Clock driven following (CKP selects clock polarity): four high performance hardwired fast clocks (HCLKs) four routed clocks (CLKs) User signals
Global power-on clear (GCLR) preset (GPSET), which drive each flip-flop chip-wide basis. When Global Fuse option Designer software unchecked default), GCLR GPSET device power-up. When option checked, GCLR GPSET= Both pins pulled HIGH when device user mode.
PSET, driven routed clocks CLKE/F/G/H user signals. driven user signals.
with C-cell, configuration R-cell perform various functions handled automatically user through Actel's extensive macro library (please Actel Macro Library Guide complete listing available RTAX-S/SL macros).
(user signals) DCIN HCLKA/B/C/D CLKE/F/G/H Internal Logic Enhanced D-FF
GPRE
GCLR
Figure 2-32 R-Cell
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Hardened Flip-Flop (DFF)
order meet stringent requirements LETTH greater than MeV-cm2/mg, internal design R-cell modified without changing functionality cell. Figure 2-33 illustrates simplified representation flip-flop SuperCluster implemented RTAX-S/SL architecture. flip-flop consists master slave latch gated opposite edges clock. Each latch constructed feeding back output input stage. potential problem space environment that either latches change state when particle with enough energy. achieve requirements, flip-flop RTAX-S/SL R-cell enhanced (Figure 2-34). Both master slave "latches" actually implemented with three latches. asynchronous self-correcting feedback paths each three latches voted with outputs other latches. three latches struck starts change state, voting with other latches prevents change from feeding back permanently latching. Care taken layout ensure that single strike could affect more than latch. Figure 2-35 page 2-68 simplified schematic test circuitry that been added test functionality components flip-flop. inputs each three latches independently controllable, voting circuitry asynchronous self-correcting feedback paths tested exhaustively. This testing performed unprogrammed array during wafer sort, final test, post-burn-in test. This test circuitry cannot used test flip-flops once device been programmed.
Figure 2-33 RTAX-S/SL R-cell Implementation Flip-Flop
Voter Gate
Figure 2-34 RTAX-S/SL R-cell Implementation Flip-Flop Using Voter Gate Logic
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Voter Gate Tst2
Tst3 Test Circuitry
Figure 2-35 RTAX-S/SL R-Cell Implementation Test Circuitry
Timing Models Waveforms
tSUD
tRCO tHASYN tWASYN tREASYN tCLR
tCPWHL
tCPWLH
tPRESET PRESET tSUE tWASYN
tHASYN
tREASYN
Figure 2-36 R-Cell Delays
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Timing Characteristics
Table 2-62 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units
R-Cell Propagation Delays tRCO tCLR tPRESET tSUD tSUE tWASYN tREASYN tHASYN tCPWHL tCPWLH Sequential Clock Asynchronous Clear Asynchronous Preset Data input setup Enable input setup Data Hold Enable Hold time Asynchronous Pulse width Asynchronous Recovery time Asynchronous Removal time Clock pulse width high Clock pulse width high 0.21 0.21 0.00 0.00 0.48 0.00 0.00 0.36 0.36 0.96 0.63 0.76 0.25 0.25 0.00 0.00 0.48 0.00 0.00 0.36 0.36 1.12 0.74 0.89
Buffer Module
Introduction
additional resource inside each SuperCluster Buffer module (Figure page 1-3). When fanout constraint applied design, synthesis tool inserts buffers needed. buffer module been added RTAX-S/SL architecture avoid logic duplication resulting from hard fanout constraints. router utilizes this logic resource save area reduce loading delays medium-to-high-fanout nets.
Timing Models Waveforms
VCCA VCCA tBFPD tBFPD
Figure 2-37 Buffer Module Timing Model
Figure 2-38 Buffer Module Waveform
Timing Characteristics
Table 2-63 Worst-Case Military Conditions VCCA VCCI 125°C '-1' Speed Parameter tBFPD Description input output Min. Max. 0.17 'Std.' Speed Min. Max. 0.20 Units
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Routing Specifications
Routing Resources
routing structure found RTAX-S/SL devices enables logic module connected other logic module while retaining high performance. There multiple paths routing resources that used route logic module another, both within SuperCluster elsewhere chip. There four primary types routing within RTAX-S/ architecture: DirectConnect, CarryConnect, FastConnect Vertical Horizontal Routing.
DirectConnect
DirectConnects provide high-speed connection between R-cell adjacent C-cell (Figure 2-39). This connection made from DCOUT C-cell DCIN R-cell configuring line R-cell. This provides connection that does require antifuse delay less than
Figure 2-39 DirectConnect CarryConnect
CarryConnect
CarryConnects used build carry chains arithmetic functions (Figure 2-39). output right C-cell two-C-cell Cluster drives input left C-cell two-C-cell Cluster immediately below This pattern continues down both sides each SuperCluster column. Similar DirectConnects, CarryConnects built without antifuse connection. This connection delay less than from two-C-cell Cluster two-C-cell Cluster immediately below (see "Carry-Chain Logic" page 2-64 more information).
then routed through single antifuse connection drive inputs logic modules either within SuperCluster SuperCluster immediately below
Vertical Horizontal Routing
Vertical Horizontal Tracks provide both local long distance routing (Figure 2-41 page 2-71). These tracks composed both short-distance, segmented routing across-chip routing tracks (segmented core tile boundaries). short-distance, segmented routing resources concatenated through antifuse connections build longer routing tracks. These short-distance routing tracks used within between SuperClusters between modules nonadjacent SuperClusters. They connected Output Tracks logic module input (R-cell, C-cell, Buffer, module).
FastConnect
high-speed routing logic signals, FastConnects used build short distance connection using single antifuse (Figure 2-40 page 2-71). FastConnects provide maximum delay outputs each logic module connect directly Output Tracks within SuperCluster. Signals Output Tracks
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across-chip horizontal vertical routing provides long-distance, routing resources. These resources interface with rest routing structures through modules (Figure 2-41 page 2-71). module used drive signals from across-chip horizontal vertical routing Output Tracks
within SuperCluster. module used drive vertical horizontal across-chip routing from either short-distance horizontal tracks from Output Tracks. module also used drive signals from vertical across-chip tracks horizontal across-chip tracks vice versa.
Figure 2-40 FastConnect Routing
Figure 2-41 Horizontal Vertical Tracks
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Timing Characteristics
Table 2-64 RTAX250S/SL (Worst-Case Military Conditions VCCA VCCI 125°C) '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Unit
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD9 tRD10 Direct connect Fast connect Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout 0.08 0.24 0.66 0.84 1.07 1.38 1.45 2.08 2.26 2.44 2.87 0.07 0.29 0.77 0.99 1.25 1.62 2.44 2.66 2.87 3.37 3.88
Table 2-65 RTAX1000S/SL (Worst-Case Military Conditions VCCA VCCI 125°C) '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Unit
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD9 tRD10 Direct connect Fast connect Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout 0.08 0.24 0.66 0.84 1.07 1.38 1.45 2.08 2.26 2.44 2.87 0.07 0.29 0.77 0.99 1.25 1.62 2.44 2.66 2.87 3.37 3.88
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Table 2-66 RTAX2000S/SL (Worst-Case Military Conditions VCCA VCCI 125°C) '-1' Speed Parameter Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD9 tRD10 Direct connect Fast connect Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout 0.08 0.24 0.66 0.84 1.07 1.38 1.45 2.08 2.26 2.44 2.87 3.30 0.07 0.29 0.77 0.99 1.25 1.62 1.70 2.44 2.66 2.87 3.37 3.88 Description Min. Max. 'Std.' Speed Min. Max. Unit
Table 2-67 RTAX4000S (Worst-Case Military Conditions VCCA VCCI 125°C) 'Std.' Speed Parameter Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD9 tRD10 Direct connect Fast connect Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout Fanout 0.07 0.29 0.77 0.99 1.25 1.62 2.44 2.66 2.87 3.37 3.88 Description Min. Max. Unit
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Global Resources
most important aspects FPGA architecture global resources clocks. RTAX-S/ family provides user with flexible easy-to-use global resources, without limitations normally found other FPGA architectures. addition, these global resources have been hardened improve performance. RTAX-S/SL architecture contains types global resources, HCLK (hardwired clock) (routed clock). Every RTAX-S/SL device provided with four HCLKs four CLKs total eight clocks, regardless device density.
Hardwired Clocks
hardwired (HCLK) low-skew network that directly drive clock inputs sequential modules (R-cells, registers embedded RAM/FIFOs) device with antifuse path. four HCLKs available everywhere chip.
Timing Characteristics
Table 2-68 RTAX250S/SL (Worst-Case Military Conditions VCCA VCCI 125°C) '-1' Speed Parameter tHCKL tHCKH Description Input High Input High Min. Max. 2.76 2.94 'Std.' Speed Min. Max. 3.24 3.46 Units
Table 2-69 RTAX250S/SL Worst-Case (VCCA 1.575 VCCI 125°C) '-1' Speed Parameter tHPWH tHPWL fHMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. 0.77 0.26 Max. 'Std.' Speed Min. 0.77 0.26 Max. Units
Note: *fHMAX 1000/(2*(MAX(tHPWH,tHPWL))) Table 2-70 RTAX1000S/SL (Worst-Case Military Conditions VCCA VCCI 125°C) '-1' Speed Parameter tHCKL tHCKH Description Input High Input High Min. Max. 3.65 3.48 'Std.' Speed Min. Max. 4.29 4.09 Units
Table 2-71 RTAX1000S/SL Worst-Case (VCCA 1.575 VCCI 125°C) '-1' Speed Parameter tHPWH tHPWL fHMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. 0.86 0.31 Max. 'Std.' Speed Min. 0.86 0.31 Max. Units
Note: *fHMAX 1000/(2*(MAX(tHPWH,tHPWL)))
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Table 2-72 RTAX2000S/SL (Worst-Case Military Conditions VCCA VCCI 125°C) '-1' Speed Parameter tHCKL tHCKH Description Input High Input High Min. Max. 3.65 3.48 'Std.' Speed Min. Max. 4.29 4.09 Units
Table 2-73 RTAX2000S/SL Worst-Case (VCCA 1.575 VCCI 125°C) '-1' Speed Parameter tHPWH tHPWL fHMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. 0.77 0.26 Max. 'Std.' Speed Min. 0.77 0.26 Max. Units
Note: *fHMAX 1000/(2*(MAX(tHPWH,tHPWL))) Table 2-74 RTAX4000S (Worst-Case Military Conditions VCCA VCCI 125°C) 'Std.' Speed Parameter tHCKL tHCKH Description Input High Input High Min. Max. 4.37 4.16 Units
Table 2-75 RTAX4000S Worst-Case (VCCA 1.575 VCCI 125°C) 'Std.' Speed Parameter tHPWH tHPWL fHMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. Max. Units
Note: *fHMAX 1000/(2*(MAX(tHPWH,tHPWL)))
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Routed Clocks
routed clock (CLK) low-skew network that drive clock inputs sequential modules device (logically equivalent HCLK), added flexibility that drive (Enable), PSET, input register (R-cells registers) well inputs C-cell device. This allows CLKs used only clocks, also other global signals high fanout nets. four CLKs available everywhere chip.
Timing Characteristics
Table 2-76 RTAX250S/SL (Worst-Case MIlitary Conditions VCCA VCCI 125°C) '-1' Speed Parameter tRCKL tRCKH tRCKSW Description Input High Input High Maximum skew Loads Maximum skew Loads Min. Max. 2.78 2.92 1.40 1.81 'Std.' Speed Min. Max. 3.26 3.43 1.65 2.13 Units
Table 2-77 RTAX250S/SL Worst-Case (VCCA 1.575 VCCI 125°C) '-1' Speed Parameter tRPWH tRPWL fRMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. 0.79 0.27 Max. 'Std.' Speed Min. 0.79 0.27 Max. Units
Note: *fRMAX 1000/(2*(MAX(tRPWH,tRPWL))) Table 2-78 RTAX1000S/SL (Worst-Case MIlitary Conditions VCCA VCCI 125°C) '-1' Speed Parameter tRCKL tRCKH tRCKSW Description Input High Input High Maximum skew Loads Maximum skew Loads Maximum skew Loads Min. Max. 3.71 3.54 1.39 1.80 1.87 'Std.' Speed Min. Max. 4.37 4.16 1.64 2.12 2.20 Units
Table 2-79 RTAX1000S/SL Worst-Case (VCCA 1.575 VCCI 125°C) '-1' Speed Parameter tRPWH tRPWL fRMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. 1.04 0.33 Max. 'Std.' Speed Min. 1.04 0.33 Max. Units
Note: *fRMAX 1000/(2*(MAX(tRPWH,tRPWL)))
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Table 2-80 RTAX2000S/SL (Worst-Case MIlitary Conditions VCCA VCCI 125°C) '-1' Speed Parameter tRCKL tRCKH tRCKSW Description Input High Input High Maximum skew Loads Maximum skew Loads Maximum skew Loads Min. Max. 3.71 3.54 1.39 1.80 2.12 'Std.' Speed Min. Max. 4.37 4.16 1.64 2.12 2.49 Units
Table 2-81 RTAX2000S/SL Worst-Case (VCCA 1.575 VCCI 125°C) '-1' Speed Parameter tRPWH tRPWL fRMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. 0.79 0.27 Max. 'Std.' Speed Min. Max. Units
Note: *fRMAX 1000/(2*(MAX(tRPWH,tRPWL))) Table 2-82 RTAX4000S (Worst-Case MIlitary Conditions VCCA VCCI 125°C) 'Std.' Speed Parameter tRCKL tRCKH tRCKSW Description Input High Input High Maximum skew Loads Maximum skew Loads Maximum skew Loads Table 2-83 RTAX4000S Worst-Case (VCCA 1.575 VCCI 125°C) 'Std.' Speed Parameter tRPWH tRPWL fRMAX1 Description Minimum Pulse width High Minimum Pulse width Maximum frequency Min. Max. Units Min. Max. 6.41 6.19 1.65 2.11 2.16 Units
Note: *fRMAX 1000/(2*(MAX(tRPWH,tRPWL)))
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Global Resource Distribution
root each global resource ClockDistBuffer (CDB). There groups four CDBs every device. group, located center north edge ring) chip, sources four HCLKs. second group, located center south edge (again ring), sources four CLKs (Figure 2-42). Regardless type global resource, HCLK CLK, each eight resources reach ClockTileDist (CTD) Cluster located center every core tile with zero skew. From ClockTileDist Cluster, four HCLKs four CLKs distributed through core tile (Figure 2-43).
Cluster
HCLKA
HCLKB
HCLKC HCLKD
CLKE
CLKF
CLKG
CLKH
Cluster
Figure 2-42 ClockDistBuffer Group
HCLK
Cluster
ClockTileDist Cluster
Cluster
Figure 2-43 Example HCLK Distributions RTAX2000S/SL
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ClockTileDist Cluster contains HCLKMux (HM) module each four HCLK trees CLKMux (CM) module each trees. HCLK branches then propagate horizontally through middle core tile HCLKColDist (HD) modules every SuperCluster column. branches propagate
vertically through center core tile CLKRowDist (RD) modules every SuperCluster row. Together, HCLK branches provide lowskew global fanout within core tile (Figure 2-44 Figure 2-45).
Figure 2-44 CTD, Module Layout
Figure 2-45 HCLK Distribution within Core Tile
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modules select between: HCLK source local signal routed generic routing resources
Global Resource Access Macros
Global resources driven three sources: external pad(s) internal net. These connections made using types macros: CLKBUF CLKINT.
This allows each core tile have eight clocks independent other core tiles device. Both HCLK segmentable, meaning that individual branches global resource used independently. Like modules, modules select between: HCLK source from module, respectively local signal routed generic routing resources
CLKBUF HCLKBUF
CLKBUF (HCLKBUF) used drive (HCLK) from external pads. These macros used either generically with specific standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.) (Figure 2-46).
Again, unused input tied ground power savings. RTAX-S/SL architecture capable supporting large number local clocks segments HCLK driving north-south segments driving east-west core tile. Actel Designer software's place-and-route takes advantage segmented clock structure found RTAX-S/SL devices turning unused clock segments. This results only better performance also lower power consumption. Future releases Designer will give user greater control over these individual clock segments.
Clock Network CLKBUF HCLKBUF
Figure 2-46 CLKBUF HCLKBUF
Package pins CLKEP CLKEN associated with CLKE; package pins HCLKAP HCLKAN associated with HCLKA, etc. Note that when CLKBUF (HCLKBUF) used with single-ended standard, must tied Ppad (HCLK) package pin. this case, (HCLK) N-pad used user signals.
CLKINT HCLKINT
CLKINT (HCLKINT) used access (HCLK) resource internally from user signals (Figure 2-47).
Logic CLKINT HCLKINT
Figure 2-47 CLKINT HCLKINT
Clock Network
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RTAX-S/SL RadTolerant FPGAs
Embedded Memory
RTAX-S/SL architecture provides extensive, highspeed memory resources user. Each 4,608-bit block contains embedded FIFO controller, allowing user configure each block either FIFO. meet needs high performance designs, memory blocks operate synchronous mode both read write operations. However, read write clocks completely independent, each operate beyond MHz. additional core logic resources required cascade address data buses when cascading different blocks. Dedicated routing runs along each column facilitate cascading. RTAX-S/SL memory block includes dedicated FIFO control logic generate internal addresses external flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read write operations occur asynchronously another, special control circuitry included prevent metastability, overflow, underflow. block diagram memory module illustrated Figure 2-48. During operation, read (RA) write (WA) addresses sourced user logic FIFO controller ignored. FIFO mode, internal addresses generated FIFO controller routed array internal MUXes. Enables with programmable polarity provided create upper address bits cascading memory blocks. When cascading memory blocks, bussed signals WEN, internally linked eliminate external routing congestion.
Table 2-84 Memory Block Options Data-Word bits) Depth 4,096 2,048 1,024 Address RA/WA[11:0] RA/WA[10:0] RA/WA[9:0] RA/WA[8:0] RA/WA[7:0] RA/WA[6:0] Data RD/WD[0] RD/WD[1:0] RD/WD[3:0] RD/WD[8:0] RD/WD[17:0] RD/WD[35:0]
[K:0] RCLK [(M-1):0] [J:0] WCLK PIPE [2:0] [2:0]
[(N-1):0]
Figure 2-48 RTAX-S/SL Memory Module
Each memory block consists 4,608 bits that organized 128x36, 256x18, 512x9, 1kx4, 2kx2, 4kx1 cascadable create larger memory sizes. This allows built-in width conversion (Table 2-84). Each block independent read write ports, which enable simultaneous read write operations. Simultaneous read write operations same address supported.
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RTAX-S/SL RadTolerant FPGAs
Clocks
RCLK WCLK have independent source polarity selection sourced global local signal. 512x9, 1kx4, 2kx2, 4kx1. allowable values shown Table 2-86. When widths one, two, four selected, ninth unused. example, when writing nine-bit values reading four-bit values, only first four bits second four bits each nine-bit value addressable read operations. ninth accessible. Conversely, when writing four-bit values reading nine-bit values, ninth read operation will undefined. Note that blocks employ little-endian byte order read write operations.
Configurations
RTAX-S/SL architecture allows read side write side RAMs organized independently, allowing conversion. example, write side 256x18 read side 512x9. Both write width read width blocks specified independently changed dynamically with (write width) (read width) pins. available configurations are: 128x36, 256x18,
Table 2-85 Signal Description Signal WCLK WA[J:0] WD[M-1:0] RCLK RA[K:0] RD[N-1:0] RW[2:0] WW[2:0] Pipe Direction Input Input Input Input Input Output Input Input Input Input Input
Description Write clock (can active either edge). Write address bus.The value dependent configuration number cascaded memory blocks. valid range from to15. Write data bus. value dependent configuration Read clock (can active either edge). Read address bus. value dependent configuration number cascaded memory blocks. valid range from Read data bus. value dependent configuration Read enable. When this signal valid active edge clock, data location will driven onto Write enable. When this signal valid active edge clock, data will written location Width read operation dataword. Width write operation dataword. Sets pipeline option off.
Table 2-86 Allowable Values RW(2:0) WW(2:0) 4kx1 2kx2 1kx4 512x9 256x18 128x36 reserved
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RTAX-S/SL RadTolerant FPGAs
Modes Operation
There read modes write mode: Read Nonpipelined (synchronous clock edge): standard read mode, data driven onto clock cycle immediately following valid. read address registered read-port active-clock edge data appears read-data after access time. Setting PIPE enables this mode. Read Pipelined (synchronous clock edges): pipelined mode incurs additional clock delay from address data, enables operation much higher frequency. read-address registered read-port active-clock edge, read data registered appears after second read clock edge. Setting PIPE enables this mode. Write (synchronous clock edge): write active-clock edge, write data written into SRAM write address when high. setup time write address, write enables, write data minimal with respect write clock. Write read transfers described with timing requirements beginning "Timing Characteristics" page 2-85.
Enhancing Performance
SRAM structures inherently susceptible upsets caused high-energy particles encountered space. High-energy particles cause SRAM cell change state, resulting loss corruption valuable data bit. allow users achieve high levels performance, Actel developed intellectual property (IP) core enhance tolerance embedded SRAM within RTAX-S/SL. This employs upset-mitigation techniques: Error Detection Correction (EDAC) background memory-refresher, scrubber
EDAC employs shortened Hamming Codes provide user with single-error correction/ double-error detection (SEC/DED) capabilities. These shortened Hamming Codes provide user with implementation that reduced number logic levels less complexity than traditional Hamming Codes. SmartGen-generated EDAC supports widths bits, with variable depth from words. memory scrubber circuitry also been embedded EDAC optional block. scrubber circuitry periodically refreshes memory background ensure that corruption contents taken place while memory use. refresh rate user. EDAC combined with embedded memory scrubber circuitry, gives RTAX-S/SL radiation performance level better than 10-10 errors/ bit-day. application note Using EDAC RadTolerant RTAX-S/SL FPGAs Axcelerator FPGAs.
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2-83
RTAX-S/SL RadTolerant FPGAs
Timing Model Waveforms
WCLK
Table 2-87 SRAM Model
RCLK
tWCKP
tWCKH
tWCKL
WCLK tWxxSU WA<11:0>, WD<35:0>, WEN<4:0> tWxxHD
Figure 2-49 Write Timing Waveforms
tRCKP
tRCKH
tRCKL
RCLK tRxxSU tRxxHD RA<11:0>, REN<4:0> tRCK2RD1 <35:0> tRCK2RD2
Figure 2-50 Read Timing Waveforms
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RTAX-S/SL RadTolerant FPGAs
Timing Characteristics
Table 2-88 Block (Worst-Case Military Conditions VCCA VCCI 125°C) Speed Parameter Write Mode tWDASU tWDAHD tWADSU tWADHD tWENSU tWENHD tWCKH tWCLKL tWCKP Read Mode tRADSU tRADHD tRENSU tRENHD tRCK2RD1 tRCK2RD2 tRCLKH tRCLKL tRCKP Read Address Setup RCLK Read Address Hold RCLK Read Enable Setup RCLK Read Enable Hold RCLK RCLK-To-OUT (Pipelined) RCLK-To-OUT (Non-Pipelined) RCLK Minimum High Pulse Width RCLK Minimum Pulse Width RCLK Minimum Period 0.77 0.93 1.70 1.08 0.00 1.08 0.00 1.77 2.90 0.77 0.93 1.70 1.27
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