This application notes describes implementation SpaceWire clock recove

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This application notes describes implementation SpaceWire clock recove

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Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
This application notes describes implementation SpaceWire clock recovery circuit Actel RTAX-S device. SpaceWire uses Data-Strobe (DS) encoding, widely used handle payload data onboard spacecraft. challenging issues when implementing SpaceWire FPGA implement SpaceWire clock recovery circuit that requires minimum timing propagation delays. This application note will demonstrate achieve minimum delay reliably RTAX-S device. application note will prove, providing detailed timing analysis, minimum timing SpaceWire clock recovery circuit achieved RTAX-S device. This application note will show minimum timing SpaceWire clock recovery circuit achieved RTAX-S device will provide detailed timing analysis. Additionally, this document will describe Actel's block methodology software flow, explaining user design import SpaceWire clock recovery circuit into main design using identical timing delay.
SpaceWire Overview
SpaceWire high-speed data link standard that intended meet needs future, high capability, remote sensing instruments space missions. SpaceWire provides unified, high-speed data-handling infrastructure connecting sensors, processing elements, mass memory units, downlink telemetry subsystems, EGSE equipment together. SpaceWire interface point-to-point cable used handle payload data on-board spacecraft. SpaceWire specification defines Physical, Electrical, Protocol layers interface. SpaceWire operates from Mbps Mbps over full-duplex, point-to-point serial link, over distance meters. SpaceWire uses Data Strobe (DS) encoding scheme that encodes transmission clock with data into Data Strobe that clock recovered simply XORing Data Strobe lines together. This coding scheme illustrated Figure Data signal follows data bitstream; i.e., high when data when data Strobe signal changes state whenever Data does change from next. encoding SpaceWire standard fully described ECSS-E-50-12A standard from European Cooperation Space Standardization.
Data
Data(D)
Strobe(S)
Figure Data-Strobe Encoding
August 2007 2007 Actel Corporation
Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
SpaceWire uses voltage differential signaling (LVDS) Data Strobe(S) signals. LVDS employs balanced signals provide very high-speed interconnection using voltage swing (350 typical). signaling levels used LVDS illustrated Figure Normally, SpaceWire link comprises pairs differential signals, pair transmitting signals direction other pair transmitting opposite direction.
Voltage Across Termination Resistor
VIN-
+250 +400 Typical -250 -400 Typical
Typical Differential)
VIN+
Receiver Input Thresholds
+100 Typical (differential) Typical VIN+ VIN-
Figure LVDS Signaling Levels
Transition Region
During implementation SpaceWire inside FPGA, designer should make sure that FPGA supports LVDS standard. Otherwise, user implement external LVDS transmitter receiver. Actel RTAX-S supports multiple standards, including LVDS. This feature allows designer implement SpaceWire other blocks with different standard same FPGA. following sections describe block diagram SpaceWire link interface explain physically extract data from signals.
SpaceWire Link Interface
SpaceWire provides means sending packets information from source node specified destination node. Figure page shows example block diagram SpaceWire encoder-decoder. transmitter responsible encoding N-Chars receives from host system data transmitting using encoding technique. transmitter will operate desired data rate. transmit clock responsible generating variable data signaling clock signals used transmitter. receiver responsible decoding signals (Data Strobe) produce sequence N-Chars that passed host system. clock recovered simply XORing received Data (Din) Strobe (Sin) signals together. Clock Recovery blocks generates receiver clock provides clock signals used receiver.
Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
CLOCK
CLOCK
TICK_IN TIME_IN CONTROL-FLAGS_IN TX_WRITE
DOUT SOUT
TRANSMITTER
TX_DATA/CONTROL-FLAG READY RESET
Enable Send_NULLs Send FCTs Send N-Chars Send Time-Codes gotFCT Time-Code gotN-Char gotNULL gotBit CreditError Rx_Err Enable_Rx
After After
TIMER
STATE MACHINE
CLOCK RESET LINK START LINK DISABLE AUTOSTART
RESET
BUFFER_READY DATA/CONTROL-FLAG
RECEIVER
BUFFER WRITE
CONTROL-FLAGS_OUT TIME_OUT
CLOCK RECOVERY
TICK_OUT
Figure SpaceWire Link Interface Block Diagram
This application note does cover full implementation SpaceWire encoder-decoder block Actel FPGAs. Full implementation SpaceWire interface (the GRSPW core) available from Gaisler Research, part Actel's CompanionCore program. Actel's CompanionCore program offers wide selection synthesizable cores that licensed, supported, maintained directly partners. GRSPW core implements SpaceWire codec with RMAP support AMBA host interface. GRSPW SpaceWire Codec Core user's manual more details.
SpaceWire Receiver blocks
SpaceWire clock recovery circuitry implemented using logic, mentioned earlier "SpaceWire Overview" section page Figure page shows SpaceWire clock recovery blocks. Data Strobe travel gate through LVDS input pairs, which generates clock. Note that user does need LVDS I/Os shown Figure page This also implemented with external LVDS drivers coming into regular inputs RTAX-S device. This mainly useful board-to-board connection where people will want isolate RTAX-S part avoid damaging RTAX-S inputs. RTAX-S device still decoding chip. output from XOR-gate then connected clock network. specific type clock network depends technology used. RTAX-S device either HCLK RCLK network. This clock used sample Data signal generate N-Chars. full implementation SpaceWire encoder-decoder there extra additional logic, this implementation XOR-gate only logic that belongs clock recovery block.
Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
Figure SpaceWire Clock Recovery Circuit
avoid race conditions between data path from DATA_P DATA_N inputs inputs flip-flops should shorter than clock path from DATA_P DATA_N inputs clock inputs same flip-flops. This verified running post-layout simulation with appropriate testbench. However, tough create testbench that covers scenarios. easiest check this static timing analysis design.
Period
DATA STROBE
delay delay delay delay
FF_R:D
delay
delay delay
delay
delay
delay
delay
delay
FF_R:CLK
delay delay delay delay
FF_F:D
delay delay delay delay delay delay delay
delay
FF_F:CLK
Figure Timing Waveform SpaceWire Clock Recovery Circuit
Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
ensure proper operation SpaceWire clock recovery circuit, there three timing verifications that must met: setup check ensure that data event arrives before clock edge generated with this same data event Longest (DATA FF:D) Shortest(DATA FF:CK) Setup (FF)
hold check ensure that Strobe event generating clock edge that captures wrong data: external DATA skewed (D_Skew), Bit_Period D_Skew Shortest (DATA FF:D) Longest (STROBE FF:CK) Hold (FF)
external Strobe skewed (S_Skew), Bit_Period S_Skew Shortest (DATA FF:D) Longest (STROBE FF:CK) Hold (FF)
minimum pulse width clock DS_CLK: external Data skewed (D_Skew), Bit_Period D_Skew Longest (DATA FF:CK) Shortest (STROBE FF:CK) Setup (FF) Hold (FF)
external Strobe skewed(S_Skew), Bit_Period S_Skew Longest (STROBE FF:CK) Shortest(DATA FF:CK) Setup (FF) Hold (FF)
These inequalities must adapted different edge combinations. Note that FF_R rising edge flip-flop FF_R falling edge flip-flop. result, delay data path FF_R when clock falling needed verify timing calculation. opposite scenario holds FF_F. example, inequality must following combinations edges FF_R flip-flop: DATA(Rise) FF:D(Rise) with DATA(Rise) FF:CK(Rise) DATA(Fall) FF:D(Fall) with DATA(Fall) FF:CK(Rise) This understood clearly examining Figure page
SpaceWire Receiver Reliable Timing Analysis
Reliable minimum timing propagation delays FPGA needed support timing demands SpaceWire core implementation. Without this reliable timing possible ensure that delay path shorter than other. Since delay through DATA paths need shorter, user needs assured that minimum delay information available RTAX-S reliable. addition, required prove that timing available static timing analysis tool correct over full temperature voltage range, full life span device, after experiencing radiation total dose effects, process variations, etc. SmartTime gate-level static timing analysis tool RTAX-S family. With SmartTime, users perform complete timing analysis their design ensure that timing constraints that design operates desired speed with right amount margin across operating conditions. safe that minimum timing maximum timing delay information supported RTAX-S SmartTime very reliable. With SmartTime user analyze required delay SpaceWire clock recovery circuit validate timing needs SpaceWire implementation. next sections introduce design example implementing clock recovery circuit, place-and-route tips implementing design, static timing analysis.
Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
Design Example
This section provides design example extract data from signal using clock recovery circuit. design example created using Actel Libero® Integrated Design Environment (IDE). Libero Actel's comprehensive FPGA design development software combines latest design creation Designer physical implementation tools from Actel. also includes best-in-class synthesis verification tools from leading vendors. Using default options settings, user should able follow design example meet timing requirements required SpaceWire implementation. Additionally, user achieve better timing using timing-driven layout with proper constraint; required, manually place macro. design example shown this application note uses data extraction scheme with selectable interface ports test interface. This used NASA design frontend with SpaceWire from NASA. Figure shows simplified block diagram this design example. Based operating mode, only logic gates will functional. example, when disabled (the output AND2 gates '0'), clock generated mode (PDATARX PSTROBERX inputs). first sets flip-flops capture Data quickly possible. second sets flip-flops synchronize data. extracted clock connected routed clock network. Alternatively, hardwired clock network connected macros positioned side die. addition, Test mode critical this implementation, timing analysis will shown this mode. design example available download from Actel website
Figure SpaceWire Receiver Design
Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
Design Implementation Timing Analysis
Designer place-and-route tool part Actel Libero IDE. Designer supports timing-driven layout, which closely integrated with SmartTime tool. Timing-driven layout works well with synchronous design. RCLK HCLK tree inherently large minimum propagation delay help eliminate race condition. design example SpaceWire asynchronous nature, user need manually place some macros better performance. achieving this performance place Data, Strobe I/Os, XOR-gate, first flip-flops (U11, U10, etc.) close each other. design example uses manual placement that defined (placement constraint) file, which part download along with example design file. already mentioned that SpaceWire operates from Mbps Mbps. this design example, will clock period Figure shows timing waveform mode simplicity, only showing signal LVDS pair inputs. timing delay number found from SmartTime tool. detailed timing analysis located Excel file Actel website tabs Setup1 Setup2 show setup check; Hold shows hold check; Pulse shows minimum pulse width check clock. simplicity, have used skew both Data Strobe during calculation. analysis shows that this SpaceWire recovery circuit meets required timing with period
Figure Timing Analysis Mode
Implementation SpaceWire Clock Recovery Logic Actel RTAX-S Devices
Block Flow
Actel Block Flow feature within Libero that allows user reuse block design application ensures consistent performance. user lock place-and-route original block, which integrated Designer Block top-level project. example discussed this application note uses single-port SpaceWire interface. user creates SpaceWire clock recovery circuit with decoder block standalone, defined block that added other designs using Actel block flow. This section briefly describes block this scenario. Refer Actel Libero User's Guide detailed information using Actel Block flow. user must create Libero projects order instantiate Designer Block Libero IDE: create publish Designer Block, another which instantiate Designer Block. First user needs create Designer Block Libero with 8-port SpaceWire interface, shown design example: Start project RTAX-S. After your project opens, click Enable Designer Block creation check main toolbar. Create SpaceWire interface Libero IDE. through standard design flow: create schematic/RTL, synthesize, place-and-route. Check timing SpaceWire interface. Publish Designer Block. publish your Designer Block design Libero IDE, Choose Publish Designer Block from File menu. Save your design return edit your Designer Block later. When publish your Designer Block, Libero creates netlist file (*.v; *.vhd), info file Libero (*.cxf), Designer Block file (*.cdb). next step instantiate this Designer Block into level, which includes other SpaceWire blocks. user needs import Designer Block Libero importing design netlist file. file imports files that needed Designer Block. After files have been imported, user will need follow normal design flow regular Libero designs.
Conclusion
SpaceWire clock recovery circuitry implemented using logic, required that delay through data path shorter than clock path avoid race condition. clock tree inherently large minimum propagation delay will help eliminate race condition that arise. Using SmartTime timing analysis tool gives reliable timing analysis, quickly easily. Actel Block Flow allows reuse design block that already required timing. SpaceWire receiver clock recovery circuitry reliably implemented RTAX-S devices with various tools Actel Libero IDE.
Related Files
Timing Analysis
Design Example
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. River Court, Meadows Business Park Station Approach, Blackwater Camberley, Surrey GU17 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 www.jp.actel.com Actel Hong Kong Suite 2114, Pacific Place Queensway, Admiralty Hong Kong Phone +852 2185 6460 +852 2185 6488 www.actel.com.cn
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This application notes describes implementation SpaceWire clock recove

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