Radiation Performance SEU-Hardened Registers Eliminate Need Tripl

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RTAX-S/SL RadTolerant FPGAs
Radiation Performance
SEU-Hardened Registers Eliminate Need TripleModule Redundancy (TMR) Immune Single-Event Upsets (SEU) LETTH MeV-cm2/mg Rate 10-10 Errors/Bit-Day Worst-Case Geosynchronous Orbit Expected SRAM Upset Rate <10-10 Errors/Bit-Day with Error Detection Correction (EDAC) (included) with Integrated SRAM Scrubber Single-Bit Correction, Double-Bit Detection Variable-Rate Background Refreshing Total Ionizing Dose krad (Si, Functional) Single-Event Latch-Up Immunity (SEL) LETTH MeVcm2/mg TM1019 Test Data Available Single Event Transient (SET) Anomalies
Leading-Edge Performance
High-Performance Embedded FIFOs 350+ System Performance 500+ Internal Performance Mb/s LVDS Capable I/Os
Specifications
Million Equivalent System Gates Equivalent ASIC Gates 20,160 SEU-Hardened Flip-Flops I/Os kbits Embedded SRAM Manufactured Advanced 0.15 CMOS Antifuse Process Technology, Layers Metal Electrostatic Discharge (ESD) 2,000 (HBM MIL-STD-883, TM3015)
Processing Flows
B-Flow MIL-STD-883B E-Flow Actel Extended Flow EV-Flow Class Equivalent Flow Processing Consistent with MIL-PRF 38535
Features
Single-Chip, Nonvolatile Solution Core Voltage Power Flexible, Multi-Standard I/Os: Mixed Voltage Operation Bank-Selectable I/Os Banks Chip Single-Ended Standards: LVTTL, LVCMOS, JTAG Boundary Scan Testing IEEE 1149.1) Differential Standards: LVPECL LVDS Voltage-Referenced Standards: GTL+, HSTL Class SSTL2 Class SSTL3 Class Hot-Swap Compliant with Cold-Sparing Support (Except PCI) Embedded Memory with Variable Aspect Ratio Organizations: Independent, Width-Configurable Read Write Ports Programmable Embedded FIFO Control Logic Emulation Capability Deterministic, User-Controllable Timing Unique In-System Diagnostic Debug Capability
Prototyping Options
Commercial Axcelerator Devices Functional Verification RTAX-S PROTO Devices with Same Functional Timing Characteristics Flight Unit Non-Hermetic Package Priced Reprogrammable ProASIC®3 Option Functional Verification
RTAX-SL Power Option
Offers Approximately Half Standby Current Standard RTAX-S Device Worst-Case Conditions
Table RTAX-S/SL Family Product Profile Device Capacity Equivalent System Gates ASIC Gates Modules Register (R-cells) Combinatorial (C-cells) Flip-Flops (maximum) Embedded RAM/FIFO (without EDAC) Core Blocks Core Bits 1,024) Clocks (segmentable) Hardwired Routed I/Os Banks User I/Os (maximum) Registers Package CCGA/LGA CQFP RTAX250S/SL 250,000 30,000 1,408 2,816 2,816 208, RTAX1000S/SL 1,000,000 125,000 6,048 12,096 12,096 1,548 RTAX2000S/SL 2,000,000 250,000 10,752 21,504 21,504 2,052 624, 1152 256, RTAX4000S/SL 4,000,000 500,000 20,160 40,320 40,320 2,520 1272
2009 2009 Actel Corporation
Actel website latest version datasheet.
RTAX-S/SL RadTolerant FPGAs
Ordering Information
RTAX2000S/SL Application MIL-STD Class E-Flow (Actel Space-Level Flow) Class Equivalent Flow Processing Consistent with MIL-PRF 38535 Package Lead Count Package Type Ceramic Quad Flat Pack Ceramic Column Grid Array Land Grid Array Sigma Column Speed Grade Blank Standard Speed Approximately Faster than Standard (applies RTAX250S/SL, RTAX1000S/SL. RTAX2000S/SL) Approximately Faster than Standard (applies RTAX4000S/SL)
Part Number RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL
Standard Family Low-Power Option 250,000 Equivalent System Gates 1,000,000 Equivalent System Gates 2,000,000 Equivalent System Gates 4,000,000 Equivalent System Gates
Note: PROTO refers RTAX-S/SL Prototype Units. CCGA PROTO units will offered with Sigma Column.
Temperature Grade Offerings
Package CQ208 CQ256 CQ352 CG624/LG624 CG1152/LG1152 CG1272/LG1272 RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL
Note: MIL-STD-883 Class E-Flow (Actel Space-Level Flow) Actel Equivalent Flow (Class processing consistent with MIL-PRF 38535)
Speed Grade Temperature Grade Matrix
RTAX250S/SL Notes: Data applies B,E,EV flow devices. Contact your Actel representative availability. RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL
RTAX-S/SL RadTolerant FPGAs
Device Resources
Device CQ208 CQ256 CQ352 CG624/LG624 CG1152/LG1152 CG1272/LG1272 User I/Os (Including Clock Buffers) RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL
Note: CQFP Ceramic Quad Flat Pack CCGA Ceramic Column Grid Array, Land Grid Array
I/Os Package
Package CQ208 CQ256 CQ352 Device RTAX250S RTAX2000S RTAX250S RTAX1000S RTAX2000S RTAX4000S CG624 RTAX250S RTAX1000S RTAX2000S CG1152 CG1272 RTAX2000S RTAX4000S Single-Ended Differential Pair Pair Total I/Os
RTAX-S/SL RadTolerant FPGAs
General Description
RTAX-S/SL offers high performance densities four million equivalent system gates space-based applications. Based upon Actel's commercial Axcelerator family, RTAX-S/SL several system-level features such embedded SRAM (with built-in FIFO control logic), segmentable clocks, chip-wide highway routing, carry logic. Featuring SEU-hardened flip-flops that offer benefits user-implemented Triple Module Redundancy (TMR) without associated overhead, RTAX-S/SL family Actel's second generation product offering space applications. RTAX-S/SL devices manufactured using 0.15 technology facility Taiwan. These devices offer levels radiation survivability excess typical CMOS devices.
three master-slave latch pairs, each with asynchronous self-correcting feedback paths. output each latch master slave side votes with outputs other latches that side. three latches struck starts change state, voting with other latches prevents that change from feeding back permanently latching. Care also taken layout ensure that single strike could affect more than latch. Please refer RTAX-S RadTolerant FPGAs datasheet more information.
Embedded Memory with EDAC Support
embedded, variable-aspect-ratio SRAM blocks have separate read write ports that configured with different widths each port. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 4kx1 bit. addition, every SRAM block embedded FIFO control unit. control unit allows SRAM block configured synchronous FIFO without using core logic modules. FIFO width depth programmable. FIFO also features programmable ALMOST-EMPTY (AEMPTY) ALMOST-FULL (AFULL) flags addition normal EMPTY FULL flags. addition flag logic, embedded FIFO control unit also contains counters necessary generation read write address pointers well control circuitry prevent metastability erroneous operation. embedded SRAM/FIFO blocks cascaded create larger configurations. FIFO control unit implemented with SEUhardened registers. Designs requiring high tolerance should implement FIFO control unit from hardened core logic. SRAM structures inherently susceptible upsets caused high-energy particles encountered space. High-energy particles cause SRAM cell change state, resulting loss corruption valuable data bit. Actel enhanced tolerance embedded SRAM within RTAX-S/SL employing upset-mitigation techniques: Actel developed Error Detection Correction (EDAC) with RTAX-S/SL. EDAC accomplished SmartGengenerated Error Correcting Codes (ECC) which employs shortened Hamming Codes. background memory-refresher, scrubber circuitry, which been embedded into EDAC embedded scrubber circuitry periodically refreshes memory background ensure that data corruption occurs while memory use.
Device Architecture
Actel's architecture, derived from highly successful SX-A sea-of-modules architecture, been designed high performance total logic module utilization (Figure page There base logic modules: Register Cell (R-cell), containing full featured flip-flop; Combinatorial Cell (C-cell), containing four-input with control carrychain logic. C-cells single R-cell form Cluster, Clusters comprise SuperCluster. SuperClusters organized into Core Tiles, which combined generate each device (see RTAX-S/SL RadTolerant FPGAs datasheet more details). Additionally, each SuperCluster contains independent Buffer Module. Buffer Modules support automatic buffer insertion high-fanout nets place-and-route tool, providing better overall system delays while improving logic utilization. architecture fully fracturable, meaning that more logic modules SuperCluster used particular signal path, other logic modules still available other paths.
SEU-Hardened D-Type Flip-Flop Description
RTAX-S/SL uses same SEU-Hardened D-Type flipflop design that employed first generation designed-for-space product from Actel, RTSX-SU. order meet stringent requirement threshold greater than MeV-mg/cm2, internal design R-cell modified without changing functionality cell. While each SEU-hardened R-cell appears single D-Type flip-flop user, each implemented silicon using triple redundancy. Each R-cell consist
RTAX-S/SL RadTolerant FPGAs
SuperCluster
RAMC
RAM/ FIFO RAM/ FIFO
RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC
Chip Layout
RAM/ FIFO RAM/ FIFO
Core Tile
Structure
Figure RTAX-S/SL Device Architecture (RTAX1000S shown)
EDAC combined with embedded memory scrubber circuitry, gives RTAX-S/SL radiation performance level better than 10-10 errors/ bit-day.
Routing
Tying device resources together hierarchical routing structure, enabling RTAX-S/SL family's high performance utilization. lowest level between SuperClusters, there three routing structures: DirectConnects, FastConnects, CarryConnects. DirectConnects provide very high performance routing inside SuperCluster, while FastConnects provide high performance routing inside SuperCluster below SuperCluster. CarryConnect routing used between SuperClusters when building arithmetic functions. core tile routing next level. Both vertical horizontal tracks across column SuperClusters within core tile, respectively. chip level, routing highways extend across full length device, both northto-south east-to-west.
I/Os
RTAX-S/SL family FPGAs also features flexible structure, supporting range mixed voltages with bank-selectable I/O: 1.5V, 1.8V, 2.5V 3.3V. total, RTAX-S/SL FPGAs support least different standards (single-ended, differential, voltagereferenced). I/Os organized into banks, with eight banks device (two side). options 3.3V tolerant; 3.3V option tolerant with external resistor. options, except 3.3V PCI, hot-insertion capable. Each input, output, SEU-enhanced registers.
RTAX-S/SL RadTolerant FPGAs
Global Resources
Each family member three types global signals available designer: HCLK, CLK, GCLR/GPSET. There four hardwired clocks (HCLK) device that directly drive clock input each R-cell. Each four routed clocks (CLK) drive clock, clear, preset, enable R-cell input C-cell (Figure page 1-3). Both these clocks segmented, allowing significantly more than eight clock domains implemented devices. RTAX1000S/SL, RTAX2000S/SL, RTAX4000S/SL devices have HCLK segments tile RCLK segments tile. RTAX250S/SL HCLK segments tile RCLK segments tile. Global clear (GCLR) global preset (GPSET) drive clear preset inputs each R-cell well each Register chip-wide basis power-up.
Prototyping with RTAX-S PROTO Units
RTAX-S PROTO units offer prototyping solution that used final timing verification flight design. RTAX-S PROTO prototype units have same timing attributes RTAX-S/SL flight units. Prototype units offered non-hermetic ceramic packages. prototype units include "PROTO" their part number, "PROTO" marked devices indicate that they intended space flight. They also intended applications, which require quality space-flight units, such qualification space-flight hardware. RT-PROTO units offer guarantee hermeticity, MIL-STD-883B processing. minimum, users should plan using class level devices qualification activities. RT-PROTO units electrically tested manner guarantee their performance over full military temperature range. RT-PROTO units will also offered standard speed grades, enable customers validate timing attributes their space designs using actual flight silicon.
Low-Cost Prototyping Solutions
Since enhanced radiation characteristics radiationtolerant devices required during prototyping phase design, Actel developed prototyping options RTAX-S/SL. early design development functional verification, Actel offers commercial Axcelerator devices while final flight design verification hardware, Actel offers RTAX-S PROTO device that same form, fit, function flight silicon.
Prototyping with ProASIC3E Reprogrammable Units
Using Actel's ProASIC3E prototyping solution offers unique advantage reprogrammability, resulting cost savings while providing faster functional verification designs prototype stage. This methodology employs footprint compatible adaptor board EDIF netlist pinout convertor easy migration. Please application note Prototyping RTAX-S RTAX-SL Devices more details.
Prototyping with Axcelerator Units
prototyping solution using commercial Axcelerator devices consists parts: well-documented design flow that allows customer target RTAX-S/SL design equivalent commercial Axcelerator device Actel Extender circuit boards that commercial device package appropriate RTAX-S package footprint
Summary
Actel's RTAX-S/SL family FPGAs extends successful RTSX-SU family radiation-tolerant FPGAs, adding embedded RAM, FIFOs, high-speed I/Os. With support suite robust software tools, design engineers incorporate high gate counts fixed pins into RTAX-S/SL design still achieve high performance efficient device utilization SEUhardened device.
This methodology provides user with cost-effective solution while maintaining short time-to-market associated with Actel FPGAs.
RTAX-S/SL RadTolerant FPGAs
Datasheet Categories
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advanced," "Production," "Datasheet Supplement." definitions these categories follows:
Product Brief
product brief summarized version datasheet (advanced production) containing general product information. This brief gives overview specific device family information.
Advanced
This datasheet version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
Unmarked (production)
This datasheet version contains information that considered final.
Datasheet Supplement
datasheet supplement gives specific device information derivative family that differs from general family datasheet. supplement used conjunction with datasheet obtain more detailed information specifications that differ between families.
International Traffic Arms Regulations (ITAR)
product described this datasheet subject International Traffic Arms Regulations (ITAR). They require approved export license prior export from United States. export includes release product disclosure technology foreign national inside outside United States.
Actel Safety Critical, Life Support, High-Reliability Applications Policy
Actel products described this advance status datasheet have completed Actel's qualification process. Actel amend enhance products during product introduction qualification process, resulting changes device functionality performance. responsibility each customer ensure fitness Actel product (but especially product) particular purpose, including appropriateness safety-critical, lifesupport, other high-reliability applications. Consult Actel's Terms Conditions specific liability exclusions relating life-support applications. reliability report covering Actel's products available Actel website Actel also offers variety enhanced qualification acceptance screening procedures. Contact your local Actel sales office additional reliability information.
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
Actel leader low-power mixed-signal FPGAs offers most comprehensive portfolio system power management solutions. Power Matters. Learn more www.actel.com. Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. River Court, Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Building 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 +852 2185 6488 www.actel.com.cn
5172169PB-11/5.09

Radiation Performance SEU-Hardened Registers Eliminate Need Tripl

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