General Characteristics Tested Total Ionizing Dose (TID) Survivab

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General Characteristics Tested Total Ionizing Dose (TID) Survivab

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RadTolerant FPGAs
General Characteristics
Tested Total Ionizing Dose (TID) Survivability Level Single Event Latch-Up Below Minimum (Linear Energy Transfer) Threshold MeV-cm2/mg (RadTolerant) Devices Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, 256-Pin Ceramic Quad Flat Pack Offered Class E-Flow (Actel Space Level Flow) Certified Devices 100% Military Temperature Tested (-55°C +125°C) System Performance User I/Os Four Fast, Low-Skew Clock Networks
Easy Logic Integration
Nonvolatile, User Programmable Pin-Compatible Commercial Devices Available Prototyping Highly Predictable Performance with 100% Automatic Place-and-Route 100% Resource Utilization with 100% Pin-Locking Secure Programming Technology Prevents Reverse Engineering Design Theft Permanently Programmed Operation Power-Up Unique In-System Diagnostic Verification Capability with Silicon Explorer
High Density Performance
4,000 20,000 Logic Equivalent Gates 2,000 10,000 ASIC Equivalent Gates Internal Performance
Product Family Profile
Table Device Capacity System Gates Logic Gates ASIC Equivalent Gates Equivalent Gates Equivalent Package 20-Pin Equivalent Packages Logic Modules S-Modules C-Modules User I/Os (Maximum) Performance System Speed (Maximum) Packages Count) CQFP RadTolerant Family RT1020 6,000 4,000 2,000 5,000 RT1280A 24,000 16,000 8.000 20,000 1,232 RT1425A 7,500 5,000 2,500 6,250 RT1460A 18,000 12,000 6,000 15.000 RT14100A 30,000 20,000 10,000 25,000 1,377
October 2004 2004 Actel Corporation
Actel's website latest version datasheet
RadTolerant FPGAs
Ordering Information
RT1280A Application (Temperature Range) Commercial +70°C) Military (-55 +125°C) MIL-STD-883 Class Extended Flow (Space Level) Package Lead Count Package Type Ceramic Quad Flat Pack (CQFP) Speed Grade Standard Speed Approximately Faster than Standard Part Number RT1020 4,000 Gates-RadTolerant RT1280A 16,000 Gates-RadTolerant RT1425A 5,000 Gates-RadTolerant RT1460A 12,000 Gates-RadTolerant RT14100A 20,000 Gates-RadTolerant A1020B 4,000 Gates-ACT A1280A 16,000 Gates-ACT A1425A 5,000 Gates-ACT A1460A 12,000 Gates-ACT A14100A 20,000 Gates-ACT
Device Resources
FPGA Device Type RT1020/A1020B RT1280A/A1280A RT1425A/A1425A RT1460A/A1460A RT14100A/A14100A Logic Modules 1,232 1,377 Gate Array Equivalent Gates 2,000 8,000 2,500 6,000 10,000 User I/Os CQFP 84-Pin CQFP 132-Pin CQFP 172-Pin CQFP 196-Pin CQFP 256-Pin
Note: Package Definition: CQFP Ceramic Quad Flat Pack
Contact your Actel sales representative product availability.
RadTolerant FPGAs
Product Plan
Speed Grade RT1020 Device 84-Pin Ceramic Quad Flat Pack (CQFP) A1020B Device (Prototyping Use) 84-Pin Ceramic Quad Flat Pack (CQFP) RT1280A Device 172-Pin Ceramic Quad Flat Pack (CQFP) A1280A Device (Prototyping Use) 172-Pin Ceramic Quad Flat Pack (CQFP) RT1425A Device 132-Pin Ceramic Quad Flat Pack (CQFP) A1425A Device (Prototyping Use) 132-Pin Ceramic Quad Flat Pack (CQFP) RT1460A Device 196-Pin Ceramic Quad Flat Pack (CQFP) A1460A Device (Prototyping Use) 196-Pin Ceramic Quad Flat Pack (CQFP) RT14100A Device 256-Pin Ceramic Quad Flat Pack (CQFP) A14100A Device (Prototyping Use) 256-Pin Ceramic Quad Flat Pack (CQFP) Note: Contact your Actel sales representative product availability. Availability: Available, Symbol Planned Speed Grade: Approx. faster than Standard Commercial Application Military MIL-STD-883 Extended Flow
RadTolerant FPGAs
Table Contents
RadTolerant FPGAs
General Description Radiation Survivability Certification Disclaimer Development Tool Support RadTolerant Architecture Logic Modules RT1020 Logic Module Absolute Maximum Ratings Package Thermal Characteristics Power Dissipation Parameter Measurement 1-14 Sequential Timing Characteristics 1-15 RT1020, A1020B Timing Characteristics 1-17 RT1280A, A1280A Timing Characteristics 1-19 RT1425A, A1425A Timing Characteristics 1-22 RT1460A, A1460A Timing Characteristics 1-25 RT14100A, A14100A Timing Characteristics 1-28 Descriptions 1-31
Package Assignments
84-Pin CQFP 132-Pin CQFP 172-Pin CQFP 196-Pin CQFP 256-Pin CQFP 2-12
Datasheet Information
List Changes Datasheet Categories Export Administration Regulations (EAR) International Traffic Arms Regulations (ITAR)
RadTolerant FPGAs
RadTolerant FPGAs
General Description
Actel builds most reliable field programmable gate arrays (FPGAs) industry, with overall antifuse reliability ratings less than failures-in-time (FITs), corresponding useful life more than years. Actel FPGAs production-proven, with more than five million devices shipped more than trillion antifuses manufactured. Actel devices fully tested prior shipment, with outgoing defect level only (further reliability data available Actel Device Reliability Report). Additionally, programmable architecture these devices offers high performance, design flexibility, fast inexpensive prototyping-all without expense test vectors, charges, long lead times, schedule cost penalties design refinements. These devices also have fully pin- functioncompatible commercially-equivalent devices easy inexpensive prototyping. A1425A-CQ132C used RT1425A, A1460A-CQ196C used RT1460A, A14100A-CQ256C used RT14100A.
Radiation Survivability
Total dose results summarized ways. first method summarizes maximum total dose level that reached when parts fail meet device specification remain functional. Actel FPGAs, parameter that exceeds specification first standby supply current (ICC). second method summarizes maximum total dose that reached prior functional failure device. Actel devices have varying total-dose radiation survivability. ability these devices survive radiation effects both device- lot-dependent. user must evaluate determine applicability these devices specific design environmental requirements. Typical results RT1020 device ~100krads (Si) standby >100krads functional failure. RT1280A device results from 10krads (Si) standby ICC, 18krads functional failure. Typical results devices 28krads ICC, 77krads functional failure. Actel will provide total dose radiation testing along with test data each pedigreed that available sale. These reports available website, contact your local sales representative receive copy. listing available lots devices also provided. These results provided only reference customer information. radiation performance summary, Radiation Performance Actel Products Actel Website. This summary also shows single event upset (SEU) single event latch-up (SEL) testing that been performed Actel FPGAs.
Device Description
RT1020 device contains same architecture A1020, A1020A, A1020B devices. architecture, combinatorial logic module, logic structure with inputs output. logic itself comprised 4-input MUX, described Figure page 1-4. addition, since RT1020 device contains same number gates I/Os same operating voltage commercial equivalent (A1020B), inexpensive commercial grade A1020B-CQ84 device used during prototype phase, replaced RT1020 flight units. RT1280A device uses A1280A from family FPGAs. utilizes two-module architecture, consisting combinatorial modules (C-modules) sequential modules (S-modules) optimized both combinatorial sequential designs. Based Actel's patented channeled array architecture, RT1280A 8,000 ASIC-equivalent gates user I/Os. RT1280A device fully pin- function-compatible with commercially-equivalent A1280A-CQ172C device easy, inexpensive prototyping. RT1425A, RT1460A RT14100A devices A1425A, A1460A A14100A dies, respectively. These devices derived from family FPGAs, which also utilizes two-module channeled array architecture, offers faster performance than RT1280A.
RadTolerant FPGAs
Certification
Actel achieved full certification, demonstrating that quality management, procedures, processes, controls place comply with MIL-PRF-38535, performance specification used Department Defense monolithic integrated circuits. certification example Actel's commitment supplying highest quality products types high-reliability, military space applications. Many suppliers microelectronics components have implemented their primary worldwide business system. Appropriate this system only helps implementation advanced technologies, also allows quality, reliable cost-effective logistics support throughout products life cycles.
Disclaimer
radiation performance information provided information purposes only guaranteed. total dose effects lot-dependent, Actel does guarantee that future devices will continue exhibit similar radiation characteristics. addition, actual performance vary widely variety factors, including limited characteristics orbit, radiation environment, proximity satellite exterior, amount inherent shielding from other sources within satellite, actual bare variations. these reasons, Actel does guarantee level radiation survivability, solely responsibility customer determine whether device will meet requirements specific design.
Actel's Designer software place-and-route tool provides comprehensive suite backend support tools FPGA development. Designer software includes timing-driven place-and-route, world-class integrated static timing analyzer constraints editor. With Designer software, user select lock package pins while only minimally impacting results place-and-route. Additionally, back-annotation flow compatible with major simulators simulation results cross-probed with Silicon Explorer Actel's integrated verification logic analysis tool. Another tool included Designer software ACTgen macro builder, which easily creates popular commonly used logic functions implementation into your schematic design. Actel's Designer software compatible with most popular FPGA design entry verification tools from companies such Mentor Graphics, Synplicity, Synopsys, Cadence Design Systems. Designer software available both Windows UNIX operating systems.
RadTolerant Architecture
Actel architecture composed fine-grained logic modules that produce fast, efficient logic designs. devices composed logic modules, routing resources, clock networks, modules, which building blocks fast logic designs.
Logic Modules
These RadTolerant devices contain types logic modules, combinatorial (C-modules) sequential (S-modules). RT1020 A1020B devices contain only Cmodules. C-module, shown Figure 1-1, implements 1-1:
Development Tool Support
HiRel devices fully supported both Actel LiberoIntegrated Design Environment (IDE) Designer FPGA Development software. Actel Libero design management environment, seamlessly integrating design tools while guiding user through design flow, managing design files, passing necessary design data among tools. Libero allows users integrate both schematic synthesis into single flow verify entire design single environment. Libero includes Synplify® Actel from Synplicity®, ViewDraw® Actel from Mentor Graphics, ModelSim® Simulator from WaveFormer Litefrom Mentor Graphics®, SynaptiCADTM, Designer software from Actel. Refer Libero flow diagram more information.
where:
Figure C-Module Implementation
RadTolerant FPGAs
S-module, shown Figure 1-2, designed implement high-speed sequential functions within single logic module. S-module implements same combinatorial logic function C-module while adding sequential element. sequential element configured either D-type flip-flop transparent latch. increase flexibility, S-module register bypassed implements purely combinatorial logic.
Flip-flops also created using C-modules. characteristics differ between S-module flip-flop flip-flop created using C-modules. details Design Techniques RadHard Field Programmable Gate Arrays application note.
GATE
7-Input Function Plus D-Type Flip-Flop with Clear
7-Input Function Plus Latch
GATE
4-Input Function Plus Latch with Clear
8-Input Function (Same C-Module)
Figure S-Module Implementation
RadTolerant FPGAs
RT1020 Logic Module
RT1020 logic module 8-input, 1-output logic circuit chosen wide range functions implements efficient interconnect routing resources (Figure 1-3).
Actel Designer software development tools provide design library macros. macro library provides macro functions that implement configurations supported RadTolerant FPGAs.
From Array
G/CLK*
Array
G/CLK* configured Latch D-Flip-Flop (Using C-Module)
Figure Module Figure RT1020 Logic Module
Routing Structure
RadTolerant device architecture uses vertical horizontal routing tracks interconnect various logic modules. These routing tracks metal interconnects that either continuous length broken into segments. Varying segment lengths allow over circuit interconnects made with only antifuse connections. Segments joined together ends, using antifuses increase their length full length track. interconnects accomplished with maximum four antifuses.
logic module implement four basic logic functions (NAND, AND, NOR) gates two, three, four inputs. Each function have many versions, with different combinations active inputs. logic module also implement variety D-latches, exclusivity functions, AND-ORs, OR-ANDs. dedicated hardwired latches flip-flops required array, since latches flip-flops constructed from logic modules wherever needed application.
Modules
modules provide interface between device pins logic array. variety user functions, determined library macro selection, implemented module (refer Macro Library Guide more information). modules contain tristate buffer, input output latches that configured input, output, bidirectional pins (Figure 1-4). RadTolerant devices contain flexible structures that each output dedicated output enable control. module used latch input and/or output data, providing fast setup time. addition, Actel Designer software tools build D-flip-flop, using C-module, register input and/or output signals.
Horizontal Routing
Horizontal channels located between rows modules, composed several routing tracks. horizontal routing tracks within channel divided into more segments. minimum horizontal segment length width module-pair, maximum horizontal segment length full length channel. segment that spans more than one-third length considered long horizontal segment. typical channel shown Figure page 1-5. Non-dedicated horizontal routing tracks used route signal nets. Dedicated routing tracks used global clock networks, power ground tie-off tracks.
Vertical Routing
Another routing tracks runs vertically through module. There three types vertical tracks that divided into more segments: input, output, long. Each segment input track dedicated input particular module. Each segment
RadTolerant FPGAs
output track dedicated output particular module. Long segments uncommitted assigned during routing. Each output segment spans four channels (two above below), except near bottom array where edge effects occur. Long vertical tracks contain either segments. example vertical routing tracks segments shown Figure 1-5.
Segmented Horizontal Routing Tracks Logic Modules
Antifuse Structures
antifuse "normally open" structure opposed normally closed fuse structure used PROMs (programmable read-only memory) PALs (programmed array logic). antifuses implement (programmable logic device) results highly testable structures, well efficient programming algorithms. structure highly testable because there preexisting connections, enabling temporary connections made using pass transistors. These temporary connections isolate individual antifuses programmed, also isolate individual circuit structures tested. This done both before after programming. example, metal tracks tested continuity shorts between adjacent tracks, functionality logic modules verified.
Antifuses
Vertical Routing Tracks
Figure Routing Structure Table Actel MIL-STD-883 Product Flow Step Screen Internal Visual Temperature Cycling Constant Acceleration Seal Fine Gross Visual Inspection Pre-Burn-In Electrical Parameters Burn-in Test Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable Final Electrical Test Static Tests 25°C (Subgroup Table -55°C +125°C (Subgroups Table Functional Tests 25°C (Subgroup Table -55°C +125°C (Subgroups Table Switching Tests 25°C (Subgroup Table External Visual 2010, Test Condition 1010, Test Condition 2001, Test Condition Orientation Only 1014 100% 100% 2009 accordance with applicable Actel device specification 1015, Condition hours 125°C hours 150°C accordance with applicable Actel device specification accordance with applicable Actel device specification, which includes 100% 5005 5005 100% 100% 100% 100% Lots Method Class Requirement 100% 100% 100%
100% 5005 5005
5005 2009
100% 100%
Note: When Destructive Physical Analysis (DPA) performed Class devices, step coverage requirement specified Method 2018 must waived.
RadTolerant FPGAs
Table Actel Extended Flow1 Step Screen Wafer Acceptance
Method 5007 with Step Coverage Waiver 2011, Condition 2010, Condition
Requirement Lots Sample 100% 100%
Destructive In-Line Bond Pull3 Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic Pre-Burn-In Test Burn-in Test Interim (Post-Burn-In) Electrical Parameters Reverse Bias Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test Static Tests 25°C (Subgroup Table1) -55°C +125°C (Subgroups Table Functional Tests 25°C (Subgroup Table -55°C +125°C (Subgroups Table Switching Tests 25°C (Subgroup Table
1010, Condition 2001, Condition Orientation Only 2020, Condition 2012 accordance with applicable Actel device specification 1015, Condition hours 125°C minimum accordance with applicable Actel device specification 1015, Condition hours 150°C minimum accordance with applicable Actel device specification Functional Parameters 25°C accordance with Actel applicable device specification, which includes 5005 5005
100% 100% 100% 100% 100% 100% 100% 100% 100% Lots 100% 100%
100% 5005 5005 5005 1014 100%
Seal Fine Gross External Visual
100%
Notes:
2009
100%
Actel offers extended flow customers that require additional screening beyond requirements MIL-STD-883, Class Actel compliant requirements MIL-STD-883, Paragraph 1.2.1, MIL-I-38535, Appendix Actel offering this extended flow incorporating majority screening procedures outlined Method 5004 MIL-STD-883 Class exceptions Method 5004 shown notes below. Wafer acceptance performed Method 5007; however, step coverage requirement specified Method 2018 must waived. Method 5004 requires percent, non-destructive bond pull (Method 2023). Actel substitutes destructive bond pull (Method 2011), Condition sample basis only.
RadTolerant FPGAs
Absolute Maximum Ratings
Stresses beyond those listed this table cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside recommended operating conditions.
Table Free Temperature Range Symbol TSTG Notes: VCC, except during device programming VCC, except during device programming GND, except during device programming Device inputs normally high impedance draw extremely current. However, when input voltage greater than less than internal protection diode will forward-biased draw excessive current. Supply Voltage Input Voltage Output Voltage Source Sink Current Storage Temperature
Parameter
Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150
Units
Table Recommended Operating Conditions Parameter Temperature Range1 Tolerance2 Commercial Military +125 Units %VCC
Power Supply Notes:
Ambient temperature (TA) used commercial industrial; case temperature (TC) used military power supplies must recommended operating range. more information, refer Power-Up Power-Down Behavior 54SX RT54SX Devices application note. Table Electrical Specifications Commercial Symbol VOH1, VOL1, ICC(S) ICC(D) Notes: Actel devices drive receive either CMOS signal levels. assignment I/Os CMOS required. Tested output time, min. tested; information only VOUT Parameter HIGH Level Output Test Condition (CMOS) (CMOS) Level Output HIGH Level Input Level Input Input Leakage 3-State Output Leakage Capacitance
Military Min. Max. Units
Min.
Max.
3.84 0.33 -0.3 -0.3
(CMOS) Inputs Inputs GND,
Standby Supply Current Dynamic Supply Current
"Power Dissipation" page 1-8.
RadTolerant FPGAs
Package Thermal Characteristics
device junction case thermal characteristic junction ambient characteristic thermal characteristics shown with different flow rates. Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed CQFP 172-pin package military temperature follows:
Max. junction temp. (°C) Max. military temp. 150°C 125°C 1.0W 25°C/W °C/W
Table Package Thermal Characteristics Package Type Ceramic Quad Flat Pack Count Still ft./min. Units °C/W °C/W °C/W °C/W °C/W
Power Dissipation
General Power Equation
[ICCstandby ICCactive] (VCC VOH)
Static Power Component
Actel FPGAs have small static power components that result power dissipation lower than that PALs PLDs. integrating multiple PALs PLDs into FPGA, even greater reduction board-level power dissipation achieved. power standby current typically small component overall power. Standby power calculated below commercial, worst-case conditions.
5.25 Power 10.5
where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH.
static power dissipated loads depends number outputs driving HIGH load current. Again, this value typically small. instance, 32-bit sinking 0.33 will generate with outputs driving LOW, with outputs driving HIGH.
Accurate values difficult determine because they depend family type, design details, system I/O. power divided into components: static active.
RadTolerant FPGAs
Active Power Component
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency-dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation.
Equivalent Capacitance
power dissipated CMOS circuit expressed 1-4: Power (uW) VCC2
where:
Equivalent capacitance Power supply volts Switching frequency
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements made over range frequencies fixed value VCC. Equivalent capacitance frequency-independent, results used over wide range operating conditions. Equivalent capacitance values shown Table 1-7.
Table Values Actel FPGAs RT1020, A1020B Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) Dedicated Clock Buffer Loads (CEQCD) Clock Buffer Loads (CEQCI) 22.1 32.1 RT1280A, A1280A 12.9 23.8 RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A 10.4
RadTolerant FPGAs
calculate active power dissipated from complete design, switching frequency each part logic must known. shows piece-wise linear summation over components. Since RT1280A A1280A have routed array clocks, dedicated_Clk IO_Clk terms apply. other devices terms apply. Power VCC2 CEQM* fm)modules CEQI* fn)inputs (CEQO+ fp)outputs CEQCR fq1)routed_Clk1 *fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2 CEQCD fs1)dedicated_Clk CEQCI fs2)IO_Clk]
where:
Number logic modules switching Number input buffers switching Number output buffers switching Number clock loads first routed array clock Number clock loads second routed array clock (not applicable RT1020 A1020B) Fixed capacitance first routed array clock Fixed capacitance second routed array clock (not applicable RT1020 A1020B) Fixed number clock loads dedicated array clock (not applicable RT1020, A1020B, RT1280A, A1280A) Fixed number clock loads dedicated clock (not applicable RT1020, A1020B, RT1280A, A1280A) Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers Equivalent capacitance routed array clock Equivalent capacitance dedicated array clock Equivalent capacitance dedicated clock Output lead capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate (not applicable RT1020 A1020B) Average dedicated array clock rate (not applicable RT1020, A1020B, RT1280A, A1280A) Average dedicated clock rate (not applicable RT1020, A1020B, RT1280A, A1280A)
Table Fixed Capacitance Values Actel FPGAs (pF) Device Type RT1020, A1020B RT1280A, A1280A RT1425A, A1425A RT1460A, A1460A RT14100A, A14100A routed_Clk1 routed_Clk2
Table Fixed Clock Loads (s1/s2 Only) Clock Loads Dedicated Array Clock Clock Loads Dedicated Clock
Device Type RT1425A, A1425A RT1460A, A1460A RT14100A, A14100A
CEQM CEQI CEQO
CEQCR CEQCD CEQCI
RadTolerant FPGAs
Determining Average Switching Frequency
determine switching frequency design, must have detailed understanding data input values circuit. guidelines below meant represent worst-case scenarios; they generally used predict upper limits power dissipation.
RT1020, A1020B, RT1280A, A1280A
Logic Modules Input Switching Outputs Switching First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) Average Dedicated Array Clock Rate (fs1) Average Dedicated Clock Rate (fs2) Combinatorial Modules Inputs/4
Outputs/4 Sequential Modules Sequential Modules F/10
F/10
RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A
Logic Modules Input Switching Outputs Switching First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) Average Dedicated Array Clock Rate (fs1) Average Dedicated Clock Rate (fs2) Combinatorial Modules Inputs/4 Outputs/4 Sequential Modules Sequential Modules
F/10
F/10
1-11
RadTolerant FPGAs
Input Delay
Internal Delays
Predicted Routing Delays
Output Delay
Module tINYL
Logic Module tIRD2
Module
tIRD1 tIRD4 tIRD8
tRD1 tRD2 tRD4 tRD8
tDLH tENHZ 12.3
ARRAY CLOCK
tCKH FMAX
Figure RT1020, A1020B Timing Model
Input Delays Internal Delays Predicted Routing Delays Output Delays
Module INYL tIRD2
Combinatorial Logic Module
Module
tDLH 14.0 tPD1 tRD1 tRH2 tRD4 tRD8
INSU INGL Sequential Logic Module
Module tDLH 14.0
Combinatorial Logic included tSUD tSUD tCKH 13.3 FMAX
tRD1
tENHZ
tOUTH tOUTSU tGLH 12.5
ARRAY CLOCKS
Notes: *Values shown RT1280A worst-case military conditions. Input module predicted routing delay Figure RT1280A, A1280A Timing Model*
RadTolerant FPGAs
Input Delays Module tIRD2
Internal Delays Combinatorial Logic Module
Predicted Routing Delays
Output Delays Module
tDHS tRD1 tRD4 tRD8
tINSU tICKY
tINH
Sequential Logic Module tRD1
Module tDHS
Combinatorial Logic included tSUD
tENZHS
ARRAY CLOCK
tOUTH tOUTSU tCKHS 14.4
tHCKH FHMAX
CLOCK
tIOCKH (pad-to-pad) FIOMAX
Note: *Values shown RT14100A worst-case military conditions. Figure RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A Timing Model*
1-13
RadTolerant FPGAs
Parameter Measurement
TRIBUFF Test Loads (shown below)
1.5V tDLH
1.5V tDHL 1.5V
1.5V tENHZ
tENZL tENLZ
tENZH
Figure Output Buffer Delays
Load (Used measure propagation delay)
Load (Used measure rising/falling edges)
Output under Test
Output under Test
tPLZ/tPZL tPHZ/tPZH
Figure 1-10 Test Load
INBUF
tINYH 1.5V 1.5V tINYL
tPHL
tPLH tPHL
tPLH
Figure 1-11 Input Buffer Delays
Figure 1-12 Combinatorial Macro Delays
RadTolerant FPGAs
Sequential Timing Characteristics
(Positive Edge Triggered)
SUENA HENA PRE, tWASYN tWCLKA
represents data functions involving multiplexed flip-flops. Figure 1-13 Flip-Flops Latches (RT1280A, A1280A)
PRESET
(Positive Edge Triggered)
tWCLKA SUENA HENA
tWASYN
represents data functions involving multiplexed flip-flops. Figure 1-14 Flip-Flops Latches (RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A)
1-15
RadTolerant FPGAs
IBDL CLKBUF tINH tINSU tHEXT tSUEXT
Figure 1-15 Input Buffer Latches (R1280A, A1280A)
OBDLHS
tOUTSU tOUTH
Figure 1-16 Output Buffer Latches (RT1280A, A1280A)
RadTolerant FPGAs
RT1020, A1020B Timing Characteristics
Table 1-10 RT1020, A1020B Logic Input Modules Worst-Case Military Conditions, 125°C Speed Parameter Logic Module Propagation Delays tPD1 tPD2 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD3 tSUENA tHENA tWCLKA tWASYN fMAX tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Setup times assume fanout Further testing information obtained from Timer utility. Optimization techniques further reduce delays 4ns. hold time DFME1A macro greater than 0ns. Designer software later) Timer check hold time this macro. Single Module Dual Module Macros Sequential Clock Latch Flip-Flop (Latch) Reset Delays1 Description Min. Max. Units
Logic Module Predicted Routing
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2 17.5
Logic Module Sequential
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
Input Module Propagation Delays High Delays1,
Input Module Predicted Routing
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1-17
RadTolerant FPGAs
Table 1-11 RT1020, A1020B Output Module Worst-Case Military Conditions, 125°C Speed Parameter Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 16.3 17.5 Description Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data High Data Enable High Enable Enable High Enable Delta High Delta High
12.3 11.1 0.07 0.10
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes:
Data High Data Enable High Enable Enable High Enable Delta High Delta High
10.2 12.3 11.1 0.13 0.07
ns/pF ns/pF
Delays based 35pF loading. information found Simultaneously Switching Noise Signal Integrity application note.
RadTolerant FPGAs
RT1280A, A1280A Timing Characteristics
Table 1-12 RT1280A, A1280A Logic Module Worst-Case Military Conditions, 125°C Speed Parameter Description Min. Max. Speed Min. Max. Units
Logic Module Propagation Delays1 tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.8
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Notes:
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
16.4
22.1
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Setup hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
1-19
RadTolerant FPGAs
Table 1-13 RT1280A, A1280A Input Module Worst-Case Military Conditions, 125°C Speed Parameter Description Min. Max. Speed Min. Max. Units
Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y G-to-Y HIGH G-to-Y
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 12.9 10.5 15.2
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays 4ns. Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency 13.8 13.7 16.0 13.8 16.2 18.9 13.3 17.9 13.3 18.2 15.7 21.1 15.7 21.4
RadTolerant FPGAs
Table 1-14 RT1280A, A1280A Output Module Worst-Case Military Conditions, 125°C Speed Parameter Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Timing1 11.0 13.9 12.3 16.1 11.5 12.4 15.5 0.09 0.17 13.0 16.4 14.4 19.0 11.5 13.6 14.6 18.2 0.11 0.20 ns/pF ns/pF Description Min. Max. Speed Min. Max. Units
Data-to-Pad HIGH Data-to-Pad Enable-to-Pad HIGH Enable-to-Pad Enable-to-Pad HIGH Enable-to-Pad G-to-Pad HIGH G-to-Pad Delta HIGH Delta HIGH Timing1
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Notes:
Data-to-Pad HIGH Data-to-Pad Enable-to-Pad HIGH Enable-to-Pad Enable-to-Pad HIGH Enable-to-Pad G-to-Pad HIGH G-to-Pad Delta HIGH Delta HIGH
14.0 11.7 12.3 16.1 11.5 12.4 15.5 0.17 0.12
16.5 13.7 14.4 19.0 11.5 13.6 14.6 18.2 0.20 0.15
ns/pF ns/pF
Delays based 50pF loading. information found Simultaneously Switching Noise Signal Integrity application note.
1-21
RadTolerant FPGAs
RT1425A, A1425A Timing Characteristics
Table 1-15 RT1425A, A1425A Logic Input Modules Worst-Case Military Conditions, 125°C Speed Parameter Description
Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tCLR tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWASYN tWCLKA fMAX tINY tICKY tOCKY tICLRY tOCLRY tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes:
Internal Array Module Sequential Clock Asynchronous Clear Delays2
Logic Module Predicted Routing
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency
Input Module Propagation Delays Input Data Input IOCLK Output IOCLK Input Asynchronous Clear Output Asynchronous Clear Delays2,
Input Module Predicted Routing
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
dual-module macros, tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays 4ns.
RadTolerant FPGAs
Table 1-16 RT1425A, A1425A Logic Input Modules Worst-Case Military Conditions, 125°C Speed Parameter Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Note: Delays based 35pF loading. Input Data Hold (w.r.t. IOCLK Pad) Input Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output Data Hold (w.r.t. IOCLK Pad) Output Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad) Timing1 11.9 10.9 10.5 15.7 0.04 0.07 0.05 0.07 14.0 12.8 11.6 11.6 11.6 17.4 0.04 0.08 0.06 0.08 ns/pF ns/pF ns/pF ns/pF 10.0 Description Min. Max. Speed Min. Max. Units
Output Module
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew Timing1
CMOS Output Module
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew
17.3 13.1 10.5 12.5 18.1 0.06 0.11 0.04 0.05
10.8 20.3 15.5 11.6 11.6 13.7 20.1 0.07 0.13 0.05 0.06
ns/pF ns/pF ns/pF ns/pF
1-23
RadTolerant FPGAs
Table 1-17 RT1425A, A1425A Clock Networks Worst-Case Military Conditions, 125°C Speed Parameter Description Min. Max. Speed Min. Max. Units
Dedicated (Hard-Wired) Clock Network tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Input High (Pad Module Input) Minimum Pulse Width High Minimum Pulse Width Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input High (Pad S-Module Input) Input High (Pad S-Module Input) Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW fRMAX Input High (FO=64) Input High (FO=64) Minimum Pulse Width High (FO=64) Minimum Pulse Width (FO=64) Maximum Skew (FO=128) Minimum Period (FO=64) Maximum Frequency (FO=64) 10.1 11.6
Clock-to-Clock Skews tIOHCKSW tIORCKSW tHRCKSW Clock H-Clock Skew Clock R-Clock Skew H-Clock R-Clock Skew max.)
Note: information found Simultaneously Switching Noise Signal Integrity application note.
RadTolerant FPGAs
RT1460A, A1460A Timing Characteristics
Table 1-18 RT1460A, A1460A Logic Input Modules Worst-Case Military Conditions, 125°C Speed Parameter Logic Module Propagation tCLR tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWASYN tWCLKA fMAX tINY tICKY tOCKY tICLRY tOCLRY tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: dual-module macros, tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays 4ns. Description Delays1 Min. Max. Speed Min. Max. Units
Internal Array Module Sequential Clock Asynchronous Clear Delays2
Logic Module Predicted Routing
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 11.6
Input Module Propagation Delays Input Data Input IOCLK Output IOCLK Input Asynchronous Clear Output Asynchronous Clear Delays2,
Predicted Input Routing
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1-25
RadTolerant FPGAs
Table 1-19 RT1460A, A1460A Output Modules Worst-Case Military Conditions, 125°C Speed Parameter Description Min. Max. Speed Min. Max. Units
Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Note: Delays based 35pF loading. Input Data Hold (w.r.t. IOCLK Pad) Input Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output Data Hold (w.r.t. IOCLK Pad) Output Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad) Timing1 11.9 10.9 11.5 10.9 11.6 17.8 0.04 0.07 0.05 0.07 14.0 12.8 13.5 12.8 13.4 19.8 0.04 0.08 0.06 0.08 ns/pF ns/pF ns/pF ns/pF 10.0
Output Module
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew Timing1
CMOS Output Module
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew
17.3 13.1 10.9 10.9 14.1 20.2 0.06 0.11 0.04 0.05
10.8 20.3 15.5 12.8 12.8 16.0 22.4 0.07 0.13 0.05 0.06
ns/pF ns/pF ns/pF ns/pF
RadTolerant FPGAs
Table 1-20 RT1460A, A1460A Clock Networks Worst-Case Military Conditions, 125°C Speed Parameter Description Min. Max. Speed Min. Max. Units
Dedicated (Hard-Wired) Clock Network tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Input High (Pad Module Input) Minimum Pulse Width High Minimum Pulse Width Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input High (Pad S-Module Input) Input High (Pad S-Module Input) Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW fRMAX Input High (FO=256) Input High (FO=256) Min. Pulse Width High (FO=256) Min. Pulse Width (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 12.9 14.5 10.5 10.5
Clock-to-Clock Skews tIOHCKSW tIORCKSW tHRCKSW Clock H-Clock Skew Clock R-Clock Skew H-Clock R-Clock Skew max.)
Note: information found Simultaneously Switching Noise Signal Integrity application note.
1-27
RadTolerant FPGAs
RT14100A, A14100A Timing Characteristics
Table 1-21 RT14100A, A14100A Logic Input Modules Worst-Case Military Conditions, 125°C Speed Parameter Logic Module Propagation tCLR tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWASYN tWCLKA fMAX tINY tICKY tOCKY tICLRY tOCLRY tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: dual-module macros, tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays 4ns. Description Delays1 Delays2 Min. Max. Speed Min. Max. Units
Internal Array Module Sequential Clock-to-Q Asynchronous Clear-to-Q
Logic Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 11.6
Input Module Propagation Delays Input Data Pad-to-Y Input IOCLK Pad-to-Y Output IOCLK Pad-to-Y Input Asynchronous Clear-to-Y Output Asynchronous Clear-to-Y Delays2,
Input Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
RadTolerant FPGAs
Table 1-22 RT14100A, A14100A Output Modules Worst-Case Military Conditions, 125°C Speed Parameter Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Note: Delays based loading. Input Flip-Flop Data Hold Input Flip-Flop Data Setup Input Data Enable Hold Input Data Enable Setup Output Flip-Flop Data Hold Output Flip-Flop Data Setup Output Data Enable Hold Output Data Enable Setup Timing1 11.9 10.9 11.9 10.9 12.2 17.8 0.04 0.07 0.05 0.07 14.0 12.8 14.0 12.8 14.0 17.8 0.04 0.08 0.06 0.08 ns/pF ns/pF ns/pF ns/pF 10.0 Description Min. Max. Speed Min. Max. Units
Output Module
Data-to-Pad, High Slew Data-to-Pad, Slew Enable-to-Pad, H/L, High Slew Enable-to-Pad, H/L, Slew Enable-to-Pad, High Slew Enable-to-Pad, Slew IOCLK Pad-to-Pad H/L, High Slew IOCLK Pad-to-Pad H/L, Slew Delta HIGH, High Slew Delta HIGH, Slew Delta HIGH LOW, High Slew Delta HIGH LOW, Slew Timing1
CMOS Output Module
Data-to-Pad, High Slew Data-to-Pad, Slew Enable-to-Pad, H/L, High Slew Enable-to-Pad, H/L, Slew Enable-to-Pad, High Slew Enable-to-Pad, Slew IOCLK Pad-to-Pad H/L, High Slew IOCLK Pad-to-Pad H/L, Slew Delta HIGH, High Slew Delta HIGH, Slew Delta HIGH LOW, High Slew Delta HIGH LOW, Slew
17.3 13.1 11.6 10.9 14.4 20.2 0.06 0.11 0.04 0.05
10.8 20.3 15.5 14.0 12.8 16.0 22.4 0.07 0.13 0.05 0.06
ns/pF ns/pF ns/pF ns/pF
1-29
RadTolerant FPGAs
Table 1-23 RT14100A, A14100A Clock Networks Worst-Case Military Conditions, 125°C Speed Parameter Description Min. Max. Speed Min. Max. Units
Dedicated (Hard-Wired) Clock Network tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Input HIGH (Pad Module Input) Minimum Pulse Width HIGH Minimum Pulse Width Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad S-Module Input) Input HIGH (Pad S-Module Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW fRMAX Input HIGH (FO=256) Input HIGH (FO=256) Min. Pulse Width HIGH (FO=256) Min. Pulse Width (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 12.9 14.5 10.5 10.5
Clock-to-Clock Skews tIOHCKSW tIORCKSW tHRCKSW Clock H-Clock Skew Clock R-Clock Skew H-Clock R-Clock Skew max.)
Note: information found Simultaneously Switching Noise Signal Integrity application note.
RadTolerant FPGAs
Descriptions
Clock (Input) IOPCL
RT1020 A1020B only. clock input global clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
CLKA Clock (Input)
Dedicated (Hard-Wired) Preset/Clear (Input)
applicable RT1020, A1020B, RT1280A A1280A. input preset clear. This global input directly wired preset clear inputs registers. This functions when preset clear macros used.
MODE Mode (Input)
applicable RT1020 A1020B. clock input global clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
CLKB Clock (Input)
applicable RT1020 A1020B. clock input global clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
DCLK Diagnostic Clock (Input)
MODE controls diagnostic pins (DCLK, PRA, PRB, SDI). When MODE HIGH, special functions active. When MODE LOW, pins function I/Os. provide debugging capability, MODE should terminated through resistor that MODE pulled HIGH when required.
Connection
This connected circuitry within device.
PRA, Probe (Output)
clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground
supply voltage.
HCLK Dedicated (Hard-Wired) Array Clock (Input)
applicable RT1020, A1020B, RT1280A A1280A. clock input sequential modules. This input directly wired each S-module, offering clock speeds independent number S-modules being driven. This also used I/O.
Input/Output (Input, Output)
Probe used output data from userdefined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. accessible when MODE HIGH. This functions when MODE LOW.
PRB, Probe (Output)
functions input, output, tristate, bidirectional buffer. Input output levels compatible with standard CMOS specifications. RT1020, A1020B, RT1280, A1280A devices, unused pins automatically driven LOW. RT1425, A1425A, RT1460, A1460A, RT14100, A14100A devices, unused pins automatically tristated.
IOCLK Dedicated (Hard-Wired) Clock (Input)
Probe used output data from userdefined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. accessible when MODE HIGH. This functions when MODE LOW.
Serial Data Input (Input)
applicable RT1020, A1020B, RT1280A A1280A. clock input modules. This input directly wired each module, offering clock speeds independent number modules being driven. This also used I/O.
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
Supply Voltage
HIGH supply voltage.
1-31
RadTolerant FPGAs
Package Assignments
84-Pin CQFP
Index
84-Pin CQFP
Figure 84-Pin CQFP (Top View)
RadTolerant FPGAs
84-Pin CQFP Number A1020B Function RT1020 Function Number
84-Pin CQFP A1020B Function CLKA, MODE SDI, DCLK, PRA, PRB, RT1020 Function CLKA, MODE SDI, Input DCLK, Input PRA, PRB, Number
84-Pin CQFP A1020B Function RT1020 Function
RadTolerant FPGAs
132-Pin CQFP
132131130129128127126125124 107106105104103
Index
132-Pin CQFP
Figure 132-Pin CQFP (Top View)
RadTolerant FPGAs
132-Pin CQFP Number A1425A Function SDI, MODE RT1425A Function SDI, MODE Number
132-Pin CQFP A1425A Function PRB, HCLK, IOPCL, RT1425A Function PRB, HCLK, IOPCL, Number
132-Pin CQFP A1425A Function IOCLK, RT1425A Function IOCLK,
RadTolerant FPGAs
132-Pin CQFP Number A1425A Function CLKA, CLKB, PRA, DCLK, RT1425A Function CLKA, CLKB, PRA, DCLK,
RadTolerant FPGAs
172-Pin CQFP
Index
172-Pin CQFP
Figure 172-Pin CQFP (Top View)
RadTolerant FPGAs
172-Pin CQFP Number A1280A Function MODE RT1280A Function MODE Number
172-Pin CQFP A1280A Function RT1280A Function Number
172-Pin CQFP A1280A Function RT1280A Function
RadTolerant FPGAs
172-Pin CQFP Number A1280A Function SDI, RT1280A Function SDI, Number
172-Pin CQFP A1280A Function PRA, CLKA, CLKB, PRB, DCLK, RT1280A Function PRA, CLKA, CLKB, PRB, DCLK,
RadTolerant FPGAs
196-Pin CQFP
Index
196-Pin CQFP
Figure 196-Pin CQFP (Top View)
RadTolerant FPGAs
196-Pin CQFP Number A1460A Function SDI, MODE RT1460A Function SDI, MODE Number
196-Pin CQFP A1460A Function RT1460A Function Number
196-Pin CQFP A1460A Function PRB, HCLK, IOPCL, RT1460A Function PRB, HCLK, IOPCL,
RadTolerant FPGAs
196-Pin CQFP Number A1460A Function RT1460A Function Number
196-Pin CQFP A1460A Function IOCLK, CLKA, CLKB, PRA, RT1460A Function IOCLK, CLKA, CLKB, PRA, Number
196-Pin CQFP A1460A Function DCLK, RT1460A Function DCLK,
2-11
RadTolerant FPGAs
256-Pin CQFP
Index
256-Pin CQFP
Figure 256-Pin CQFP (Top View)
RadTolerant FPGAs
256-Pin CQFP Number A14100A Function SDI, MODE RT14100A Function SDI, MODE Number
256-Pin CQFP A14100A Function RT14100A Function Number
256-Pin CQFP A14100A Function PRB, HCLK, RT14100A Function PRB, HCLK,
2-13
RadTolerant FPGAs
256-Pin CQFP Number A14100A Function IOPCL, RT14100A Function IOPCL, Number
256-Pin CQFP A14100A Function RT14100A Function Number
256-Pin CQFP A14100A Function IOCLK, RT14100A Function IOCLK,
RadTolerant FPGAs
256-Pin CQFP Number A14100A Function CLKA, CLKB, PRA, RT14100A Function CLKA, CLKB, PRA, Number
256-Pin CQFP A14100A Function DCLK, RT14100A Function DCLK,
2-15
RadTolerant FPGAs
Datasheet Information
List Changes
following table lists critical changes that were made current version document.
Previous Version Changes Current Version v3.0 Page
following pins changed "84-Pin CQFP" table: change SDI, Input RT1020 device. change DCLK, Input RT1020 device.
following pins changed "256-Pin CQFP" table: change A14100A RT14100A devices. changed IOPCL A14100A RT14100A devices.
2-14
Datasheet Categories
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advanced," "Production," "Datasheet Supplement." definitions these categories follows:
Product Brief
product brief summarized version datasheet (advanced production) containing general product information. This brief gives overview specific device family information.
Advanced
This datasheet version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
Unmarked (production)
This datasheet version contains information that considered final.
Datasheet Supplement
datasheet supplement gives specific device information derivative family that differs from general family datasheet. supplement used conjunction with datasheet obtain more detailed information specifications that differ between families.
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product described this datasheet could subject either Export Administration Regulations (EAR) some cases International Traffic Arms Regulations (ITAR). They could require approved export license prior export from United States. export includes release product disclosure technology foreign national inside outside United States.
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General Characteristics Tested Total Ionizing Dose (TID) Survivab

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