Actel IGLOO® ProASIC®3L families FPGA devices based Actel nonvolatile
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Flash*Freeze Control Using JTAG
Actel IGLOO® ProASIC®3L families FPGA devices based Actel nonvolatile flash technology single-chip ProASIC3 FPGA architecture. These devices part operating voltage, offering industry's lowest power consumption, smallest footprint, competitive prices, many advanced features. Flash*Freeze technology used IGLOO ProASIC3L devices enables entering exiting Power mode that consumes little power while retaining SRAM register data. Flash*Freeze technology simplifies power management through input/output clock management, with rapid recovery full operational mode. Refer IGLOO Low-Power Flash FPGAs Handbook ProASIC3L Low-Power Flash FPGAs Handbook additional information device features Flash*Freeze pin. applications where device Flash*Freeze mode most operation cases such remote deployment with Flash*Freeze asserted, there need control Flash*Freeze entry exit from within device save power, simplify software, avoid continuous toggling Flash*Freeze pin. addition, IGLOO ProASIC3L devices cannot programmed while Flash*Freeze mode logic that enables authentication encrypted programming turned default save power. Therefore, solution needed bring device Flash*Freeze mode internally turn authentication circuit applications where physical access Flash*Freeze available. This logic, which programmed into device along with user application, acts Master Flash*Freeze mode. distinct models have been developed address this type application. choose either these solutions, depending individual application requirements: Flash*Freeze control using JTAG: This solution provides on-demand wake-up device programming also authentication. Flash*Freeze control using internal oscillator
This application note describes Flash*Freeze control with JTAG IGLOO ProASIC3L devices addresses following requirements: Entry exit from Flash*Freeze mode using JTAG instructions without toggling Flash*Freeze Programming when device Flash*Freeze mode, while addressing need remote programming On-demand authentication turning authentication circuit required encrypted secure programming
Files this application note downloaded from Actel website: Note: files Verilog 2001 compliant. internal oscillator approach described Flash*Freeze Control Using Internal Oscillator.
June 2009 2009 Actel Corporation
Flash*Freeze Control Using JTAG
Flash*Freeze Control with JTAG
This model takes advantage active JTAG pins during Flash*Freeze mode. functionality accomplished using macro which consists following elements: UJTAG Custom finite state machine (FSM) User static macro ULSICC_AUTH
UJTAG provides 8-bit parallel data corresponding serial data coming from test data input (TDI) pin. This data decoded determine state into which design should move. ULSICC_AUTH macro, which variant ultra-low static macro, used control Flash*Freeze mode authentication circuit. Figure shows block diagram this macro.
Flash_Freeze Programming Circuit
UJTAG
Authentication
AUTH_ON
LSI_ON
AUTHEN
LSICC
ULSICC_AUTH
Figure ULSICC_AUTH Macro Block Diagram
Design States
design programmed IGLOO ProASIC3L device these states: Active: Normal operational mode design Flash*Freeze: Asserts LSICC input ULSICC_AUTH macro enter power state. device enters Flash*Freeze mode only when external Flash*Freeze also asserted. Authenticate: This design state rather device state. AUTHEN input ULSICC_AUTH asserted turn authentication circuit. default, AUTHEN turned off, saving approximately device current.
Flash*Freeze Control Using JTAG
JTAG Instructions
decodes JTAG instructions described Table user-defined instructions were specifically defined this macro.
Table Supported JTAG Instructions Instruction U_FF U_ACTIVE U_HW AES_INIT VERIFY_DMK DESCRAMBLE BYPASS Opcode 0x7E 0x7F 0x7D 0xDD 0x0A 0xDF 0xFF Description Comment
Takes device into Flash*Freeze mode. Flash*Freeze instruction must asserted. Takes device into Active mode. Puts device under control Flash*Freeze pin. Enables authentication circuit (authenticate state). Keeps authentication circuit (authenticate state). Keeps authentication circuit (authenticate state). Keeps authentication circuit (authenticate state). instruction instruction Existing instruction Existing instruction Existing instruction Existing instruction
Description
four distinct states (Figure page Since JTAG pins active during Flash*Freeze mode, uses clocking, provided FlashPro3/STAPL player other programming circuitry. Note: During Flash*Freeze, external clocks seen inside core. accomplishes required functionality controlling LSICC AUTH_EN inputs ULSICC_AUTH macro. Depending state Flash*Freeze incoming JTAG instruction, places device into these states: HWControl: U_HW instruction brings into this state. This also state reset. Active: device active, Flash*Freeze mode. U_ACTIVE instruction brings into this state. needs active state before programming JTAG boundary scan test initiated. Flash*Freeze: Software control Flash*Freeze. U_FF instruction brings into this state. Authenticate: authenticate circuit AES_INIT instruction brings into this state VERIFY_DMK/ DESCRAMBLE/BYPASS instructions keep this state. Authentication circuit this state.
Flash*Freeze Control Using JTAG
Upon reset, device defaults with Flash*Freeze control external Flash*Freeze pin.
F*F_Pin HW_Control
_INIT
Active Flash*Freeze
Autheticate Other Instruction Logic Reset) ious tate ACTIVE) S_IN BYPASS
Figure States
S_IN
Other Instruction Logic Reset) ious tate F*F)
Theory Operation
typical IGLOO ProASIC3L application, Flash*Freeze asserted (active Low) board. device Flash*Freeze mode with LSICC asserted (active High). FSM, which part design programmed into FPGA, listens reacts JTAG instructions coming Prior programming device, device first needs brought Flash*Freeze mode into Active mode JTAG instruction U_ACTIVE (0x7F).
Flash*Freeze Control Using JTAG
Sample STAPL Code
TAKE_TO_ACTIVE TAKE_TO_FF STAPL procedures take Actel device into active state Flash*Freeze state respectively. AES_INIT instruction required authenticate state entry part existing STAPL files there need additional procedures:
PROCEDURE TAKE_TO_ACTIVE USES PRINT "Get into Active State"; IRSCAN $7F; WAIT IDLE, CYCLES; WAIT 1000 USEC; ENDPROC; PROCEDURE TAKE_TO_FF USES PRINT "Get into State"; IRSCAN $7E; WAIT IDLE, CYCLES; WAIT 1000 USEC; ENDPROC;
action blocks defined these procedures:
ACTION IN_ACT TAKE_TO_ACTIVE; ACTION IN_FF TAKE_TO_FF;
bring device Active mode before programming, PROGRAM action must modified include TAKE_TO_ACTIVE procedure first procedure action. After programming, IN_FF takes device back into Flash*Freeze mode. action PROGRAM_IN_FF should used when device Flash*Freeze mode:
ACTION PROGRAM_IN_FF TAKE_TO_ACTIVE, W_INITIALIZE, DO_ERASE, DO_PROGRAM, DO_VERIFY_BOL, DO_PROGRAM_RLOCK, DO_PROGRAM_SECURITY RECOMMENDED, DO_EXIT;
Since STAPL file been edited, check will fail. avoid this, value STAPL file must changed zero. This last line STAPL file:
Limitation
ARM® CortexTM-M1 designs with debug from FlashPro3 interface UJTAG macro. IGLOO ProASIC3L devices have only instance UJTAG. Since this macro requires another instance UJTAG, this macro cannot used with designs that have Cortex-M1 FlashPro3 interface.
Flash*Freeze Control Using JTAG
Utilization Details
This design verified Actel's AGL600-256 FBGA IGLOO device, easily instantiated other IGLOO ProASIC3L devices that contain minimum required resources. utilization details AGL600-256 FBGA described Table
Table Resource Core I/Os Global (chip quadrant) RAM/FIFO static User JTAG Utilization Total 13,824 Percentage 0.57% 1.69% 0.00% 0.00% 0.00% 100.00% 100.00%
Conclusion
Flash*Freeze control with JTAG minor STAPL file modifications gives control Flash*Freeze mode authentication circuit, allowing secure programming from within Flash*Freeze mode. Software control Flash*Freeze mode provides flexibility control that otherwise possible.
Related Documents
IGLOO Low-Power Flash FPGAs Handbook ProASIC3L Low-Power Flash FPGAs Handbook Flash*Freeze Control Using Internal Oscillator
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Actel leader low-power mixed-signal FPGAs offers most comprehensive portfolio system power management solutions. Power Matters. Learn more www.actel.com. Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. River Court, Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Building 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 +852 2185 6488 www.actel.com.cn
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