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Embedded SRAM Initialization Using External Serial EEPROM
Embedded SRAM blocks have become common FPGA design. Since SRAM volatile memory type, stored data vanishes absence power. When power restored, memory empty. many applications operate data stored SRAM, must filled, initialized, power-up. Actel IGLOO®, ProASIC®3, Axcelerator, ProASICPLUS, ProASIC FPGA families devices support embedded SRAM blocks. method initializing on-chip SRAM blocks store initialization data external non-volatile EEPROM transfer internal SRAM blocks power-up. This document offers efficient low-cost solution implementing this initialization method. Figure page shows block diagram initialization using external serial EEPROM. reference design provided that used (shown Interface Figure page Actel FPGAs that contain embedded memory blocks. reference design simulated, simulation files also included this application note.
Embedded SRAM Blocks Actel FPGAs
Table lists several features SRAM blocks various FPGA devices clarifies their differences.
Table FPGA Embedded SRAM Features FPGA Family IGLOO IGLOOe IGLOO PLUS ProASIC3E ProASIC3 Axcelerator ProASIC
PLUS
Maximum SRAM Bits 144k 504k 504k 144k 288k 198k
Variable-Aspect Ratio
True Dual-Port
ProASIC Note:
more information embedded SRAM blocks, refer each FPGA datasheet located Actel website (www.actel.com).
illustrated Table there variations size features memory blocks different FPGA families. Although these variations require changes specific implementation, they significant enough affect fundamentals reference design. Therefore, single reference design targeting ProASICPLUS FPGAs presented this document. effects feature size variations discussed "Instantiation Reference Interface User Design" section page
Serial EEPROM Devices
serial EEPROM used source initialization data following reasons: cost small footprint. There many vendors providing different types serial EEPROM devices; however, majority them have similar pins functionality. reference design this application note connects serial EEPROM devices from Atmel that interface protocol.
November 2008 2008 Actel Corporation
serial EEPROM usually configured into multiple pages multiple bytes. example, Atmel AT24C02A device contains memory bits that configured into pages eight bytes each. Therefore, eight bits address required address particular memory location (containing data byte) within this device. Complete information about configuration, functionality, operating condition, electrical characteristics Atmel Serial EEPROM devices available Atmel (www.atmel.com) other serial EEPROM vendor's website. datasheet Atmel AT24C02A serial EEPROM used this application note Two-Wire Serial EEPROM AT24C02A/04A/08A/16A.
Initialization Reference Design
reference design described analyzed three sections. first section discusses functionality, architecture, operation basics design. second section presents VHDL code that implements initialization design demonstrates functionality code illustrating simulation results. final section provides guidelines instantiate, reference design user design, connect FPGA serial EEPROM.
Architecture Functionality
This design implements master interface that will read data from external EEPROM (AT24C02A) power-up initialize 256x8 internal SRAM block. When external logic signals Non-Volatile Memory (NVM) write access, block reads data from external source writes specified address.
Clock Management
reference design runs main clock input named CLK. described AT24C02A datasheet, transitions line EEPROM only allowed while input low; otherwise will cause start stop condition. Therefore, divided provide initialization clock. This clock called BTCK. clock division allows design fast clock (CLK) data transfer easily coordinated with active edges initialization clock (BTCK). clock outputs reference design (ICLK SCK) derived from BTCK. clock input serial EEPROM. follows BTCK except when reference design generating start stop condition. these cases, kept high that transitions data line (SDA input AT24C02A) enter EEPROM start stop condition. ICLK embedded SRAM initialization clock. Writing into SRAM synchronized with rising edge ICLK. ICLK inverted version BTCK since data transmission from external EEPROM synchronized falling edge clock.
State Machine
heart design 9-stage state machine. following state definitions: 0000 reset state: generate start load 0xA0 command 0001 send byte: load 0x00 address 0010 send byte: generate start load 0xA1 command 0011 send byte: clear byte count 0100 receive byte: byte count! acknowledge, count++, state 0100 else assert "nack" 0101 stop: assert stop loop until updt then generate start load 0xA0 0110 send byte: send byte; nack asserted 0101, else load write address 0111 send byte: send write address, load write data 1000 send byte: send write data 0101 state machine implemented this design actually counter that starts zero counts then jumps back 0101 counts again, returning zero only when global reset asserted low.
Counters
reference design tracks number bits words received from external EEPROM using counters: BCNT CCNT. BCNT 4-bit counter that increments state 0100 (reading from RAM) with falling edge whenever BTCK low. BCNT reaching value indicates transfer eight bits. counter cleared whenever reaches value one. then starts counting next data word. CCNT counts number data words received during power-up initialization (from 0x00 0xFF this example). CCNT output also used embedded SRAM write address.
SRAM Interface Ports
Embedded SRAM blocks FPGA connect interface design through following ports: IENB: output interface, which acts write enable SRAM. This signal driven (enabled) interface during each acknowledge step after receiving eight bits data (one byte). This because embedded SRAM this reference design configured 256x8 block. IADDR: Directly extracted from CCNT output, connects write address SRAM block IDATA: Write data input SRAM. ICLK: SRAM initialization clock
Acknowledge
Acknowledge handshaking process between EEPROM FPGA different operations. During data read (initialization), FPGA should send value zero data bus, after receiving eight bits data, acknowledge receipt byte. EEPROM starts sending next byte data after receiving acknowledge signal. Also after each device addressing operation write operation, EEPROM sends value zero order confirm receipt data from FPGA. During operations which interface (FPGA) needs send acknowledge signal (e.g., read), reference design places value zero data line (SDO) automatically after receiving eight bits data (checking BCNT). When acknowledge signal sent EEPROM (e.g., device addressing), checks data (SDI) after receiving eight bits (ninth bit). data line high during ninth bit, activates "not acknowledged" flag (NACK). state machine states 0000 0011, assertion NACK will cause state machine back 0000. states 0100 higher, assertion NACK will cause state machine state 0101 (STOP) wait UPDT RESET.
Status Output
INIT output reference design indicates state I2C. power-up reset, asserted high indicate start initialization process. remains high until state machine enters state 0101 (STOP). This will indicate initialization process that interface available write into EEPROM.
Writing into EEPROM
initialization interface design features byte-write into EEPROM. reference design assumes that data written into EEPROM supplied external FIFO; however, imported from source within user design. write process starts once INIT (state machine state 0101) UPDT input asserted high. UADDR UDATA address data inputs sent EEPROM. UENB output used active read enable external logic (e.g., FIFO). UENB becomes active state 0111 when interface finishing sending write address EEPROM. user's design should clear UPDT control unless another address data byte ready written into EEPROM.
Operation Flow Diagram
Figure illustrates flow diagram interface design summarizes procedures functionalities explained above.
Power Reset
Generate Start Device Addressing (Write)
Clear Byte Counter Ninth Ack?
Ninth Ack?
Receive bits Acknowledge Byte Counter
Load Write Address
Ninth Ack?
Load Address 0x00
Byte Counter
Ninth Ack? Acknowledge Generate Stop Generate Start Device Addressing (Read) Updt Load Write Data
Ninth Ack?
Generate start Device Addressing (Write)
Figure Interface Design Flow Diagram
Interface Source
design files Actel website provide both VHDL Verilog versions code interface reference design, called eeprom_interface. mentioned earlier, eeprom_interface design targets Atmel AT24C02A device initializes 256x8 embedded SRAM block FPGA. Table shows utilization eeprom_interface design three different Actel FPGAs.
Table Utilization Reference Design Actel FPGAs Device Utilization AX250 2.89% APA150 3.2% A3P400 1.94%
simple model1 been developed partially simulate AT24C02A serial EEPROM behavior. This model, along with testbench, accompanies eeprom_interface design simulation purposes.
Instantiation Reference Interface User Design
eeprom_interface design presented previous section used along with rest user design. Therefore, should instantiated top-level user's design, connecting embedded SRAM blocks. This section provides guidelines eeprom_interface upper level design.
Connection External EEPROM
FPGA connects serial EEPROM main ports: SCK. optional; tied ground. Please refer Two-Wire Serial EEPROM AT24C02A/04A/08A/16A more information. input serial EEPROM connects directly output eeprom_interface design. standard used FPGA depends value EEPROM device:
VIL: Between -0.6V 0.3xVCC VIH: Between 0.7xVCC
external serial EEPROM uses (bidirectional line) data. eeprom_interface ports, each direction: SDO. top-level design FPGA should connect these ports EEPROM. top-level user's design must create open-collector bidirectional driver connect SDA. This done using following statements top-level HDL:
SDA; when (SDO '0') else 'Z';
where top-level port design connecting serial EEPROM. addition, line board must pulled VCC. high impedance value second statement should modified high during simulation design resemble external pull-up line.
Connection Embedded SRAM Blocks
reference design connects internal embedded SRAM four ports: IENB, IADDR, IDATA, ICLK. functionality these ports defined previous sections. IGLOO ProASIC3 families devices offer true dual- port embedded SRAM blocks. Therefore, eeprom_interface SRAM interface ports connect ports while user design accesses other. embedded SRAM blocks Axcelerator ProASICPLUS FPGAs two-port memory blocks offering read write port. eeprom_interface should connect write port SRAM during initialization. user's design needs access write port embedded SRAM block, simple arbiter should implemented, shown Figure page
AT24C02A model offered with this application note complete model this device. This model been certified Atmel, Actel, other vendor. This simulation model intended used only verify functionality reference design this application note.
User Design
RCLK RADDR RDATA ADDR WCLK WADDR
UPD_NVM WDATA DATA
eeprom_interface
WCLK
RCLK
WADDR RADDR UDATA UPDT UENB UADDR RESET_N ICLK IADDR IDATA IENB INIT WDATA RDATA
Embedded SRAM
EEPROM
FPGA
Figure Arbiter Access Two-Port
designers intend build dual-port blocks ProASICPLUS Axcelerator FPGAs using embedded SRAM blocks, guidelines given following application notes located Actel website: Implementing Multi-Port Memories ProASICPLUS Devices Implementing Multi-Port Memories Axcelerator Devices.
Timing Requirements
commercial two-wire serial EEPROMs available market very clock speeds hundred kilohertz megahertz). Therefore, interface design does require strict timing constraints meet required initialization speed. However, clock signals routed through global networks they prone considerable amount skew. Users should check possibility hold time violations presence clock skew.
Interfacing SRAM Blocks Different Depth Width
target eeprom_interface design presented this application note 256x8 SRAM block. memory blocks user's design different, minor adjustments required reference design.
Depth depth SRAM block different from 256, size CCNT counter IADDR must modified accordingly. Width data transaction EEPROM side interface consistently done 9-bit (8-bits data 1-bit acknowledge) packets. Therefore, size BCNT should modified. SRAM blocks Axcelerator, ProASIC3, IGLOO families devices offer variable-aspect ratio. This feature facilitates
memory initialization when memory width other than 8-bit. this feature used, write port should width eight while read port configured according user's design requirements. However, variable-aspect ratio feature used target FPGA ProASICPLUS device, then eeprom_interface design should modified accordingly. example, target SRAM configured 256x16 block, following modifications/adjustments will required order perform complete initialization: external EEPROM should least (512x8). consecutive memory locations store initialization word (16-bit). first byte stores upper half word second byte stores lower half. 8-bit MSB_REG register code. CCNT number BYTES this example CCNT should nine bits wide). Generate write enables; first writes into MSB_REG when CCNT(0) second uses MSB_REG SDATA (concatenation) write into memory 16-bits wide when CCNT(0) With above modifications, IENB removed from reference design code.
Conclusion
Volatile SRAM blocks, embedded within FPGAs, initialized after power-up using external serial EEPROM. This example application uses minimum FPGA user I/Os interface with external EEPROM. external memory also updated (written into) FPGA needed. This application note presents interface that instantiated into user's design, performing initialization power-up. reference design utilizes very small portion FPGA logic implementation does affect performance main design. design this document initializes 256x8 SRAM block easily modified support memory organizations different width depth.
References
Two-Wire Serial EEPROM AT24C02A/04A/08A/16A Implementing Multi-Port Memories ProASICPLUS Devices Implementing Multi-Port Memories Axcelerator Devices
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
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