Intended Intended Processor-Based Subsystem with Flash Memory

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Intended Intended Processor-Based Subsystem with Flash Memory

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CoreRemap
Intended
Intended Processor-Based Subsystem with Flash Memory
Contents
General Description Connecting CoreRemap CoreConsole Programmer's Model Resource Requirements Ordering Information List Changes Datasheet Categories
Features
Supplied SysBASIC Core Bundle Tiny Area Flexible Externally Software Programmable
Optimized with CoreMP7 CortexTM-M1
General Description
This slave small control block that singlebit register which intended control aliasing memory resources bottom processor address space. Typically nonvolatile Flash located slot bottom memory default, SRAM made appear base address space setting Remap high which case slot addressable slot RemapDefault input determines value Remap output following reset. Remap output CoreRemap module normally connected Remap input CoreAHB CoreAHBLite. RemapDefault input connected top-level subsystem provide means controlling reset value Remap.
Benefits
Ideal Debugging Flash-Based Subsystem Auto Stitch CoreConsole Compatible with AMBA, CoreMP7, Cortex-M1
Supported Device Families
Fusion IGLOOIGLOOe ProASIC® ProASIC3 ProASIC3E
Synthesis Simulation Support
Supported Actel Libero® Integrated Design Environment (IDE)
Verification Compliance
Compliant with AMBA
January 2008 2008 Actel Corporation
CoreRemap
Connecting CoreRemap CoreConsole
Table lists ports present CoreRemap describes connect these CoreConsole.
Table System Control Block Connections Connection CoreConsole Label Required Connections Slave Interface PCLK PRESETn Remap APBslave PCLK PRESETn Remap Connect this interface available slave slot Bus. clock signal Normally connected HCLK output CoreMP7Bridge Cortex-M1 Active reset input Normally connected HRESETn output CoreMP7Bridge Cortex-M1 This output driven internal control register intended used controlling memory aliasing. This signal should connected Remap input Controller (CoreAHB CoreAHBLite). Optional Connections Default Setting Remap RemapDefault This input determines value Remap output following reset. This signal connected subsystem top-level allow external control memory aliasing after reset. connection made this port, will tied low. Description
Programmer's Model
CoreRemap contains single register offset 0x00 (and aliased throughout slot) which described Table
Table System Control Register Bits 31:1 Name Remap Type Read/Write Reserved Control which drives Remap output Function
Resource Requirements
utilization CoreRemap ProASIC3 device tiles.
Ordering Information
CoreRemap included SysBASIC core bundle that supplied with Actel CoreConsole Deployment Platform tool. obfuscated version SysBASIC (SysBASIC-OC) available free with CoreConsole. source version SysBASIC (SysBASIC-RM) ordered through your local Actel sales representative. CoreRemap cannot ordered separately from SysBASIC core bundle.
v2.1
CoreRemap
List Changes
following table lists critical changes that were made current version document.
Previous Version Changes Current Version v2.0 "Supported Device Families" section updated include ProASIC3L. "Resource Requirements" section updated change ProASIC3E ProASIC3. Advanced v0.1 "Product Summary" section updated include Cortex-M1 IGLOO/e information. Table System Control Block Connections updated include Cortex-M1 PCLK PRESETn. Page
Datasheet Categories
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advanced," "Production." definitions these categories follows:
Product Brief
product brief summarized version advanced production datasheet containing general product information. This brief summarizes specific device family information unreleased products.
Advanced
This datasheet version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
Unmarked (production)
This datasheet version contains information that considered final.
v2.1
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. River Court, Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Building 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 www.jp.actel.com Actel Hong Kong Room 2107, China Resources Building Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 +852 2185 6488 www.actel.com.cn
51700071-2/1.08

Intended Intended Processor-Based Subsystem with Flash Memory

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