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BSDL standard data format subset VHDL) that describes implementation J


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Actel BSDL Files Format Description
BSDL standard data format subset VHDL) that describes implementation JTAG (IEEE 1149.1) device. BSDL approved IEEE Standard 1149.1b. Understanding JTAG architecture becomes especially important with possibility reprogramming ProASIC® ProASICPLUS® device JTAG port. This application note describes elements BSDL implemented BSDL files that provided support Actel devices. These files available Actel website using following link: Note that BSDL files also generated from Designer software. procedure described under "Actel BSDL Files" section.
BSDL?
purpose BSDL provide common language describe boundary scan implementations different devices from multiple vendors. Vendors components supporting 1149.1 standard expected supply BSDL descriptions customers. Customers then more BSDL files following: Describe test logic Synthesize test logic Enable generation test loaded board
third item most important. description BSDL file enables user determine sequences required when performing chip tests using JTAG. These tests include reading serial JTAG chain well stimulating device outputs. latter done inserting shifting serial test vectors. quick summary features included file follows: Length structure boundary scan register Binary instruction codes Device identification code Availability TRST Physical locations JTAG pins
BSDL only describes features test logic that vary from device device-optional features. Mandatory features included file. next section describes file content format more detail.
Actel BSDL Files
Actel BSDL files grouped into categories: generic device-specific. Generic files available product families generic files assign user I/Os inout. Generic BSDL files also generated most product families Designer software using File Export Auxiliary Files. Device-specific files assign user I/Os input, output, inout. However, note that device-specific files still generic names user I/Os (e.g., IO_19). choice generic device-specific file controlled GENERICBSDL variable Designer software. This changed Options Variable. value indicates generic file, whereas value will generate device-specific file. Although generic version used many cases, there some situations where device-specific version required. example ProASICPLUS design that uses Schmitt-trigger inputs. configured Schmitt-trigger input functions input-
July 2006 2006 Actel Corporation
Actel BSDL Files Format Description
only during testing, definition file must changed accordingly. generic file used JTAG tester tries configure output, boundary scan test fails. Actel BSDL description device consists following elements: Entity descriptions Generic parameter Logical port description statements mapping(s) Scan Port identification Instruction Register description Register access description Boundary Register description
These descriptions discussed more detail below keyed sample BSDL file "Appendix page
Entity Description
entity statement names Actel device package combination. this case, Actel RT54SX-S family RT54SX32S device CQFP-208 package. entity description begins with entity statement terminates with statement.
entity a54200rtscqfp208s [statements describe entity here] a54200rtscqfp208s
Generic Parameter
generic parameter Actel files package type (e.g., "cqfp208s").
generic (PHYSICAL_PIN_MAP string "cqfp208s");
Logical Port Description
port description gives logical names pins (system pins). JTAG inputs outputs, nature what user expects-either input output. User outputs bidirectionals denoted BSDL file outputs inouts, respectively. However, user inputs, situation more complicated. user input denoted inout BSDL file. Both user input user bidirectional employ SAME boundary-scan cell structure: three cells associated with input buffer, output buffer, enable. structure used input only, output buffer itself always disabled disabling enable signal. However, scan cell still load output buffer's input data from chip core, just like behavior inout structure. summary, user input will marked inout Actel BSDL file. addition out, inout, identified type linkage. This used no-connects (NC), power (VCC), ground (GND).
port( TMS: bit; TCK: bit; TDI: bit; TRST: bit;
Actel BSDL Files Format Description
TDO: bit; CLKA: bit; CLKB: bit; FCLK: bit; IO_51: bit; IO_37: bit; IO_36: bit; IO_31: inout bit; IO_29: inout bit; IO_24: inout bit; linkage bit_vector(1 VCC: linkage bit_vector(1 15); GND: linkage bit_vector(1
Statement
statement refers IEEE standard package external definitions found packages package bodies. There three versions package corresponding code released with 1990 (draft), 1994, 2001 versions IEEE Standard 1149.1. Actel files currently reference 1990 draft version package. more details "Appendix page
STD_1149_1_1990.all;
Mapping(s)
mapping provides mapping logical signals physical pins particular device package.
attribute PIN_MAP a54200rtscqfp208s entity PHYSICAL_PIN_MAP;
constant cqfp208s PIN_MAP_STRING:= "TRST: 30,"& "TMS: 11,"& "TDI: 2,"& "TCK: 208,"& "CLKB: 181,"& "CLKA: 180,"& "TDO: 103,"& "FCLK: 82,"& "VCC: 201, 184, 164, 148, 145, 130,"& 115, 114, 60),"&
"GND: 185, 183, 157, 146, 131, 129,"& 105, 77),"&
"NC: 182, 132, 65),"& "IO_51: 51,"&
Actel BSDL Files Format Description
"IO_37: 37,"& "IO_36: 36,"& "IO_31: 31,"& "IO_29: 29,"& "IO_24: 24,"&
Scan Port Identification
scan port identification statements identify signals present device's TAP. addition, maximum value designated MHz.
attribute TAP_SCAN_IN signal TRUE;
attribute TAP_SCAN_OUT signal TRUE;
attribute TAP_SCAN_MODE signal TRUE;
attribute TAP_SCAN_CLOCK signal (10.0e6, BOTH);
Instruction Register Description
following example, RT54SX-S 5-bit instruction code. example also provides legal instruction mnemonics opcodes. remainder this section lists additional device-dependent characteristics Instruction Register. INSTRUCTION_CAPTURE attribute specifies pattern loaded into Instruction Register when Controller passes through Capture-IR state. INSTRUCTION_DISABLE attribute lists opcodes which device outputs disabled (this applies HIGHZ instruction). statement file associates name with correct opcode. INSTRUCTION_GUARD attribute identifies opcode that places Bypass Register between while driving device outputs with previous contents Boundary Scan Register. This equivalent JTAG CLAMP instruction; again, statement file associates this with correct opcode. Note that INSTRUCTION_DISABLE INSTRUCTION_GUARD attributes have been dropped from STD_1149_1_1994 STD_1149_1_2001. INSTRUCTION_PRIVATE attribute identifies Actel-only commands-potentially unsafe customers use.
attribute INSTRUCTION_LENGTH a54200rtscqfp208s: entity attribute INSTRUCTION_OPCODE a54200rtscqfp208s: entity "EXTEST(00000),"& "SAMPLE(00001),"& "INTEST(00010),"& -"USERCODE(00011),"& "IDCODE(00100),"& -"USRSC(00101),"& "HIGHZ(01110),"& "CLAMP(01111),"& "PROBE(10000),"& "BYPASS(11111)";
Actel BSDL Files Format Description
attribute INSTRUCTION_CAPTURE a54200rtscqfp208s: entity "XXX01"; attribute INSTRUCTION_DISABLE a54200rtscqfp208s: entity "HIGHZ"; attribute INSTRUCTION_GUARD a54200rtscqfp208s: entity "CLAMP"; attribute INSTRUCTION_PRIVATE a54200rtscqfp208s: entity "PROBE";
Register Access Description
These commands indicate structure registers user instructions such instructions IDCODE. REGISTER_ACCESS defines which register placed between each instruction. example shows that HIGHZ CLAMP instructions select Bypass Register.
attribute REGISTER_ACCESS a54200rtscqfp208s: entity "BYPASS (HIGHZ, CLAMP)"; attribute IDCODE_REGISTER a54200rtscqfp208s: entity "XXXX"&-Version "XXXXXXXXXXXXXXXX"&-Device "00000101111"&-Manufacturer "1";-Required
Boundary Register Description
Boundary Register description contains list boundary scan cells, along with information regarding cell type associated control. BOUNDARY_CELLS included example, which gives list cell types (BC_0 through BC-10) used. These standard types provided IEEE package file; this example only BC-1 used. with INSTRUCTION_GUARD INSTRUCTION_DISABLE, BOUNDARY_CELLS been dropped from STD_1149_1_1994 STD_1149_1_2001. BOUNDARY_LENGTH length boundary scan chain-729 this case. BOUNDARY_REGISTER list boundary scan cells. list below shortened version give idea different types cells. This explains gaps cell numbering (the first entry each field). entry PIN51 "Third Line (Enable Scan Cell)" section page following parts (note that there three lines, each boundary scan cell associated with this pin):
First Line (Input Scan Cell)
cell number BC_1 boundary cell type (from IEEE package) Port (the null element) indicates internal cell output control (see next element) internal internal cell value that should loaded into scan-cell flip-flops when board-level software might choose random value. this case, indicates "don't care."
Second Line (Output Scan Cell)
cell number BC_1 boundary cell type (from IEEE package) IO_51 Port system output connected cell output3 cell that drives data tristate output
Actel BSDL Files Format Description
value that should loaded into scan-cell flip-flops when board-level software might choose random value. this case indicates "don't care." control cell that disable output. this case, Enable scan cell from Line value that must scanned into control cell (cell disable output IO_51 condition output driver when disabled
Third Line (Enable Scan Cell)
cell number BC_1 boundary cell type (from IEEE package) Port (the null element) indicates internal cell output control (see next element) control output control value that should loaded into scan-cell flip-flops when board-level software might choose random value
attribute BOUNDARY_CELLS a54200rtscqfp208s: entity "BC_1"; attribute BOUNDARY_LENGTH a54200rtscqfp208s: entity 729; attribute BOUNDARY_REGISTER a54200rtscqfp208s: entity -BSR75, PIN51, spec=BIN_OUT 0(BC_1, *,internal,
1(BC_1, IO_51,output3, 2(BC_1, *,control,
-BSR73, 6(BC_1, internal, 7(BC_1, internal, 8(BC_1, internal,
-BSR56, PIN37 48(BC_1, *,internal,
49(BC_1, IO_37,output3, 50(BC_1, *,control,
-BSR55, PIN36 51(BC_1, internal, 52(BC_1, IO_36,output3, 53(BC_1, *,control,
-BSR44, PIN31 78(BC_1, IO_31,input,
79(BC_1, IO_31,output3, 80(BC_1, *,control,
-BSR43, PIN30, spec=TRSTB
Actel BSDL Files Format Description
-BSR42, PIN29 81(BC_1, IO_29,input,
82(BC_1, IO_29,output3, 83(BC_1, *,control,
-BSR37, PIN24 84(BC_1, IO_24,input,
85(BC_1, IO_24,output3, 86(BC_1, *,control,
List Changes
following table lists critical changes that were made current version document.
Previous Version 51900003-0/11.02 Changes Current Version (51900003-1/7.06*) "Actel BSDL Files" section updated. Page
Note: *The part number located last page document.
Actel BSDL Files Format Description
Appendix
Sample Actel BSDL File
DESIGN:sxstdma32 FAMILY:54SXA DEVICE:54200rts PACKAGE:cqfp208s RESTRICT JTAG:1 RESTRICT TRST:1
entity a54200rtscqfp208s generic (PHYSICAL_PIN_MAP string "cqfp208s"); port( TMS: bit; TCK: bit; TDI: bit; TRST: bit; TDO: bit; CLKA: bit; CLKB: bit; FCLK: bit; IO_51: bit; IO_37: bit; IO_36: bit; IO_31: inout bit; IO_29: inout bit; IO_24: inout bit; linkage bit_vector(1 VCC: linkage bit_vector(1 15); GND: linkage bit_vector(1
STD_1149_1_1990.all;
attribute PIN_MAP a54200rtscqfp208s entity PHYSICAL_PIN_MAP;
constant cqfp208s PIN_MAP_STRING:= "TRST: 30,"& "TMS: 11,"& "TDI: 2,"&
Actel BSDL Files Format Description
"TCK: 208,"& "CLKB: 181,"& "CLKA: 180,"& "TDO: 103,"& "FCLK: 82,"& "VCC: 201, 184, 164, 148, 145, 130,"& 115, 114, 60),"&
"GND: 185, 183, 157, 146, 131, 129,"& 105, 77),"&
"NC: 182, 132, 65),"& "IO_51: 51,"& "IO_37: 37,"& "IO_36: 36,"& "IO_31: 31,"& "IO_29: 29,"& "IO_24: 24,"& attribute TAP_SCAN_IN TDI: signal true; attribute TAP_SCAN_MODE TMS: signal true; attribute TAP_SCAN_OUT TDO: signal true; attribute TAP_SCAN_RESET TRST: signal true; attribute TAP_SCAN_CLOCK TCK: signal (10.00E6, BOTH);
attribute INSTRUCTION_LENGTH a54200rtscqfp208s: entity attribute INSTRUCTION_OPCODE a54200rtscqfp208s: entity "EXTEST(00000),"& "SAMPLE(00001),"& "INTEST(00010),"& -"USERCODE(00011),"& "IDCODE(00100),"& -"USRSC(00101),"& "HIGHZ(01110),"& "CLAMP(01111),"& "PROBE(10000),"& "BYPASS(11111)";
attribute INSTRUCTION_CAPTURE a54200rtscqfp208s: entity "XXX01"; attribute INSTRUCTION_DISABLE a54200rtscqfp208s: entity "HIGHZ"; attribute INSTRUCTION_GUARD a54200rtscqfp208s: entity "CLAMP"; attribute INSTRUCTION_PRIVATE a54200rtscqfp208s: entity "PROBE"; attribute REGISTER_ACCESS a54200rtscqfp208s: entity
Actel BSDL Files Format Description
"BYPASS (HIGHZ, CLAMP)"; attribute IDCODE_REGISTER a54200rtscqfp208s: entity "XXXX"&-Version "XXXXXXXXXXXXXXXX"&-Device "00000101111"&-Manufacturer "1";-Required
attribute BOUNDARY_CELLS a54200rtscqfp208s: entity "BC_1"; attribute BOUNDARY_LENGTH a54200rtscqfp208s: entity 729; attribute BOUNDARY_REGISTER a54200rtscqfp208s: entity
-BSR75, PIN51, spec=BIN_OUT 0(BC_1, *,internal,
1(BC_1, IO_51,output3, 2(BC_1, *,control,
-BSR73, 6(BC_1, internal, 7(BC_1, internal, 8(BC_1, internal,
-BSR56, PIN37 48(BC_1, *,internal,
49(BC_1, IO_37,output3, 50(BC_1, *,control,
-BSR55, PIN36 51(BC_1, internal, 52(BC_1, IO_36,output3, 53(BC_1, *,control,
-BSR44, PIN31 78(BC_1, IO_31,input,
79(BC_1, IO_31,output3, 80(BC_1, *,control,
-BSR43, PIN30, spec=TRSTB
-BSR42, PIN29 81(BC_1, IO_29,input,
Actel BSDL Files Format Description
82(BC_1, IO_29,output3, 83(BC_1, *,control,
-BSR37, PIN24 84(BC_1, IO_24,input,
85(BC_1, IO_24,output3, 86(BC_1, *,control,
a54200rtscqfp208s;
Actel BSDL Files Format Description
Appendix
Standard VHDL Package STD_1149_1_2001
This appendix contains code 1990 version IEEE package that referenced Actel files. Note that there minor differences 1994 2001 packages. Here summary only those attributes that used Actel files: Five 1990 attributes-INSTRUCTION GUARD, INSTRUCTION_DISABLE, INSTRUCTION_SEQUENCE, INSTRUCTION_USAGE-were deleted. BOUNDARY_CELLS,
1990 version, device register named IDCODE REGISTER_ACCESS attribute. name since been changed DEVICE_ID.
STD_1149_1_1990 BSDL Version
VHDL Package Package Body support
source
revision
date
%G%-%U%
package STD_1149_1_1990
Created 900525
Give mapping declarations
attribute PIN_MAP string; subtype PIN_MAP_STRING string;
Give control declarations
type CLOCK_LEVEL (LOW, BOTH); type CLOCK_INFO FREQ real; LEVEL: CLOCK_LEVEL; record; record
attribute attribute attribute attribute attribute
TAP_SCAN_IN TAP_SCAN_OUT
boolean; boolean;
TAP_SCAN_CLOCK: CLOCK_INFO; TAP_SCAN_MODE boolean; TAP_SCAN_RESET: boolean;
Actel BSDL Files Format Description
Give instruction register declarations
attribute attribute attribute attribute attribute attribute attribute attribute
INSTRUCTION_LENGTH integer; INSTRUCTION_OPCODE string; INSTRUCTION_CAPTURE string; INSTRUCTION_DISABLE string; INSTRUCTION_GUARD string; INSTRUCTION_PRIVATE string; INSTRUCTION_USAGE string; INSTRUCTION_SEQUENCE string;
Give USER code declarations
type ID_BITS ('0', '1', 'x', 'X'); type ID_STRING array downto ID_BITS; attribute IDCODE_REGISTER ID_STRING; ID_STRING;
attribute USERCODE_REGISTER:
Give register declarations
attribute REGISTER_ACCESS string;
Give boundary cell declarations
type BSCAN_INST (EXTEST, SAMPLE, INTEST, RUNBIST); type CELL_TYPE (INPUT, INTERNAL, CLOCK, CONTROL, CONTROLR, OUTPUT2, OUTPUT3, BIDIR_IN, BIDIR_OUT); type CAP_DATA (PI, UPD, CAP, ZERO, ONE); type CELL_DATA record CELL_TYPE; BSCAN_INST;
CAP_DATA; record; type CELL_INFO array (positive range CELL_DATA;
Boundary Cell defered constants (see package body)
constant BC_1 constant BC_2
CELL_INFO; CELL_INFO;
Actel BSDL Files Format Description
constant BC_3 constant BC_4 constant BC_5 constant BC_6
CELL_INFO; CELL_INFO; CELL_INFO; CELL_INFO;
Boundary Register declarations
attribute BOUNDARY_CELLS string; attribute BOUNDARY_LENGTH integer; attribute BOUNDARY_REGISTER string;
Miscellaneous
attribute DESIGN_WARNING string; STD_1149_1_1990; 1149.1-1990 Package
package body STD_1149_1_1990
Standard Boundary Cells Written Parker 900525
Description f10-12, f10-16, f10-18c, f10-18d, f10-21c
constant BC_1 CELL_INFO ((INPUT, (INPUT, (INPUT, (INPUT, EXTEST, SAMPLE, INTEST, PI), PI), PI), (OUTPUT2, (OUTPUT2, (OUTPUT2, (OUTPUT2, EXTEST, SAMPLE, INTEST, PI), PI), PI),
RUNBIST, PI), PI), PI), PI),
RUNBIST, PI), PI), PI), PI),
(OUTPUT3, EXTEST, (OUTPUT3, SAMPLE, (OUTPUT3, INTEST,
(INTERNAL, EXTEST, (INTERNAL, SAMPLE, (INTERNAL, INTEST,
(OUTPUT3, RUNBIST, PI), (CONTROL, EXTEST, (CONTROL, SAMPLE, (CONTROL, INTEST, PI), PI), PI),
(INTERNAL, RUNBIST, PI), (CONTROLR, EXTEST, (CONTROLR, SAMPLE, (CONTROLR, INTEST, PI), PI), PI),
(CONTROL, RUNBIST, PI),
(CONTROLR, RUNBIST,
Description f10-8, f10-17, f10-19c, f10-19d, f10-22c
constant BC_2 CELL_INFO ((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, UPD),
Actel BSDL Files Format Description
(INPUT, (INPUT, (INPUT,
SAMPLE, INTEST,
PI), UPD),
(OUTPUT2, SAMPLE,
PI),
Intest output2 supported
RUNBIST, UPD), (OUTPUT2, RUNBIST, UPD), UPD), (INTERNAL, EXTEST, PI), PI), (INTERNAL, SAMPLE, (INTERNAL, INTEST, PI), PI), UPD),
(OUTPUT3, EXTEST, (OUTPUT3, SAMPLE, (OUTPUT3, INTEST,
(OUTPUT3, RUNBIST, PI), (CONTROL, EXTEST, (CONTROL, SAMPLE, (CONTROL, INTEST,
(INTERNAL, RUNBIST, UPD),
UPD), (CONTROLR, EXTEST, UPD), PI), PI), (CONTROLR, SAMPLE, (CONTROLR, INTEST, PI), PI),
(CONTROL, RUNBIST, PI),
(CONTROLR, RUNBIST,
Description f10-9
constant BC_3 CELL_INFO ((INPUT, EXTEST, (INPUT, SAMPLE, (INPUT, INTEST, PI), PI), PI), (INTERNAL, EXTEST, (INTERNAL, SAMPLE, (INTERNAL, INTEST, PI), PI), PI),
(INPUT, RUNBIST, PI),
(INTERNAL, RUNBIST,
Description f10-10, f10-11
constant BC_4 CELL_INFO ((INPUT, EXTEST, (INPUT, SAMPLE, (CLOCK, EXTEST, (CLOCK, SAMPLE, (CLOCK, INTEST, PI), PI), PI), PI), PI), Intest input supported Runbist input supported (INTERNAL, EXTEST, (INTERNAL, SAMPLE, (INTERNAL, INTEST, PI), PI), PI),
(CLOCK, RUNBIST, PI),
(INTERNAL, RUNBIST,
Description f10-20c, combined Input/Control
constant BC_5 CELL_INFO ((INPUT, EXTEST, (INPUT, SAMPLE, (INPUT, INTEST, PI), PI), UPD), (CONTROL, EXTEST, (CONTROL, SAMPLE, (CONTROL, INTEST, PI), PI), UPD),
(INPUT, RUNBIST, PI),
(CONTROL, RUNBIST,
Description f10-22d, reversible cell
Actel BSDL Files Format Description
constant BC_6 CELL_INFO ((BIDIR_IN, EXTEST, (BIDIR_IN, SAMPLE, (BIDIR_IN, INTEST, PI), PI), (BIDIR_OUT, EXTEST, (BIDIR_OUT, SAMPLE, UPD), PI), PI),
UPD), (BIDIR_OUT, INTEST,
(BIDIR_IN, RUNBIST, UPD), (BIDIR_OUT, RUNBIST,
STD_1149_1_1990;
1149.1-1990 Package Body
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Camberley, Surrey GU15 United Kingdom Phone 1276 1276 Actel Japan www.jp.actel.com EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 Actel Hong Kong www.actel.com.cn Suite 2114, Pacific Place Queensway, Admiralty Hong Kong Phone +852 2185 6460 +852 2185 6488
51900003-1/7.06

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