Waveform generators widely used high-speed applications. examples incl

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32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
Waveform generators widely used high-speed applications. examples include communication design test, pulse generation, high-speed, low-jitter data clock source, mixed-signal design test. This application note describes implement 32-channel waveform generator with resolution Actel's Axcelerator FPGAs. Based user-defined 10-bit inputs each channel, this waveform generator generate channels output waveforms independently. With Axcelerator's high-performance phase locked loop (PLL) core, designer obtain system clock, which guarantees resolution waveform generation. example, Channel Figure generating pulses, respectively. advanced feature demonstrated this design system GHz, generate output data with resolution. Other SRAM-based FPGAs only clock (both edges) using their output register modes achieve 1.25 resolution. high-performance, low-jitter, Axcelerator used generate system clock from input reference clock. system clock distributed low-skew, global networks, allowing manual placement Designer ChipPlanner particular logic blocks minimize routing delay.
Channel Enable
Channel 32-Channel Waveform Generator With Interchannel Resolution=1.0ns Channel
Input Data
Input Data
Figure Top-Level Diagram Waveform Generator
2004 Actel Corporation
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
Design Description
Figure shows waveform generator basic block diagram channel. Input Data registered 10-bit Data Input Register then propagated 10-bit Parallel-In-Serial-Out (PISO) Shift Register. Load Instruction Bits Generator generates Parallel Load Instruction sends 10-bit PISO Shift Register every clock cycles. Once 10-bit PISO Shift Register receives Load Instruction, loads 10-bit Registered Input Data parallel format shifts them serial format, which becomes output waveform.
Input Reference Clock 50MHz 10-bit Shift Register (SHREG10)
Shift Data
Register Replication
Load Instruction Bits Generator
LOAD[4:0]
LOAD[4:0]
System Clock 1.0GHZ
Parallel Load Instruction
DATA_INPUT[9:0]
10-bit Data Input Register (REGCC10)
NEW_VALUE[9:0]
10-bit PISO Shift Register (SHREG10_LD)
DATA_OUTPUT Channel Waveform
Figure Block Diagram Waveform Generator Channel
Design Implementation
Since this design extremely aggressive timing requirements-1.0 system clock-a schematic representation with embedded ACTgen cores chosen over behavioral VHDL approach achieve high degree control. implementation different functional blocks illustrated below. Table shows resources needed this design implementation.
Table Design Resources Design Environment Target Device Programmer LiberoIntegrated Design Environment (IDE) v5.2 newer versions AX250 FG484 (Utilization: R-cell 1120/1408 C-cell 1280/2816) Silicon Sculptor
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
System Clock Generator-PLL
system clock generated from Axcelerator PLL. Figure shows configuration PLL.
Figure System Clock Generator-PLL Configuration
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
10-Bit Data Input Register
10-bit Data Input Register (instance name: REGCC10) deployed this design ACTgen core, where configuration found Figure Sequential Type Combinatorial. This uses macro implement register instead R-cell order down utilization R-cells.1 rest design consumed around available R-cells.
Figure 10-bit Data Input Register ACTgen Configuration
macro sequential logic composed C-cells. Usually, these C-cells adjacent physical location chip.
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
Load Instruction Bits Generator
main components Load Instruction Bits Generator 10-bit shift registers (instance name: SHREG10), illustrated Figure 10-bit shift register generates one-clock cycle High pulse every clock cycles. shift register blocks were replicated average load each timing concerns. pulses from shift registers registered combined into LOAD instruction bits. Figure shows waveform Load Instruction Bits Generator functionality.
Figure Load Instruction Bits Generator
REG[9:0]
REG8 LOAD[4:0]
Figure Load Instruction Bits Generator Functionality Waveform
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
10-Bit PISO Shift Register
10-bit PISO Shift Register critical part running system clock also needs support parallel load capability. Normally, this would require logic level between each register that introduces additional delay. MUXed R-cell, DFMB, used implement same logic removes additional logic minimizes register-to-register delay. Figure shows implementation details. When LOAD[4:0] "11111," NEW_VALUE[9:0] parallel loading performed when LOAD[4:0] "00000," loaded data NEW_VALUE[9:0] shifting. REG9 real output waveform. Figure shows details functionality waveform.
Figure 10-bit PISO Shift Register Implementation
Parallel Load DATA[9:0] CLOCK(ENABLE) NEW_VALUE[9:0]
Shifting
LOAD[4:0] SHREG10_LD/REG9
DATA9 DATA8
Figure 10-bit PISO Shift Register Functionality Waveform
DATA1 DATA0
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
Each channel Waveform Generator independently after channel enabled. Based different input data pattern, output signal changed increment. RESET signal deasserted after locked. valid input data begins assertion after RESET deassertion ensure they captured properly. channel ENABLE signal works clock signal Data Input Register block, which period system clock cycles. DATA_INPUT_B reloaded every cycles, following pattern "000," "001," "003". "3FE," "3FF," while DATA_INPUT_A follows pattern "3FF," "3FE," "3FC,". "001," "000." Figure illustrates functional simulation results. Shifting "3FF" Ch0~Ch15; Shifting "000" Ch16~Ch31 Shifting "3F0" Ch0~Ch15; Shifting "00F" Ch16~Ch31
Figure Functional Simulation Result
Design Features
Some specific Axcelerator design features used this design. system clock generated from high-performance Axcelerator with jitter fast acquisition (lock) time. Output PLL, system clock, distributed low-skew global networks. ChipPlanner allows designer manually place logic cells functional blocks, such 10-bit PISO Shift Register. This minimized routing delay meet system performance requirement. information using ChipPlanner, refer Designer online help. MUXed registers (DFMB) used 10-bit PISO Shift Register block implement shift register, with parallel load capability. Figure page illustrates DFMB macro Table page presents truth table. input DFMB mapped DCIN input R-cell. Figure page illustrates Axcelerator R-cell architecture. DCIN input driven DCOUT adjacent C-cell DirectConnect routing resource. more details, refer Axcelerator Family FPGAs datasheet.
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
Figure DFMB Macro Table DFMB Truth Table
DIN(user signals) DCIN HCLKA/B/C/D CLKE/F/G/H Internal Logic
GCLR
Figure R-Cell
PSET GPSET
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
this design, BUFD used hand-placed adjacent C-cell DFMB order bring parallel load data into input DFMB DirectConnect. corresponding view ChipPlanner illustrated Figure This design implemented Axcelerator speed grade commercial devices even under worst-case conditions. increase timing margin, designer higher voltage than minimum requirement worst-case condition (worst 1.425V, typical 1.500V, best 1.575V). analysis this design done 1.575V, which best-case voltage. However, other factors affecting timing analysis still remain worst-case, such temperature process.
Figure ChipPlanner View DirectConnect
Conclusion
design used this application note demonstrated that Axcelerator's high-performance stable manner outperform other SRAM-based FPGA products. nonvolatile feature makes possible Waveform Generator provide high-resolution waveforms test equipment right after power-up. channels independently generate user-defined waveforms. They also used together chosen separately different time create various waveforms given target device. designer change configuration adjust system clock frequency system performance waveform resolution requirements different.
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
Related Documents
Datasheets
Axcelerator Family FPGAs
User's Guides
Antifuse Macro Library Guide Libero User Guide Designer User Guide ChipPlanner MultiView Navigator User Guide ACTgen Cores Reference Guide
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
Appendix
Figure shows hierarchy this design.
Figure Design Hierarchy
Among these blocks, "inbuf10," "inbuf32," "outbuf32," "clk1gig_pll," "regcc10" ACTgen cores; rest schematics. whole design Libero project directory with top-level folder named "wfg32" located wfg32.zip file. Figure illustrates design directory hierarchy.
Figure Design Directory Hierarchy
32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA
.ADB file with compilation layout done located inside \designer folder. user open .ADB file Designer v5.2 newer check compile layout information, timing analysis Timer, review manual placement results ChipPlanner, generate various reports. \designer folder also _ba.vhd _ba.sdf files, which used post-layout simulation. \hdl folder contains .GEN files corresponding .VHD files ACTgen macros this design. user reload these .GEN files into ACTgen Core Generator check configurations these macros. \stimulus folder includes testbenches different levels this design. user different level root Libero simulation after associating corresponding testbench. \viewdraw folder schematic files symbol files this design.
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
http://www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Camberley, Surrey GU15 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 Actel Hong Kong 39th Floor, Pacific Place Queensway, Admiralty Hong Kong Phone +852.227.35712 +852.227.35999
51900076-0/07.04

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