modern warfare, laser-guided weapons play significant role ensuring ea
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Laser Range Finder Using Actel's Axcelerator FPGA
modern warfare, laser-guided weapons play significant role ensuring each warhead deployed will only strike intended target. Each laser-guided missile bomb laser seeker that consists array photodiodes, these photodiodes sensitive predefined laser's optical wavelength. high-intensity laser designator must acquire lock onto target-either from from ground. This necessary allow missile bomb identify target. Once laser-guided weapon launched, laser seeker senses laser beam reflected from target, seeker's control system will then guide missile straight target (Figure general, laser pulse width presented control system very short. control system must fast enough reliably capture this laser pulse pattern calculate range target. This application note describes details implementing such laser range finder design using Actel's Axcelerator family. However, this reference design could applied application where precise timing ability capture narrow pulse width required.
Display
Electronic hand control Attack computer
Pave Tack computer Laser-range receiver
Target
Figure Laser-Guided Weapon System Overview
Design Description
This particular design application requires capturing pulse width. Capturing pulse reliably using single clock would require clock flip-flop toggle rate above GHz. Instead, multiple clocks created phase-shifted order capture this narrow pulse width. system must able sample every that pulse captured reliably least three consecutive clock cycles. sample pulse every four clocks (CLKA, CLKB, CLKC, CLKD) running created phase shifted using Axcelerator PLLs programmable delay lines. shown Figure page original input reference clock multiplied PLLs each successive clock shifted phase additional from base clock, CLKA. Axcelerator family provides register cells (R-cell) with toggle rate combinatorial cells (C-cell) implement various logic functions. R-cell contains flip-flop featuring asynchronous clear, asynchronous preset, active-low enable control logic. clock source each R-cell hardwired clock, routed clock, internal logic. Moreover, R-cell registers feature selectable clock
2004 Actel Corporation
Laser Range Finder Using Actel's Axcelerator FPGA
polarity register-by-register basis with timing penalty. With four hardwired clocks, four routed clocks, eight PLLs with maximum output frequency GHz, Axcelerator used meet most challenging design specifications. this particular design, four PLLs, programmable delay lines, selectable clock polarity R-cell features were used. Using selectable clock polarity feature R-cell, clock edges Figure page also used sample short data pulse. result, eight samples taken Figure page shows phase relationship four output clocks.
DataA
CLKA Delay
DataB PLL1 DATA_IN DataC
PLL2 Clock PLL3
CLKB Delay
DataD Data Register
CLKC Delay
DataF
PLL4
CLKD Delay
DataG
DataH
DataI
Figure Simplified Block Diagram
Laser Range Finder Using Actel's Axcelerator FPGA
250ps 250ps 250ps
Clock Register dataA
CLKA CLKA'
dataE
CLKB
dataB dataF
CLKB'
CLKC
dataC
CLKC'
dataG
CLKD
dataD
CLKD'
dataH
Figure Output Clock Phase Relationship (250 Sampling Interval)
Design Implementation
This reference design developed using Actel LiberoIntegrated Design Environment (IDE), which provides everything required from schematic capture entry place-and-route tools. Table summarizes Libero features used this design. more information, visit When design completed verified through simulation static timing analysis, device programmed using Actel Silicon Sculptor programmer. more information regarding programming Actel's devices using Silicon Sculptor visit Note that Actel provides design files this reference design. Please refer "Appendix" page detailed information obtaining these files.
Table Libero Features Function Project Manager, editor Synthesis Simulation Testbench Creation Timing/Constraints, Macro Generation, Place-and-Route, Programming Programming Software ChipPlanner, Tool LiberoIDE Synplify® ModelSimAE WaveFormer Lite Designer Silicon Sculptor Company Actel Synplicity® Mentor Graphics® SynaptiCADActel Actel
Laser Range Finder Using Actel's Axcelerator FPGA
Design Creation
Create top-level VHDL design called Top_level.vhd, ACTgen macro builder generate macros. Clock Routed (Figure setting Routed Clock ACTgen, blocks south side chip will used, each output capable driving (routed clock) network. Four PLLs (and hence four generated CLKs) used this part design, leaving four PLLs four HCLKs remaining design implementation. other hand, clock outputs were chosen hardwired, block would located north side chip. Four PLLs with different delay settings used generating clock system that sample narrow pulse width every (Table Refer Axcelerator Family Clock Management application note ACTgen User's Guide more information.
Figure Macro Generation Using ACTgen Table Clock System Settings File pll_a.gen pll_b.gen pll_c.gen pll_d.gen Input Frequency (MHz) Output Frequency (MHz) Static Delay (ps)
Laser Range Finder Using Actel's Axcelerator FPGA
Design Verification-Functional Simulation
After describing design, must verify functionality. After creating testbench, Top_Level_tbench.vhd, using SynaptiCAD WaveFormer Lite Actel Edition (AE), Mentor Graphics ModelSim simulator perform functional simulation your design.
Synthesis
Since this HDL-based design, must synthesized generate EDIF netlist. Synplicity Synplify generate your EDIF netlist want reverify your design performing postsynthesis simulation using ModelSim simulator.
Design Implementation
This reference design implemented AX125-3 FGA256 device. Four PLLs were used only R-cells (3.57%) were needed, leaving most remaining logic resources free. Actel Designer software automatically places routes design returns timing information. Since this application requires capturing very narrow pulse width, precise timing important. With unique routing structures offered Axcelerator family, skew each register pair using same clock source virtually eliminated manually placing registers. Designer software Timer tool then used verify that register pair using same clock source uniform timing delay. Figure illustrates routing structures Axcelerator devices. FastConnects provide high-performance, horizontal routing inside SuperCluster, vertical routing SuperCluster immediately below. This particular design takes advantage FastConnect used vertical routing. register pairs, using same output clock, manually placed vertically immediately with each other. example, register dataA placed directly below register dataE (Figure page ChipPlanner manually place register (Figure page When registers manually placed committed software, place-and-route tool will change placement those registers. After design, compile, layout stages, Designer Timer tool used ensure output clock arrives both halves register pair same time. shown Figure each register pair same timing delay from corresponding reference clock.
Figure Axcelerator Routing Structure
Laser Range Finder Using Actel's Axcelerator FPGA
dataH dataG dataF dataE dataA dataB dataC dataD
Figure Designer ChipPlanner Manual Placement Data Registers
Figure Timing Delay Each Register Pair
Laser Range Finder Using Actel's Axcelerator FPGA
Post-Layout Simulation
After design implementation completed, verify that your design meets timing specifications performing post-layout simulation. Figure illustrates best-case conditions, Figure page shows same simulation under worst-case conditions. Figure (best-case), five samples were captured successfully registers dataC, dataD, dataE, dataF, dataG. Figure page (worstcase), samples were captured successfully registers dataB, dataC, dataD, dataE, dataF, dataG. Changing from best-case worst-case conditions involves changing setting Libero under Options Project Settings Simulation. best-case condition, vsim command should minimum maximum worst-case condition (Figure page
data samples captured successfully
Figure Simulation Under Best-Case Condition
Laser Range Finder Using Actel's Axcelerator FPGA
data samples captured successfully
Figure Simulation Under Worst-Case Condition
Figure Changing Simulation Condition
Laser Range Finder Using Actel's Axcelerator FPGA
Device Programming
Finally, create .AFM programming file. Silicon Sculptor perform devices programming.
Conclusion
Axcelerator family's unique architecture offers flexibility designs where high performance precise timing important. this reference design, PLLs Axcelerator devices offer programmable delay programmable output-to-input frequency ratios enable flexible clock system. Such system reliably capture very narrow laser pulse width needed military applications other applications that require high sampling rate.
Related Documents
Application Notes
Axcelerator Family Clock Management
User's Guides
ACTgen Cores Reference Guide ACTgen User's Guide MultiView Navigator User's Guide Designer User's Guide Libero User's Guide Timer User's Guide
Laser Range Finder Using Actel's Axcelerator FPGA
Appendix
Using this reference design requires that Actel Libero installed. Extract hs_sample.zip file your hard drive open project file hs_sample.prj from Libero IDE. Figure shows design hierarchy, Figure shows design files this reference design. Please refer Table description design files.
Figure Design Hierarchy
Figure File Manager Table Description Design Files File name Top_Level.vhd Top_Level_ba.vhd Top_Level_ba.sdf Top_Level.edn Top_Level_tbench.vhd Top_Level_tbench.btim pll_a.vhd pll_b.vhd pll_c.vhd pll_d.vhd *.gen level this reference design Structural netlist post-layout simulation Standard delay file post-layout simulation netlist generate from Synplify Testbench generated Waveformer Lite simulation Waveformer Lite project file testbench generation Multiply input frequency with delay Multiply input frequency with 250ps delay Multiply input frequency with 500ps delay Multiply input frequency with 750ps delay ACTgen macros PLLs Description
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http://www.actel.com
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