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64-common 160-segment 1-icon common Bitmap Driver NJU6655 bitmap


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NJU6655
64-common 160-segment 1-icon common Bitmap Driver
NJU6655 bitmap driver display graphics characters. contains 10,400 bits display data RAM, microprocessor interface circuits, instruction decoder, 64-common 160-segment 1-icon-common drivers. image display data transferred display data serial 8-bit parallel interface. dots graphics 10-character 4-line dots character with icon displayed NJU6655 itself. wide operating voltage from 5.5V operating current suitable battery-powered applications. build-in Electrical Variable Resistance very precision, furthermore rectangle outlook very applicable Slim TCP.
PACKAGE OUTLINE
NJU6655CJ
FEATURES
Direct Correspondence between Display Data Pixel Display Data 10,400 bits Drivers 64-common 160-segment 1-icon common Direct Microprocessor Interface both type Serial Interface (SI, SCL, CS1b, CS2) Programmable Bias selection 1/5,1/7,1/9 bias Useful Instruction Display On/Off Cont, Initial Display Line Set, Page Address Set, Column Address Set, Status Read, Display Data Read/Write, Select, Inverse Display, Entire Display On/Off, Bias Select, Read Modify Write, End, Reset, Common Direction Register Set, Power control set, Feedback Resistor Ratio Set, Mode Set, Register Set, Static Indicator On/Off, Static Indicator Register Set, Power Save, Power Save Reset, n-line Inverse Drive Register Set, n-line Inverse Drive Reset, Partial Select, Internal Oscillation Circuit Power Supply Circuits Incorporated Voltage Booster Circuits (4-time Maximum), Voltage Adjust Circuits, Voltage Follower Voltage Regulator Incorporated Precision Electrical Variable Resistance (64-step) Power Consumption T.B.D.uA(Typ.). Operating Voltage (All voltages based VDD=0V.) Logic Operating Voltage -2.4V -5.5V Voltage Booster Operating Voltage -2.4V -6.0V Driving Voltage -4.5V -18.0V Rectangle outlook Package Outline Bump-chip C-MOS Technology (Substrate
Ver.2007-11-20
NJU6655
COMM DUMMY23 DUMMY24 DUMMY25 DUMMY26 DUMMY20 DUMMY21 DUMMY22 S157 S158 S159
LOCATION
DUMMY1 DUMMY2 TEST1 SYNC DOFb SYNC CS1b RESb D6(SCL) D7(SI) VSS2 VSS2 VSS2 VSS2 VSS2 VOUT VOUT C3C3+ C1C1 C2C2+ DUMMY3 DUMMY4 TEST2 DUMMY5 DUMMY6
DUMMY19 DUMMY18 DUMMY17 S156 S155
Chip Center X=0um, Y=0um Chip Size X=8.88mm,Y=2.77mm Chip Thickness 675um 30um Bump Size 130um 31um Bump Pitch 50um(Min.) Bump Height 17.5um(Typ.) Bump Material Voltage Boosting Polarity Negative Voltage (VDD common) Substrate
DUMMY16 DUMMY15 DUMMY14 DUMMY13 DUMMY12 DUMMY11 COMM DUMMY10 DUMMY9 DUMMY8 DUMMY7
Ver.2007-11-20
NJU6655
COORDINATES
Chip Size 8.88 2.77mm(Chip Center X=0um, Y=0um) Terminal 1622 -1213 1672 -1213 1722 -1213 1772 -1213 1822 -1213 1872 -1213 DUMMY3 1922 -1213 DUMMY4 1972 -1213 2022 -1213 2072 -1213 2122 -1213 2172 -1213 2222 -1213 2272 -1213 2322 -1213 2372 -1213 2422 -1213 2472 -1213 2522 -1213 2572 -1213 2622 -1213 2672 -1213 2796 -1213 2953 -1213 3076 -1213 3199 -1213 3356 -1213 3480 -1213 TEST2 3603 -1213 3726 -1213 3849 -1213 3972 -1213 DUMMY5 4022 -1213 DUMMY6 4072 -1213 DUMMY7 4265 -1037 DUMMY8 4265 -987 DUMMY9 4265 -937 DUMMY10 4265 -887 4265 -837 4265 -787 4265 -737 4265 -687 4265 -637 4265 -587 4265 -537 4265 -487 4265 -437 4265 -387 4265 -337 4265 -287
Terminal DUMMY1 DUMMY2 TEST1 SYNC DOFb SYNC CS1b RESb D6(SCL) D7(SI) VSS2 VSS2 VSS2 VSS2 VSS2 VOUT VOUT C3C3C1+ C1C1C2C2-
-4092 -4042 -3919 -3796 -3637 -3417 -3197 -2976 -2756 -2598 -2474 -2317 -2194 -2071 -1914 -1790 -1667 -1510 -1387 -1229 -1008 -788 -567 -347 -127 1022 1072 1122 1172 1222 1272 1322 1372 1422 1472 1522 1572
-1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213 -1213
Ver.2007-11-20
NJU6655
Terminal COMM DUMMY11 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16
4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4265 4115 4065 4015 3965 3915 3865 3815 3765 3715 3665 3615 3565 3515 3465 3415 3365 3315 3265 3215 3165 3115 3065 3015
-237 -187 -137 1013 1063 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213
Terminal
2965 2915 2865 2815 2765 2715 2665 2615 2565 2515 2465 2415 2365 2315 2265 2215 2165 2115 2065 2015 1965 1915 1865 1815 1765 1715 1665 1615 1565 1515 1465 1415 1365 1315 1265 1215 1165 1115 1065 1015
1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213
Ver.2007-11-20
NJU6655
Terminal S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122
-135 -185 -235 -285 -335 -385 -435 -485 -535 -585 -635 -685 -735 -785 -835 -885 -935 -985 -1035 -1085 -1135 -1185 -1235 -1285 -1335 -1385 -1435 -1485 -1535 -1585 -1635 -1685 -1735 -1785 -1835 -1885 -1935 -1985
1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213
Terminal S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 DUMMY17 DUMMY18 DUMMY19 DUMMY20 DUMMY21 DUMMY22 S157 S158 S159
-2035 -2085 -2135 -2185 -2235 -2285 -2335 -2385 -2435 -2485 -2535 -2585 -2635 -2685 -2735 -2785 -2835 -2885 -2935 -2985 -3035 -3085 -3135 -3185 -3235 -3285 -3335 -3385 -3435 -3485 -3535 -3585 -3635 -3685 -4015 -4065 -4115 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265
1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1213 1063 1013
Ver.2007-11-20
NJU6655
Terminal COMM DUMMY23 DUMMY24 DUMMY25 DUMMY26
-4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265 -4265
-137 -187 -237 -287 -337 -387 -437 -487 -537 -587 -637 -687 -737 -787 -837 -887 -937 -987 -1037
Ver.2007-11-20
NJU6655
BLOCK DIAGRAM
S159
COMM
Internal Power Circuits VOUT
Voltage Followers Voltage
Regulator
Shift Register
Shift Register
COMM
Common Drivers
Segment Drivers
Common Drivers
Common Timing
Display Data Latch Address Decoder
Line Address Decoder
C3VSS2
Display Data 10,400-bit
Common Direction
Column Address Decoder Display Timing SYNC DOFb
Buffer
Column Address Counter 8bit Page Address Register
Column Address Register 8bit Oscillator Multiplexer
Instruction Decoder
Status Internal Line
Busy Flag
Holder
Reset
Interface
RESb
CS1b
(SI)
(SCL)
Initial Display Line
C2+/C2-
Ver.2007-11-20
Line Counter
Voltage Converter
NJU6655
TERMINAL DISCRIPTION
SYMBOL FUNCTION 1,2,57,58, DUMMY1 Dummy terminals. These open terminals electrically. 130, DUMMY26 290, 13,19, Power Power supply terminal. 59,60,72, 78,82 10,16, Ground terminal. 53,54,75, VSS2 Power Reference voltage voltage booster. 55,56 Power External reference voltage input terminal. Normally open. Power driving voltage supplying terminal. 61,62 63,64 When internal voltage booster used, supply each level driving 65,66 voltage from outside with following relation. 67,68 VDDV1V2V3V4V5VOUT 69,70 When internal power supply internal circuits generate supply following bias voltage from terminal. Bias Bias V5+4/5VLCD V5+3/5VLCD V5+2/5VLCD V5+1/5VLCD Bias V5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5+1/7VLCD Bias V5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5+1/9VLCD (VLCD=VDD-V5) Boosted capacitor connecting terminals used voltage booster. 45,46 C147,48 51,52 C249,50 43,44 C341,42 VOUT Voltage booster output terminal. Connect boosted capacitor between this terminal VSS2. Voltage adjustment terminal Connect external feedback resistor control driving voltage This terminal effective when IRS="L". Data input/output terminals. (26, (SCL, P/S="H" Tri-state bi-directional Data terminal 8-bit parallel operation. P/S="L" D7=Serial data input terminal. D6=Serial data clock signal input terminal. terminals Hi-impedance. Data from loaded rising edge latched parallel data rising edge SCL. When CS1b="H", terminals Hi-impedance. Data discrimination signal input terminal. Connect Address MPU. data distinguished between Display data Instruction status Distinction Display Data Instruction RESb Reset terminal. When RESb terminal goes "L", initialization performed. Reset operation executing during state RESb.
Ver.2007-11-20
NJU6655
SYMBOL CS1b
FUNCTION Chip select terminal. Data Input/Output available during CS1b="L" CS2="H". case Type MPU> signal type input terminal. Active During this signal terminals output. case Type MPU> Enable signal type input terminal. Active case Type MPU> Connect type signal. Active "L". data data input synchronizing rise edge this signal. case Type MPU> read/write control signal type input terminal. State Read Write interface type selection terminal. This terminal must connect VSS. State Type Type Serial parallel interface selection terminal. Chip Select Data/Instruction Data Read/Write CS1b,CS2 D0toD7 RDb,WRb SI(D7) CS1b,CS2 case serial interface (P/S="L") data status read operation work mode serial interface. must fixed "L", high impedance. Terminal select whether enable disable display clock internal oscillator circuit. CLS="H" Internal oscillator circuit enable CLS="L" Internal oscillator circuit disabled (requires external input) When CLS="L", input display clock through terminal. This terminal selects master/slave operation NJU6655. Master operation outputs timing signals that required display, while slave operation inputs timing signals required LCD, synchronizing system. Master operation Slave operation following true depending status: Power DOFb OSC. Supply Circuit Available Available Output Output Output Output Avail. Available Input Output Output Output Avail. Avail. Input Input Output Input *:Don't Care Display clock input/output terminal. following true depending status. Output Input Input *:Don't Care Serial Clock SCL(D6)
(R/W)
Ver.2007-11-20
NJU6655
SYMBOL SYNC DOFb
FUNCTION alternating current signal terminal. M/S="H" Output M/S="L" Input synchronizing current signal terminal. M/S="H" Output M/S="L" Input Display blanking control terminal. M/S="H" Output terminal. Display "On" "H", Display "Off" M/S="L" Input terminal. External control. Refer following table. DOFb Instruction Display Display Internal Feedback Resistor Select IRS="H" Internal feedback IRS="L" External feedback resistor This setting effective master operation. ineffective slave operation should fixed "L". output terminal static drive. This terminal used conjunction with SYNC terminal. driving signal output terminals. -Common output terminals -Segment output terminals S159 Common output terminals following output voltages selected combination alternating (FR) signal Common scanning data.
124, S159 284,
Scan Data
Output Voltage
Segment output terminals following output voltages selected combination alternating (FR) signal display data RAM. Data Output Voltage Normal Reverse
121,326
COMM TEST1 TEST2
output terminals indicator. Both terminals output same signal. Leave these open they used. Maker test only. Normally open. Maker test only. This terminal must connect VSS.
Ver.2007-11-20
NJU6655
FUNCTIONAL DESCRIPTION
Description each blocks (1-1) Busy Flag (BF) During internal operation, being busy can't accept instructions except "status read". data output through terminal "status read" instruction. When cycle time (tcyc) mentioned characteristics" satisfied, check isn't required after each instruction, that processing performance improved. (1-2) Initial display line register initial display line register assigns DDRAM line address, which corresponds COM0 "initial display line set" instruction. used only normal display also vertical display scrolling page switching without changing contents DDRAM. However, 65th address icon display can't assigned initial display line address. (1-3) Line counter line counter provides DDRAM line address. initializes contents switching frame timing signal (FR), also counts-up synchronization with common timing signal. (1-4) Column address counter column address counter 8-bit preset counter, which provides DDRAM column address, independent below-mentioned page address register. will increment (+1) column address whenever "display data read" "display data write" instructions issued. However, counter will locked when no-existing address above addressed. count-lock will able released "column address set" instruction again. counter invert correspondence between column address segment driver direction means "ADC set" instruction. (1-5) Page address register page address register provides DDRAM page address. last page address should used icon display because only valid. (1-6) Display data (DDRAM) DDRAM contains 10,400-bit, stores display data, which 1-to-1 correspondents panel pixels. When normal display mode, display data turns turns pixels. When inverse display mode, turns turns
Ver.2007-11-20
NJU6655
Page Address
Data
Display Pattern
Line Address
D3,D2,D1,D0 (0,0,0,0)
PAGE
D3,D2,D1,D0 (0,0,0,1)
PAGE
D3,D2,D1,D0 (0,0,1,0)
PAGE
Common Driver COMM*
D3,D2,D1,D0 (0,1,1,1)
PAGE
(1,0,0,0)
Column Address
D0="0" D0="1"
PAGE
Segment Drivers
example Initial display 08H.
Fig.1 Display data (DDRAM) COMM independent "Initial display line set" instruction always corresponds 65th line.
Ver.2007-11-20
NJU6655
(1-7) Common direction register common direction register selected "Partial Select" "Common Direction instructions shown Table When using partial display function, COM0 COM15 COM63 terminals cannot used. Table Common direction Common drivers Partial Common Select Direction Register name COM0 COM31 COM63 COM63 COM32 COM0 name COM16 COM31 COM47 COM47 COM32 COM16 Register Set" COM48
COM32 COM31 COM32 COM31
(1-8) Reset circuit reset circuit initializes following status using reset signal into RESb terminal. -Reset status using RESb terminal: Display Normal display (Non-inverse display) select Normal mode (D0="0") Power control register clear D2,D1,D0="0,0,0" Serial interface register clear bias select D1,D0="0,0"(1/9 bias) Power save reset Entire display Normal mode Internal oscillation circuit stop 10.Partial select D0="0"(1/65 duty) 11.Static indicator Static indicator register D1,D2="0,0" 12.Read modify write 13.Initial display line address 14.Column address 15.Page address page 16.Common direction register D3="0"(Normal) 17.Feedback resistors ratio D2,D1,D0="0,0,0" 18.EVR mode register: D5,D4,D3,D2,D1,D0="1,0,0,0,0,0" 19.n-line inverse drive register D3,D2,D1,D0="0,0,0,0"(n-line inverse reset) 20.Test mode reset (Test mode Test mode terminal should connected MPU's reset terminal, reset operation should executed same timing reset. described "BUS TIMING CHARACTERISTICS", necessary input 1.5us(min.) over level signal into terminal order carry reset operation. will return normal operation after about 1.5us(max.) from rising edge reset signal. reset operation RESb="L" initializes each register setting above reset status, internal oscillation circuit output terminals affected. reset operation necessary avoid malfunctions. Note "Reset" instruction Table.4 can't substituted reset operation using terminal. executes above-mentioned only items. Note reset terminal susceptible external noise, design layout consideration noise. Note case using external power supply driving voltage, RESb terminal required being level when external power supply turned-on.
Ver.2007-11-20
NJU6655
(1-9) driving circuits Common segment drivers drivers consist 64-common drivers, 160-segment divers 1-icon-common driver. shown driving waveform", driving waveforms generated combination display data, common timing signal internal timing signal. Display data latch circuit display data latch circuit temporally stores 160-bit display data transferred from DDRAM synchronization with common timing signal, then transfers these stored data segment drivers. "Display on/off", "inverse display on/off" "entire display on/off" instructions control only contents this latch circuit, they can't change contents DDRAM. addition, display isn't affected DDRAM accuses during displaying because data read-out timing from this latch circuit segment drivers independent accessing timing DDRAM. Line counter latch signal latch Circuits clock line counter latch signal latch circuits generated from internal display clock (CL). line address display data renewed synchronizing with display clock (CL). 160bits display data latched display latch circuits synchronizing with display clock, then output driving circuits. display data transfer driving circuits executed independently with access MPU. Display timing generator display timing generates timing signal display system combination master clock driving signal refer Fig.2 frame signal alternative signal generate driving waveform 2-frame alternative driving method n-line inverse driving method.
Ver.2007-11-20
NJU6655
Common timing generation common timing generated display clock (refer Fig.2)
DATA
Fig.2-1 2-frame alternating drive mode
DATA
Fig.2-2 n-line inverse drive mode (n=7, line inverting register sets
Ver.2007-11-20
NJU6655
Oscillator This power consumption oscillator which provides display clock voltage converter timing clock. Internal power circuits internal power circuits composed boost voltage converter, output voltage regulator including 64-step voltage followers. optimum values external passive components internal power circuits, such capacitors terminals feed back resistors terminal, depend panel size. Therefore, necessary evaluate actual module with these external components order determine optimum values. Each portion internal power circuits controlled "power control set" instruction shown Table.2. addition, combination power supply circuits described Table.3. Table.2 Power control
Portions Status
Voltage converter Voltage regulator Voltage followers
Table.3 Power supply combinations
Status
Voltage converter
Voltage regulator
Voltage followers
External voltage
Using internal power circuits Using voltage regulator Voltage
followers
VSS2 VOUT,VSS2 VOUT,V5,VSS2 VOUT,V1~V5
Capacitor terminals Open Open Open
Using voltage followers Using only external power supply Capacitor input terminals: C1+, C1-, C2+, C2-, other combinations except examples Table.3.
internal power supply designed drive small panels such cellular phones. Thus, used drive large panel, make sure whether works with internal power supply needs external power supply. selections external components bias circuit, voltage booster feedback loop depend panel sizes, make sure what best values particular application.
Ver.2007-11-20
NJU6655
Power Supply applications Power Control Instruction Boost Circuit Voltage Regulator Voltage Follower Internal power supply Example. Internal Booster, Voltage Regulator, Voltage Follower using (D2,D1,D0) (1,1,1) Only VOUT Supply from outside Example. Internal Voltage Regulator, Voltage Follower using. (D2,D1,D0) (0,1,1)
VOUT VSS2 C1C1+ C3C2
VOUT VSS2
VOUT Supply from outside Example. Internal Voltage Follower using. (D2,D1,D0) (0,0,1)
External Power Supply Example. VOUT supply from outside (D2,D1,D0) (0,0,0)
VOUT VSS2
VOUT VSS2
These switches should open during power save mode. Note) When using voltage follower circuit, external resistors necessary stabilize V1,V2,V3 voltages.
Ver.2007-11-20
NJU6655
Instruction NJU6655 distinguishes signal data Instruction combination WRb(R/W). decode instruction execution performs with only high speed Internal timing without relation external clock. Therefore busy flag check required normally. case serial interface, data input MSB(D7) first serially. Table. 4-1,4-2 shows instruction codes NJU6655. Table.
Instruction Display On/Off Initial Display Line Page Address Column Address Upper Order 4bits Column Address Lower Order 4bits Status Read Write Display Data Read Display Data Select Normal Inverse On/Off Whole Display On/Off Bias Select Read Modify Write
Instruction table
Instruction code Write Data Read Data Bias
Don't Care)
Description Display On/Off D0=0:Off D0=1:On Determine Display Line COM0 page Page Address Register Upper order bits Column Address Register Lower order bits Column Address Register Read internal Status Write data into Display Data Read data from Display Data Segment D0=0 :Normal 1:Inverse Inverse Display D0=0 :Normal 1:Inverse Whole Display Turns D0=0: Normal D0=1: Whole Disp. Select Bias Increment Column Address Register when writing no-change when reading Release from Read Modify write Mode Initialize Internal Circuits scanning order common drivers Register D3=0 Normal, D3=1 Inverse status internal power circuits status internal resistors ratio (Rb/Ra)
Line Address Page Address Upper Order Column Address Lower Order Column Address
Status
Reset Common Direction Select
Power Control Feedback Resistor Ratio
Operating Mode Resistor Ratio
Ver.2007-11-20
NJU6655
Table.
Instruction Mode Register Static Indicator On/Off Static Indicator Register Pawer Save Pawer Save Reset n-line Inverse Drive Register n-line Inverse Drive Reset Partial Select Internal Oscillation Circuit
Instruction table
Instruction code
Don't Care)
Description mode output level register D0=0 Off, D0=1 static indicator register D0=0 Standby mode D0=1 Sleep mode Release from Pawer Save Mode number inverse drive line Release line inverse drive D0=0 (1/65 Duty) D0=1 (1/33 Duty) Start operation Internal Oscillation circuit Mode
Setting Data
Number Inverse Lines
Ver.2007-11-20
NJU6655
(2-1) Explanation Instruction Code Display On/Off This instruction selects display turn-on turn-off regardless contents DDRAM. Display Display
Initial Display Line This instruction specifies DDRAM line address which corresponds COM0 position. means repeating this instruction, initial display line address will dynamically changed; means smooth display scrolling will enabled. Page Address order access DDRAM writing reading display data, both "page address set" "column address set" instructions required before accessing. last page address should used icon display because only valid. Page
Line Address (HEX)
Ver.2007-11-20
NJU6655
Column Address above-mentioned, order access DDRAM writing reading display data, necessary execute both "page address set" "column address set" before accessing. 8-bit column address data will valid when both upper 4-bit lower 4-bit data into column address register. Once column address set, will automatically increment (+1) whenever DDRAM will accessed, that DDRAM will able continuously accessed without "column address set" instruction. column address will stop increment page address will changed when last address addressed. Status Read This instruction reads internal status regarding "busy flag", "ADC select", "display on/off" "reset". BUSY BUSY
Upper 4-bit Lower 4-bit
Column Address (HEX)
ON/OFF RESET
When "1", being busy can't accept instructions. shows correspondence between column address segment drivers. When "0", column address (159-n) corresponds segment driver When "1", column address corresponds segment driver Please careful that read data opposite "ADC select" instruction data. shows display status. When "0", display-on status. When "1", display-off status. Please careful that read data opposite "Display On/Off" instruction data. shows reset status. When "0", normal operation. When "1", during reset operation.
ON/OFF
RESET
Display Data Write This instruction writes display data into selected column address DDRAM. column address automatically increments (+1) whenever display data written this instruction, that this instruction continuously issued without "column address set" instruction. Write Data
Ver.2007-11-20
NJU6655
Display Data Read This instruction reads display data stored selected column address DDRAM. column address automatically increments (+1) whenever display data read this instruction, that this instruction continuously issued without "column address set" instruction. After "column address set" instruction, dummy read will required, please refer (4-4). case using serial interface mode, this instruction can't used. Select This instruction selects segment driver direction. correspondence between column address segment driver direction shown Fig.1. This function reduces restrictions position module. Read Data
Clockwise Output (Normal) Segment Driver S159 Counterclockwise Output (Inverse) Segment Driver S159
Inverse Display On/Off This instruction inverses status turn-on turn-off entire pixels. doesn't change contents DDRAM. Normal Inverse
data correspond "On" data correspond "On"
Whole Display On/Off This instruction turns entire pixels regardless contents DDRAM. doesn't change contents DDRAM. This instruction should performed prior "Inverse display On/Off" instruction.
Normal Display Whole Display Turns Bias Select This instruction selects bias value.
(Whole Display Off) (Whole Display
Bias Prohibited* Because malfunction-operate, (D1,D0) (1,1).
Ver.2007-11-20
NJU6655
Read Modify Write This instruction controls column address increment. using this instruction, column address can't increment when read operation increment when write operation. This status will continued until below-mentioned "end" instruction will issued. This instruction reduce load MPU, during display data specific DDRAM area repeatedly changed cursor blink others.
Note) this "Read Modify Write" mode, display data "Read" "Write", instructions except "Column Address Set" executed. Sequence Cursor Blink Display
Page Address Column Address Start Address Cursor Display
Read Modify Write Dummy Read Data Read
Start Read Modify Write data ignored Column Counter doesn't increase Data inverse
Data Write Dummy Read Data Read Data Write Dummy Read Data Read Data Write
Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase
Repeating
Read Modify Write
Finish?
Ver.2007-11-20
NJU6655
"end" instruction cancels read modify write mode makes column address return initial value just before "read modify write" started.
Return Column Address Reset This instruction reset following status, however doesn't change contents DDRAM. Please careful that can't substituted reset operation using RESb terminal. Reset status "reset" instruction: Static indicator register D1,D0 "0,0" Read modify write Initial display line address Column address Page address page Common direction register D3="0"(Normal mode) Feedback resistors ratio D2,D1,D0 "0,0,0" mode register D5,D4,D3,D2,D1,D0 "1,0,0,0,0,0" n-line inverse drive register D3,D2,D1,D0 "0,0,0,0" Test mode reset (Test mode Test mode affected this initialization. -N+m
Read modify write
Common Driver Direction Select This instruction selects common driver direction. Please refer (1-7) common driver direction more detail. Normal Inverse
Don't Care)
Common driver direction C63) (C16 C47) Common driver direction (C63 (C47 C16)
Ver.2007-11-20
NJU6655
Power Control This instruction controls status internal power circuits. Please refer (1-9) Driving Circuits internal power circuits more detail.
Voltage Converter Voltage Converter Voltage Regulator Voltage Regulator Voltage Followers Voltage Followers
Note) internal power supply must when external power supply using. wait time depends COUT capacitors, VLCD Voltage. Therefore requires actual evaluation using module correct time. Feedback Resistor Ratio This instruction used determine internal feedback resistor ratio. Please refer (3-2) Voltage Adjust Circuits more detail. VLCD 1+(Rb/Ra) Minimum Maximum
Internal resistor ratio 1+(Rb/Ra)
Ver.2007-11-20
NJU6655
mode This instruction sets into mode, always used combination with "EVR register set". can't accept instructions except "EVR register set" during mode. This mode will released after "EVR register set" instruction.
Register This instruction sets 6-bit data into register determine output voltage "V5" internal voltage regulator. Static Indicator Static Indicator On/Off This instruction selects static indicator turn-on turn-off, always used combination with static indicator register set".
Don't Care)
VLCD Minimum Maximum
Static Indicator Static Indicator
Static Indicator Register
Don't Care)
Indicator display Status (Blink 1.0s intervals) (Blink 0.5s intervals) (Turn time)
Ver.2007-11-20
NJU6655
Power Save This instruction sets into power save mode. This instruction reducing operating current well static operations. internal status contents DDRAM will remained just before "Power save" instruction. addition, DDRAM accessed during power save mode. There power save modes, sleep mode standby mode. Standby Mode Sleep Mode
<Sleep Mode> functions halted that operating current reduced standby current. system stops follows, Oscillator internal power circuits stop. common segment drivers output level. <Standby Mode> part functions halted. only static drive system indicator operates. system except static indicator stops follows, Internal power circuits stop. (Oscillator operating.) driving stopped. common segment drivers output level. only static indicator working. Pawer Save Reset This instruction releases power save mode.
Ver.2007-11-20
NJU6655
n-line Inverse Drive Register This instruction specifies number n-line. Please refer (1-9)LCD Driving Circuits (e)Common timing generation Fig.2-1, Fig.2-2 more detail.
Inverse Lines -(*)
2-frame mode.
alternating drive
n-line Inverse Drive Reset This instruction releases n-line inversion, does change contents n-line register. Patial Select This instruction starts partial mode operation.
1/65 Duty (Partial Select Off) 1/33 Duty (Partial Select Display structure Partial Select Partial Select (1/65 Duty) COM0~COM7 COM8~COM15 COM16~COM23 COM24~COM31 COM32~COM39 COM40~COM47 COM48~COM55 COM56~COM63 COMM 160seg Partial Select (1/33 Duty) COM0~COM7 COM8~COM15 COM16~COM23 COM24~COM31 COM32~COM39 COM40~COM47 COM48~COM55 COM56~COM63 COMM 160seg
64com+1
32com+1
Active Display-block
Ver.2007-11-20
NJU6655
Internal Oscillation Circuit This setting effective when M/S="1" CLS="1". (z)NOP Operation.
Ver.2007-11-20
NJU6655
Example Instruction Setting (Reference) <Conditions> VDD=3V, 4-time booster, Using internal feedback resistor, Using internal oscillator, Using n-line inverse drive, Using 80-type I/F. Example Initialize Sequence VDD-VSS Power
Stabilizing Power Supply
VDD=3V, VSS=0V input
Reset Input WAIT
Instruction Setting
Refer (1-8) Reset circuit. Wait 1.5[us] more.
Segment driver S159 Normal display Bias Common direction Resistor Ratio Mode Register "1.0.0.0.0.0" Static indicator Static indicator n-line inverse 1/65 Duty Oscillation circuit Voltage converter "ON", Voltage Regulator "OFF, Voltage Follower "OFF" Voltage converter "ON", Voltage Regulator "ON, Voltage Follower "OFF" Voltage converter "ON", Voltage Regulator "ON, Voltage Follower "ON"
Select
Normal Inverse display
Bias Select
Common Direction Select Feedback Resistor Ratio Mode Register Static Indicator ON/OFF Static Indicator Register n-line Inverse Drive Register
Partial Select
Internal Oscillation Circuit
Power Control WAIT Note)
Power Control WAIT Note)
Power Control WAIT Note)
*:Don't Care
Note) Wait time stabilizing internal power supply differs external components (Cout, C1~C8), VDD, VLCD. Make sure what wait time particular application.
Ver.2007-11-20
NJU6655
Example Display Data Write Sequence Optional Status
Instruction Setting
Line address Page address page Column address (upper) Column address (lower) Writing display data Checker flag pattern
Initial Display Line Page Address Column Address
Write Display Data
(Other page requires from "Page Address Set") Display
Write Display Data Display ON/OFF
Example Power Supply Sequence
Optional Status
Display Sleep mode Voltage converter "OFF", Voltage Regulator "OFF, Voltage Follower "OFF"
Display ON/OFF Power Save Power Control
VDD-VSS
Ver.2007-11-20
NJU6655
Internal power circuits (3-1) Voltage converter voltage converter generates maximum boosted negative-voltage from voltage between VSS2. boosted voltage output from VOUT terminal. internal oscillator required operating when using this converter, because divided signal provided from oscillator used internal timing this circuit. boosted voltage between VOUT must exceed 18.0V. voltage converter requires external capacitors boosting shown below. boosted voltage VDD, VSS2 VDD=+3V VSS2=0V VOUT=-3V VOUT=-6V VOUT=-9V boost Example connecting capacitors boost VSS2 C1C1+ C3C2+ C2VOUT boost boost
boost VSS2 C1C1+
boost VSS2 C1C1+
C2VOUT
VOUT
Ver.2007-11-20
NJU6655
(3-2) Voltage Adjust Circuits voltage adjust circuits composed reference voltage circuit, 64-step E.V.R. feedback resistors. adjust circuits produces driving voltage terminal, using VOUT voltage supplied from internal booster. Using Internal Feedback Resistors contrast fine-tuned adjusting voltage through setting internal feedback resistors E.V.R. voltage calculated from foemula (1), where |V5| |VOUT|. VLCD VDD-V5 (1+(Rb/Ra)) VCON [VCON (EVR) (VREG)] (1+(Rb/Ra)) (EVR) VREG [EVR (n+99) 162] VLCD Driving Voltage Ra,Rb Feedback Resistors VCON Contrast Control Voltage E.V.R. Setting Value VREG Reference Voltage VCON (VREG EVR)
Internal
VLCD
VOUT Internal
Fig.3-1 Voltage adjust circuits (Using internal feedback resistors) VREG regulated voltage with temperature coefficient, follows. Temperature Coefficient 0.05[%/°C] (Typ.) VREG 2.15[V] (Typ.)
Internal Power Supply
adjusted 64-step setting 6-bit data into E.V.R. register, follows. E.V.R. Register (0,0,0,0,0,0) (0,0,0,0,0,1) (0,0,0,0,1,0) (1,1,1,1,0,1) (1,1,1,1,1,0) (1,1,1,1,1,1) E.V.R. Value (99/162) (100/162) (101/162) (160/162) (161/162) (162/162) VLCD Minimum Maximum
Ver.2007-11-20
NJU6655
ratio (Ra/Rb) selected options "Feedback Resistor set" instruction. Register Feedback Resistor (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 1+(Rb/Ra) VLCD Minimum Maximum
resistance feedback resistors certain amount error. impact contrast external feedback resistors should considered. Using External Feedback Resistors When IRS="L", voltage adjusted external feedback resistors. E.V.R. function applied combination, fine-tunes contrast through software. voltage calculated from formula (2), where |V5| |VOUT|. VLCD VDD-V5 (1+(Rb/Ra)) VCON [VCON (EVR) (VREG)] (1+(Rb/Ra)) (EVR) VREG [EVR (n+99) 162] VLCD Driving Voltage Ra,Rb Feedback Resistors VCON Contrast Control Voltage E.V.R. Setting Value VREG Reference Voltage VCON (VREG EVR)
External
VLCD
VOUT External
Fig.3-2 Voltage adjust circuits (Using external feedback resistors) When using either internal feedback resistors E.V.R. both, voltage generator buffer amplifiers must activated. terminal only used external feedback resistors. This must open when using internal feedback resistors.
Ver.2007-11-20
NJU6655
<Design example adjustable range Reference> Using external resistors(Not using variable resistor), VLCD=7V Power supply VDD=3.0V, VSS=0V E.V.R. register (D5,D4,D3,D2,D1,D0) (1,0,0,0,0,0) formula VLCD VDD-V5 (1+(Rb/Ra)) (EVR) VREG 7[V] (1+(Rb/Ra)) (131/162) 2.15 Rb/Ra 3.03
case current value sets 5uA, which flows Ra+Rb 1.4M formula (3), Ra+3.03Ra= 1.4M 347k Therefore, 1.4M 347k 1053k
adjustable range step voltage calculated follows formula (2). case setting E.V.R. register, VLCD =(1+(Rb/Ra)) (EVR) VREG =(1+3.03) [(99/162) 2.15] =5.29V case setting E.V.R. register, VLCD =(1+(Rb/Ra)) (EVR) VREG =(1+3.03) [(162/162) 2.15] =8.66V
VLCD Adjustable Range VLCD Step Voltage
(min.) (max.) 5.29 8.66[V] [mV]
case VDD=3V
Ver.2007-11-20
NJU6655
(3-3) Driving Voltage Generation Circuits driving bias voltage V1,V2,V3,V4 generated internally dividing VLCD (VLCD=VDD-V5) voltage with internal bleeder resistance. supplied driving circuits after impedance conversion with voltage follower circuit. shown Five capacitors required connect each driving voltage terminal voltage stabilizing. value capacitors determined depending actual panel display evaluation. Using internal Power Supply
VSS2 C1C1
Using external Power Supply
C1C1+
COUT
VOUT
VOUT
NJU6655
NJU6655
External Voltage Generator
Fig.4
Driving Voltage Generation Circuits
Short wiring sealed wiring terminal required high impedance terminal. Following connection VOUT required when external power supply using. (1): When VOUT=V5 (2): When VOUT=VSS
Reference value VLCD=VDD-V5=7.0 10.5V
~1.0uF ~1.0uF 0.47uF 232k 115k 1.053M
Ver.2007-11-20
COUT C1~C3, C4~C7
NJU6655
interface (4-1) Interface type selection NJU6655 interfaces with 8-bit bidirectional data serial (SI:D7). parallel serial interface determined condition terminal connecting level shown Table case serial interface, status data read operation impossible. Table.5 Type Parallel Serial Relation between terminal each terminal CS1b SI(D7) SCL(D6) CS1b Hi-Z CS1b "Hi-Z" Hi-impedance They should fixed "L".
Parallel Interface NJU6655 interfaces type directly when parallel interface (P/S="H") selected. type determined condition terminal connecting shown Table Table.6 Type type type Relation between terminal each terminal CS1b CS1b CS1b
(4-2) Discrimination Data Signal NJU6655 discriminates mean signal data combination R/W, (RDb,WRb) signals shown Table Table.7 Relation between terminal 68/80 type terminal type Function Read Display Data Write Display Data Status Read Write into Register(Instruction)
Common
type
Ver.2007-11-20
NJU6655
(4-3) Serial Interface (P/S="L") Serial interface circuits consist bits shift register bits counter. input activated when chip select terminal CS1b "L", "H"and terminal "L". bits shift register bits counter reset initial condition when chip selected. data input from terminal first like order D7,D6,- data entered into shift register synchronizing with rise edge serial clock SCL. data shift register converted parallel data serial clock rise edge input. Discrimination display data instruction serial input data executed condition serial clock rise edge. A0="H" display data A0="L" instruction. When RESb terminal becomes CS1b terminal becomes (CS2 terminal becomes "L") before serial clock rise edge, NJU6655 recognizes them instruction data incorrectly. Therefore unit serial data must structured 8-bit. time chart serial interface shown Fig. avoid noise trouble, short wiring required input. Note) read function, such status data read out, supported this serial interface.
CS1b
Fig.5
Signal chart serial interface
Ver.2007-11-20
NJU6655
(4-4) Access Display Data Internal Register NJU6655 operating pipe-line processor bus-holder connecting internal data adjust operation frequency between Display Data Internal Register. example, when reads data from Display Data RAM, read data data read cycle (dummy read) held bus-holder, then read from bus-holder system next data read cycle. When writes data into Display Data RAM, data held bus-holder, then written into Display Data next data write cycle. Therefore high speed data transmission between NJU6655 available because limited tACC display data access time limited system cycle time (W). cycle time kept operation, should inserted system instead waiting operation. read operation does read data pointed address just after address operation. second read operation read data correctly from pointed address. Therefore, dummy read operation required after address setting write cycle shown Fig. example Read Modify Write operation mentioned (2-1) Instruction (l)The sequence inverse display. Write Operation DATA Internal Timing holder Read Operation DATA Internal Timing Address Column address holder Fig.6 Dummy read Data read Data read
Relation between display data write/read internal timing
(4-5) Chip select CS1b, Chip Select terminals. case CS1b="L" CS2="H", interface with available. case CS1b="H" CS2="L", high impedance RDb, WRb, D7(SI) D6(SCL) inputs ignored. serial interface selected when CS1b="H" CS2="L", shift register counter reset. However, reset always operated conditions CS1b CS2.
Ver.2007-11-20
NJU6655
ABSOLUTE MAXIMUMN RATINGS
PARAMETER Supply Voltage Supply Voltage (When using voltage converter) (When using voltage converter) Supply Voltage Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature (Chip) SYMBOL Vss2 V5,VOUT V1,V2,V3,V4 VOUT Topr Tstg RATINGS -0.3 +7.0 -7.0 +0.3 -6.0 +0.3 -4.5 +0.3 -18.0 +0.3 +0.3 -0.3 -0.3 +125 (Ta=25°C) UNIT
VSS2,
Note VSS2, VOUT voltage values specified Note relation VDD>V1>V2>V3>V4>V5>VOUT VDD>VSS>VOUT must maintained. case inputting external driving voltage, drive voltage should start supplying NJU6655 mean time turning power supply after turned VDD. voltage boost circuit, condition that supply voltage >VDD-VOUT necessary. Note used condition beyond absolute maximum rating, destroyed. Using within electrical characteristics strongly recommended normal operation. beyond electric characteristics conditions will cause malfunction poor reliability. Note Decoupling capacitor should connected between stabilized operation voltage converter.
Ver.2007-11-20
NJU6655
Electrical Characteristics
PARAMETER Power Supply Power Supply Power Supply
SYMBOL
VSS2 V1,V2 V3,V4 VIHC1 VILC1 VOHC1 VOLC1 RON1 RON2 ISSQ fOSC VSS2 VOUT RQUAD VOUT2 IDDQ1 IDDQ2 IDD1 IDD2
CONDITIONS Recommend Possible common common common
Level Input Voltage Level Input Voltage Level Output Voltage Level Output Voltage
Leakage Current Driver On-resistance Stand-by Current
Output Leakage Current
Input Terminal Capacitance
IOH=-0.5mA IOL= 0.5mA input terminals terminals, Hi-Z state Ta=25°C V5=-14.0V V5=-8.0V V5=-18.0V (VDD common) Ta=25°C VDD=3V,Ta=25°C External input common, 3-times boost common, 4-times boost common 4-times boost, C1-C3, COUT=1uF VDD=3V, VSS=VSS2 Voltage boost operation External power supply Voltage adjustment circuit External power supply Power save mode (Sleep mode) Power save mode (Standby mode) VDD=3V, V5=-11V COM/SEG open, Without access, Checker flag display Ta=25°C VDD=3V
Oscillation Frequency
Display Clock Frequency
(VDD=2.4 3.6V, VSS=0V, 85°C) UNIT NOTE -6.0 -2.4 -4.5 0.4V5 0.6V5 0.8VDD 0.2VDD 0.8VDD 0.2VDD -1.0 -3.0 0.01 0.01 17.0 20.8 24.6 4.25 -6.0 -4.5 -18.0 5.20 0.01 2.04 2.15 -0.05 6.15 -2.4 -2.4 -6.0 -4.5 2.26 %/°C
Input Voltage Output Voltage On-resistance Adjustment Range Driving Voltage Voltage Follower Operating Voltage Operating current
-18.0 -18.0
Voltage Booster
Reference Voltage Temperature Coefficient
VREF
Note Although NJU6655 operate wide range operating voltage, shall guaranteed sudden voltage fluctuation during access with MPU. Note resistance values supplying 0.1V voltage-difference between power supply terminals (V1,V2,V3,V4) each output terminals (common segment). This specified within range Operating Voltage (2). Note Apply RDb, WRb, CS1b, CS2, RESb, terminals. Note voltage adjustment circuit controls within range voltage follower operating voltage. Note Each operating current shall defined being measured following condition.
Ver.2007-11-20
NJU6655
Symbol IDD1 IDD2
Power Control
Voltage converter
Operating Condition Voltage regulator
Voltage followers
External Voltage Supply (Input Terminal) Use(VSS2) Use(VOUT,V1V5)
measurement circuits: :IDD1
NJU6655
C2C3-
VOUT
:IDD2
NJU6655
C2C3VOUT
Ver.2007-11-20
NJU6655
TIMING CHARACTERISTICS
Read Write characteristics type MPU) CS2=H (1)CS1b (2)WRb,RDb tAW8 (1)WRb,RDb (2)CS1b tCCH tCCL tDS8 (Write) tACC8 (Read) tDH8 tOH8
tCYC8
tAH8
PARAMETER Address Hold Time Address Time System Cycle Time Control Pulse Width (WRb) Control Pulse Width (RDb) Control Pulse Width (WRb) Control Pulse Width (RDb) Data Time Data Hold Time Access Time Output Disable Time Input Signal Rising, Falling Edge
(VSS=0V, VDD=2.4 3.6V, Ta=-40 85°C) TERMINAL SYMBOL CONDITION UNIT A0,CS1b tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 CL=100pF tOH8 CS1b,CS2, WRb,RDb, A0,D0
Note Each timing specified based 0.2xVDD 0.8xVDD. Accessed signal when CS1b="L". Accessed CS1b signal when ="L".
Ver.2007-11-20
NJU6655
Read Write characteristics type MPU) CS2=H (1)E (2)CS1b (1)CS1b (2)E tEWL tAW6 tEWH tAH6 tCYC6
A0,R/W tDS6 (Write) tACC6 (Read) tOH6 tDH6
PARAMETER Address Hold Time Address Time System Cycle Time Enable Pulse Width (Read) Enable Pulse Width (Write) Enable Pulse Width (Read) Enable Pulse Width (Write) Data Time Data Hold Time Access Time Output Disable Time Input Signal Rising, Falling Edge
(VSS=0V, VDD=2.4 3.6V, Ta=-40 85°C) TERMINAL SYMBOL CONDITION UNIT A0,CS1b tAH6 tAW6 tCYC6 tEWHR E(RDb) tEWHW tEWLR tEWLW tDS6 tDH6 tACC6 CL=100pF tOH6 E(RDb), R/W(WRb), A0,D0
Note Each timing specified based 0.2xVDD 0.8xVDD. Accessed signal when CS1b="L". Accessed CS1b signal when ="L".
Ver.2007-11-20
NJU6655
Write characteristics (Serial interface) CS2=H CS1b tSAS tSCYC tSLW tSHW tSDS tSDH tSAH
tCSS
tCSH
PARAMETER Serial Clock Cycle Pulse Width Pulse Width Address Time Address Hold Time Data Time Data Hold Time CS1b-SCL Time Input Signal Rising, Falling Edge
(VSS=0V, VDD=2.4 3.6V, Ta=-40 85°C) UNIT TERMINAL SYMBOL CONDITION tSCYC SCL(D6) tSHW tSLW tSAS tSAH tSDS SI(D7) tSDH tCSS CS1b,CS2 tCSH SCL(D6),A0, CS1b,CS2, tr,, SI(D7)
Note Each timing specified based 0.2xVDD 0.8xVDD.
Ver.2007-11-20
NJU6655
Display control timing characteristics (OUT) tDFR tDSNC SYNC
PARAMETER Delay Time SYNC Delay Time
(VSS=0V, VDD=2.4 3.6V, Ta=-40 85°C) TERMINAL SYMBOL CONDITION UNIT tDFR CL=50pF SYNC tDSNC CL=50pF
Note Each timing specified based 0.2xVDD 0.8xVDD. (The delay time applied master operation only.) Reset input timing RESb Internal circuit status During reset reset
(VSS=0V, VDD=2.4 3.6V, Ta=-40 85°C) TERMINAL SYMBOL CONDITION UNIT PARAMETER Reset Time Reset Level Pulse RESb Width Note Each timing specified based 0.2xVDD 0.8xVDD.
Ver.2007-11-20
NJU6655
DRIVING WAVEFORM
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
Ver.2007-11-20
NJU6655
APPLICATION CIRCUIT
Microprocessor Interface Example NJU6655 interfaces type type directly. serial interface also communicate with MPU. terminal must fixed VSS. Type
A1~A7
CS1b
IORQ
Decoder
NJU6655
D0~D7
D0~D7 RESb
RESET
Type
A1~A15
CS1b
Decoder
NJU6655
D0~D7
D0~D7 RESb
RESET
Serial Interface
A1~A7
CS1b
Decoder
NJU6655
Port Port RESET
RESb
Ver.2007-11-20
NJU6655
dots Driving Application Circuits Example (Common Segment Drivers Extension using NJU6655)
Panel
NJU6655 Master SYNC DOFb SYNC DOFb
NJU6655 Slave
[CAUTION] specifications this databook only given information without guarantee regards either mistakes omissions. application circuits this databook described only show representative usages product intended guarantee permission right including industrial rights.
Ver.2007-11-20

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