FLASH MEMORY CMOS (512K MBM29F040C-55/-70/-90 FEAT

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FLASH MEMORY CMOS (512K MBM29F040C-55/-70/-90 FEAT

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DS05-20842-4E
FLASH MEMORY
CMOS
(512K
MBM29F040C-55/-70/-90
FEATURES
Single read, program erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: 32-pin TSOP(I) (Package suffix: 32-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type) Minimum 100,000 write/erase cycles High performance maximum access time Sector erase architecture equal size sectors bytes each combination sectors concurrently erased. Also supports full chip erase. Embedded EraseAlgorithms Automatically pre-programs erases chip sector Embedded ProgramAlgorithms Automatically writes verifies data specified address Data Polling Toggle feature detection program erase cycle completion write inhibit Sector protection Hardware method disables combination sectors from write erase operations Erase Suspend/Resume Suspends erase operation allow read data another sector within same device
Embedded EraseTM, Embedded Programand ExpressFlashare trademarks Advanced Micro Devices, Inc.
MBM29F040C-55/-70/-90
PACKAGE
32-pin Plastic (PLCC) Marking Side
(LCC-32P-M02) 32-pin Plastic TSOP Marking Side 32-pin Plastic TSOP
Marking Side (FPT-32P-M24 Assembly: Malaysia) (FPT-32P-M25 Assembly: Malaysia)
MBM29F040C-55/-70/-90
GENERAL DESCRIPTION
MBM29F040C 4M-bit, V-only Flash memory organized 512K bytes bits each. MBM29F040C offered 32-pin PLCC 32-pin TSOP(I) package. This device designed programmed in-system with standard system supply. 12.0 required write erase operations. device also reprogrammed standard EPROM programmers. standard MBM29F040C offers access times allowing operation high-speed microprocessors without wait states. eliminate contention device separate chip enable (CE), write enable (WE), output enable (OE) controls. MBM29F040C command compatible with JEDEC standard E2PROMs. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 Flash EPROM devices. MBM29F040C programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Typically, each sector programmed verified less than seconds. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. individual sector typically erased verified second. already completely preprogrammed.) device also features sector erase architecture. sector mode allows byte sectors memory erased reprogrammed without affecting other sectors. MBM29F040C erased when shipped from factory. device features single power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations loss power. program erase detected Data Polling Toggle feature DQ6. Once program erase cycle been completed, device internally resets read mode. Fujitsu's Flash technology combines years EPROM E2PROM experience produce highest levels quality, reliability cost effectiveness. MBM29F040C memory electrically erases entire chip bits within sector simultaneously Fowler-Nordheim tunneling. bytes programmed byte time using EPROM programming mechanism electron injection.
MBM29F040C-55/-70/-90
FLEXIBLE SECTOR-ERASE ARCHITECTURE
Byte sector Individual-sector, multiple-sector, bulk-erase capability Individual multiple-sector protection user definable 7FFFFH 6FFFFH 5FFFFH byte sector 4FFFFH 3FFFFH 2FFFFH 1FFFFH 0FFFFH 00000H
MBM29F040C-55/-70/-90
PRODUCT LINE
Part Ordering Part ±10% Max. Address Access Time (ns) Max. Access Time (ns) Max. Access Time (ns) MBM29F040C
BLOCK DIAGRAM
Erase Voltage Generator Input/Output Buffers
State Control Command Register Program Voltage Generator Chip Enable Output Enable Logic Data Latch
Y-Decoder
Y-Gating
Detector
Timer Program/Erase
Address Latch
X-Decoder
Cell Matrix
MBM29F040C-55/-70/-90
CONNECTION DIAGRAMS
PLCC
LCC-32P-M02 TSOP
Marking Side
MBM29F040C Standard Pinout
FPT-32P-M24
Marking Side
MBM29F040C Reverse Pinout
FPT-32P-M25
MBM29F040C-55/-70/-90
LOGIC SYMBOL
Table
MBM29F040C Configuration Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Device Ground Device Power Supply
Table Operation
MBM29F040C User Operations Code Code DOUT HIGH-Z HIGH-Z Code
Auto-Select Manufacturer Code Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Protection Verify Sector Protection Legend: VIL, VIH, VIH,
Pulse Input. Characteristics voltage levels.
Notes: Manufacturer device codes also accessed command register write sequence. Table Refer section Sector Protection. VIL, initiates write operations.
MBM29F040C-55/-70/-90
ORDERING INFORMATION Standard Products
Fujitsu standard products available several packages. order number formed combination
MBM29F040
PACKAGE TYPE =32-Pin Rectangular Plastic Leaded Chip Carrier (PLCC) PFTN 32-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR =32-Pin Thin Small Outline Package (TSOP) Reverse Pinout SPEED OPTION Product Selector Guide
Device Revision DEVICE NUMBER/DESCRIPTION MBM29F040 4Mega-bit (512K 8-Bit) CMOS Flash Memory V-only Read, Program, Erase Byte Sectors
MBM29F040C-55/-70/-90
FUNCTIONAL DESCRIPTION Read Mode
MBM29F040C control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins (assuming addresses have been stable least tACC-tOE time).
Standby Mode
MBM29F040C standby modes, CMOS standby mode input held ±0.3 V.), when current consumed less than standby mode held VIH) when current required reduced approximately During Embedded Algorithm operation, Active current (ICC2) required even VIH. device read with standard access time (tCE) from either these standby modes. standby mode outputs high impedance state, independent input. device deselected during erasure programming, device will draw active current until operation completed.
Output Disable
With input logic high level (VIH), output from device disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from device will identify manufacturer type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate this mode, programming equipment must force (11.5 12.5 address identifier bytes then sequenced from device outputs toggling address from VIH. addresses DON'T CARES except (Recommend other pins.) manufacturer device codes also read command register, instances when MBM29F040C erased programmed system without access high voltage pin. command sequence illustrated Table (Refer Autoselect Command section.) Byte VIL) represents manufacture's code (Fujitsu 04H) byte VIH) represents device identifier code (MBM29F040C A4H). These bytes given Table identifiers manufactures device will exhibit parity with (DQ7) defined parity bit. order read proper device codes when executing autoselect, must VIL. (See Table
MBM29F040C-55/-70/-90
Table Type Manufacture's Code Device Code Sector Protection MBM29F040C Sector Protection Verify Autoselect Codes Code (HEX) 01H*
Sector Addresses
Outputs protected sector addresses unprotected sector addresses. Table Sector Address Sector Address Tables Address Range 00000H 0FFFFH 10000H 1FFFFH 20000H 2FFFFH 30000H 3FFFFH 40000H 4FFFFH 50000H 5FFFFH 60000H 6FFFFH 70000H 7FFFFH
Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge whichever happens first. Standard microprocessor write timings used. Refer Write Characteristics Erase/Programming Waveforms specific timing parameters.
Sector Protection
MBM29F040C features hardware sector protection. This feature will disable both program erase operations number sectors through sector protection feature enabled using programming equipment user's site. device shipped with sectors unprotected. activate this mode, programming equipment must force address control (suggest 11.5 VIH. sector addresses (A18, A16) should sector protected. Table defines sector address each eight individual sectors. Programming protection circuitry begins falling edge pulse terminated with rising edge same. Sector addresses must held constant during pulse. figures sector protection waveforms algorithm.
MBM29F040C-55/-70/-90
verify programming protection circuitry, programming equipment must force address with VIH. Scanning sector addresses (A16, A18) while (A6, will produce logical code device output protected sector. Otherwise device will read unprotected sector. this mode, lower order addresses, except DON'T CARES. Address locations with reserved Autoselect manufacturer device codes. also possible determine sector protected system writing Autoselect command. Performing read operation address location XX02H, where higher order addresses (A16, A18) sector address will produce logical protected sector. Table Autoselect codes. Table Command Sequence Read/Reset Read/Reset* Read/Reset* Autoselect Byte Program Chip Erase Sector Erase
Write Cycles Req'd
MBM29F040C Command Definitions
Fifth Sixth First Second Third Fourth Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data XXXH 555H 555H 555H 555H 555H 2AAH 2AAH 2AAH 2AAH 2AAH 555H 555H 555H 555H 555H 2AAH 2AAH 555H
555H 555H
Sector Erase Suspend Sector Erase Resume
Erase suspended during sector erase with Addr ("H" "L"). Data (B0H) Erase resumed after suspend with Addr ("H" "L"). Data (30H)
Notes: Address bits address commands except Program Address (PA) Sector Address (SA). operations defined Table Address memory location read. Address memory location programmed. Addresses latched falling edge pulse. Address sector erased. combination A18, A17, will uniquely select sector. Data read from location during read operation. Data programmed location Data latched falling edge Either reset commands will reset device.
Command Definitions
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Table defines valid register command sequences. Note that Erase Suspend (B0H) Erase Resume (30H) commands valid only while Sector Erase operation progress. Moreover, both Read/ Reset Commands functionally equivalent, resetting device read mode.
MBM29F040C-55/-70/-90
Read/Reset Command
read reset operation initiated writing Read/Reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until command register contents altered. device will automatically power-up read/reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufacture device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage (VID 11.5 12.5). However, multiplexing high voltage onto address lines generally desired system design practice. device contains Autoselect command operation supplement traditional PROM programming methodology. operation initiated writing Autoselect command sequence into command register. Following command write, read cycle from address XX00H retrieves manufacture code 04H. read cycle from address XX01H returns device code A4H. (see Table manufacturer device codes will exhibit parity with (DQ7) defined parity bit. Sector state (protection unprotection) will informed address XX02H. Scanning sector addresses (A16, A17, A18) while (A6, will produce logical device output protected sector. programming verification should perform margin mode protected sector. (See Table terminate operation, necessary write Read/Reset command sequence into register, also write Autoselect command during operation, execute after writing Read/Reset command sequence.
Byte Programming
device programmed byte-by-byte basis. Programming four cycle operation. There "unlock" write cycles. These followed program setup command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence, system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. automatic programming operation completed when data equivalent data written this (See Write Operation Status section.) which time device returns read mode addresses longer latched. (See Table Hardware Sequence Flags.) Therefore, device requires that valid address device supplied system this particular instance time. Hence, Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting either hang device (Exceed timing limits.), result apparent success according data polling algorithm read from reset/read mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded ProgramAlgorithm using typical command strings operations.
MBM29F040C-55/-70/-90
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence device will automatically program verify entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. automatic erase begins rising edge last pulse command sequence terminates when data (see Write Operation Status section.) which time device returns read mode. Figure illustrates Embedded Erase Algorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed Sector Erase command. sector address (Any address location within desired sector.) latched falling edge while command (Data 30H) latched rising edge time-out from rising edge last sector erase command will initiate sector erase command(s). Multiple sectors erased concurrently writing cycle operations described above. This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than otherwise that command will accepted. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out from rising edge last will initiate execution Sector Erase command(s). another falling edge occurs within time-out window timer reset. (Monitor determine sector erase timer window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this time-out period will reset device read mode, ignoring previous command string. Resetting device once execution begun will corrupt data sector. that case, restart erase those sectors allow them complete. (Refer Write Operation Status section Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors Sector erase does require user program device prior erase. device automatically programs memory locations sector(s) erased prior electrical erase. When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. automatic sector erase begins after time from rising edge pulse last sector erase command pulse terminates when data (See Write Operation Status section.) which time device returns read mode. During execution Sector Erase command, only Erase Suspend Erase Resume commands allowed. other commands will reset device read mode. Data polling must performed address within sectors being erased. Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
MBM29F040C-55/-70/-90
Erase Suspend
Erase Suspend command allows user interrupt Sector Erase operation then perform data reads from programs sector being erased. This command applicable ONLY during Sector Erase operation which include time-out period sector erase. Erase Suspend command will ignored written during Chip Erase operation Embedded Program Algorithm. Writting Erase Suspend command during Sector Erase time-out results immediate termination time-out period suspension erase operation. other command written during Erase Suspend mode will ignored except Erase Resume command. Writing Erase Resume command resumes erase operation. addresses "DON'T CARES" when writing Erase Suspend Erase Resume command. When Erase Suspend command written during Sector Erase operation, device will take maximum suspend erase operation. When devices have entered erase-suspended mode, will logic "1", will stop toggling. user must address erasing sector reading determine erase operation been suspended. Further writes Erase Suspend command ignored. When erase operation been suspended, devices default erase-suspend-read mode. Reading data this mode same reading from standard read mode except that data must read from sectors that have been erase-suspended. Successively reading from erase-suspended sector while device erase-suspend-read mode will cause toggle. (See section DQ2.) After entering erase-suspend-read mode, user program device writing appropriate command sequence Program. This Program mode known erase-suspend-program mode. Again, programming this mode same programming regular Program mode except that data must programmed sectors that erase-suspended. Successively reading from erase-suspended sector while devices erase-suspend-program mode will cause toggle. erasesuspended Program operation detected Data polling DQ7, Toggle (DQ6) which same regular Program operation. Note that must read from Program address while read from address. resume operation Sector Erase, Resume command (30H) should written. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed erasing.
MBM29F040C-55/-70/-90
Write Operation Status
Table Status Embedded Program Algorithm Embedded Erase Algorithm Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program Non-Erase Suspended Sector) Embedded Program Algorithm Program/Erase Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode Hardware Sequence Flags Data Toggle Toggle Data Toggle (Note Toggle Toggle Toggle Data Data Toggle Toggle Data (Note
Notes: Performing successive read operations from address will cause toggle. Reading byte address being programmed while erase-suspend program mode will indicate logic bit. However, successive reads from erase-suspended sector will cause toggle. reserve pins future use. Fujitsu internal only.
Data Polling MBM29F040C device features Data Polling method indicate host that Embedded Algorithms progress completed. During Embedded Program Algorithm attempt read device will produce compliment data last written DQ7. Upon completion Embedded Program Algorithm, attempt read device will produce true data last written DQ7. During Embedded Erase Algorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce output. flowchart Data Polling (DQ7) shown Figure chip erase, sector erase Data Polling valid after rising edge sixth pulse write pulse sequence. sector erase, Data Polling valid after last rising edge sector erase pulse. Data Polling must performed sector address within sectors being erased protected sector. Otherwise, status valid. Once Embedded Algorithm operation close being completed, MBM29F040C data pins (DQ7) change asynchronously while output enable (OE) asserted low. This means that device driving status information instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Algorithm operation valid data, data outputs still invalid. valid data will read successive read attempts. Data Polling feature only active during Embedded Programming Algorithm, Embedded Erase Algorithm, sector erase time-out. (See Table Figure Data Polling timing specifications diagrams.
MBM29F040C-55/-70/-90
Toggle MBM29F040C also features "Toggle method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from device will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempts. During programming, Toggle valid after rising edge fourth pulse four write pulse sequence. chip erase sector erase, Toggle valid after rising edge sixth pulse write pulse sequence. Toggle active during sector time out. programming, sector being written protected, toggle will toggle about then stop toggling without data having changed. erase, device will erase selected sectors except ones that protected. selected sectors protected, chip will toggle toggle about then drop back into read mode, having changed none data. Either toggling will cause toggle. addition, Erase Suspend/Resume command will cause toggle. Figure Toggle timing specifications diagrams.
Exceeded Timing Limits will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling DQ7, only operating function device under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described Table failure condition also appear user tries program blank location without erasing. this case device locks never completes Embedded Algorithm operation. Hence, system never reads valid data never stops toggling. Once device exceeded timing limits, will indicate "1." Please note that this device failure condition since device incorrectly used. this occurs, reset device with command sequence.
Sector Erase Timer After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command. used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent sector erase command. were high second status check, command have been accepted. Refer Table Hardware Sequence Flags.
MBM29F040C-55/-70/-90
Toggle This Toggle along with DQ6, used determine whether devices Embedded Erase Algorithm Erase Suspend. Successive reads from erasing sector will cause toggle during Embedded Erase Algorithm. devices erase-suspended-read mode, successive reads from erase-suspended sector will cause toggle. When devices erase-suspended-program mode, successive reads from byte address non-erase suspended sector will indicate logic bit. different from that toggles only when standard program Erase, Erase Suspend Program operation progress. behavior these status bits, along with that DQ7, summarized follows: Mode Program Erase Erase Suspend Read (Erase-Suspended Sector) (Note Erase Suspend Program (Note toggles toggles toggles toggles toggles (Note
Notes: These status flags apply when outputs read from sector that been erase-suspended. These status flags apply when outputs read from byte address non-erase suspended sector.
Data Protection
MBM29F040C designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power device automatically resets internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequences. device also incorporates several features prevent inadvertent write cycles resulting form power-up power-down transitions system noise.
Write Inhibit
avoid initiation write cycle during power-up power-down, write cycle locked less than (typically VLKO, command register disabled internal program/erase circuits disabled. Under this condition device will reset read mode. Subsequent writes will ignored until level greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Logical Inhibit
Writing inhibited holding VIL, VIH, VIH. initiate write cycle must logical zero while logical one.
MBM29F040C-55/-70/-90
Power-Up Write Inhibit
Power-up device with will accept commands rising edge internal state machine automatically reset read mode power-up.
MBM29F040C-55/-70/-90
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -55°C +125°C Ambient Temperature with Power Applied -40°C +85°C Voltage with Respect Ground pins except (Note -2.0 +7.0 (Note -2.0 +7.0 (Note -2.0 +13.5 Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs negative overshoot -2.0 periods Maximum voltage output pins +0.5 During voltage transitions, outputs positive overshoot +2.0 periods Minimum input voltage pins -0.5 During voltage transitions, pins negative overshoot -2.0 periods Maximum input voltage pins +13.5 which overshoot 14.0 periods WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING RANGES
Ambient Temperature (TA) -40°C +85°C Supply Voltages MBM29F040C-55. +4.75 +5.25 MBM29F040C-70/-90 +4.50 +5.50 Operating ranges define those limits between which functionality device guaranteed. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
MBM29F040C-55/-70/-90
MAXIMUM OVERSHOOT
+0.8 -0.5 -2.0
Figure
Maximum Negative Overshoot Waveform
VCC+2.0 VCC+0.5 +2.0
Figure
Maximum Positive Overshoot Waveform
+14.0 +13.0 VCC+0.5
This waveform applied
Figure
Maximum Positive Overshoot Waveform
MBM29F040C-55/-70/-90
CHARACTERISTICS
Parameter Symbol ILIT ICC1 ICC2 ICC3 VOH1 Output High Voltage Level VOH2 VLKO Lock-Out Voltage -100 VCC-0.4 Parameter Description Input Leakage Current Output Leakage Current Input Leakage Current Active Current (Note Active Current (Note Current (Standby) Max., VCC±0.3 Input Level Input High Level Voltage Autoselect Sector Protection (A9, (Note Output Voltage Level 12.0 -2.5 -0.5 11.5 VCC+0.3 12.5 0.45 Test Conditions VCC, VOUT VCC, Max., 12.0 VIL, VIL, Max., Min. Max. ±1.0 ±1.0 Unit
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically mA/MHz, with VIH. active while Embedded Algorithm (program erase) progress. Applicable sector protection function. (VID VCC) exceed
MBM29F040C-55/-70/-90
CHARACTERISTICS
Read Only Operations Characteristics Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tACC Read Cycle Time Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output HIGH-Z Output Enable Output HIGH-Z Output Hold Time From Addresses, Whichever Occurs First Min. Max. Max. Max. Max. Max. Min. (Note1) (Note2) (Note2) Unit
Description
Test Setup
Note: Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: to3.0 Timing measurement reference level Input: Output:
Note: Test Conditions: Oput Load: gate Input rise fall times: Input pulse levels: 0.45 Timing measurement reference level Input: Output:
IN3064 Equivalent Device Under Test Diodes IN3064 Equivalent
Note: 1.CL including capacitance 2.CL including capacitance Figure Test Conditions
MBM29F040C-55/-70/-90
Write/Erase/Program Operations
Parameter Symbols
MBM29F040C Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. Max. Min. Min. Min. Min. Min. Max. Unit
JEDEC Standard tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 tOES tOEH tGHWL tGHEL tWPH tCPH
Read Recover Time Before Write Read Recover Time Before Write Setup Time Setup Time Hold Time Hold Time Write Pulse Width Pulse Width Write Pulse Width High Pulse Width High
tWHWH1 Byte Programming Operation tWHWH2 Sector Erase Operation (Note tVCS tVLHT tWPP tOESP tCSP tEOE Setup Time Voltage Transition Time (Notes Write Pulse Width (Note Setup Time Active (Note Setup Time Active (Note Delay Time from Embedded Output Enable
Notes: This does include preprogramming time. This timing only Sector Protect operations.
MBM29F040C-55/-70/-90
SWITCHING WAVEFORMS
Switching Waveforms
WAVEFORM INPUTS Must Steady Change from Change from Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing State Unknown Center Line HighImpedance "Off" State
Addresses tACC Addresses Stable
tOEH
High-Z Output Valid High-Z
Outputs
Figure
Waveforms Read Operations
MBM29F040C-55/-70/-90
Cycle Addresses
555H
Data Polling
tGHWL
tWPH
tWHWH1
DOUT DOUT
Data
5.0V
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure
Waveforms Alternate Controlled Program Operations
MBM29F040C-55/-70/-90
Cycle
Data Polling
Addresses
555H
tGHEL
tCPH Data
tWHWH1
DOUT
5.0V
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure
Waveforms Alternate Controlled Program Operations
MBM29F040C-55/-70/-90
Addresses
555H 2AAH 555H 555H 2AAH
tGHWL
tWPH Data
10H/30H
tVCS
sector address Sector Erase. Addresses 555H Chip Erase
Figure
Waveforms Chip/Sector Erase Operations
MBM29F040C-55/-70/-90
tOEH
Data Valid Data
High-Z
tWHWH1
Data Output Flag
Valid Data
High-Z
tEOE
Valid Data (The device completed Embedded operation.) Figure Waveforms Data Polling during Embedded Algorithm Operations
tOEH tOES
Data
Toggle
Toggle
Stop Toggling
Valid
stops toggling (The device completed Embedded operation). Figure Waveforms Toggle during Embedded Algorithm Operations
MBM29F040C-55/-70/-90
tVLHT tWPP tOESP tCSP tVLHT tVLHT tVLHT
Data tVCS
Sector Address initial sector Sector Address next sector
Figure
Waveforms Sector Protection Timing Diagram
MBM29F040C-55/-70/-90
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Toggle with
Note: read from erase-suspended sector. Figure
MBM29F040C-55/-70/-90
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See below)
Data Polling Device
Increment Address
Last Address
Programming Completed
Program Command Sequence (Address/Command)
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
Figure
Embedded ProgramAlgorithm
MBM29F040C-55/-70/-90
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequece (See below) Data Polling Toggle Successfully Completed
Erasure Completed Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555H/AAH
Chip Erase Command Sequence (Address/Command): 555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands optional.
Sector Address/30H
Figure
Embedded EraseAlgorithm
MBM29F040C-55/-70/-90
Start
Read Byte (DQ0 DQ7) Addr.
Data Read Byte (DQ0 DQ7) Addr.
Byte address programming sector addresses within sector being erased during sector erase multiple sector erases operation. sector addresses within sector being protected during sector erase multiple sector erases operation.
Data Fail
Pass
Note: rechecked even because change simultaneously with DQ5.
Figure
Data Polling Algorithm
MBM29F040C-55/-70/-90
Start
Read Byte (DQ0 DQ7) Addr.
Toggle Read Byte (DQ0 DQ7) Addr.
Toggle Fail
Pass
Note: rechecked even because stop toggling same time changing "1".
Figure
Toggle Algorithm
MBM29F040C-55/-70/-90
Start
Setup Sector Addr. (A18, A17, A16)
PLSCNT
VID, VID,
Activate Pulse
Increment PLSCNT
Time
VIH, should remain VID)
Read from Sector Addr. PLSCNT Remove from Write Reset Command Data 01H? Protect Another Sector Device Failed Remove from Write Reset Command
Sector Protection Completed
Figure
Sector Protection Algorithm
MBM29F040C-55/-70/-90
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Min. Sector Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycle 100,000 Typ. Max. cycles Excludes programming prior erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
TSOP(I) CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Typ. Max. Unit
Note: Test conditions 25°C,
PLCC CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Typ. Max. Unit
Note: Test conditions 25°C,
MBM29F040C-55/-70/-90
PACKAGE DIMENSIONS
32-pin plastic QFJ(PLCC) (LCC-32P-M02)
12.37±0.13 (.487±.005) 11.43±0.08 (.450±.003)
3.40±0.16 (.134±.006) 2.25±0.38 (.089±.015) 0.64(.025)
7.62(.300)REF 1.27±0.13 (.050±.005)
INDEX 13.97±0.08 14.94±0.13 (.550±.003) (.588±.005) 12.95±0.51 (.510±.020) 10.16(.400)
R0.95(.037)
0.66(.026) 0.20 -0.02 +.002 .008 -.001 0.43(.017) 10.41±0.51 (.410±.020)
+0.05
0.10(.004)
1994 FUJITSU LIMITED C32021S-2C-4
Dimensions mm(inches)
(Continued)
MBM29F040C-55/-70/-90
32-pin plastic TSOP(I) (FPT-32P-M24)
LEAD
Details part 0.15(.006) 0.35(.014)
INDEX
0.15(.006)
0.25(.010)
0.15±0.05 (.006±.002) 20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008) 0.50(.0197) 0.50±0.10 (.020±.004) 8.00±0.20 (.315±.008)
0.05(.002)MIN (STAND OFF) 1.10 -0.05 .043 -.002
(Mounting Height)
+0.10 +.004
0.10(.004) 19.00±0.20 (.748±.008)
7.50(.295) REF. 0.20±0.10 (.008±.004)
0.10(.004)
1994 FUJITSU LIMITED F32035S-2C-1
Dimensions mm(inches)
(Continued)
MBM29F040C-55/-70/-90
(Continued)
32-pin plastic TSOP(I) (FPT-32P-M25)
LEAD
Details part 0.15(.006) 0.35(.014)
INDEX
0.15(.006)
0.25(.010)
0.20±0.10 (.008±.004) 0.15±0.05 (.006±.002) 19.00±0.20 (.748±.008) 0.10(.004) 0.50±0.10 (.020±.004) 0.50(.0197) 7.50(.295) REF.
0.10(.004)
0.05(.002)MIN (STAND OFF)
18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008)
1.10 -0.05 .043 -.002 8.00±0.20 (.315±.008)
(Mounting Height)
+0.10
+.004
1997 FUJITSU LIMITED F32036S-2C-2
Dimensions mm(inches)
MBM29F040C-55/-70/-90
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inhereut chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
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F9903 FUJITSU LIMITED Printed Japan

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