ASSP Video Applications CMOS 8-bit MSPS Converter MB40C

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ASSP Video Applications CMOS 8-bit MSPS Converter MB40C

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DS04-28218-1E
ASSP Video Applications
CMOS
8-bit MSPS Converter
MB40C328V
DESCRIPTION
MB40C328V high-speed converter using fast CMOS technology.
FEATURES
Resolution Linearity error Maximum conversion rate Power supply voltage ±0.40% (standard) MSPS (minimum) (standard: digital input) (standard: converter) level (100 single phase input CLK, two-phase input CLKA, CLKB) level (RESET) CMOS level (CE, CKSEL, DSEL) CMOS level compatible Vp-p) (standard) (standard) Reference voltage generator circuit: VREFT VREFB High impedance output, power down function demultiplex output enable (RESET action enable) deviding clock output Cross sampling (two-phase CLK) enable (CLKA, CLKB) LQFP48 lead pitch
Clock input voltage range Digital input voltage range Digital output voltage range Analog input voltage range Analog input capacitance Power dissipation Additional features
Package
PACKAGE
48-pin Plastic LQFP
(FPT-48P-M05)
MB40C328V
ASSIGNMENT
(LSB)
CLKOA
VREFT
DVDD
AVDD
DVSS
AVSS
AVDD AVSS VREFB AVSS VINA AVDD CKSEL AVSS
(TOP VIEW)
(MSB) DVSS CLKA CLKB RESET DVDDI (LSB)
AVDD
DVDD
DVSS
(MSB)
DSEL
CLKOB
MB40C328V
DESCRIPTION
Symbol AVDD DVDD DVDDI AVSS DVSS CKSEL DSEL RESET CLKA CLKB CLKOA CLKOB VINA VREFT VREFB Analog power supply (+3.3 Digital power supply (+3.3 Digital power supply digital input Analog power supply ground Digital power supply ground Digital output (Port DA7: MSB, DA0: Digital output (Port DB7: MSB, DB0: Power down input (internal pull-up resistor) Digital output (Both Port clock output (CLKOA, CLKOB) high impedance input "H". Mode operation setting input (Refer MODE SETTING) Dividing circuit reset input (See TIMING DIAGRAM Clock input (max MHz) clock input (max MHz) clock input (max MHz) Clock output (See TIMING DIAGRAM Clock output (See TIMING DIAGRAM Analog input Input range Vp-p) Reference voltage output (Add AVSS) Reference voltage output (Add AVSS) Reference voltage output (Add AVSS) Reference voltage input side Reference voltage output connecting VRT, AVDD generated. Reference voltage input bottom side Reference voltage output connecting VRB, AVDD generated. Description
values parentheses standard.
MB40C328V
BLOCK DIAGRAM
CKSEL DSEL
VINA
CLKOA
DVDDI
AVDD
DVDD
VREFT
Mode setting Timing circuit
AVDD
CLKA output buffer
select
Output selector
CLKB
output buffer
Timing circuit AVDD AVSS
RESET
CLKOB
AVSS
DVSS
VREFB
MB40C328V
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Symbol AVDD, DVDD DVDDI VINA, VRT, VRB, VREFT, VREFB, VR1, VR2, VR3, CKSEL Input/output voltage DA7, DB7, CLKOA, CLKOB, DSEL, CLKA, CLKB, RESET Storage temperature exceed +4.0 exceed +7.0 WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings. TSTG Rating Min. -0.3 -0.3 -0.3 Max. +4.0 +7.0 AVDD+0.3*1 Unit
-0.3
DVDD+0.3*1
-0.3
DVDDI+0.3*2 +125
MB40C328V
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Analog input voltage Analog reference voltage: Analog reference voltage: Analog reference voltage range DSEL Digital level input voltage CKSEL, CLK, CLKA, CLKB, RESET DSEL Digital level input voltage Digital input current Single-phase clock frequency Two-phase clock frequency Minimum clock pulse width (single-phase) Minimum clock pulse width (two-phase) Clock pulse rising/falling time RESET signal setup time RESET signal hold time Operating temperature range CKSEL, CLK, CLKA, CLKB, RESET fCLK fCLKA, fCLKB
Symbol AVDD, DVDD DVDDI VINA
Value Min. 3.00 4.75 0.00 1.90 DVDD AVDD Typ. 3.30 5.00 2.00 10.0 Max. 3.60 5.25 3.00 2.10
Unit
VIHD
VILD
WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
MB40C328V
ELECTRICAL CHARACTERISTICS
Characteristics Analog Section
(AVDD DVDD 3.00 3.60 DVDDI 4.75 5.25 -20°C +70°C) Parameter Resolution Linearity error Differential linearity error Analog input capacity Reference voltage: Reference voltage: Reference current Analog supply current Digital supply current Standby current Symbol CINA VREFT VREFB AIDD DIDD DIDDI Value Min. 0.88 AVDD 0.27 AVDD Typ. ±0.40 ±0.20 0.91 AVDD AVDD 42.0 20.0 Max. ±0.6 ±0.36 0.94 AVDD 0.33 AVDD 85.0 40.0 Unit
Characteristics Digital Section
(AVDD DVDD 3.00 3.60 DVDDI 4.75 5.25 -20°C +70°C) Parameter Digital level output voltage Digital level output voltage Digital level output current Digital level output current Symbol VOHD VOLD IOHD IOLD Value Min. DVDD -400 Typ. Max. DVDD Unit
MB40C328V
Switching Characteristics
(AVDD DVDD 3.00 3.60 DVDDI 4.75 5.25 -20°C +70°C) Parameter Maximum conversion rate Aperture time Timing diagram Timing diagram Digital output delay time Timing diagram Timing diagram Symbol tpdS tpdSO tpdM1 tpdM1O tpdM2 tpdM2O tpdD tpdDO Value Min. tWS+
Typ. tWS+
Max. tWS+
Unit MSPS
DIGITAL OUTPUT BUFFER LOAD CIRCUIT
measurement point
Measurement point
DVSS
Note: includes stray capacitance probe fixture.
MODE SETTING
CKSEL DSEL Mode input-straight output mode input-demultiplex output (in-phase) mode input-demultiplex output (two-phase) mode Two-phase input mode (CLKA, CLKB) Timing Diagram Timing diagram Timing diagram Timing diagram Timing diagram
MB40C328V
TIMING DIAGRAM
input-straight output mode (max) CLKA CLKB (DVSS) CKSEL (AVDD) DSEL (DVDD) RESET (DVDDI) (AVSS) (DVSS)
DVDDI
tWS+
tWS-
VIHD input VILD
tpdS (max) tpdS (typ) tpdS (min)
VINA input
VOHD VOLD VOHD VOLD VOHD CLKOA VOLD VOHD CLKOB VOLD
DVDD
tpdSO(max) tpdSO(typ) tpdSO(min) DVDD
VINA input Sampling rising Output (after tpdS from Sampling) rising
MB40C328V
TIMING DIAGRAM
input-demultiplex output (in-phase) mode (max) CLKA CLKB (DVSS) CKSEL (AVDD) DSEL (DVSS) (AVSS) (DVSS)
DVDD
tWS+ tWS-
VIHD input VILD
VINA input VOHD VOLD
VOHD VOLD VOHD CLKOA VOLD VOHD CLKOB VOLD
tpdM1(max) tpdM1(typ) tpdM1(min) DVDD 0.4V tpdM1(max) tpdM1(typ) tpdM1(min) DVDD 0.4V tpdM1O(max) tpdM1O(typ) tpdM1O(min) DVDD
VIHD RESET input VILD
VINA input Sampling rising Output (after tpdM1 from Sampling) rising Output (after tpdM1 from Sampling) rising
MB40C328V
TIMING DIAGRAM
input-demultiplex output (two-phase) mode (max) CLKA CLKB (DVSS) CKSEL (AVSS) DSEL (DVDD) (AVSS) (DVSS)
tWS+ tWS-
VIHD input VILD
DVDD
VINA input
VOHD VOLD
tpdM2(max) tpdM2(typ) tpdM2(min) tpdM2(max) tpdM2(typ) tpdM2(min)
DVDD
VOHD VOLD VOHD CLKOA VOLD
DVDD-0.4 tpdM2O(max) tpdM2O(typ) tpdM2O(min)
VOHD CLKOB VOLD
DVDD tpdM2O(max) tpdM2O(typ) tpdM2O(min) DVDD
VIHD RESET input VILD
VINA input Sampling rising Output (after tpdM2 from Sampling) rising Output (after tpdM2 from Sampling) rising
MB40C328V
TIMING DIAGRAM
Two-phase input mode (CLKA, CLKB) (DVSS) (DVDDI) CLKA CLKB (max) CKSEL (AVSS) DSEL (DVSS) RESET (DVDDI) (DVSS) (AVSS) (DVSS)
tWD-
tWD+
DVDD
VIHD CLKA input VILD
tWD+ tWD-
DVDD
VIHD CLKB input VILD VINA input
N(Ach)
1(Bch) 2(Ach) 3(Bch) 4(Ach) 5(Bch) 6(Ach) 7(Bch)
tpdD(max) tpdD(typ) tpdD(min)
VOHD VOLD VOHD VOLD
DVDD-0.4 tpdD(max) tpdD(typ) tpdD(min)
tpdDO(max) tpdDO(typ) tpdDO(min)
DVDD
VOHD CLKOA VOLD VOHD CLKOB VOLD
DVDD
VINA input Sampling CLKA falling Sampling CLKB falling Output (after tpdD from Sampling) CLKA rising Output (after tpdD from Sampling) CLKB rising
MB40C328V
TYPICAL APPLICATION
DA0(LSB)
CLKOA
+3.3
+3.3
VREFT
AVDD
AVSS
DVDD
CLKOA
DVSS
(LSB)DA0
AVDD AVSS
DA7(MSB)
(MSB)DA7 DVSS (TOP VIEW) CLKA CLKB RESET DVDDI (LSB)DB0 DB7(MSB) CLKOB DSEL DVDD AVDD DVSS
VREFB AVSS
CLKA CLKB RESET
VINA
VINA AVDD
CKSEL
CKSEL AVSS
DB0(LSB)
DSEL
CLKOB
(MSB)DB7
avoid voltage fluctuation operation reference voltage generator circuit (VREFT, VREFB)
VREFT: VREFB:
MB40C328V
USAGE PRECAUTIONS
sure ground pins AVDD, DVDD, DVDDI, VRT, VRB, VR1, VR2, high-frequency capacitor. Place high-frequency capacitor close possible pin. avoid generation undesired current owing indetermination internal logic, powering input more than five clock pulses just after operation (CE:
ORDERING INFORMATION
Part number MB40C328VPFV Package 48-pin Plastic LQFP (FPT-48P-M05) Remark
MB40C328V
PACKAGE DIMENSION
48-pin Plastic LQFP (FPT-48P-M05)
9.00±0.20(.354±.008)SQ 7.00±0.10(.276±.004)SQ
0.08(.003)
INDEX
Details part 1.50 -0.10
+0.20 +.008
(Mounting height)
.059 -.004
LEAD
0.50±0.08 (.020±.003)
0.18 -0.03 .007
+0.08 +.003 -.001
0.08(.003)
0.145±0.055 (.006±.002)
0~8°
0.50±0.20 (.020±.008) 0.45/0.75 (.018/.030)
0.10±0.10 (.004±.004) (Stand off) 0.25(.010)
1998 FUJITSU LIMITED F48013S-3C-6
Dimensions (inches).
MB40C328V
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9903 FUJITSU LIMITED Printed Japan

ASSP Video Applications CMOS 8-bit MSPS Converter MB40C

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