CMOS Dual Port 67130/67140 very power CMOS dual port static RAMs

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CMOS Dual Port 67130/67140 very power CMOS dual port static RAMs

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M67130/M67140
CMOS Dual Port
67130/67140 very power CMOS dual port static RAMs organized 1024 They designed used stand-alone dual port combination MASTER/SLAVE dual port bits more width systems. MASTER/SLAVE dual port approach memory system applications results full speed, error free operation without need additional discrete logic. Master slave devices provide independent ports with separate control, address pins that permit independent, asynchronous access reads writes location memory. automatic power down feature controlled permits onchip circuitry each port order enter very stand power mode. Using array eight transistors (8T) memory cell fabricated with state lithography named SCMOS, M67130/140 combine extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability 67130/140 processed according methods latest revision (class and/or 9000.
Features
Fast access time preliminary commercial only 67130L/67140L power 67130V/67140V very power Expandable data bits more using master/slave devices when using more than device. chip arbitration logic BUSY output flag master BUSY input flag slave flag port port communication Fully asynchronous operation from either port Battery backup operation data retention compatible Single Power Supply
versions also available. Please consult sales.
MATRA Rev. Fev.
M67130/M67140
Interface
Block Diagram
Notes 67130 (MASTER) BUSY open drain output requires pullup resistor 67140 (SLAVE) BUSY input Open drain output requires pull-up resistor
Configuration
PLCC (top view) (top view)
(top view), ceramic, plastic mils
R/WL BUSYL INTL I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L R/WR BUSYR INTR I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R
VQFP (top view)
MATRA Rev. Fev.
M67130/M67140
Names
LEFT PORT
R/WL I/O0L BUSYL INTL
RIGHT PORT
R/WR I/O0R BUSYR INTR
NAMES
Chip select Write Enable Output Enable Address Data Input/Output Busy Flag Interrupt Flag Power Ground
Functional Description
67130/M67140 ports with separate control, address pins that permit independent read/write access memory location. These devices have automatic power-down feature controlled controls on-chip power-down circuitry which causes port concerned into stand-by mode when selected high). When port selected access full memory array permitted. Each port Output Enable control (OE). read mode, port's turns Output drivers when LOW. Non-conflicting READ/WRITE conditions illustrated table
BUSY flags required when both ports attempt access same location simultaneously.Should this conflict arise, on-chip arbitration logic will determine which port access BUSY flag inhibited port. BUSY speeds that allow processor hold operation with associated address data. should noted that operation invalid port which BUSY LOW. inhibited port will given access when BUSY goes inactive. conflict will occur when both left right ports active addresses coincide. on-chip arbitration determines access these circumstances. modes arbitration provided addresses match valid before on-chip control logic arbitrates between access before address match, on-chip control logic arbitrates between left right addresses access (refer table inhibited port's BUSY flag will reset when port granted access completes operation both arbitration modes.
Data Width Expansion Master/Slave Description
Expanding data width more bits dual-port system means that several chips active simultaneously. every chip hardware arbitrator, addresses each chip arrive same time chip activate BUSY signal while another activates BUSY signal. Both sides busy CPUs will wait indefinitely their port become free. overcome this "Busy Lock-Out" problem, developed MASTER/SLAVE system which uses single hardware arbitrator located MASTER. SLAVE BUSY inputs which allow direct interface MASTER with external components, giving speed advantage over other systems. When dual-port RAMs expanded width, SLAVE RAMs must prevented from writing until BUSY input been settled. Otherwise, SLAVE chip begin write cycle during conflict situation. opposite, write pulse must extend hold time beyond BUSY ensure that write cycle occurs once conflict resolved. This timing inherent dual-port memory systems where more than chip active same time. write pulse SLAVE must inhibited MASTER's maximum arbitration time. conflict then occurs, write SLAVE will inhibited because MASTER's BUSY signal.
Interrupt Logic
interrupt flag (INT) allows communication between ports systems. user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) when right port writes memory location (HEX). left port clears interrupt reading address location 3FE. Similarly, right port interrupt flag (INTR) when left port writes memory location (hex), right port must read memory location order clear interrupt flag (INTR). message user-defined. interrupt function used, address locations reserved mail boxes become part RAM. table interrupt function.
Arbitration Logic
arbitration logic will resolve address match chip select match down minimum determine which port access. cases, active BUSY flag will inhibited port.
MATRA Rev. Fev.
M67130/M67140
Truth Table
Table Contention Read/Write Control(4)
LEFT RIGHT PORT(1)
Notes
D0-7
DATAIN DATAOUT
FUNCTION
Port Disabled Power Down Mode. ICCSB ICCSB1 Data Port Written into memory(2) Data Memory Output Port(3) High Impedance Outputs
A9R. BUSY data written. BUSY data valid, tWDD tDDD timing. HIGH, LOW, DON'T CARE, HIGH IMPEDANCE.
Table Arbitration(6)
LEFT PORT
LL5R RL5L LW5R LW5R Notes LV5R RV5L Same Same
RIGHT PORT
LL5R RL5L LW5R LW5R LV5R RV5L Same Same
FLAGS BUSYL BUSYR
FUNCTION
Contention Contention Contention Contention L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
ADDRESS ARBITRATION WITH BEFORE ADDRESS MATCH
ARBITRATION WITH ADDRESS MATCH BEFORE
Flags Don't Care. DON'T CARE, LOW, HIGH. LV5R Left Address Valid before right address. RV5L Right Address Valid before left address. Same Left Right Addresses match within each other. LL5R Left before Right RL5L Right before left LW5R Left Right LOWwithin each other.
Table Interrupt Flag
LEFT PORT R/WL
Notes
RIGHT PORT INTL
L(9) H(8)
AOL-A9L
R/WR
AOR-A9R
INTR
L(8) H(9)
FUNCTION
Right INTR Flag Reset Right INTR Flag Left INTL Flag Reset Left INTL Flag
Assumes BUSYL BUSYR BUSYL then BUSYR then HIGH, LOW, DON'T CARE, CHANGE.
MATRA Rev. Fev.
M67130/M67140
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC-GND) -0.3 Input output voltage applied (GND -0.3 (VCC Storage temperature -65°C 150°C Notice Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device.This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extented periods affect reliability.
OPERATING RANGE
Military Automotive Industrial Commercial
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Parameters
67130/140-30 67130/140-35 67130/140-45 67130/140-55 Parameter Description Versio Preliminary 1000 1000 Unit Value AUTO AUTO AUTO 2000 1000 2000 1000 2000
ICCSB (11) ICCSB1 (12) ICCOP (13) ICCOP1 (14) Notes
Standby supply current (Both ports level inputs) Standby supply current (Both ports CMOS level inputs) Operating supply current (Both ports active) Operating supply current (One port active port standby)
Both ports active Maximum frequency Outputs open VIH. port active fMAX) Output open port stand-by CMOS Level inputs
PARAMETER
II/O(15) VIL(16) VIH(16) VOL(17) VOH(17) IN(21) OUT(21) Notes
DESCRIPTION
Input/Output leakage current Input voltage Input high voltage Output voltage (I/O0-I/O7) Open drain output voltage (BUSY, INT) Output high voltage Input capacitance Output capacitance
67130-30/35/45/55 67140-30/35/45/55
UNIT
VALUE
VCC, VIH, Vout VCC. pulse width min,
MATRA Rev. Fev.
M67130/M67140
Data-Retention Mode
CMOS RAMs designed with battery backup mind. Data retention voltage supply current guaranteed over temperature. following rules insure data retention Chip select (CS) must held high during data retention within VCCDR. must kept between during power power down transitions. begin operation after reaches minimum operating voltage (4.5 volts).
Timing
PARAMETER TEST CONDITIONS (18)
ICCDR1 ICCDR2 VCCDR VCCDR
AUTO
UNIT
Notes Vcc, Vcc. Read cycle time.
Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Figure Output Load. Output Reference Levels Output Load figures
Figure Output load. (For tHZ, tLZ, tWZ, tOW)
MATRA Rev. Fev.
M67130/M67140
Parameters
READ CYCLE PARAMETER SYMBOL SYMBOL (23) (24) TAVAVR TAVQV TELQV TGLQV TAVQX TELQZ TEHQZ Notes (*). (**). tACS tAOE Read cycle time Address access time Chip Select access time (22) Output enable access time Output hold from address change Output time (20, Output high time (20, Chip Select power time (21) Chip disable power down time (21) M67130-30(*) M67140-30(*) MIN. MAX. M67130-35(**) M67140-35(**) MIN. MAX. M67130-45 M67140-45 M67130-55 M67140-55 UNIT
MIN. MAX. MIN. MAX.
PRELIMINARY
Transition measured from high impedance voltage with load (figures This parameter guaranteed tested. access VIL. symbol. symbol. Commercial only, available DIP. package available commercial only.
Timing Waveform Read Cycle Either Side (25,
Timing Waveform Read Cycle Either Side (25,
Notes
high read cycles. Device continuously enabled, VIL. Addresses valid prior coincident with transition low. VIL. access RAM, VIL.
MATRA Rev. Fev.
M67130/M67140
Parameters
WRITE CYCLE PARAMETER SYMBOL SYMBOL (34) (35) TAVAVW TELWH TAVWH TAVWL TWLWH TWHAX TDVWH TGHQZ TWHDX TWLQZ TWHQX Notes Write cycle time Chip select write (32) Address valid write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid write Output high time (30, Data hold time (33) Write enable output high (30, Output active from write (30, M67130-30(*) M67140-30(*) MIN. MAX. M67130-35(**) M67140-35(**) MIN. MAX. M67130-45 M67140-45 M67130-55 M67140-55 UNIT
MIN. MAX. MIN. MAX.
PRELIMINARY
Transition measured from high impedance voltage with load (figures This parameter guaranteed tested. access VIL. This condition must valid entire time. specification must device supplying write data under operating conditions. Although values vary over voltage temperature, actual will always smaller than actual tOW. symbol. symbol. (*). Commercial only. available DIP. (**). package available commercial only.
MATRA Rev. Fev.
M67130/M67140
Timing Waveform Write Cycle Controlled Timing (36,
ADDRESS tHZ(41) (43) tWP(42)
tWZ(41) DATAOUT (39) DATAIN (39)
Timing Waveform Write Cycle Controlled Timing (36,
ADDRESS (43)
DATAIN
Notes
must high during address transitions. write occurs during overlap (tSW tWP) R/W. measured from earlier going high write cycle. During this period, pins output state, input signals must applied. transition occurs simultaneously with after transition, outputs remain high impedance state. Transition measured from steady state with load (including scope jig). This parameter sampled tested. during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. high during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIL.
MATRA Rev. Fev.
M67130/M67140
Parameters
Symbol PARAMETER M67130-30(*) M67140-30(*) MIN. BUSY TIMING (For M67130 only) PRELIMINARY tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD BUSY Access time address BUSY Disable time address BUSY Access time Chip Select BUSY Disable time Chip Select Write Pulse data delay (44) Write data valid read data delay (44) Arbitration priority set-up time (45) BUSY disable valid data BUSY TIMING (For 67140 only) tWDD tDDD Notes Write BUSY input (47) Write hold after BUSY (48) Write pulse data delay (49) Write data valid read data delay (49) Note Note Note Note MAX. M67130-35 M67140-35 MIN. MAX. M67130-45 M67140-45 MIN. MAX. M67130-55 67140-55 MIN. MAX. UNIT
Port-to-port delay through cells from writing port reading port, refer "Timing Waveform Read with BUSY (For M67130 only)". ensure that earlier ports wins. tBDD calculated parameter greater tWDD (actual) tDDD (actual). ensure that write cycle inhibited during contention. ensure that write cycle completed after contention. Port-to-port delay through cells from writing port reading port, refer "Timing Waveforms Read with Port port delay (For M67140 only)". (*). Commercial only. available DIP. (**). package available commercial only.
MATRA Rev. Fev.
M67130/M67140
Timing Waveform Read with BUSY (50, (For M67130)
ADDRR MATCH
R/WR
DATAIN tAPS ADDRL (50) MATCH tBDA VALID
tBDD
BUSYL tWDD DATAOUT tDDD(53) VALID
Notes
ensure that earlier port wins. Write cycle parameters should adhered ensure proper writing. Device continuously enabled both ports. reading port.
Timing Waveform Write with Port-to-port (54, (For M67140 only)
ADDRR MATCH
R/WR
DATAIN VALID
ADDRL
MATCH
tWDD DATAOUT tDDD VALID
Notes
Assume BUSY writing port, reading port. Write cycle parameters should adhered ensure proper writing. Device continuously enabled both ports.
MATRA Rev. Fev.
M67130/M67140
Timing Waveform Write with BUSY (For M67140)
Timing Waveform Contention Cycle Arbitration (For M67130 only)
MATRA Rev. Fev.
M67130/M67140
Timing Waveform Contention Cycle Address Valid Abritration (For M67130 only) (57) Left Address Valid First
Right Address Valid First
Note
Master/Slave Dual-port Memory Systems
Note
arbitration M67140 (SLAVE). BUSY-IN inhibits write M67140 (SLAVE).
MATRA Rev. Fev.
M67130/M67140
Waveform Interrupt Timing (59)
Notes
timing same left right ports. Port either left right port. Port port opposite from "A". interrupt thruth table. Timing depends which enable signal asserted last. Timing depends which enable signal de-asserted first.
Electrical Characteristics over Full Operating Temperature Supply Voltage Range
INTERRUPT TIMING SYMBOL
tINS tINR Address set-up time Write recovery time Interrupt time Interrupt reset time
PARAMETER
67130/140-30 MIN.
67130/140-35 (**) MIN.
67130/140-45 MIN.
67130/140-55 UNIT MIN.
MAX.
MAX.
MAX.
MAX.
(*). Commercial only. available DIP. (**). package available commercial only.
MATRA Rev. Fev.
M67130/M67140
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 67130V SPEED FLOW
ceramic mils side-brazed mils PLCC plastic mils VQFP 67130 67140
Master Slave power Very power Very power tolerant blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX standards Class PIND test 9000 level Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape reel Tape reel pack pack
Commercial Industrial Automotive Military Space
-40° -40° -55° -55°
+70°C +85°C +125°C +125°C +125°C
information contained herein subject change without notice. responsibility assumed MATRA using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
MATRA Rev. Fev.

CMOS Dual Port 67130/67140 very power CMOS dual port static RAMs

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