High-Efficiency Buck Converter Notebook Computers Robert Blattner
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AN710
High-Efficiency Buck Converter Notebook Computers
Robert Blattner
Today, untethering electronic equipment given rise need lightweight power sources power regulation. Extremely efficient buck converters answer part this need. losses these converters eliminate need heavy heat sinks power device packaging. addition, energy that normally consumed power converter available application. this application note, present dc-to-dc converter which intended notebook computers other portable products. This converter designed maximum efficiency, which made possible innovations-lossless current sensing synchronous rectification. converter rated load current
achieves maximum efficiency while producing with input voltage same design also configured produce efficiency achieved with input output output current total area about 2.25 in.2, with height 0.25 components except inductor surface-mount packages. Furthermore, there lead-formed TO-220s DPAKs, which results very light weight small size.
Si9150CY Description
Si9150CY BiCMOS controller with active components necessary synchronous buck converter. designed used with LITTLE FOOTr series low-voltage MOSFETs.
0.46 Power Down UVLO
GATE
Oscillator, Comparators, Error
Reference Generator
Current Limit
STBY
ISENSE
Strobe Error Amplifier COMP SYNC Break Before Make Logic
GATE
VREF
Figure Si9150CY Block Diagram
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using higher cell densities (2.5 million cells square inch), both high-side MOSFET switch synchronous rectifier (SR) housed single 8-pin small-outline package. While n-channel MOSFET obvious choice ground-referenced either n-channel MOSFETs used high-side switch. N-channel MOSFETs require charge pump and/or bootstrap circuits generate sufficient gate voltage channel enhancement. P-channel devices simple drive have higher on-resistance given size. Because recent improvements p-channel MOSFET designs, p-channel approach chosen simplicity. Si9943 includes 160-mW p-channel 100-mW n-channel MOSFET SOIC-8 package. Si9150CY controller housed 14-pin SOIC. Since pin-by-pin description Si9150CY included data sheet, limit this discussion some interesting details functional blocks. current limit. comparator relatively slow, allowing about system settle down after p-channel MOSFET turned Once p-channel MOSFET driven appears circuit drain-to-source resistance. using this resistor sense current, additional resistors current transformers eliminated. This reduces both cost losses, making possible achieve extremely high efficiency. does, however, restrict current limit trip point, which determined MOSFET on-resistance.
Oscillator
oscillator works applying pin. current flowing mirrored into pin. When reaches internal MOSFET pulls SYNC low. voltage SYNC causes pulled low, resetting clock. Allowing small offset voltages, frequency,
Break-Before-Make
prevent shoot-through essential turn MOSFET before turning opposing MOSFET. Si9150CY senses voltages N-GATE P-GATE pins. N-GATE will pulled high until P-GATE within volts VDD. Likewise, P-GATE will pulled down until N-GATE volts above GND. thresholds determined using asymmetrical CMOS inverters, i.e., transistor significantly larger than other, that logic threshold becomes gate-to-source threshold larger device. There also delay while signal, once enabled, buffered output drivers. This delay typically total deadtime (both MOSFETs off) equal about
where Cosc Rosc capacitor resistor values tied pins, respectively. SYNC voltage also passed through three inverters square edges, signal used reset circuitry Since clock resets whenever SYNC pulled low, Si9150CYs synchronized connecting their SYNC pins together. synchronization external clock desired, SYNC should pulled short period using 2N7002 similar MOSFET. recommended reset pulsewidth approximately
Current Limit Reference Generator
current limit strobed slow-acting comparator which monitors drain p-channel MOSFET. triggered when voltage minus that ISENSE greater than 0.46 typical, provided that P-GATE been pulled below about Once current limit triggered, pulled until shuts down, resetting dc-to-dc converter reference generator temperature- compensated bandgap, which powered whenever high. output from bandgap through trimmed voltage divider amplifier that source about VREF pin. more than drawn from amplifier, will shut down momentarily.
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sink current capability only about however. Since reference available more than hundred times much pull-up pull-down current, noise power pins effectively rectified. When this happens, either voltage higher than relatively low-frequency sawtooth present VREF pin. Since this voltage used parts will perform specification reference specification. recommend bypassing VREF with minimum capacitor value ground. operate. With both STBY pins high, other systems switched With pulled low, only pull-up resistor consumes power. Under very load conditions efficiency switch mode power converters decreases very rapidly. When desirable operate under light load (<50 extended period time beneficial implement linear regulator. With STBY high, Si9150CY provides voltage reference needed implementation linear regulator.
Power Down
power down section group load switches switchable current mirrors. With high STBY low, only reference generator, lockout, pull-up STBY will
Design Example
dc-to-dc converter shown Figure designed especially notebook computers. With 10-cell NiCd battery power computer, necessary convert variable voltage
PGND LGND
STANDBY
33.2 Si9943DY Si9150CY 4700
STBY COMP VREF ISENSE
VOUT
0.039
MBS120T3
PGND
LGND
33.2 Output
0.01
64.9
Figure Synchronous Buck Regulator Schematic
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assumed converters, each output voltage. This duplication increases component cost somewhat allows simple implementation independent regulation current limits. typical computer would about each voltage, times would need While weight efficiency optimized, cost effectiveness also kept mind. converter considered depth because, many respects, more difficult design. order reconfigure resulting converter output, necessary merely change assumed supply power while computer shut down. Ishutdown specification important during this time. Imax current that load needs operate. (Actually, this specification redundant with minimum Icl, include here clarity.) maximum current limit trip point must occur current that does cause safety concerns. Likewise, output voltage must within operating voltage requirements load. most circuitry, this 10%. This range must padded account voltage drops noise generated load. deviation from broken down into accuracy, noise, step-load response. Since, most designs, load will jump from microseconds, step-load figure divided half. load's decoupling capacitors trace resistances provide filter which smoothes output voltage, allowing value output ripple voltage used. Thus, error, half step-load response, ripple should less than equal about above explanation based rules thumb should scrutinized system designer before use. safest specification uses peak ripple full step response. Also note that converter will tend degrees above ambient temperature, will operated while computer outside temperature range.
Converter Specification
specifications given Table representative typical portable application. current limit been specified fairly loosely, because most applications will permit because lossless current limit circuit requires wide current limit spread.
Table DC-to-DC Converter Specifications
Spec
Imax load Ishutdown Vout Step-load Output ripple Input ripple Start time Efficiency Operating temp Switching frequency
Unit
mVrms mVrms
Conditions
150_C under fault conditions
4.85
16.5 5.15
Design Methodology
Iout 16.5 16.5 Iout
description buck converter design procedure given here. This particular design employs Si9150CY driving Si9943DY complementary half-bridge, other converters designed using same method. first step designing with Si9150CY choose p-channel MOSFET switch meet load current requirements. rDS(on) variations over spec ranges voltage temperature will affect output current limit trip point, ICL, since rDS(on) used current sensing resistor. Once verified that maximum load requirements met, inductor designed meet efficiency size requirements. discussion below, ripple power losses calculated surface-mount tantalum capacitors, some criteria given selection Schottky diode. explanation feedback network given, finally softstart capacitor selection board layout considerations discussed.
Iout
load maximum current that permissible unloaded converter consume while operating. this level high typical computer's shut-down mode, linear regulator small bang-bang converter
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Worst-Case Current Limit Calculations
There three important current limit values that must considered when choosing p-channel MOSFET. First, minimum current which current limit will trip (ICLmin). This value needed ensure that converter will power load under conditions. Secondly, maximum current which current limit will trip (ICLmax). This value needed satisfy safety system specifications, well inductor design. Finally, maximum current (ICLtherm) with MOSFET's junction maximum rated temperature needed verify converter's ability survive short circuit under worst-case conditions. current limit will trip voltage across p-channel MOSFET more than while MOSFET fully peak drain current average inductor current half ripple current. Therefore, ripple DS(on) linear region that converter efficient, current running through p-channel MOSFET given equation ripple
where Ip(t) current through p-channel MOSFET, input voltage, Vout output voltage, Iout converter output current, inductance Henries, Iripple inductor peak-to-peak ripple current. when p-channel MOSFET turns and, Iripple times divided quantity Vout when MOSFET turns off. current through MOSFET (Irmsp) given ripple
rmsp
Conduction loss (Pconp) calculated. conp DS(on) ripple
values VCL, rDS(on), Iripple that used calculate each current limit ratings given Table Unfortunately, equations these parameters non-linear interdependent. Therefore, iterative approach needed, consisting following steps.
Table Worst-case Parameters Used Current Limit Calculations
Energy lost switching transition approximated
Type
ICLmin ICLmax ICLtherm
rDS(on)
Iripple
Here, equivalent switching time MOSFET. conservative number with Si9943DY This number will scale with gate charge, other MOSFETs used. Including both transitions, switching losses (Pswp) calculated using equation
Begin estimating 150_C 16.5 assuming Iripple that rDS(on) determined. Calculate power dissipation, including switching conduction losses. Iterate calculations find correct Determine allowable ripple ICLmin Iout(MAX) which yields minimum value Having found rDS(on) verify operation ICLmin ICLtherm. Power dissipation comes from sources-switching losses conduction losses. conduction losses equal square current times rDS(on) MOSFET. Assuming that inductor operating
where clock frequency. total power dissipated p-channel MOSFET conp
calculate allowable Iripple, ICLmin specification must recalculated using calculated value Using RthJA
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equations frequency (76kHz), graph normalized rDS(on) versus estimated calculated. Here ambient temperature, 50_C, Rthja, junction-to-ambient thermal resistance, assumed 62.5_C/W. After couple iterations, 90.7_C ICLmin 2.02 This allows maximum Iripple Using equation Ip(t) above, ripple out) (10) fully saturated current ICLmax cost small size Acceptable efficiency meet these criteria, conveniently sized core chosen, efficiency resulting inductor checked. efficiency acceptable, design done. not, inductor's size adjusted until acceptable efficiency reached. approximate size type material must chosen. Usually, either power ferrite with used this type application. this example, toroid will used. following values needed-inductance (L), peak magnetic field which core material linear (Bpk), peak current which inductor linear (Ipk), core equivalent length (le), core equivalent cross section (Ae), available core permeability values. Using units, inductance (11)
Therefore, this ripple current corresponds inductance with worst case 16.5 that limits ripple current known, survivability converter checked rDS(on) values corresponding both 16.5 Using equation graph rDS(on) versus actual ICLtherm calculated.
Table Calculated Worst-case Current Limits Including Temperature Ripple Current Effects
Spec
ICLmin ICLmin ICLtherm ICLtherm ICLmax
16.5
Inductance
Large Large Large
Current
1.62 1.53 2.89 2.76
91_C 86_C 141_C 134_C
where 3.14 number turns. Also, using following relationships, (14) (12)
(13)
When used together, Si9943DY Si9150CY produce converter which counted produce which will tolerate overcurrent situation which might arise.
maximum value determined from (15)
Inductor Design
Having selected p-channel MOSFET determined ripple current minimum current which inductor fully saturated, inductor other power components selected. inductor must meet five criteria: Inductance more than Linear while current converter's operating range
Magnetics Inc. core size 55040 larger than necessary, 55290 size checked. Under normal operation inductance should remain constant, Since soft saturation characteristic, used aggressively, 5500 gauss chosen. ferrite used, ferrite's Bsat 150_C would used prevent complete saturation under worst-case conditions.
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adjusted give desired equivalent permeability. ungapped ferrite should used. 55290 core 0.095 2.18 Plugging these numbers into above equation, mmax 131. Referring catalog, next lower permeability available. Using above equations, (16)
core 0.489 0.0039 i.28
2.14
(21) Although this number exact, evident that core losses problem. total loss inductor about 1.5% output power-small enough this application.
125, less than 25.4 turns. Using 55290 core with turns equation above, 42.7 Since there some leeway ICLmin specification, this value acceptable. Now, losses inductor calculated. While p-channel MOSFET current inductor same current through p-channel MOSFET. When MOSFET off, current ramps back down same level Thus, inductor current (Irmsi) calculated rmsi ripple
Capacitor Selection
load source capacitances ignored, minimum capacitance maximum values obtained, which used conservative design. Such approach leads overdesign. Instead, input capacitor chosen avoid significant losses voltage drop, input output capacitor values assumed halved power source load capacitors. 33-mF, 20-V 47-mF, 10-V tantalum capacitors checked input output filters. Three capacitors paralleled input, output. After halving, maximum rated surface-mount capacitors input output, respectively. Although ripple voltage usually limiting factor, power dissipated capacitors will discussed first. current flowing through input capacitor (Icap) Icap (22)
(17)
resistance inductor wire equals wire length times resistance unit length, which turns 24-gauge copper wire 0.839 (18)
Next wire losses (Pwire) inductor calculated. Since converter will typically less than Iout been wire (19)
where Ip(t) current through p-channel MOSFET Ip(t) average input current. input capacitor current (Irmsci) rmsci 2(t) p(t) (23)
about 0.8% output power. Finally, core losses calculated. ripple field (DB) given out) (20)
rmsci
ripple
out2
(24)
Substituting (the input voltage which inductor voltage symmetric square wave), 1,238 gauss. Using equation supplied core vendor, loss Siliconix
Now, power dissipated input capacitor calculated using capacitor ESR. ESRin I2rmsci (25)
AN710
With ESRin Vout Iout power dissipated 1.2% converter's output power). Likewise, current through output capacitor (Irmsco) rmsco ripple (26) worst-case conditions input output ripple voltages (Vin 16.5 Iout ESRout Cout mF), Vrmsio Comparing peak-to-peak capacitive ripples, respectively capacitive component will enough voltage make ripple exceed This high number, still less than specified. similar analysis voltage across input capacitor reveals expected voltage input less than
power dissipated ESRout I2rmsco (27)
Schottky Diode
Under same conditions used input capacitor power calculation above, 0.4%. input output voltage ripple will considered. Voltage ripple caused effects, capacitor times ripple current, charge transfer divided capacitance.
Vpkio ESRout Iripple
(28)
VRMSIO ESRout IRMSCO (29)
where Vpkio peak-to-peak output ripple voltage Vrmsio output ripple voltage, both output capacitor ESR. peak-to-peak ripple voltage capacitance (Vpkqo) pkqo ripple (30)
Schottky diode included circuit prevent internal diode n-channel MOSFET from turning internal MOSFET should remain reasons. First, being silicon diode, reverse recovery charge that will cause effect similar shoot-through. estimate these losses, reverse recovery charge should multiplied input voltage converter clock frequency. charge estimated 130% half di/dt times reverse recovery time squared. this converter, with 16.5 Iout loss would about Note that while n-channel MOSFET causing this power loss, heat generated p-channel MOSFET. second reason that Schottky included that lower forward drop than n-channel MOSFET internal diode. Schottky diode conducts while both MOSFETs off. During normal operation, this period totals about cycle. During current limit caused very load resistance, inductor completely discharge though Schottky. Schottky will generate much less heat than MOSFET diode while inductor discharging. Schottky should chosen that forward drop less than forward drop n-channel MOSFET internal diode ICLtherm. This selection will prevent additional heat from reverse-recovery charge from overheating p-channel MOSFET during high current condition.
Since input ripple somewhat harder calculate, input current assumed larger than Iripple. Under these conditions, pkii pkqi (32) where Vpkii input ripple's component Vpkqi input ripple's capacitive component. Using ripple (31)
Feedback Network Design
high-efficiency converter requires output filter with losses high fast 180-degree phase shift large increase gain filter resonant frequency complicate design feedback network. purposes this discussion, converter will simplified behavioral model shown Figure gain phase output filter given Figure Siliconix
AN710
Si9943DY U1:B Circuitry Si9943DY U1:A PGND Figure Actual Circuit
COMP
VOUT
FEEDBACK
Error Amplifier VREF
COUT
COMP Drive Voltage (VD)
VOUT COUT
FEEDBACK
ESRout
(COMP-1
Figure Behavioral Model Feedback Loop Analysis
GAIN (dB)
PHASE (Degrees)
Figure Output Filter Response -180
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frequencies, impedance inductor small while impedance capacitor large, causing output voltage about same input voltage. high frequencies, inductor controls current reaching capacitor. current through inductor lags input voltage degrees. Likewise, voltage across capacitor lags current through inductor degrees. Therefore, since output voltage lags input voltage degrees, voltage actually inverted filter. approaches used compensation buck converter power stage. Figure shows low-performance (integrator) compensation method. circuit values corresponding these plots follows: 0.01 (R2, used). using dominant low-frequency pole loop gain reduced frequency substantially below filter resonant frequency. This results slow dynamic response. obtain better performance, gain converter must greater than resonant frequency. achieve this improvement designing feedback circuit differentiate, rather than integrate, near resonant frequency. This approach, which referred lead-lag network, used compensation buck converter. Figure gives Bode plots feedback network total loop gain circuit values given Figure
GAIN (dB) PHASE (Degrees) GAIN (dB) PHASE (Degrees)
-180
-180
Figure Low-performance Feedback Network Transfer Function
Figure High-performance Feedback Network Transfer Function
GAIN (dB)
PHASE (Degrees)
GAIN (dB)
PHASE (Degrees)
-180
-180
Figure Open-loop Gain Converter With Low-performance Feedback Network
Figure Open-loop Gain Converter With High-performance Feedback Network
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Dynamic Response Limitations
Synchronous operation converter ensures that inductor flux left zero, since inductor current flow reverse direction. Thus converter runs continuous conduction mode times. minimum excursion output voltage which theoretically achieved continuous conduction limited output filter components. Assuming ideal feedback network, controller responds step increase load immediately applying full voltage, Vin, output filter. Also assume that output filter switching circuit lossless. Thus, using behavioral model Figure with both resistors solving Vout, following equations obtained: out(t) Vex(t) Vout(t) Vout(0) (t)| step (t)| Solving equation yields ex(t) step sin(w
Figure Error Amplifier Bode Plot
high-performance compensation circuit used. low-performance compensation circuit used, size capacitor will even larger. error amplifier characteristics which limit feedback loop well. First, open loop gain typically This represented pole where feedback network with ideal would reach gain Secondly, source only about frequency amplitude where more than required keep feedback reference voltage, network will begin resemble wire, instead integrator. This should happen well above unity gain crossover frequency control loop. Finally, limited gain bandwidth, illustrated below Figure
out(t)
(33) (34) (35) (36)
Phase degrees) Gain
(37)
(38)
Softstart Capacitor Selection
After current limit been triggered, following sequence events occurs. First, pins pulled current limit circuitry. Once shut Si9150CY, both Si9943DY MOSFETs off. resistor pulls rate determined capacitor pF). Once passes threshold voltage, reference current source STBY activated. After STBY passes threshold, current feedback circuitry turned After clock cycle, circuitry activated. Meanwhile, error amplifier output restricted about above voltage. voltage ramps allowing COMP voltage increase. During this period, converter output voltage will ramp rate approximately Vin/2.5 times ramp rate voltage.
[Vin Vout (0)]
where (39)
Vex(t) extreme given
*Istep out(0)
(40)
Thus, given inductor, there minimum capacitor which must used achieve given step response. This value should padded factor Siliconix
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Layout Considerations
STBY COMP Vout
stable operation reliable current limiting (i.e., false trips), necessary bypass capacitors Si9150CY grounds properly. Also, high-efficiency high-current traces should made wide minimize parasitic losses. These layout-related topics covered here. lossless current sense circuit uses reference. Therefore, Si9150CY should tied directly source p-channel MOSFET. Since there switching noise source p-channel MOSFET, ground should broken into logic ground power ground shown Figure bypass capacitor Si9150CY should tied logic ground. connection between power logic grounds should much longer than p-channel source connection. result, logic ground will track spikes p-channel source rather than n-channel source. course, signal components, including feedback network, should referenced logic ground. Figure also shows current paths. most critical loop defined p-channel MOSFET, n-channel MOSFET parallel with
Figure Startup Waveforms RLOAD
Since pulled (typical), rent needed charge output capacitor (Istartup) startup (41)
where value soft start capacitor rads. Istartup should limited value enough trigger current limit when combined with load that converter will initially.
High Frequency Bypass (About MHz)
Si9150CY
U1:B Si9943DY
U1:A Si9943DY
VOUT
VREF LGND
PGND
Figure Ground Layout High frequency Bypassing
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This loop should kept very short keep resonant frequencies high, that will excited switching p-channel MOSFET. There high-current paths whose trace resistances should minimized, shown Figure figure also shows currents which must carried input output filter capacitors. efficiency exceeds 90%. converter efficiency also measured 3.3-V output (change from 33.2 kW), shown Figure Peak efficiency Iout both 3.3-V cases, efficiency reduced increases. This reduction mainly increased switching inductor core losses indicates that NiCd NiMH cells should used maximum efficiency Si9150CY control integrates required control functions synchronous rectified buck converter-including lossless current sensing, break-before-make timing, control functions. When driving Si9943DY MOSFET half-bridge, surface-mount, 1.5-A buck regulator occupies only 2.25 square inches circuit board.
Conclusion
Cost-effective small dc-to-dc converters with greater than efficiency longer require exotic technologies. Figure plots efficiency versus load current converter design described above. Peak efficiency achieved Iout Over broad range line load conditions
Path Si9150CY STBY PGND Path Input Capacitor Current ripple Output Capacitor Current ripple COMP ISEN SYNC U1:A Si9943DY U1:B Si9943DY VOUT
Figure Current Paths
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Efficiency Efficiency
IOUT Figure Output Buck Regulator Measured Efficiency
IOUT
Figure 3.3-V Buck Regulator Measured Efficiency
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